1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #ifndef SHIFT_COUNT_TRUNCATED
95 #define SHIFT_COUNT_TRUNCATED 0
98 /* It is not safe to use ordinary gen_lowpart in combine.
99 Use gen_lowpart_for_combine instead. See comments there. */
100 #define gen_lowpart dont_use_gen_lowpart_you_dummy
102 /* Number of attempts to combine instructions in this function. */
104 static int combine_attempts;
106 /* Number of attempts that got as far as substitution in this function. */
108 static int combine_merges;
110 /* Number of instructions combined with added SETs in this function. */
112 static int combine_extras;
114 /* Number of instructions combined in this function. */
116 static int combine_successes;
118 /* Totals over entire compilation. */
120 static int total_attempts, total_merges, total_extras, total_successes;
123 /* Vector mapping INSN_UIDs to cuids.
124 The cuids are like uids but increase monotonically always.
125 Combine always uses cuids so that it can compare them.
126 But actually renumbering the uids, which we used to do,
127 proves to be a bad idea because it makes it hard to compare
128 the dumps produced by earlier passes with those from later passes. */
130 static int *uid_cuid;
131 static int max_uid_cuid;
133 /* Get the cuid of an insn. */
135 #define INSN_CUID(INSN) \
136 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
138 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
139 BITS_PER_WORD would invoke undefined behavior. Work around it. */
141 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
142 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
144 #define nonzero_bits(X, M) \
145 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
147 #define num_sign_bit_copies(X, M) \
148 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
150 /* Maximum register number, which is the size of the tables below. */
152 static unsigned int combine_max_regno;
154 /* Record last point of death of (hard or pseudo) register n. */
156 static rtx *reg_last_death;
158 /* Record last point of modification of (hard or pseudo) register n. */
160 static rtx *reg_last_set;
162 /* Record the cuid of the last insn that invalidated memory
163 (anything that writes memory, and subroutine calls, but not pushes). */
165 static int mem_last_set;
167 /* Record the cuid of the last CALL_INSN
168 so we can tell whether a potential combination crosses any calls. */
170 static int last_call_cuid;
172 /* When `subst' is called, this is the insn that is being modified
173 (by combining in a previous insn). The PATTERN of this insn
174 is still the old pattern partially modified and it should not be
175 looked at, but this may be used to examine the successors of the insn
176 to judge whether a simplification is valid. */
178 static rtx subst_insn;
180 /* This is the lowest CUID that `subst' is currently dealing with.
181 get_last_value will not return a value if the register was set at or
182 after this CUID. If not for this mechanism, we could get confused if
183 I2 or I1 in try_combine were an insn that used the old value of a register
184 to obtain a new value. In that case, we might erroneously get the
185 new value of the register when we wanted the old one. */
187 static int subst_low_cuid;
189 /* This contains any hard registers that are used in newpat; reg_dead_at_p
190 must consider all these registers to be always live. */
192 static HARD_REG_SET newpat_used_regs;
194 /* This is an insn to which a LOG_LINKS entry has been added. If this
195 insn is the earlier than I2 or I3, combine should rescan starting at
198 static rtx added_links_insn;
200 /* Basic block in which we are performing combines. */
201 static basic_block this_basic_block;
203 /* A bitmap indicating which blocks had registers go dead at entry.
204 After combine, we'll need to re-do global life analysis with
205 those blocks as starting points. */
206 static sbitmap refresh_blocks;
208 /* The next group of arrays allows the recording of the last value assigned
209 to (hard or pseudo) register n. We use this information to see if an
210 operation being processed is redundant given a prior operation performed
211 on the register. For example, an `and' with a constant is redundant if
212 all the zero bits are already known to be turned off.
214 We use an approach similar to that used by cse, but change it in the
217 (1) We do not want to reinitialize at each label.
218 (2) It is useful, but not critical, to know the actual value assigned
219 to a register. Often just its form is helpful.
221 Therefore, we maintain the following arrays:
223 reg_last_set_value the last value assigned
224 reg_last_set_label records the value of label_tick when the
225 register was assigned
226 reg_last_set_table_tick records the value of label_tick when a
227 value using the register is assigned
228 reg_last_set_invalid set to nonzero when it is not valid
229 to use the value of this register in some
232 To understand the usage of these tables, it is important to understand
233 the distinction between the value in reg_last_set_value being valid
234 and the register being validly contained in some other expression in the
237 Entry I in reg_last_set_value is valid if it is nonzero, and either
238 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
240 Register I may validly appear in any expression returned for the value
241 of another register if reg_n_sets[i] is 1. It may also appear in the
242 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
243 reg_last_set_invalid[j] is zero.
245 If an expression is found in the table containing a register which may
246 not validly appear in an expression, the register is replaced by
247 something that won't match, (clobber (const_int 0)).
249 reg_last_set_invalid[i] is set nonzero when register I is being assigned
250 to and reg_last_set_table_tick[i] == label_tick. */
252 /* Record last value assigned to (hard or pseudo) register n. */
254 static rtx *reg_last_set_value;
256 /* Record the value of label_tick when the value for register n is placed in
257 reg_last_set_value[n]. */
259 static int *reg_last_set_label;
261 /* Record the value of label_tick when an expression involving register n
262 is placed in reg_last_set_value. */
264 static int *reg_last_set_table_tick;
266 /* Set nonzero if references to register n in expressions should not be
269 static char *reg_last_set_invalid;
271 /* Incremented for each label. */
273 static int label_tick;
275 /* Some registers that are set more than once and used in more than one
276 basic block are nevertheless always set in similar ways. For example,
277 a QImode register may be loaded from memory in two places on a machine
278 where byte loads zero extend.
280 We record in the following array what we know about the nonzero
281 bits of a register, specifically which bits are known to be zero.
283 If an entry is zero, it means that we don't know anything special. */
285 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
287 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
288 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
290 static enum machine_mode nonzero_bits_mode;
292 /* Nonzero if we know that a register has some leading bits that are always
293 equal to the sign bit. */
295 static unsigned char *reg_sign_bit_copies;
297 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
298 It is zero while computing them and after combine has completed. This
299 former test prevents propagating values based on previously set values,
300 which can be incorrect if a variable is modified in a loop. */
302 static int nonzero_sign_valid;
304 /* These arrays are maintained in parallel with reg_last_set_value
305 and are used to store the mode in which the register was last set,
306 the bits that were known to be zero when it was last set, and the
307 number of sign bits copies it was known to have when it was last set. */
309 static enum machine_mode *reg_last_set_mode;
310 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
311 static char *reg_last_set_sign_bit_copies;
313 /* Record one modification to rtl structure
314 to be undone by storing old_contents into *where.
315 is_int is 1 if the contents are an int. */
321 union {rtx r; int i;} old_contents;
322 union {rtx *r; int *i;} where;
325 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
326 num_undo says how many are currently recorded.
328 other_insn is nonzero if we have modified some other insn in the process
329 of working on subst_insn. It must be verified too. */
338 static struct undobuf undobuf;
340 /* Number of times the pseudo being substituted for
341 was found and replaced. */
343 static int n_occurrences;
345 static void do_SUBST (rtx *, rtx);
346 static void do_SUBST_INT (int *, int);
347 static void init_reg_last_arrays (void);
348 static void setup_incoming_promotions (void);
349 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
350 static int cant_combine_insn_p (rtx);
351 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
352 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
353 static int contains_muldiv (rtx);
354 static rtx try_combine (rtx, rtx, rtx, int *);
355 static void undo_all (void);
356 static void undo_commit (void);
357 static rtx *find_split_point (rtx *, rtx);
358 static rtx subst (rtx, rtx, rtx, int, int);
359 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
360 static rtx simplify_if_then_else (rtx);
361 static rtx simplify_set (rtx);
362 static rtx simplify_logical (rtx, int);
363 static rtx expand_compound_operation (rtx);
364 static rtx expand_field_assignment (rtx);
365 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
366 rtx, unsigned HOST_WIDE_INT, int, int, int);
367 static rtx extract_left_shift (rtx, int);
368 static rtx make_compound_operation (rtx, enum rtx_code);
369 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
370 unsigned HOST_WIDE_INT *);
371 static rtx force_to_mode (rtx, enum machine_mode,
372 unsigned HOST_WIDE_INT, rtx, int);
373 static rtx if_then_else_cond (rtx, rtx *, rtx *);
374 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
375 static int rtx_equal_for_field_assignment_p (rtx, rtx);
376 static rtx make_field_assignment (rtx);
377 static rtx apply_distributive_law (rtx);
378 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
379 unsigned HOST_WIDE_INT);
380 static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
381 rtx, enum machine_mode,
382 unsigned HOST_WIDE_INT);
383 static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
385 unsigned HOST_WIDE_INT);
386 static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
389 static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
390 enum machine_mode, unsigned int);
391 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
392 HOST_WIDE_INT, enum machine_mode, int *);
393 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
395 static int recog_for_combine (rtx *, rtx, rtx *);
396 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
397 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
398 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
399 static void update_table_tick (rtx);
400 static void record_value_for_reg (rtx, rtx, rtx);
401 static void check_promoted_subreg (rtx, rtx);
402 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
403 static void record_dead_and_set_regs (rtx);
404 static int get_last_value_validate (rtx *, rtx, int, int);
405 static rtx get_last_value (rtx);
406 static int use_crosses_set_p (rtx, int);
407 static void reg_dead_at_p_1 (rtx, rtx, void *);
408 static int reg_dead_at_p (rtx, rtx);
409 static void move_deaths (rtx, rtx, int, rtx, rtx *);
410 static int reg_bitfield_target_p (rtx, rtx);
411 static void distribute_notes (rtx, rtx, rtx, rtx);
412 static void distribute_links (rtx);
413 static void mark_used_regs_combine (rtx);
414 static int insn_cuid (rtx);
415 static void record_promoted_value (rtx, rtx);
416 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
417 static enum rtx_code combine_reversed_comparison_code (rtx);
419 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
420 insn. The substitution can be undone by undo_all. If INTO is already
421 set to NEWVAL, do not record this change. Because computing NEWVAL might
422 also call SUBST, we have to compute it before we put anything into
426 do_SUBST (rtx *into, rtx newval)
431 if (oldval == newval)
434 /* We'd like to catch as many invalid transformations here as
435 possible. Unfortunately, there are way too many mode changes
436 that are perfectly valid, so we'd waste too much effort for
437 little gain doing the checks here. Focus on catching invalid
438 transformations involving integer constants. */
439 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
440 && GET_CODE (newval) == CONST_INT)
442 /* Sanity check that we're replacing oldval with a CONST_INT
443 that is a valid sign-extension for the original mode. */
444 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
448 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
449 CONST_INT is not valid, because after the replacement, the
450 original mode would be gone. Unfortunately, we can't tell
451 when do_SUBST is called to replace the operand thereof, so we
452 perform this test on oldval instead, checking whether an
453 invalid replacement took place before we got here. */
454 if ((GET_CODE (oldval) == SUBREG
455 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
456 || (GET_CODE (oldval) == ZERO_EXTEND
457 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
462 buf = undobuf.frees, undobuf.frees = buf->next;
464 buf = xmalloc (sizeof (struct undo));
468 buf->old_contents.r = oldval;
471 buf->next = undobuf.undos, undobuf.undos = buf;
474 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
476 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
477 for the value of a HOST_WIDE_INT value (including CONST_INT) is
481 do_SUBST_INT (int *into, int newval)
486 if (oldval == newval)
490 buf = undobuf.frees, undobuf.frees = buf->next;
492 buf = xmalloc (sizeof (struct undo));
496 buf->old_contents.i = oldval;
499 buf->next = undobuf.undos, undobuf.undos = buf;
502 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
504 /* Main entry point for combiner. F is the first insn of the function.
505 NREGS is the first unused pseudo-reg number.
507 Return nonzero if the combiner has turned an indirect jump
508 instruction into a direct jump. */
510 combine_instructions (rtx f, unsigned int nregs)
517 rtx links, nextlinks;
519 int new_direct_jump_p = 0;
521 combine_attempts = 0;
524 combine_successes = 0;
526 combine_max_regno = nregs;
528 reg_nonzero_bits = xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT));
529 reg_sign_bit_copies = xcalloc (nregs, sizeof (unsigned char));
531 reg_last_death = xmalloc (nregs * sizeof (rtx));
532 reg_last_set = xmalloc (nregs * sizeof (rtx));
533 reg_last_set_value = xmalloc (nregs * sizeof (rtx));
534 reg_last_set_table_tick = xmalloc (nregs * sizeof (int));
535 reg_last_set_label = xmalloc (nregs * sizeof (int));
536 reg_last_set_invalid = xmalloc (nregs * sizeof (char));
537 reg_last_set_mode = xmalloc (nregs * sizeof (enum machine_mode));
538 reg_last_set_nonzero_bits = xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies = xmalloc (nregs * sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
548 if (INSN_UID (insn) > i)
551 uid_cuid = xmalloc ((i + 1) * sizeof (int));
554 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid = 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 setup_incoming_promotions ();
576 refresh_blocks = sbitmap_alloc (last_basic_block);
577 sbitmap_zero (refresh_blocks);
579 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
581 uid_cuid[INSN_UID (insn)] = ++i;
587 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
589 record_dead_and_set_regs (insn);
592 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
593 if (REG_NOTE_KIND (links) == REG_INC)
594 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
599 if (GET_CODE (insn) == CODE_LABEL)
603 nonzero_sign_valid = 1;
605 /* Now scan all the insns in forward order. */
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 FOR_EACH_BB (this_basic_block)
615 for (insn = BB_HEAD (this_basic_block);
616 insn != NEXT_INSN (BB_END (this_basic_block));
617 insn = next ? next : NEXT_INSN (insn))
621 if (GET_CODE (insn) == CODE_LABEL)
624 else if (INSN_P (insn))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn, PATTERN (insn));
630 /* Try this insn with each insn it links back to. */
632 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
633 if ((next = try_combine (insn, XEXP (links, 0),
634 NULL_RTX, &new_direct_jump_p)) != 0)
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 rtx link = XEXP (links, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in pursuing this chain any further. */
645 if (GET_CODE (link) == NOTE)
648 for (nextlinks = LOG_LINKS (link);
650 nextlinks = XEXP (nextlinks, 1))
651 if ((next = try_combine (insn, link,
653 &new_direct_jump_p)) != 0)
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn) == JUMP_INSN
666 && (prev = prev_nonnote_insn (insn)) != 0
667 && GET_CODE (prev) == INSN
668 && sets_cc0_p (PATTERN (prev)))
670 if ((next = try_combine (insn, prev,
671 NULL_RTX, &new_direct_jump_p)) != 0)
674 for (nextlinks = LOG_LINKS (prev); nextlinks;
675 nextlinks = XEXP (nextlinks, 1))
676 if ((next = try_combine (insn, prev,
678 &new_direct_jump_p)) != 0)
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn) == INSN
684 && (prev = prev_nonnote_insn (insn)) != 0
685 && GET_CODE (prev) == INSN
686 && sets_cc0_p (PATTERN (prev))
687 && GET_CODE (PATTERN (insn)) == SET
688 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
690 if ((next = try_combine (insn, prev,
691 NULL_RTX, &new_direct_jump_p)) != 0)
694 for (nextlinks = LOG_LINKS (prev); nextlinks;
695 nextlinks = XEXP (nextlinks, 1))
696 if ((next = try_combine (insn, prev,
698 &new_direct_jump_p)) != 0)
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
706 if (GET_CODE (XEXP (links, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
708 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
709 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
710 && GET_CODE (prev) == INSN
711 && sets_cc0_p (PATTERN (prev))
712 && (next = try_combine (insn, XEXP (links, 0),
713 prev, &new_direct_jump_p)) != 0)
717 /* Try combining an insn with two different insns whose results it
719 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
720 for (nextlinks = XEXP (links, 1); nextlinks;
721 nextlinks = XEXP (nextlinks, 1))
722 if ((next = try_combine (insn, XEXP (links, 0),
724 &new_direct_jump_p)) != 0)
727 if (GET_CODE (insn) != NOTE)
728 record_dead_and_set_regs (insn);
737 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
738 BASIC_BLOCK (i)->flags |= BB_DIRTY);
739 new_direct_jump_p |= purge_all_dead_edges (0);
740 delete_noop_moves (f);
742 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
743 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
744 | PROP_KILL_DEAD_CODE);
747 sbitmap_free (refresh_blocks);
748 free (reg_nonzero_bits);
749 free (reg_sign_bit_copies);
750 free (reg_last_death);
752 free (reg_last_set_value);
753 free (reg_last_set_table_tick);
754 free (reg_last_set_label);
755 free (reg_last_set_invalid);
756 free (reg_last_set_mode);
757 free (reg_last_set_nonzero_bits);
758 free (reg_last_set_sign_bit_copies);
762 struct undo *undo, *next;
763 for (undo = undobuf.frees; undo; undo = next)
771 total_attempts += combine_attempts;
772 total_merges += combine_merges;
773 total_extras += combine_extras;
774 total_successes += combine_successes;
776 nonzero_sign_valid = 0;
778 /* Make recognizer allow volatile MEMs again. */
781 return new_direct_jump_p;
784 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
787 init_reg_last_arrays (void)
789 unsigned int nregs = combine_max_regno;
791 memset (reg_last_death, 0, nregs * sizeof (rtx));
792 memset (reg_last_set, 0, nregs * sizeof (rtx));
793 memset (reg_last_set_value, 0, nregs * sizeof (rtx));
794 memset (reg_last_set_table_tick, 0, nregs * sizeof (int));
795 memset (reg_last_set_label, 0, nregs * sizeof (int));
796 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
797 memset (reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
798 memset (reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
799 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
802 /* Set up any promoted values for incoming argument registers. */
805 setup_incoming_promotions (void)
809 enum machine_mode mode;
811 rtx first = get_insns ();
813 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
815 #ifndef OUTGOING_REGNO
816 #define OUTGOING_REGNO(N) N
818 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
819 /* Check whether this register can hold an incoming pointer
820 argument. FUNCTION_ARG_REGNO_P tests outgoing register
821 numbers, so translate if necessary due to register windows. */
822 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
823 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
826 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
829 gen_rtx_CLOBBER (mode, const0_rtx)));
834 /* Called via note_stores. If X is a pseudo that is narrower than
835 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
837 If we are setting only a portion of X and we can't figure out what
838 portion, assume all bits will be used since we don't know what will
841 Similarly, set how many bits of X are known to be copies of the sign bit
842 at all locations in the function. This is the smallest number implied
846 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
847 void *data ATTRIBUTE_UNUSED)
851 if (GET_CODE (x) == REG
852 && REGNO (x) >= FIRST_PSEUDO_REGISTER
853 /* If this register is undefined at the start of the file, we can't
854 say what its contents were. */
855 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
856 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
858 if (set == 0 || GET_CODE (set) == CLOBBER)
860 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
861 reg_sign_bit_copies[REGNO (x)] = 1;
865 /* If this is a complex assignment, see if we can convert it into a
866 simple assignment. */
867 set = expand_field_assignment (set);
869 /* If this is a simple assignment, or we have a paradoxical SUBREG,
870 set what we know about X. */
872 if (SET_DEST (set) == x
873 || (GET_CODE (SET_DEST (set)) == SUBREG
874 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
875 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
876 && SUBREG_REG (SET_DEST (set)) == x))
878 rtx src = SET_SRC (set);
880 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
881 /* If X is narrower than a word and SRC is a non-negative
882 constant that would appear negative in the mode of X,
883 sign-extend it for use in reg_nonzero_bits because some
884 machines (maybe most) will actually do the sign-extension
885 and this is the conservative approach.
887 ??? For 2.5, try to tighten up the MD files in this regard
888 instead of this kludge. */
890 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
891 && GET_CODE (src) == CONST_INT
893 && 0 != (INTVAL (src)
895 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
896 src = GEN_INT (INTVAL (src)
897 | ((HOST_WIDE_INT) (-1)
898 << GET_MODE_BITSIZE (GET_MODE (x))));
901 /* Don't call nonzero_bits if it cannot change anything. */
902 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
903 reg_nonzero_bits[REGNO (x)]
904 |= nonzero_bits (src, nonzero_bits_mode);
905 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
906 if (reg_sign_bit_copies[REGNO (x)] == 0
907 || reg_sign_bit_copies[REGNO (x)] > num)
908 reg_sign_bit_copies[REGNO (x)] = num;
912 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
913 reg_sign_bit_copies[REGNO (x)] = 1;
918 /* See if INSN can be combined into I3. PRED and SUCC are optionally
919 insns that were previously combined into I3 or that will be combined
920 into the merger of INSN and I3.
922 Return 0 if the combination is not allowed for any reason.
924 If the combination is allowed, *PDEST will be set to the single
925 destination of INSN and *PSRC to the single source, and this function
929 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
930 rtx *pdest, rtx *psrc)
933 rtx set = 0, src, dest;
938 int all_adjacent = (succ ? (next_active_insn (insn) == succ
939 && next_active_insn (succ) == i3)
940 : next_active_insn (insn) == i3);
942 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
943 or a PARALLEL consisting of such a SET and CLOBBERs.
945 If INSN has CLOBBER parallel parts, ignore them for our processing.
946 By definition, these happen during the execution of the insn. When it
947 is merged with another insn, all bets are off. If they are, in fact,
948 needed and aren't also supplied in I3, they may be added by
949 recog_for_combine. Otherwise, it won't match.
951 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
954 Get the source and destination of INSN. If more than one, can't
957 if (GET_CODE (PATTERN (insn)) == SET)
958 set = PATTERN (insn);
959 else if (GET_CODE (PATTERN (insn)) == PARALLEL
960 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
962 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
964 rtx elt = XVECEXP (PATTERN (insn), 0, i);
967 switch (GET_CODE (elt))
969 /* This is important to combine floating point insns
972 /* Combining an isolated USE doesn't make sense.
973 We depend here on combinable_i3pat to reject them. */
974 /* The code below this loop only verifies that the inputs of
975 the SET in INSN do not change. We call reg_set_between_p
976 to verify that the REG in the USE does not change between
978 If the USE in INSN was for a pseudo register, the matching
979 insn pattern will likely match any register; combining this
980 with any other USE would only be safe if we knew that the
981 used registers have identical values, or if there was
982 something to tell them apart, e.g. different modes. For
983 now, we forgo such complicated tests and simply disallow
984 combining of USES of pseudo registers with any other USE. */
985 if (GET_CODE (XEXP (elt, 0)) == REG
986 && GET_CODE (PATTERN (i3)) == PARALLEL)
988 rtx i3pat = PATTERN (i3);
989 int i = XVECLEN (i3pat, 0) - 1;
990 unsigned int regno = REGNO (XEXP (elt, 0));
994 rtx i3elt = XVECEXP (i3pat, 0, i);
996 if (GET_CODE (i3elt) == USE
997 && GET_CODE (XEXP (i3elt, 0)) == REG
998 && (REGNO (XEXP (i3elt, 0)) == regno
999 ? reg_set_between_p (XEXP (elt, 0),
1000 PREV_INSN (insn), i3)
1001 : regno >= FIRST_PSEUDO_REGISTER))
1008 /* We can ignore CLOBBERs. */
1013 /* Ignore SETs whose result isn't used but not those that
1014 have side-effects. */
1015 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1016 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1017 || INTVAL (XEXP (note, 0)) <= 0)
1018 && ! side_effects_p (elt))
1021 /* If we have already found a SET, this is a second one and
1022 so we cannot combine with this insn. */
1030 /* Anything else means we can't combine. */
1036 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1037 so don't do anything with it. */
1038 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1047 set = expand_field_assignment (set);
1048 src = SET_SRC (set), dest = SET_DEST (set);
1050 /* Don't eliminate a store in the stack pointer. */
1051 if (dest == stack_pointer_rtx
1052 /* Don't combine with an insn that sets a register to itself if it has
1053 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1054 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1055 /* Can't merge an ASM_OPERANDS. */
1056 || GET_CODE (src) == ASM_OPERANDS
1057 /* Can't merge a function call. */
1058 || GET_CODE (src) == CALL
1059 /* Don't eliminate a function call argument. */
1060 || (GET_CODE (i3) == CALL_INSN
1061 && (find_reg_fusage (i3, USE, dest)
1062 || (GET_CODE (dest) == REG
1063 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1064 && global_regs[REGNO (dest)])))
1065 /* Don't substitute into an incremented register. */
1066 || FIND_REG_INC_NOTE (i3, dest)
1067 || (succ && FIND_REG_INC_NOTE (succ, dest))
1069 /* Don't combine the end of a libcall into anything. */
1070 /* ??? This gives worse code, and appears to be unnecessary, since no
1071 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1072 use REG_RETVAL notes for noconflict blocks, but other code here
1073 makes sure that those insns don't disappear. */
1074 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1076 /* Make sure that DEST is not used after SUCC but before I3. */
1077 || (succ && ! all_adjacent
1078 && reg_used_between_p (dest, succ, i3))
1079 /* Make sure that the value that is to be substituted for the register
1080 does not use any registers whose values alter in between. However,
1081 If the insns are adjacent, a use can't cross a set even though we
1082 think it might (this can happen for a sequence of insns each setting
1083 the same destination; reg_last_set of that register might point to
1084 a NOTE). If INSN has a REG_EQUIV note, the register is always
1085 equivalent to the memory so the substitution is valid even if there
1086 are intervening stores. Also, don't move a volatile asm or
1087 UNSPEC_VOLATILE across any other insns. */
1089 && (((GET_CODE (src) != MEM
1090 || ! find_reg_note (insn, REG_EQUIV, src))
1091 && use_crosses_set_p (src, INSN_CUID (insn)))
1092 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1093 || GET_CODE (src) == UNSPEC_VOLATILE))
1094 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1095 better register allocation by not doing the combine. */
1096 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1097 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1098 /* Don't combine across a CALL_INSN, because that would possibly
1099 change whether the life span of some REGs crosses calls or not,
1100 and it is a pain to update that information.
1101 Exception: if source is a constant, moving it later can't hurt.
1102 Accept that special case, because it helps -fforce-addr a lot. */
1103 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1106 /* DEST must either be a REG or CC0. */
1107 if (GET_CODE (dest) == REG)
1109 /* If register alignment is being enforced for multi-word items in all
1110 cases except for parameters, it is possible to have a register copy
1111 insn referencing a hard register that is not allowed to contain the
1112 mode being copied and which would not be valid as an operand of most
1113 insns. Eliminate this problem by not combining with such an insn.
1115 Also, on some machines we don't want to extend the life of a hard
1118 if (GET_CODE (src) == REG
1119 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1120 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1121 /* Don't extend the life of a hard register unless it is
1122 user variable (if we have few registers) or it can't
1123 fit into the desired register (meaning something special
1125 Also avoid substituting a return register into I3, because
1126 reload can't handle a conflict with constraints of other
1128 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1132 else if (GET_CODE (dest) != CC0)
1135 /* Don't substitute for a register intended as a clobberable operand.
1136 Similarly, don't substitute an expression containing a register that
1137 will be clobbered in I3. */
1138 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1139 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1140 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1141 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1143 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1146 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1147 or not), reject, unless nothing volatile comes between it and I3 */
1149 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1151 /* Make sure succ doesn't contain a volatile reference. */
1152 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1155 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1156 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1160 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1161 to be an explicit register variable, and was chosen for a reason. */
1163 if (GET_CODE (src) == ASM_OPERANDS
1164 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1167 /* If there are any volatile insns between INSN and I3, reject, because
1168 they might affect machine state. */
1170 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1171 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1174 /* If INSN or I2 contains an autoincrement or autodecrement,
1175 make sure that register is not used between there and I3,
1176 and not already used in I3 either.
1177 Also insist that I3 not be a jump; if it were one
1178 and the incremented register were spilled, we would lose. */
1181 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1182 if (REG_NOTE_KIND (link) == REG_INC
1183 && (GET_CODE (i3) == JUMP_INSN
1184 || reg_used_between_p (XEXP (link, 0), insn, i3)
1185 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1190 /* Don't combine an insn that follows a CC0-setting insn.
1191 An insn that uses CC0 must not be separated from the one that sets it.
1192 We do, however, allow I2 to follow a CC0-setting insn if that insn
1193 is passed as I1; in that case it will be deleted also.
1194 We also allow combining in this case if all the insns are adjacent
1195 because that would leave the two CC0 insns adjacent as well.
1196 It would be more logical to test whether CC0 occurs inside I1 or I2,
1197 but that would be much slower, and this ought to be equivalent. */
1199 p = prev_nonnote_insn (insn);
1200 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1205 /* If we get here, we have passed all the tests and the combination is
1214 /* LOC is the location within I3 that contains its pattern or the component
1215 of a PARALLEL of the pattern. We validate that it is valid for combining.
1217 One problem is if I3 modifies its output, as opposed to replacing it
1218 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1219 so would produce an insn that is not equivalent to the original insns.
1223 (set (reg:DI 101) (reg:DI 100))
1224 (set (subreg:SI (reg:DI 101) 0) <foo>)
1226 This is NOT equivalent to:
1228 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1229 (set (reg:DI 101) (reg:DI 100))])
1231 Not only does this modify 100 (in which case it might still be valid
1232 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1234 We can also run into a problem if I2 sets a register that I1
1235 uses and I1 gets directly substituted into I3 (not via I2). In that
1236 case, we would be getting the wrong value of I2DEST into I3, so we
1237 must reject the combination. This case occurs when I2 and I1 both
1238 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1239 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1240 of a SET must prevent combination from occurring.
1242 Before doing the above check, we first try to expand a field assignment
1243 into a set of logical operations.
1245 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1246 we place a register that is both set and used within I3. If more than one
1247 such register is detected, we fail.
1249 Return 1 if the combination is valid, zero otherwise. */
1252 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1253 int i1_not_in_src, rtx *pi3dest_killed)
1257 if (GET_CODE (x) == SET)
1260 rtx dest = SET_DEST (set);
1261 rtx src = SET_SRC (set);
1262 rtx inner_dest = dest;
1264 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1265 || GET_CODE (inner_dest) == SUBREG
1266 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1267 inner_dest = XEXP (inner_dest, 0);
1269 /* Check for the case where I3 modifies its output, as discussed
1270 above. We don't want to prevent pseudos from being combined
1271 into the address of a MEM, so only prevent the combination if
1272 i1 or i2 set the same MEM. */
1273 if ((inner_dest != dest &&
1274 (GET_CODE (inner_dest) != MEM
1275 || rtx_equal_p (i2dest, inner_dest)
1276 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1277 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1278 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1280 /* This is the same test done in can_combine_p except we can't test
1281 all_adjacent; we don't have to, since this instruction will stay
1282 in place, thus we are not considering increasing the lifetime of
1285 Also, if this insn sets a function argument, combining it with
1286 something that might need a spill could clobber a previous
1287 function argument; the all_adjacent test in can_combine_p also
1288 checks this; here, we do a more specific test for this case. */
1290 || (GET_CODE (inner_dest) == REG
1291 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1292 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1293 GET_MODE (inner_dest))))
1294 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1297 /* If DEST is used in I3, it is being killed in this insn,
1298 so record that for later.
1299 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1300 STACK_POINTER_REGNUM, since these are always considered to be
1301 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1302 if (pi3dest_killed && GET_CODE (dest) == REG
1303 && reg_referenced_p (dest, PATTERN (i3))
1304 && REGNO (dest) != FRAME_POINTER_REGNUM
1305 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1306 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1308 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1309 && (REGNO (dest) != ARG_POINTER_REGNUM
1310 || ! fixed_regs [REGNO (dest)])
1312 && REGNO (dest) != STACK_POINTER_REGNUM)
1314 if (*pi3dest_killed)
1317 *pi3dest_killed = dest;
1321 else if (GET_CODE (x) == PARALLEL)
1325 for (i = 0; i < XVECLEN (x, 0); i++)
1326 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1327 i1_not_in_src, pi3dest_killed))
1334 /* Return 1 if X is an arithmetic expression that contains a multiplication
1335 and division. We don't count multiplications by powers of two here. */
1338 contains_muldiv (rtx x)
1340 switch (GET_CODE (x))
1342 case MOD: case DIV: case UMOD: case UDIV:
1346 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1347 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1349 switch (GET_RTX_CLASS (GET_CODE (x)))
1351 case 'c': case '<': case '2':
1352 return contains_muldiv (XEXP (x, 0))
1353 || contains_muldiv (XEXP (x, 1));
1356 return contains_muldiv (XEXP (x, 0));
1364 /* Determine whether INSN can be used in a combination. Return nonzero if
1365 not. This is used in try_combine to detect early some cases where we
1366 can't perform combinations. */
1369 cant_combine_insn_p (rtx insn)
1374 /* If this isn't really an insn, we can't do anything.
1375 This can occur when flow deletes an insn that it has merged into an
1376 auto-increment address. */
1377 if (! INSN_P (insn))
1380 /* Never combine loads and stores involving hard regs that are likely
1381 to be spilled. The register allocator can usually handle such
1382 reg-reg moves by tying. If we allow the combiner to make
1383 substitutions of likely-spilled regs, we may abort in reload.
1384 As an exception, we allow combinations involving fixed regs; these are
1385 not available to the register allocator so there's no risk involved. */
1387 set = single_set (insn);
1390 src = SET_SRC (set);
1391 dest = SET_DEST (set);
1392 if (GET_CODE (src) == SUBREG)
1393 src = SUBREG_REG (src);
1394 if (GET_CODE (dest) == SUBREG)
1395 dest = SUBREG_REG (dest);
1396 if (REG_P (src) && REG_P (dest)
1397 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1398 && ! fixed_regs[REGNO (src)]
1399 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1400 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1401 && ! fixed_regs[REGNO (dest)]
1402 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1408 /* Adjust INSN after we made a change to its destination.
1410 Changing the destination can invalidate notes that say something about
1411 the results of the insn and a LOG_LINK pointing to the insn. */
1414 adjust_for_new_dest (rtx insn)
1418 /* For notes, be conservative and simply remove them. */
1419 loc = ®_NOTES (insn);
1422 enum reg_note kind = REG_NOTE_KIND (*loc);
1423 if (kind == REG_EQUAL || kind == REG_EQUIV)
1424 *loc = XEXP (*loc, 1);
1426 loc = &XEXP (*loc, 1);
1429 /* The new insn will have a destination that was previously the destination
1430 of an insn just above it. Call distribute_links to make a LOG_LINK from
1431 the next use of that destination. */
1432 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1435 /* Try to combine the insns I1 and I2 into I3.
1436 Here I1 and I2 appear earlier than I3.
1437 I1 can be zero; then we combine just I2 into I3.
1439 If we are combining three insns and the resulting insn is not recognized,
1440 try splitting it into two insns. If that happens, I2 and I3 are retained
1441 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1444 Return 0 if the combination does not work. Then nothing is changed.
1445 If we did the combination, return the insn at which combine should
1448 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1449 new direct jump instruction. */
1452 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1454 /* New patterns for I3 and I2, respectively. */
1455 rtx newpat, newi2pat = 0;
1456 int substed_i2 = 0, substed_i1 = 0;
1457 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1458 int added_sets_1, added_sets_2;
1459 /* Total number of SETs to put into I3. */
1461 /* Nonzero is I2's body now appears in I3. */
1463 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1464 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1465 /* Contains I3 if the destination of I3 is used in its source, which means
1466 that the old life of I3 is being killed. If that usage is placed into
1467 I2 and not in I3, a REG_DEAD note must be made. */
1468 rtx i3dest_killed = 0;
1469 /* SET_DEST and SET_SRC of I2 and I1. */
1470 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1471 /* PATTERN (I2), or a copy of it in certain cases. */
1473 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1474 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1475 int i1_feeds_i3 = 0;
1476 /* Notes that must be added to REG_NOTES in I3 and I2. */
1477 rtx new_i3_notes, new_i2_notes;
1478 /* Notes that we substituted I3 into I2 instead of the normal case. */
1479 int i3_subst_into_i2 = 0;
1480 /* Notes that I1, I2 or I3 is a MULT operation. */
1488 /* Exit early if one of the insns involved can't be used for
1490 if (cant_combine_insn_p (i3)
1491 || cant_combine_insn_p (i2)
1492 || (i1 && cant_combine_insn_p (i1))
1493 /* We also can't do anything if I3 has a
1494 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1497 /* ??? This gives worse code, and appears to be unnecessary, since no
1498 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1499 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1505 undobuf.other_insn = 0;
1507 /* Reset the hard register usage information. */
1508 CLEAR_HARD_REG_SET (newpat_used_regs);
1510 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1511 code below, set I1 to be the earlier of the two insns. */
1512 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1513 temp = i1, i1 = i2, i2 = temp;
1515 added_links_insn = 0;
1517 /* First check for one important special-case that the code below will
1518 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1519 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1520 we may be able to replace that destination with the destination of I3.
1521 This occurs in the common code where we compute both a quotient and
1522 remainder into a structure, in which case we want to do the computation
1523 directly into the structure to avoid register-register copies.
1525 Note that this case handles both multiple sets in I2 and also
1526 cases where I2 has a number of CLOBBER or PARALLELs.
1528 We make very conservative checks below and only try to handle the
1529 most common cases of this. For example, we only handle the case
1530 where I2 and I3 are adjacent to avoid making difficult register
1533 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1534 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1535 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1536 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1537 && GET_CODE (PATTERN (i2)) == PARALLEL
1538 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1539 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1540 below would need to check what is inside (and reg_overlap_mentioned_p
1541 doesn't support those codes anyway). Don't allow those destinations;
1542 the resulting insn isn't likely to be recognized anyway. */
1543 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1544 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1545 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1546 SET_DEST (PATTERN (i3)))
1547 && next_real_insn (i2) == i3)
1549 rtx p2 = PATTERN (i2);
1551 /* Make sure that the destination of I3,
1552 which we are going to substitute into one output of I2,
1553 is not used within another output of I2. We must avoid making this:
1554 (parallel [(set (mem (reg 69)) ...)
1555 (set (reg 69) ...)])
1556 which is not well-defined as to order of actions.
1557 (Besides, reload can't handle output reloads for this.)
1559 The problem can also happen if the dest of I3 is a memory ref,
1560 if another dest in I2 is an indirect memory ref. */
1561 for (i = 0; i < XVECLEN (p2, 0); i++)
1562 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1563 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1564 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1565 SET_DEST (XVECEXP (p2, 0, i))))
1568 if (i == XVECLEN (p2, 0))
1569 for (i = 0; i < XVECLEN (p2, 0); i++)
1570 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1571 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1572 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1577 subst_low_cuid = INSN_CUID (i2);
1579 added_sets_2 = added_sets_1 = 0;
1580 i2dest = SET_SRC (PATTERN (i3));
1582 /* Replace the dest in I2 with our dest and make the resulting
1583 insn the new pattern for I3. Then skip to where we
1584 validate the pattern. Everything was set up above. */
1585 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1586 SET_DEST (PATTERN (i3)));
1589 i3_subst_into_i2 = 1;
1590 goto validate_replacement;
1594 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1595 one of those words to another constant, merge them by making a new
1598 && (temp = single_set (i2)) != 0
1599 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1600 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1601 && GET_CODE (SET_DEST (temp)) == REG
1602 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1603 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1604 && GET_CODE (PATTERN (i3)) == SET
1605 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1606 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1607 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1608 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1609 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1611 HOST_WIDE_INT lo, hi;
1613 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1614 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1617 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1618 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1621 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1623 /* We don't handle the case of the target word being wider
1624 than a host wide int. */
1625 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1628 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1629 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1630 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1632 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1633 hi = INTVAL (SET_SRC (PATTERN (i3)));
1634 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1636 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1637 >> (HOST_BITS_PER_WIDE_INT - 1));
1639 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1640 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1641 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1642 (INTVAL (SET_SRC (PATTERN (i3)))));
1644 hi = lo < 0 ? -1 : 0;
1647 /* We don't handle the case of the higher word not fitting
1648 entirely in either hi or lo. */
1653 subst_low_cuid = INSN_CUID (i2);
1654 added_sets_2 = added_sets_1 = 0;
1655 i2dest = SET_DEST (temp);
1657 SUBST (SET_SRC (temp),
1658 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1660 newpat = PATTERN (i2);
1661 goto validate_replacement;
1665 /* If we have no I1 and I2 looks like:
1666 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1668 make up a dummy I1 that is
1671 (set (reg:CC X) (compare:CC Y (const_int 0)))
1673 (We can ignore any trailing CLOBBERs.)
1675 This undoes a previous combination and allows us to match a branch-and-
1678 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1679 && XVECLEN (PATTERN (i2), 0) >= 2
1680 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1681 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1683 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1684 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1685 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1686 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1687 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1688 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1690 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1691 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1696 /* We make I1 with the same INSN_UID as I2. This gives it
1697 the same INSN_CUID for value tracking. Our fake I1 will
1698 never appear in the insn stream so giving it the same INSN_UID
1699 as I2 will not cause a problem. */
1701 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1702 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1703 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1706 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1707 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1708 SET_DEST (PATTERN (i1)));
1713 /* Verify that I2 and I1 are valid for combining. */
1714 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1715 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1721 /* Record whether I2DEST is used in I2SRC and similarly for the other
1722 cases. Knowing this will help in register status updating below. */
1723 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1724 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1725 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1727 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1729 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1731 /* Ensure that I3's pattern can be the destination of combines. */
1732 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1733 i1 && i2dest_in_i1src && i1_feeds_i3,
1740 /* See if any of the insns is a MULT operation. Unless one is, we will
1741 reject a combination that is, since it must be slower. Be conservative
1743 if (GET_CODE (i2src) == MULT
1744 || (i1 != 0 && GET_CODE (i1src) == MULT)
1745 || (GET_CODE (PATTERN (i3)) == SET
1746 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1749 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1750 We used to do this EXCEPT in one case: I3 has a post-inc in an
1751 output operand. However, that exception can give rise to insns like
1753 which is a famous insn on the PDP-11 where the value of r3 used as the
1754 source was model-dependent. Avoid this sort of thing. */
1757 if (!(GET_CODE (PATTERN (i3)) == SET
1758 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1759 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1760 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1761 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1762 /* It's not the exception. */
1765 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1766 if (REG_NOTE_KIND (link) == REG_INC
1767 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1769 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1776 /* See if the SETs in I1 or I2 need to be kept around in the merged
1777 instruction: whenever the value set there is still needed past I3.
1778 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1780 For the SET in I1, we have two cases: If I1 and I2 independently
1781 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1782 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1783 in I1 needs to be kept around unless I1DEST dies or is set in either
1784 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1785 I1DEST. If so, we know I1 feeds into I2. */
1787 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1790 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1791 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1793 /* If the set in I2 needs to be kept around, we must make a copy of
1794 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1795 PATTERN (I2), we are only substituting for the original I1DEST, not into
1796 an already-substituted copy. This also prevents making self-referential
1797 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1800 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1801 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1805 i2pat = copy_rtx (i2pat);
1809 /* Substitute in the latest insn for the regs set by the earlier ones. */
1811 maxreg = max_reg_num ();
1815 /* It is possible that the source of I2 or I1 may be performing an
1816 unneeded operation, such as a ZERO_EXTEND of something that is known
1817 to have the high part zero. Handle that case by letting subst look at
1818 the innermost one of them.
1820 Another way to do this would be to have a function that tries to
1821 simplify a single insn instead of merging two or more insns. We don't
1822 do this because of the potential of infinite loops and because
1823 of the potential extra memory required. However, doing it the way
1824 we are is a bit of a kludge and doesn't catch all cases.
1826 But only do this if -fexpensive-optimizations since it slows things down
1827 and doesn't usually win. */
1829 if (flag_expensive_optimizations)
1831 /* Pass pc_rtx so no substitutions are done, just simplifications.
1832 The cases that we are interested in here do not involve the few
1833 cases were is_replaced is checked. */
1836 subst_low_cuid = INSN_CUID (i1);
1837 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1841 subst_low_cuid = INSN_CUID (i2);
1842 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1847 /* Many machines that don't use CC0 have insns that can both perform an
1848 arithmetic operation and set the condition code. These operations will
1849 be represented as a PARALLEL with the first element of the vector
1850 being a COMPARE of an arithmetic operation with the constant zero.
1851 The second element of the vector will set some pseudo to the result
1852 of the same arithmetic operation. If we simplify the COMPARE, we won't
1853 match such a pattern and so will generate an extra insn. Here we test
1854 for this case, where both the comparison and the operation result are
1855 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1856 I2SRC. Later we will make the PARALLEL that contains I2. */
1858 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1859 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1860 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1861 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1863 #ifdef SELECT_CC_MODE
1865 enum machine_mode compare_mode;
1868 newpat = PATTERN (i3);
1869 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1873 #ifdef SELECT_CC_MODE
1874 /* See if a COMPARE with the operand we substituted in should be done
1875 with the mode that is currently being used. If not, do the same
1876 processing we do in `subst' for a SET; namely, if the destination
1877 is used only once, try to replace it with a register of the proper
1878 mode and also replace the COMPARE. */
1879 if (undobuf.other_insn == 0
1880 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1881 &undobuf.other_insn))
1882 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1884 != GET_MODE (SET_DEST (newpat))))
1886 unsigned int regno = REGNO (SET_DEST (newpat));
1887 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1889 if (regno < FIRST_PSEUDO_REGISTER
1890 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1891 && ! REG_USERVAR_P (SET_DEST (newpat))))
1893 if (regno >= FIRST_PSEUDO_REGISTER)
1894 SUBST (regno_reg_rtx[regno], new_dest);
1896 SUBST (SET_DEST (newpat), new_dest);
1897 SUBST (XEXP (*cc_use, 0), new_dest);
1898 SUBST (SET_SRC (newpat),
1899 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1902 undobuf.other_insn = 0;
1909 n_occurrences = 0; /* `subst' counts here */
1911 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1912 need to make a unique copy of I2SRC each time we substitute it
1913 to avoid self-referential rtl. */
1915 subst_low_cuid = INSN_CUID (i2);
1916 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1917 ! i1_feeds_i3 && i1dest_in_i1src);
1920 /* Record whether i2's body now appears within i3's body. */
1921 i2_is_used = n_occurrences;
1924 /* If we already got a failure, don't try to do more. Otherwise,
1925 try to substitute in I1 if we have it. */
1927 if (i1 && GET_CODE (newpat) != CLOBBER)
1929 /* Before we can do this substitution, we must redo the test done
1930 above (see detailed comments there) that ensures that I1DEST
1931 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1933 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1941 subst_low_cuid = INSN_CUID (i1);
1942 newpat = subst (newpat, i1dest, i1src, 0, 0);
1946 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1947 to count all the ways that I2SRC and I1SRC can be used. */
1948 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1949 && i2_is_used + added_sets_2 > 1)
1950 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1951 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1953 /* Fail if we tried to make a new register (we used to abort, but there's
1954 really no reason to). */
1955 || max_reg_num () != maxreg
1956 /* Fail if we couldn't do something and have a CLOBBER. */
1957 || GET_CODE (newpat) == CLOBBER
1958 /* Fail if this new pattern is a MULT and we didn't have one before
1959 at the outer level. */
1960 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1967 /* If the actions of the earlier insns must be kept
1968 in addition to substituting them into the latest one,
1969 we must make a new PARALLEL for the latest insn
1970 to hold additional the SETs. */
1972 if (added_sets_1 || added_sets_2)
1976 if (GET_CODE (newpat) == PARALLEL)
1978 rtvec old = XVEC (newpat, 0);
1979 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1980 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1981 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
1982 sizeof (old->elem[0]) * old->num_elem);
1987 total_sets = 1 + added_sets_1 + added_sets_2;
1988 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1989 XVECEXP (newpat, 0, 0) = old;
1993 XVECEXP (newpat, 0, --total_sets)
1994 = (GET_CODE (PATTERN (i1)) == PARALLEL
1995 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1999 /* If there is no I1, use I2's body as is. We used to also not do
2000 the subst call below if I2 was substituted into I3,
2001 but that could lose a simplification. */
2003 XVECEXP (newpat, 0, --total_sets) = i2pat;
2005 /* See comment where i2pat is assigned. */
2006 XVECEXP (newpat, 0, --total_sets)
2007 = subst (i2pat, i1dest, i1src, 0, 0);
2011 /* We come here when we are replacing a destination in I2 with the
2012 destination of I3. */
2013 validate_replacement:
2015 /* Note which hard regs this insn has as inputs. */
2016 mark_used_regs_combine (newpat);
2018 /* Is the result of combination a valid instruction? */
2019 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2021 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2022 the second SET's destination is a register that is unused and isn't
2023 marked as an instruction that might trap in an EH region. In that case,
2024 we just need the first SET. This can occur when simplifying a divmod
2025 insn. We *must* test for this case here because the code below that
2026 splits two independent SETs doesn't handle this case correctly when it
2027 updates the register status. Also check the case where the first
2028 SET's destination is unused. That would not cause incorrect code, but
2029 does cause an unneeded insn to remain. */
2031 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2032 && XVECLEN (newpat, 0) == 2
2033 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2034 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2035 && asm_noperands (newpat) < 0)
2037 rtx set0 = XVECEXP (newpat, 0, 0);
2038 rtx set1 = XVECEXP (newpat, 0, 1);
2041 if (((GET_CODE (SET_DEST (set1)) == REG
2042 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2043 || (GET_CODE (SET_DEST (set1)) == SUBREG
2044 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2045 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2046 || INTVAL (XEXP (note, 0)) <= 0)
2047 && ! side_effects_p (SET_SRC (set1)))
2050 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2053 else if (((GET_CODE (SET_DEST (set0)) == REG
2054 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2055 || (GET_CODE (SET_DEST (set0)) == SUBREG
2056 && find_reg_note (i3, REG_UNUSED,
2057 SUBREG_REG (SET_DEST (set0)))))
2058 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2059 || INTVAL (XEXP (note, 0)) <= 0)
2060 && ! side_effects_p (SET_SRC (set0)))
2063 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2065 if (insn_code_number >= 0)
2067 /* If we will be able to accept this, we have made a
2068 change to the destination of I3. This requires us to
2069 do a few adjustments. */
2071 PATTERN (i3) = newpat;
2072 adjust_for_new_dest (i3);
2077 /* If we were combining three insns and the result is a simple SET
2078 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2079 insns. There are two ways to do this. It can be split using a
2080 machine-specific method (like when you have an addition of a large
2081 constant) or by combine in the function find_split_point. */
2083 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2084 && asm_noperands (newpat) < 0)
2086 rtx m_split, *split;
2087 rtx ni2dest = i2dest;
2089 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2090 use I2DEST as a scratch register will help. In the latter case,
2091 convert I2DEST to the mode of the source of NEWPAT if we can. */
2093 m_split = split_insns (newpat, i3);
2095 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2096 inputs of NEWPAT. */
2098 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2099 possible to try that as a scratch reg. This would require adding
2100 more code to make it work though. */
2102 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2104 /* If I2DEST is a hard register or the only use of a pseudo,
2105 we can change its mode. */
2106 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2107 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2108 && GET_CODE (i2dest) == REG
2109 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2110 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2111 && ! REG_USERVAR_P (i2dest))))
2112 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2115 m_split = split_insns (gen_rtx_PARALLEL
2117 gen_rtvec (2, newpat,
2118 gen_rtx_CLOBBER (VOIDmode,
2121 /* If the split with the mode-changed register didn't work, try
2122 the original register. */
2123 if (! m_split && ni2dest != i2dest)
2126 m_split = split_insns (gen_rtx_PARALLEL
2128 gen_rtvec (2, newpat,
2129 gen_rtx_CLOBBER (VOIDmode,
2135 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2137 m_split = PATTERN (m_split);
2138 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2139 if (insn_code_number >= 0)
2142 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2143 && (next_real_insn (i2) == i3
2144 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2147 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2148 newi2pat = PATTERN (m_split);
2150 i3set = single_set (NEXT_INSN (m_split));
2151 i2set = single_set (m_split);
2153 /* In case we changed the mode of I2DEST, replace it in the
2154 pseudo-register table here. We can't do it above in case this
2155 code doesn't get executed and we do a split the other way. */
2157 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2158 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2160 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2162 /* If I2 or I3 has multiple SETs, we won't know how to track
2163 register status, so don't use these insns. If I2's destination
2164 is used between I2 and I3, we also can't use these insns. */
2166 if (i2_code_number >= 0 && i2set && i3set
2167 && (next_real_insn (i2) == i3
2168 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2169 insn_code_number = recog_for_combine (&newi3pat, i3,
2171 if (insn_code_number >= 0)
2174 /* It is possible that both insns now set the destination of I3.
2175 If so, we must show an extra use of it. */
2177 if (insn_code_number >= 0)
2179 rtx new_i3_dest = SET_DEST (i3set);
2180 rtx new_i2_dest = SET_DEST (i2set);
2182 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2183 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2184 || GET_CODE (new_i3_dest) == SUBREG)
2185 new_i3_dest = XEXP (new_i3_dest, 0);
2187 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2188 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2189 || GET_CODE (new_i2_dest) == SUBREG)
2190 new_i2_dest = XEXP (new_i2_dest, 0);
2192 if (GET_CODE (new_i3_dest) == REG
2193 && GET_CODE (new_i2_dest) == REG
2194 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2195 REG_N_SETS (REGNO (new_i2_dest))++;
2199 /* If we can split it and use I2DEST, go ahead and see if that
2200 helps things be recognized. Verify that none of the registers
2201 are set between I2 and I3. */
2202 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2204 && GET_CODE (i2dest) == REG
2206 /* We need I2DEST in the proper mode. If it is a hard register
2207 or the only use of a pseudo, we can change its mode. */
2208 && (GET_MODE (*split) == GET_MODE (i2dest)
2209 || GET_MODE (*split) == VOIDmode
2210 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2211 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2212 && ! REG_USERVAR_P (i2dest)))
2213 && (next_real_insn (i2) == i3
2214 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2215 /* We can't overwrite I2DEST if its value is still used by
2217 && ! reg_referenced_p (i2dest, newpat))
2219 rtx newdest = i2dest;
2220 enum rtx_code split_code = GET_CODE (*split);
2221 enum machine_mode split_mode = GET_MODE (*split);
2223 /* Get NEWDEST as a register in the proper mode. We have already
2224 validated that we can do this. */
2225 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2227 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2229 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2230 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2233 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2234 an ASHIFT. This can occur if it was inside a PLUS and hence
2235 appeared to be a memory address. This is a kludge. */
2236 if (split_code == MULT
2237 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2238 && INTVAL (XEXP (*split, 1)) > 0
2239 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2241 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2242 XEXP (*split, 0), GEN_INT (i)));
2243 /* Update split_code because we may not have a multiply
2245 split_code = GET_CODE (*split);
2248 #ifdef INSN_SCHEDULING
2249 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2250 be written as a ZERO_EXTEND. */
2251 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2253 #ifdef LOAD_EXTEND_OP
2254 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2255 what it really is. */
2256 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2258 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2259 SUBREG_REG (*split)));
2262 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2263 SUBREG_REG (*split)));
2267 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2268 SUBST (*split, newdest);
2269 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2271 /* If the split point was a MULT and we didn't have one before,
2272 don't use one now. */
2273 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2274 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2278 /* Check for a case where we loaded from memory in a narrow mode and
2279 then sign extended it, but we need both registers. In that case,
2280 we have a PARALLEL with both loads from the same memory location.
2281 We can split this into a load from memory followed by a register-register
2282 copy. This saves at least one insn, more if register allocation can
2285 We cannot do this if the destination of the first assignment is a
2286 condition code register or cc0. We eliminate this case by making sure
2287 the SET_DEST and SET_SRC have the same mode.
2289 We cannot do this if the destination of the second assignment is
2290 a register that we have already assumed is zero-extended. Similarly
2291 for a SUBREG of such a register. */
2293 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2294 && GET_CODE (newpat) == PARALLEL
2295 && XVECLEN (newpat, 0) == 2
2296 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2297 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2298 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2299 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2300 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2301 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2302 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2303 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2305 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2306 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2307 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2308 (GET_CODE (temp) == REG
2309 && reg_nonzero_bits[REGNO (temp)] != 0
2310 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2311 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2312 && (reg_nonzero_bits[REGNO (temp)]
2313 != GET_MODE_MASK (word_mode))))
2314 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2315 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2316 (GET_CODE (temp) == REG
2317 && reg_nonzero_bits[REGNO (temp)] != 0
2318 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2319 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2320 && (reg_nonzero_bits[REGNO (temp)]
2321 != GET_MODE_MASK (word_mode)))))
2322 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2323 SET_SRC (XVECEXP (newpat, 0, 1)))
2324 && ! find_reg_note (i3, REG_UNUSED,
2325 SET_DEST (XVECEXP (newpat, 0, 0))))
2329 newi2pat = XVECEXP (newpat, 0, 0);
2330 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2331 newpat = XVECEXP (newpat, 0, 1);
2332 SUBST (SET_SRC (newpat),
2333 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2334 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2336 if (i2_code_number >= 0)
2337 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2339 if (insn_code_number >= 0)
2344 /* If we will be able to accept this, we have made a change to the
2345 destination of I3. This requires us to do a few adjustments. */
2346 PATTERN (i3) = newpat;
2347 adjust_for_new_dest (i3);
2349 /* I3 now uses what used to be its destination and which is
2350 now I2's destination. That means we need a LOG_LINK from
2351 I3 to I2. But we used to have one, so we still will.
2353 However, some later insn might be using I2's dest and have
2354 a LOG_LINK pointing at I3. We must remove this link.
2355 The simplest way to remove the link is to point it at I1,
2356 which we know will be a NOTE. */
2358 for (insn = NEXT_INSN (i3);
2359 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2360 || insn != BB_HEAD (this_basic_block->next_bb));
2361 insn = NEXT_INSN (insn))
2363 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2365 for (link = LOG_LINKS (insn); link;
2366 link = XEXP (link, 1))
2367 if (XEXP (link, 0) == i3)
2368 XEXP (link, 0) = i1;
2376 /* Similarly, check for a case where we have a PARALLEL of two independent
2377 SETs but we started with three insns. In this case, we can do the sets
2378 as two separate insns. This case occurs when some SET allows two
2379 other insns to combine, but the destination of that SET is still live. */
2381 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2382 && GET_CODE (newpat) == PARALLEL
2383 && XVECLEN (newpat, 0) == 2
2384 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2385 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2386 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2387 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2388 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2389 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2390 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2392 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2393 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2394 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2395 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2396 XVECEXP (newpat, 0, 0))
2397 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2398 XVECEXP (newpat, 0, 1))
2399 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2400 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2402 /* Normally, it doesn't matter which of the two is done first,
2403 but it does if one references cc0. In that case, it has to
2406 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2408 newi2pat = XVECEXP (newpat, 0, 0);
2409 newpat = XVECEXP (newpat, 0, 1);
2414 newi2pat = XVECEXP (newpat, 0, 1);
2415 newpat = XVECEXP (newpat, 0, 0);
2418 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2420 if (i2_code_number >= 0)
2421 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2424 /* If it still isn't recognized, fail and change things back the way they
2426 if ((insn_code_number < 0
2427 /* Is the result a reasonable ASM_OPERANDS? */
2428 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2434 /* If we had to change another insn, make sure it is valid also. */
2435 if (undobuf.other_insn)
2437 rtx other_pat = PATTERN (undobuf.other_insn);
2438 rtx new_other_notes;
2441 CLEAR_HARD_REG_SET (newpat_used_regs);
2443 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2446 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2452 PATTERN (undobuf.other_insn) = other_pat;
2454 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2455 are still valid. Then add any non-duplicate notes added by
2456 recog_for_combine. */
2457 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2459 next = XEXP (note, 1);
2461 if (REG_NOTE_KIND (note) == REG_UNUSED
2462 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2464 if (GET_CODE (XEXP (note, 0)) == REG)
2465 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2467 remove_note (undobuf.other_insn, note);
2471 for (note = new_other_notes; note; note = XEXP (note, 1))
2472 if (GET_CODE (XEXP (note, 0)) == REG)
2473 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2475 distribute_notes (new_other_notes, undobuf.other_insn,
2476 undobuf.other_insn, NULL_RTX);
2479 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2480 they are adjacent to each other or not. */
2482 rtx p = prev_nonnote_insn (i3);
2483 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2484 && sets_cc0_p (newi2pat))
2492 /* We now know that we can do this combination. Merge the insns and
2493 update the status of registers and LOG_LINKS. */
2496 rtx i3notes, i2notes, i1notes = 0;
2497 rtx i3links, i2links, i1links = 0;
2501 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2503 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2504 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2506 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2508 /* Ensure that we do not have something that should not be shared but
2509 occurs multiple times in the new insns. Check this by first
2510 resetting all the `used' flags and then copying anything is shared. */
2512 reset_used_flags (i3notes);
2513 reset_used_flags (i2notes);
2514 reset_used_flags (i1notes);
2515 reset_used_flags (newpat);
2516 reset_used_flags (newi2pat);
2517 if (undobuf.other_insn)
2518 reset_used_flags (PATTERN (undobuf.other_insn));
2520 i3notes = copy_rtx_if_shared (i3notes);
2521 i2notes = copy_rtx_if_shared (i2notes);
2522 i1notes = copy_rtx_if_shared (i1notes);
2523 newpat = copy_rtx_if_shared (newpat);
2524 newi2pat = copy_rtx_if_shared (newi2pat);
2525 if (undobuf.other_insn)
2526 reset_used_flags (PATTERN (undobuf.other_insn));
2528 INSN_CODE (i3) = insn_code_number;
2529 PATTERN (i3) = newpat;
2531 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2533 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2535 reset_used_flags (call_usage);
2536 call_usage = copy_rtx (call_usage);
2539 replace_rtx (call_usage, i2dest, i2src);
2542 replace_rtx (call_usage, i1dest, i1src);
2544 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2547 if (undobuf.other_insn)
2548 INSN_CODE (undobuf.other_insn) = other_code_number;
2550 /* We had one special case above where I2 had more than one set and
2551 we replaced a destination of one of those sets with the destination
2552 of I3. In that case, we have to update LOG_LINKS of insns later
2553 in this basic block. Note that this (expensive) case is rare.
2555 Also, in this case, we must pretend that all REG_NOTEs for I2
2556 actually came from I3, so that REG_UNUSED notes from I2 will be
2557 properly handled. */
2559 if (i3_subst_into_i2)
2561 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2562 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2563 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2564 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2565 && ! find_reg_note (i2, REG_UNUSED,
2566 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2567 for (temp = NEXT_INSN (i2);
2568 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2569 || BB_HEAD (this_basic_block) != temp);
2570 temp = NEXT_INSN (temp))
2571 if (temp != i3 && INSN_P (temp))
2572 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2573 if (XEXP (link, 0) == i2)
2574 XEXP (link, 0) = i3;
2579 while (XEXP (link, 1))
2580 link = XEXP (link, 1);
2581 XEXP (link, 1) = i2notes;
2595 INSN_CODE (i2) = i2_code_number;
2596 PATTERN (i2) = newi2pat;
2600 PUT_CODE (i2, NOTE);
2601 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2602 NOTE_SOURCE_FILE (i2) = 0;
2609 PUT_CODE (i1, NOTE);
2610 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2611 NOTE_SOURCE_FILE (i1) = 0;
2614 /* Get death notes for everything that is now used in either I3 or
2615 I2 and used to die in a previous insn. If we built two new
2616 patterns, move from I1 to I2 then I2 to I3 so that we get the
2617 proper movement on registers that I2 modifies. */
2621 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2622 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2625 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2628 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2630 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2632 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2634 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2636 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2638 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2639 know these are REG_UNUSED and want them to go to the desired insn,
2640 so we always pass it as i3. We have not counted the notes in
2641 reg_n_deaths yet, so we need to do so now. */
2643 if (newi2pat && new_i2_notes)
2645 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2646 if (GET_CODE (XEXP (temp, 0)) == REG)
2647 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2649 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2654 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2655 if (GET_CODE (XEXP (temp, 0)) == REG)
2656 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2658 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2661 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2662 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2663 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2664 in that case, it might delete I2. Similarly for I2 and I1.
2665 Show an additional death due to the REG_DEAD note we make here. If
2666 we discard it in distribute_notes, we will decrement it again. */
2670 if (GET_CODE (i3dest_killed) == REG)
2671 REG_N_DEATHS (REGNO (i3dest_killed))++;
2673 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2674 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2676 NULL_RTX, i2, NULL_RTX);
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2680 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2683 if (i2dest_in_i2src)
2685 if (GET_CODE (i2dest) == REG)
2686 REG_N_DEATHS (REGNO (i2dest))++;
2688 if (newi2pat && reg_set_p (i2dest, newi2pat))
2689 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2690 NULL_RTX, i2, NULL_RTX);
2692 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2693 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2696 if (i1dest_in_i1src)
2698 if (GET_CODE (i1dest) == REG)
2699 REG_N_DEATHS (REGNO (i1dest))++;
2701 if (newi2pat && reg_set_p (i1dest, newi2pat))
2702 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2703 NULL_RTX, i2, NULL_RTX);
2705 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2706 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2709 distribute_links (i3links);
2710 distribute_links (i2links);
2711 distribute_links (i1links);
2713 if (GET_CODE (i2dest) == REG)
2716 rtx i2_insn = 0, i2_val = 0, set;
2718 /* The insn that used to set this register doesn't exist, and
2719 this life of the register may not exist either. See if one of
2720 I3's links points to an insn that sets I2DEST. If it does,
2721 that is now the last known value for I2DEST. If we don't update
2722 this and I2 set the register to a value that depended on its old
2723 contents, we will get confused. If this insn is used, thing
2724 will be set correctly in combine_instructions. */
2726 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2727 if ((set = single_set (XEXP (link, 0))) != 0
2728 && rtx_equal_p (i2dest, SET_DEST (set)))
2729 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2731 record_value_for_reg (i2dest, i2_insn, i2_val);
2733 /* If the reg formerly set in I2 died only once and that was in I3,
2734 zero its use count so it won't make `reload' do any work. */
2736 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2737 && ! i2dest_in_i2src)
2739 regno = REGNO (i2dest);
2740 REG_N_SETS (regno)--;
2744 if (i1 && GET_CODE (i1dest) == REG)
2747 rtx i1_insn = 0, i1_val = 0, set;
2749 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2750 if ((set = single_set (XEXP (link, 0))) != 0
2751 && rtx_equal_p (i1dest, SET_DEST (set)))
2752 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2754 record_value_for_reg (i1dest, i1_insn, i1_val);
2756 regno = REGNO (i1dest);
2757 if (! added_sets_1 && ! i1dest_in_i1src)
2758 REG_N_SETS (regno)--;
2761 /* Update reg_nonzero_bits et al for any changes that may have been made
2762 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2763 important. Because newi2pat can affect nonzero_bits of newpat */
2765 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2766 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2768 /* Set new_direct_jump_p if a new return or simple jump instruction
2771 If I3 is now an unconditional jump, ensure that it has a
2772 BARRIER following it since it may have initially been a
2773 conditional jump. It may also be the last nonnote insn. */
2775 if (returnjump_p (i3) || any_uncondjump_p (i3))
2777 *new_direct_jump_p = 1;
2778 mark_jump_label (PATTERN (i3), i3, 0);
2780 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2781 || GET_CODE (temp) != BARRIER)
2782 emit_barrier_after (i3);
2785 if (undobuf.other_insn != NULL_RTX
2786 && (returnjump_p (undobuf.other_insn)
2787 || any_uncondjump_p (undobuf.other_insn)))
2789 *new_direct_jump_p = 1;
2791 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2792 || GET_CODE (temp) != BARRIER)
2793 emit_barrier_after (undobuf.other_insn);
2796 /* An NOOP jump does not need barrier, but it does need cleaning up
2798 if (GET_CODE (newpat) == SET
2799 && SET_SRC (newpat) == pc_rtx
2800 && SET_DEST (newpat) == pc_rtx)
2801 *new_direct_jump_p = 1;
2804 combine_successes++;
2807 if (added_links_insn
2808 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2809 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2810 return added_links_insn;
2812 return newi2pat ? i2 : i3;
2815 /* Undo all the modifications recorded in undobuf. */
2820 struct undo *undo, *next;
2822 for (undo = undobuf.undos; undo; undo = next)
2826 *undo->where.i = undo->old_contents.i;
2828 *undo->where.r = undo->old_contents.r;
2830 undo->next = undobuf.frees;
2831 undobuf.frees = undo;
2837 /* We've committed to accepting the changes we made. Move all
2838 of the undos to the free list. */
2843 struct undo *undo, *next;
2845 for (undo = undobuf.undos; undo; undo = next)
2848 undo->next = undobuf.frees;
2849 undobuf.frees = undo;
2855 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2856 where we have an arithmetic expression and return that point. LOC will
2859 try_combine will call this function to see if an insn can be split into
2863 find_split_point (rtx *loc, rtx insn)
2866 enum rtx_code code = GET_CODE (x);
2868 unsigned HOST_WIDE_INT len = 0;
2869 HOST_WIDE_INT pos = 0;
2871 rtx inner = NULL_RTX;
2873 /* First special-case some codes. */
2877 #ifdef INSN_SCHEDULING
2878 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2880 if (GET_CODE (SUBREG_REG (x)) == MEM)
2883 return find_split_point (&SUBREG_REG (x), insn);
2887 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2888 using LO_SUM and HIGH. */
2889 if (GET_CODE (XEXP (x, 0)) == CONST
2890 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2893 gen_rtx_LO_SUM (Pmode,
2894 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2896 return &XEXP (XEXP (x, 0), 0);
2900 /* If we have a PLUS whose second operand is a constant and the
2901 address is not valid, perhaps will can split it up using
2902 the machine-specific way to split large constants. We use
2903 the first pseudo-reg (one of the virtual regs) as a placeholder;
2904 it will not remain in the result. */
2905 if (GET_CODE (XEXP (x, 0)) == PLUS
2906 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2907 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2909 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2910 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2913 /* This should have produced two insns, each of which sets our
2914 placeholder. If the source of the second is a valid address,
2915 we can make put both sources together and make a split point
2919 && NEXT_INSN (seq) != NULL_RTX
2920 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2921 && GET_CODE (seq) == INSN
2922 && GET_CODE (PATTERN (seq)) == SET
2923 && SET_DEST (PATTERN (seq)) == reg
2924 && ! reg_mentioned_p (reg,
2925 SET_SRC (PATTERN (seq)))
2926 && GET_CODE (NEXT_INSN (seq)) == INSN
2927 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2928 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2929 && memory_address_p (GET_MODE (x),
2930 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2932 rtx src1 = SET_SRC (PATTERN (seq));
2933 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2935 /* Replace the placeholder in SRC2 with SRC1. If we can
2936 find where in SRC2 it was placed, that can become our
2937 split point and we can replace this address with SRC2.
2938 Just try two obvious places. */
2940 src2 = replace_rtx (src2, reg, src1);
2942 if (XEXP (src2, 0) == src1)
2943 split = &XEXP (src2, 0);
2944 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2945 && XEXP (XEXP (src2, 0), 0) == src1)
2946 split = &XEXP (XEXP (src2, 0), 0);
2950 SUBST (XEXP (x, 0), src2);
2955 /* If that didn't work, perhaps the first operand is complex and
2956 needs to be computed separately, so make a split point there.
2957 This will occur on machines that just support REG + CONST
2958 and have a constant moved through some previous computation. */
2960 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2961 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2962 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2964 return &XEXP (XEXP (x, 0), 0);
2970 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2971 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2972 we need to put the operand into a register. So split at that
2975 if (SET_DEST (x) == cc0_rtx
2976 && GET_CODE (SET_SRC (x)) != COMPARE
2977 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2978 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2979 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2980 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2981 return &SET_SRC (x);
2984 /* See if we can split SET_SRC as it stands. */
2985 split = find_split_point (&SET_SRC (x), insn);
2986 if (split && split != &SET_SRC (x))
2989 /* See if we can split SET_DEST as it stands. */
2990 split = find_split_point (&SET_DEST (x), insn);
2991 if (split && split != &SET_DEST (x))
2994 /* See if this is a bitfield assignment with everything constant. If
2995 so, this is an IOR of an AND, so split it into that. */
2996 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2997 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2998 <= HOST_BITS_PER_WIDE_INT)
2999 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3000 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3001 && GET_CODE (SET_SRC (x)) == CONST_INT
3002 && ((INTVAL (XEXP (SET_DEST (x), 1))
3003 + INTVAL (XEXP (SET_DEST (x), 2)))
3004 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3005 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3007 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3008 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3009 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3010 rtx dest = XEXP (SET_DEST (x), 0);
3011 enum machine_mode mode = GET_MODE (dest);
3012 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3014 if (BITS_BIG_ENDIAN)
3015 pos = GET_MODE_BITSIZE (mode) - len - pos;
3019 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3022 gen_binary (IOR, mode,
3023 gen_binary (AND, mode, dest,
3024 gen_int_mode (~(mask << pos),
3026 GEN_INT (src << pos)));
3028 SUBST (SET_DEST (x), dest);
3030 split = find_split_point (&SET_SRC (x), insn);
3031 if (split && split != &SET_SRC (x))
3035 /* Otherwise, see if this is an operation that we can split into two.
3036 If so, try to split that. */
3037 code = GET_CODE (SET_SRC (x));
3042 /* If we are AND'ing with a large constant that is only a single
3043 bit and the result is only being used in a context where we
3044 need to know if it is zero or nonzero, replace it with a bit
3045 extraction. This will avoid the large constant, which might
3046 have taken more than one insn to make. If the constant were
3047 not a valid argument to the AND but took only one insn to make,
3048 this is no worse, but if it took more than one insn, it will
3051 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3052 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3053 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3054 && GET_CODE (SET_DEST (x)) == REG
3055 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3056 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3057 && XEXP (*split, 0) == SET_DEST (x)
3058 && XEXP (*split, 1) == const0_rtx)
3060 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3061 XEXP (SET_SRC (x), 0),
3062 pos, NULL_RTX, 1, 1, 0, 0);
3063 if (extraction != 0)
3065 SUBST (SET_SRC (x), extraction);
3066 return find_split_point (loc, insn);
3072 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3073 is known to be on, this can be converted into a NEG of a shift. */
3074 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3075 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3076 && 1 <= (pos = exact_log2
3077 (nonzero_bits (XEXP (SET_SRC (x), 0),
3078 GET_MODE (XEXP (SET_SRC (x), 0))))))
3080 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3084 gen_rtx_LSHIFTRT (mode,
3085 XEXP (SET_SRC (x), 0),
3088 split = find_split_point (&SET_SRC (x), insn);
3089 if (split && split != &SET_SRC (x))
3095 inner = XEXP (SET_SRC (x), 0);
3097 /* We can't optimize if either mode is a partial integer
3098 mode as we don't know how many bits are significant
3100 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3101 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3105 len = GET_MODE_BITSIZE (GET_MODE (inner));
3111 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3112 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3114 inner = XEXP (SET_SRC (x), 0);
3115 len = INTVAL (XEXP (SET_SRC (x), 1));
3116 pos = INTVAL (XEXP (SET_SRC (x), 2));
3118 if (BITS_BIG_ENDIAN)
3119 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3120 unsignedp = (code == ZERO_EXTRACT);
3128 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3130 enum machine_mode mode = GET_MODE (SET_SRC (x));
3132 /* For unsigned, we have a choice of a shift followed by an
3133 AND or two shifts. Use two shifts for field sizes where the
3134 constant might be too large. We assume here that we can
3135 always at least get 8-bit constants in an AND insn, which is
3136 true for every current RISC. */
3138 if (unsignedp && len <= 8)
3143 (mode, gen_lowpart_for_combine (mode, inner),
3145 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3147 split = find_split_point (&SET_SRC (x), insn);
3148 if (split && split != &SET_SRC (x))
3155 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3156 gen_rtx_ASHIFT (mode,
3157 gen_lowpart_for_combine (mode, inner),
3158 GEN_INT (GET_MODE_BITSIZE (mode)
3160 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3162 split = find_split_point (&SET_SRC (x), insn);
3163 if (split && split != &SET_SRC (x))
3168 /* See if this is a simple operation with a constant as the second
3169 operand. It might be that this constant is out of range and hence
3170 could be used as a split point. */
3171 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3172 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3173 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3174 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3175 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3176 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3177 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3179 return &XEXP (SET_SRC (x), 1);
3181 /* Finally, see if this is a simple operation with its first operand
3182 not in a register. The operation might require this operand in a
3183 register, so return it as a split point. We can always do this
3184 because if the first operand were another operation, we would have
3185 already found it as a split point. */
3186 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3187 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3188 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3189 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3190 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3191 return &XEXP (SET_SRC (x), 0);
3197 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3198 it is better to write this as (not (ior A B)) so we can split it.
3199 Similarly for IOR. */
3200 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3203 gen_rtx_NOT (GET_MODE (x),
3204 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3206 XEXP (XEXP (x, 0), 0),
3207 XEXP (XEXP (x, 1), 0))));
3208 return find_split_point (loc, insn);
3211 /* Many RISC machines have a large set of logical insns. If the
3212 second operand is a NOT, put it first so we will try to split the
3213 other operand first. */
3214 if (GET_CODE (XEXP (x, 1)) == NOT)
3216 rtx tem = XEXP (x, 0);
3217 SUBST (XEXP (x, 0), XEXP (x, 1));
3218 SUBST (XEXP (x, 1), tem);
3226 /* Otherwise, select our actions depending on our rtx class. */
3227 switch (GET_RTX_CLASS (code))
3229 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3231 split = find_split_point (&XEXP (x, 2), insn);
3234 /* ... fall through ... */
3238 split = find_split_point (&XEXP (x, 1), insn);
3241 /* ... fall through ... */
3243 /* Some machines have (and (shift ...) ...) insns. If X is not
3244 an AND, but XEXP (X, 0) is, use it as our split point. */
3245 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3246 return &XEXP (x, 0);
3248 split = find_split_point (&XEXP (x, 0), insn);
3254 /* Otherwise, we don't have a split point. */
3258 /* Throughout X, replace FROM with TO, and return the result.
3259 The result is TO if X is FROM;
3260 otherwise the result is X, but its contents may have been modified.
3261 If they were modified, a record was made in undobuf so that
3262 undo_all will (among other things) return X to its original state.
3264 If the number of changes necessary is too much to record to undo,
3265 the excess changes are not made, so the result is invalid.
3266 The changes already made can still be undone.
3267 undobuf.num_undo is incremented for such changes, so by testing that
3268 the caller can tell whether the result is valid.
3270 `n_occurrences' is incremented each time FROM is replaced.
3272 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3274 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3275 by copying if `n_occurrences' is nonzero. */
3278 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3280 enum rtx_code code = GET_CODE (x);
3281 enum machine_mode op0_mode = VOIDmode;
3286 /* Two expressions are equal if they are identical copies of a shared
3287 RTX or if they are both registers with the same register number
3290 #define COMBINE_RTX_EQUAL_P(X,Y) \
3292 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3293 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3295 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3298 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3301 /* If X and FROM are the same register but different modes, they will
3302 not have been seen as equal above. However, flow.c will make a
3303 LOG_LINKS entry for that case. If we do nothing, we will try to
3304 rerecognize our original insn and, when it succeeds, we will
3305 delete the feeding insn, which is incorrect.
3307 So force this insn not to match in this (rare) case. */
3308 if (! in_dest && code == REG && GET_CODE (from) == REG
3309 && REGNO (x) == REGNO (from))
3310 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3312 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3313 of which may contain things that can be combined. */
3314 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3317 /* It is possible to have a subexpression appear twice in the insn.
3318 Suppose that FROM is a register that appears within TO.
3319 Then, after that subexpression has been scanned once by `subst',
3320 the second time it is scanned, TO may be found. If we were
3321 to scan TO here, we would find FROM within it and create a
3322 self-referent rtl structure which is completely wrong. */
3323 if (COMBINE_RTX_EQUAL_P (x, to))
3326 /* Parallel asm_operands need special attention because all of the
3327 inputs are shared across the arms. Furthermore, unsharing the
3328 rtl results in recognition failures. Failure to handle this case
3329 specially can result in circular rtl.
3331 Solve this by doing a normal pass across the first entry of the
3332 parallel, and only processing the SET_DESTs of the subsequent
3335 if (code == PARALLEL
3336 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3337 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3339 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3341 /* If this substitution failed, this whole thing fails. */
3342 if (GET_CODE (new) == CLOBBER
3343 && XEXP (new, 0) == const0_rtx)
3346 SUBST (XVECEXP (x, 0, 0), new);
3348 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3350 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3352 if (GET_CODE (dest) != REG
3353 && GET_CODE (dest) != CC0
3354 && GET_CODE (dest) != PC)
3356 new = subst (dest, from, to, 0, unique_copy);
3358 /* If this substitution failed, this whole thing fails. */
3359 if (GET_CODE (new) == CLOBBER
3360 && XEXP (new, 0) == const0_rtx)
3363 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3369 len = GET_RTX_LENGTH (code);
3370 fmt = GET_RTX_FORMAT (code);
3372 /* We don't need to process a SET_DEST that is a register, CC0,
3373 or PC, so set up to skip this common case. All other cases
3374 where we want to suppress replacing something inside a
3375 SET_SRC are handled via the IN_DEST operand. */
3377 && (GET_CODE (SET_DEST (x)) == REG
3378 || GET_CODE (SET_DEST (x)) == CC0
3379 || GET_CODE (SET_DEST (x)) == PC))
3382 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3385 op0_mode = GET_MODE (XEXP (x, 0));
3387 for (i = 0; i < len; i++)
3392 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3394 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3396 new = (unique_copy && n_occurrences
3397 ? copy_rtx (to) : to);
3402 new = subst (XVECEXP (x, i, j), from, to, 0,
3405 /* If this substitution failed, this whole thing
3407 if (GET_CODE (new) == CLOBBER
3408 && XEXP (new, 0) == const0_rtx)
3412 SUBST (XVECEXP (x, i, j), new);
3415 else if (fmt[i] == 'e')
3417 /* If this is a register being set, ignore it. */
3420 && (code == SUBREG || code == STRICT_LOW_PART
3421 || code == ZERO_EXTRACT)
3423 && GET_CODE (new) == REG)
3426 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3428 /* In general, don't install a subreg involving two
3429 modes not tieable. It can worsen register
3430 allocation, and can even make invalid reload
3431 insns, since the reg inside may need to be copied
3432 from in the outside mode, and that may be invalid
3433 if it is an fp reg copied in integer mode.
3435 We allow two exceptions to this: It is valid if
3436 it is inside another SUBREG and the mode of that
3437 SUBREG and the mode of the inside of TO is
3438 tieable and it is valid if X is a SET that copies
3441 if (GET_CODE (to) == SUBREG
3442 && ! MODES_TIEABLE_P (GET_MODE (to),
3443 GET_MODE (SUBREG_REG (to)))
3444 && ! (code == SUBREG
3445 && MODES_TIEABLE_P (GET_MODE (x),
3446 GET_MODE (SUBREG_REG (to))))
3448 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3451 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3453 #ifdef CANNOT_CHANGE_MODE_CLASS
3455 && GET_CODE (to) == REG
3456 && REGNO (to) < FIRST_PSEUDO_REGISTER
3457 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3460 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3463 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3467 /* If we are in a SET_DEST, suppress most cases unless we
3468 have gone inside a MEM, in which case we want to
3469 simplify the address. We assume here that things that
3470 are actually part of the destination have their inner
3471 parts in the first expression. This is true for SUBREG,
3472 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3473 things aside from REG and MEM that should appear in a
3475 new = subst (XEXP (x, i), from, to,
3477 && (code == SUBREG || code == STRICT_LOW_PART
3478 || code == ZERO_EXTRACT))
3480 && i == 0), unique_copy);
3482 /* If we found that we will have to reject this combination,
3483 indicate that by returning the CLOBBER ourselves, rather than
3484 an expression containing it. This will speed things up as
3485 well as prevent accidents where two CLOBBERs are considered
3486 to be equal, thus producing an incorrect simplification. */
3488 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3491 if (GET_CODE (x) == SUBREG
3492 && (GET_CODE (new) == CONST_INT
3493 || GET_CODE (new) == CONST_DOUBLE))
3495 enum machine_mode mode = GET_MODE (x);
3497 x = simplify_subreg (GET_MODE (x), new,
3498 GET_MODE (SUBREG_REG (x)),
3501 x = gen_rtx_CLOBBER (mode, const0_rtx);
3503 else if (GET_CODE (new) == CONST_INT
3504 && GET_CODE (x) == ZERO_EXTEND)
3506 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3507 new, GET_MODE (XEXP (x, 0)));
3512 SUBST (XEXP (x, i), new);
3517 /* Try to simplify X. If the simplification changed the code, it is likely
3518 that further simplification will help, so loop, but limit the number
3519 of repetitions that will be performed. */
3521 for (i = 0; i < 4; i++)
3523 /* If X is sufficiently simple, don't bother trying to do anything
3525 if (code != CONST_INT && code != REG && code != CLOBBER)
3526 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3528 if (GET_CODE (x) == code)
3531 code = GET_CODE (x);
3533 /* We no longer know the original mode of operand 0 since we
3534 have changed the form of X) */
3535 op0_mode = VOIDmode;
3541 /* Simplify X, a piece of RTL. We just operate on the expression at the
3542 outer level; call `subst' to simplify recursively. Return the new
3545 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3546 will be the iteration even if an expression with a code different from
3547 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3550 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int last,
3553 enum rtx_code code = GET_CODE (x);
3554 enum machine_mode mode = GET_MODE (x);
3559 /* If this is a commutative operation, put a constant last and a complex
3560 expression first. We don't need to do this for comparisons here. */
3561 if (GET_RTX_CLASS (code) == 'c'
3562 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3565 SUBST (XEXP (x, 0), XEXP (x, 1));
3566 SUBST (XEXP (x, 1), temp);
3569 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3570 sign extension of a PLUS with a constant, reverse the order of the sign
3571 extension and the addition. Note that this not the same as the original
3572 code, but overflow is undefined for signed values. Also note that the
3573 PLUS will have been partially moved "inside" the sign-extension, so that
3574 the first operand of X will really look like:
3575 (ashiftrt (plus (ashift A C4) C5) C4).
3577 (plus (ashiftrt (ashift A C4) C2) C4)
3578 and replace the first operand of X with that expression. Later parts
3579 of this function may simplify the expression further.
3581 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3582 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3583 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3585 We do this to simplify address expressions. */
3587 if ((code == PLUS || code == MINUS || code == MULT)
3588 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3589 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3590 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3591 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3592 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3593 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3594 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3595 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3596 XEXP (XEXP (XEXP (x, 0), 0), 1),
3597 XEXP (XEXP (x, 0), 1))) != 0)
3600 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3601 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3602 INTVAL (XEXP (XEXP (x, 0), 1)));
3604 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3605 INTVAL (XEXP (XEXP (x, 0), 1)));
3607 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3610 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3611 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3612 things. Check for cases where both arms are testing the same
3615 Don't do anything if all operands are very simple. */
3617 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3618 || GET_RTX_CLASS (code) == '<')
3619 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3620 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3621 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3623 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3624 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3625 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3627 || (GET_RTX_CLASS (code) == '1'
3628 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3629 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3630 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3633 rtx cond, true_rtx, false_rtx;
3635 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3637 /* If everything is a comparison, what we have is highly unlikely
3638 to be simpler, so don't use it. */
3639 && ! (GET_RTX_CLASS (code) == '<'
3640 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3641 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3643 rtx cop1 = const0_rtx;
3644 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3646 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3649 /* Simplify the alternative arms; this may collapse the true and
3650 false arms to store-flag values. Be careful to use copy_rtx
3651 here since true_rtx or false_rtx might share RTL with x as a
3652 result of the if_then_else_cond call above. */
3653 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3654 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3656 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3657 is unlikely to be simpler. */
3658 if (general_operand (true_rtx, VOIDmode)
3659 && general_operand (false_rtx, VOIDmode))
3661 enum rtx_code reversed;
3663 /* Restarting if we generate a store-flag expression will cause
3664 us to loop. Just drop through in this case. */
3666 /* If the result values are STORE_FLAG_VALUE and zero, we can
3667 just make the comparison operation. */
3668 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3669 x = gen_binary (cond_code, mode, cond, cop1);
3670 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3671 && ((reversed = reversed_comparison_code_parts
3672 (cond_code, cond, cop1, NULL))
3674 x = gen_binary (reversed, mode, cond, cop1);
3676 /* Likewise, we can make the negate of a comparison operation
3677 if the result values are - STORE_FLAG_VALUE and zero. */
3678 else if (GET_CODE (true_rtx) == CONST_INT
3679 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3680 && false_rtx == const0_rtx)
3681 x = simplify_gen_unary (NEG, mode,
3682 gen_binary (cond_code, mode, cond,
3685 else if (GET_CODE (false_rtx) == CONST_INT
3686 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3687 && true_rtx == const0_rtx
3688 && ((reversed = reversed_comparison_code_parts
3689 (cond_code, cond, cop1, NULL))
3691 x = simplify_gen_unary (NEG, mode,
3692 gen_binary (reversed, mode,
3696 return gen_rtx_IF_THEN_ELSE (mode,
3697 gen_binary (cond_code, VOIDmode,
3699 true_rtx, false_rtx);
3701 code = GET_CODE (x);
3702 op0_mode = VOIDmode;
3707 /* Try to fold this expression in case we have constants that weren't
3710 switch (GET_RTX_CLASS (code))
3713 if (op0_mode == VOIDmode)
3714 op0_mode = GET_MODE (XEXP (x, 0));
3715 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3718 if (! VECTOR_MODE_P (mode))
3720 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3721 if (cmp_mode == VOIDmode)
3723 cmp_mode = GET_MODE (XEXP (x, 1));
3724 if (cmp_mode == VOIDmode)
3725 cmp_mode = op0_mode;
3727 temp = simplify_relational_operation (code, cmp_mode,
3728 XEXP (x, 0), XEXP (x, 1));
3729 #ifdef FLOAT_STORE_FLAG_VALUE
3730 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3732 if (temp == const0_rtx)
3733 temp = CONST0_RTX (mode);
3735 temp = CONST_DOUBLE_FROM_REAL_VALUE
3736 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3743 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3747 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3748 XEXP (x, 1), XEXP (x, 2));
3755 code = GET_CODE (temp);
3756 op0_mode = VOIDmode;
3757 mode = GET_MODE (temp);
3760 /* First see if we can apply the inverse distributive law. */
3761 if (code == PLUS || code == MINUS
3762 || code == AND || code == IOR || code == XOR)
3764 x = apply_distributive_law (x);
3765 code = GET_CODE (x);
3766 op0_mode = VOIDmode;
3769 /* If CODE is an associative operation not otherwise handled, see if we
3770 can associate some operands. This can win if they are constants or
3771 if they are logically related (i.e. (a & b) & a). */
3772 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3773 || code == AND || code == IOR || code == XOR
3774 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3775 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3776 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3778 if (GET_CODE (XEXP (x, 0)) == code)
3780 rtx other = XEXP (XEXP (x, 0), 0);
3781 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3782 rtx inner_op1 = XEXP (x, 1);
3785 /* Make sure we pass the constant operand if any as the second
3786 one if this is a commutative operation. */
3787 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3789 rtx tem = inner_op0;
3790 inner_op0 = inner_op1;
3793 inner = simplify_binary_operation (code == MINUS ? PLUS
3794 : code == DIV ? MULT
3796 mode, inner_op0, inner_op1);
3798 /* For commutative operations, try the other pair if that one
3800 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3802 other = XEXP (XEXP (x, 0), 1);
3803 inner = simplify_binary_operation (code, mode,
3804 XEXP (XEXP (x, 0), 0),
3809 return gen_binary (code, mode, other, inner);
3813 /* A little bit of algebraic simplification here. */
3817 /* Ensure that our address has any ASHIFTs converted to MULT in case
3818 address-recognizing predicates are called later. */
3819 temp = make_compound_operation (XEXP (x, 0), MEM);
3820 SUBST (XEXP (x, 0), temp);
3824 if (op0_mode == VOIDmode)
3825 op0_mode = GET_MODE (SUBREG_REG (x));
3827 /* simplify_subreg can't use gen_lowpart_for_combine. */
3828 if (CONSTANT_P (SUBREG_REG (x))
3829 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3830 /* Don't call gen_lowpart_for_combine if the inner mode
3831 is VOIDmode and we cannot simplify it, as SUBREG without
3832 inner mode is invalid. */
3833 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3834 || gen_lowpart_common (mode, SUBREG_REG (x))))
3835 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3837 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3841 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3847 /* Don't change the mode of the MEM if that would change the meaning
3849 if (GET_CODE (SUBREG_REG (x)) == MEM
3850 && (MEM_VOLATILE_P (SUBREG_REG (x))
3851 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3852 return gen_rtx_CLOBBER (mode, const0_rtx);
3854 /* Note that we cannot do any narrowing for non-constants since
3855 we might have been counting on using the fact that some bits were
3856 zero. We now do this in the SET. */
3861 if (GET_CODE (XEXP (x, 0)) == SUBREG
3862 && subreg_lowpart_p (XEXP (x, 0))
3863 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3864 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3865 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3866 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3868 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3870 x = gen_rtx_ROTATE (inner_mode,
3871 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3873 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3874 return gen_lowpart_for_combine (mode, x);
3877 /* Apply De Morgan's laws to reduce number of patterns for machines
3878 with negating logical insns (and-not, nand, etc.). If result has
3879 only one NOT, put it first, since that is how the patterns are
3882 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3884 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3885 enum machine_mode op_mode;
3887 op_mode = GET_MODE (in1);
3888 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3890 op_mode = GET_MODE (in2);
3891 if (op_mode == VOIDmode)
3893 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3895 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3898 in2 = in1; in1 = tem;
3901 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3907 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3908 if (GET_CODE (XEXP (x, 0)) == XOR
3909 && XEXP (XEXP (x, 0), 1) == const1_rtx
3910 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3911 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3913 temp = expand_compound_operation (XEXP (x, 0));
3915 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3916 replaced by (lshiftrt X C). This will convert
3917 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3919 if (GET_CODE (temp) == ASHIFTRT
3920 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3921 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3922 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3923 INTVAL (XEXP (temp, 1)));
3925 /* If X has only a single bit that might be nonzero, say, bit I, convert
3926 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3927 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3928 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3929 or a SUBREG of one since we'd be making the expression more
3930 complex if it was just a register. */
3932 if (GET_CODE (temp) != REG
3933 && ! (GET_CODE (temp) == SUBREG
3934 && GET_CODE (SUBREG_REG (temp)) == REG)
3935 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3937 rtx temp1 = simplify_shift_const
3938 (NULL_RTX, ASHIFTRT, mode,
3939 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3940 GET_MODE_BITSIZE (mode) - 1 - i),
3941 GET_MODE_BITSIZE (mode) - 1 - i);
3943 /* If all we did was surround TEMP with the two shifts, we
3944 haven't improved anything, so don't use it. Otherwise,
3945 we are better off with TEMP1. */
3946 if (GET_CODE (temp1) != ASHIFTRT
3947 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3948 || XEXP (XEXP (temp1, 0), 0) != temp)
3954 /* We can't handle truncation to a partial integer mode here
3955 because we don't know the real bitsize of the partial
3957 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3960 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3961 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3962 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3964 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3965 GET_MODE_MASK (mode), NULL_RTX, 0));
3967 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3968 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3969 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3970 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3971 return XEXP (XEXP (x, 0), 0);
3973 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3974 (OP:SI foo:SI) if OP is NEG or ABS. */
3975 if ((GET_CODE (XEXP (x, 0)) == ABS
3976 || GET_CODE (XEXP (x, 0)) == NEG)
3977 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3978 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3979 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3980 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
3981 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
3983 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3985 if (GET_CODE (XEXP (x, 0)) == SUBREG
3986 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3987 && subreg_lowpart_p (XEXP (x, 0)))
3988 return SUBREG_REG (XEXP (x, 0));
3990 /* If we know that the value is already truncated, we can
3991 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3992 is nonzero for the corresponding modes. But don't do this
3993 for an (LSHIFTRT (MULT ...)) since this will cause problems
3994 with the umulXi3_highpart patterns. */
3995 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3996 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3997 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3998 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
3999 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4000 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4001 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4003 /* A truncate of a comparison can be replaced with a subreg if
4004 STORE_FLAG_VALUE permits. This is like the previous test,
4005 but it works even if the comparison is done in a mode larger
4006 than HOST_BITS_PER_WIDE_INT. */
4007 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4008 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4009 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4010 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4012 /* Similarly, a truncate of a register whose value is a
4013 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4015 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4016 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4017 && (temp = get_last_value (XEXP (x, 0)))
4018 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4019 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4023 case FLOAT_TRUNCATE:
4024 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4025 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4026 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4027 return XEXP (XEXP (x, 0), 0);
4029 /* (float_truncate:SF (float_truncate:DF foo:XF))
4030 = (float_truncate:SF foo:XF).
4031 This may eliminate double rounding, so it is unsafe.
4033 (float_truncate:SF (float_extend:XF foo:DF))
4034 = (float_truncate:SF foo:DF).
4036 (float_truncate:DF (float_extend:XF foo:SF))
4037 = (float_extend:SF foo:DF). */
4038 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4039 && flag_unsafe_math_optimizations)
4040 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4041 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4043 > GET_MODE_SIZE (mode)
4044 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4046 XEXP (XEXP (x, 0), 0), mode);
4048 /* (float_truncate (float x)) is (float x) */
4049 if (GET_CODE (XEXP (x, 0)) == FLOAT
4050 && (flag_unsafe_math_optimizations
4051 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4052 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4053 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4054 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4055 return simplify_gen_unary (FLOAT, mode,
4056 XEXP (XEXP (x, 0), 0),
4057 GET_MODE (XEXP (XEXP (x, 0), 0)));
4059 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4060 (OP:SF foo:SF) if OP is NEG or ABS. */
4061 if ((GET_CODE (XEXP (x, 0)) == ABS
4062 || GET_CODE (XEXP (x, 0)) == NEG)
4063 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4064 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4065 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4066 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4068 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4069 is (float_truncate:SF x). */
4070 if (GET_CODE (XEXP (x, 0)) == SUBREG
4071 && subreg_lowpart_p (XEXP (x, 0))
4072 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4073 return SUBREG_REG (XEXP (x, 0));
4076 /* (float_extend (float_extend x)) is (float_extend x)
4078 (float_extend (float x)) is (float x) assuming that double
4079 rounding can't happen.
4081 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4082 || (GET_CODE (XEXP (x, 0)) == FLOAT
4083 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4084 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4085 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4086 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4087 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4088 XEXP (XEXP (x, 0), 0),
4089 GET_MODE (XEXP (XEXP (x, 0), 0)));
4094 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4095 using cc0, in which case we want to leave it as a COMPARE
4096 so we can distinguish it from a register-register-copy. */
4097 if (XEXP (x, 1) == const0_rtx)
4100 /* x - 0 is the same as x unless x's mode has signed zeros and
4101 allows rounding towards -infinity. Under those conditions,
4103 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4104 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4105 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4111 /* (const (const X)) can become (const X). Do it this way rather than
4112 returning the inner CONST since CONST can be shared with a
4114 if (GET_CODE (XEXP (x, 0)) == CONST)
4115 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4120 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4121 can add in an offset. find_split_point will split this address up
4122 again if it doesn't match. */
4123 if (GET_CODE (XEXP (x, 0)) == HIGH
4124 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4130 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4132 if (GET_CODE (XEXP (x, 0)) == MULT
4133 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4137 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4138 in2 = XEXP (XEXP (x, 0), 1);
4139 return gen_binary (MINUS, mode, XEXP (x, 1),
4140 gen_binary (MULT, mode, in1, in2));
4143 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4144 outermost. That's because that's the way indexed addresses are
4145 supposed to appear. This code used to check many more cases, but
4146 they are now checked elsewhere. */
4147 if (GET_CODE (XEXP (x, 0)) == PLUS
4148 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4149 return gen_binary (PLUS, mode,
4150 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4152 XEXP (XEXP (x, 0), 1));
4154 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4155 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4156 bit-field and can be replaced by either a sign_extend or a
4157 sign_extract. The `and' may be a zero_extend and the two
4158 <c>, -<c> constants may be reversed. */
4159 if (GET_CODE (XEXP (x, 0)) == XOR
4160 && GET_CODE (XEXP (x, 1)) == CONST_INT
4161 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4162 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4163 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4164 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4165 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4166 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4167 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4168 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4169 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4170 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4171 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4172 == (unsigned int) i + 1))))
4173 return simplify_shift_const
4174 (NULL_RTX, ASHIFTRT, mode,
4175 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4176 XEXP (XEXP (XEXP (x, 0), 0), 0),
4177 GET_MODE_BITSIZE (mode) - (i + 1)),
4178 GET_MODE_BITSIZE (mode) - (i + 1));
4180 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4181 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4182 is 1. This produces better code than the alternative immediately
4184 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4185 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4186 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4187 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4188 XEXP (XEXP (x, 0), 0),
4189 XEXP (XEXP (x, 0), 1))))
4191 simplify_gen_unary (NEG, mode, reversed, mode);
4193 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4194 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4195 the bitsize of the mode - 1. This allows simplification of
4196 "a = (b & 8) == 0;" */
4197 if (XEXP (x, 1) == constm1_rtx
4198 && GET_CODE (XEXP (x, 0)) != REG
4199 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4200 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4201 && nonzero_bits (XEXP (x, 0), mode) == 1)
4202 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4203 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4204 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4205 GET_MODE_BITSIZE (mode) - 1),
4206 GET_MODE_BITSIZE (mode) - 1);
4208 /* If we are adding two things that have no bits in common, convert
4209 the addition into an IOR. This will often be further simplified,
4210 for example in cases like ((a & 1) + (a & 2)), which can
4213 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4214 && (nonzero_bits (XEXP (x, 0), mode)
4215 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4217 /* Try to simplify the expression further. */
4218 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4219 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4221 /* If we could, great. If not, do not go ahead with the IOR
4222 replacement, since PLUS appears in many special purpose
4223 address arithmetic instructions. */
4224 if (GET_CODE (temp) != CLOBBER && temp != tor)
4230 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4231 by reversing the comparison code if valid. */
4232 if (STORE_FLAG_VALUE == 1
4233 && XEXP (x, 0) == const1_rtx
4234 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4235 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4236 XEXP (XEXP (x, 1), 0),
4237 XEXP (XEXP (x, 1), 1))))
4240 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4241 (and <foo> (const_int pow2-1)) */
4242 if (GET_CODE (XEXP (x, 1)) == AND
4243 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4244 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4245 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4246 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4247 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4249 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4251 if (GET_CODE (XEXP (x, 1)) == MULT
4252 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4256 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4257 in2 = XEXP (XEXP (x, 1), 1);
4258 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4262 /* Canonicalize (minus (neg A) (mult B C)) to
4263 (minus (mult (neg B) C) A). */
4264 if (GET_CODE (XEXP (x, 1)) == MULT
4265 && GET_CODE (XEXP (x, 0)) == NEG)
4269 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4270 in2 = XEXP (XEXP (x, 1), 1);
4271 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4272 XEXP (XEXP (x, 0), 0));
4275 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4277 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4278 return gen_binary (MINUS, mode,
4279 gen_binary (MINUS, mode, XEXP (x, 0),
4280 XEXP (XEXP (x, 1), 0)),
4281 XEXP (XEXP (x, 1), 1));
4285 /* If we have (mult (plus A B) C), apply the distributive law and then
4286 the inverse distributive law to see if things simplify. This
4287 occurs mostly in addresses, often when unrolling loops. */
4289 if (GET_CODE (XEXP (x, 0)) == PLUS)
4291 x = apply_distributive_law
4292 (gen_binary (PLUS, mode,
4293 gen_binary (MULT, mode,
4294 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4295 gen_binary (MULT, mode,
4296 XEXP (XEXP (x, 0), 1),
4297 copy_rtx (XEXP (x, 1)))));
4299 if (GET_CODE (x) != MULT)
4302 /* Try simplify a*(b/c) as (a*b)/c. */
4303 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4304 && GET_CODE (XEXP (x, 0)) == DIV)
4306 rtx tem = simplify_binary_operation (MULT, mode,
4307 XEXP (XEXP (x, 0), 0),
4310 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4315 /* If this is a divide by a power of two, treat it as a shift if
4316 its first operand is a shift. */
4317 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4318 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4319 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4320 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4321 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4322 || GET_CODE (XEXP (x, 0)) == ROTATE
4323 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4324 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4328 case GT: case GTU: case GE: case GEU:
4329 case LT: case LTU: case LE: case LEU:
4330 case UNEQ: case LTGT:
4331 case UNGT: case UNGE:
4332 case UNLT: case UNLE:
4333 case UNORDERED: case ORDERED:
4334 /* If the first operand is a condition code, we can't do anything
4336 if (GET_CODE (XEXP (x, 0)) == COMPARE
4337 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4338 && ! CC0_P (XEXP (x, 0))))
4340 rtx op0 = XEXP (x, 0);
4341 rtx op1 = XEXP (x, 1);
4342 enum rtx_code new_code;
4344 if (GET_CODE (op0) == COMPARE)
4345 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4347 /* Simplify our comparison, if possible. */
4348 new_code = simplify_comparison (code, &op0, &op1);
4350 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4351 if only the low-order bit is possibly nonzero in X (such as when
4352 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4353 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4354 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4357 Remove any ZERO_EXTRACT we made when thinking this was a
4358 comparison. It may now be simpler to use, e.g., an AND. If a
4359 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4360 the call to make_compound_operation in the SET case. */
4362 if (STORE_FLAG_VALUE == 1
4363 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4364 && op1 == const0_rtx
4365 && mode == GET_MODE (op0)
4366 && nonzero_bits (op0, mode) == 1)
4367 return gen_lowpart_for_combine (mode,
4368 expand_compound_operation (op0));
4370 else if (STORE_FLAG_VALUE == 1
4371 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4372 && op1 == const0_rtx
4373 && mode == GET_MODE (op0)
4374 && (num_sign_bit_copies (op0, mode)
4375 == GET_MODE_BITSIZE (mode)))
4377 op0 = expand_compound_operation (op0);
4378 return simplify_gen_unary (NEG, mode,
4379 gen_lowpart_for_combine (mode, op0),
4383 else if (STORE_FLAG_VALUE == 1
4384 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4385 && op1 == const0_rtx
4386 && mode == GET_MODE (op0)
4387 && nonzero_bits (op0, mode) == 1)
4389 op0 = expand_compound_operation (op0);
4390 return gen_binary (XOR, mode,
4391 gen_lowpart_for_combine (mode, op0),
4395 else if (STORE_FLAG_VALUE == 1
4396 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4397 && op1 == const0_rtx
4398 && mode == GET_MODE (op0)
4399 && (num_sign_bit_copies (op0, mode)
4400 == GET_MODE_BITSIZE (mode)))
4402 op0 = expand_compound_operation (op0);
4403 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4406 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4408 if (STORE_FLAG_VALUE == -1
4409 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4410 && op1 == const0_rtx
4411 && (num_sign_bit_copies (op0, mode)
4412 == GET_MODE_BITSIZE (mode)))
4413 return gen_lowpart_for_combine (mode,
4414 expand_compound_operation (op0));
4416 else if (STORE_FLAG_VALUE == -1
4417 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4418 && op1 == const0_rtx
4419 && mode == GET_MODE (op0)
4420 && nonzero_bits (op0, mode) == 1)
4422 op0 = expand_compound_operation (op0);
4423 return simplify_gen_unary (NEG, mode,
4424 gen_lowpart_for_combine (mode, op0),
4428 else if (STORE_FLAG_VALUE == -1
4429 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4430 && op1 == const0_rtx
4431 && mode == GET_MODE (op0)
4432 && (num_sign_bit_copies (op0, mode)
4433 == GET_MODE_BITSIZE (mode)))
4435 op0 = expand_compound_operation (op0);
4436 return simplify_gen_unary (NOT, mode,
4437 gen_lowpart_for_combine (mode, op0),
4441 /* If X is 0/1, (eq X 0) is X-1. */
4442 else if (STORE_FLAG_VALUE == -1
4443 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4444 && op1 == const0_rtx
4445 && mode == GET_MODE (op0)
4446 && nonzero_bits (op0, mode) == 1)
4448 op0 = expand_compound_operation (op0);
4449 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4452 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4453 one bit that might be nonzero, we can convert (ne x 0) to
4454 (ashift x c) where C puts the bit in the sign bit. Remove any
4455 AND with STORE_FLAG_VALUE when we are done, since we are only
4456 going to test the sign bit. */
4457 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4458 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4459 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4460 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4461 && op1 == const0_rtx
4462 && mode == GET_MODE (op0)
4463 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4465 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4466 expand_compound_operation (op0),
4467 GET_MODE_BITSIZE (mode) - 1 - i);
4468 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4474 /* If the code changed, return a whole new comparison. */
4475 if (new_code != code)
4476 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4478 /* Otherwise, keep this operation, but maybe change its operands.
4479 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4480 SUBST (XEXP (x, 0), op0);
4481 SUBST (XEXP (x, 1), op1);
4486 return simplify_if_then_else (x);
4492 /* If we are processing SET_DEST, we are done. */
4496 return expand_compound_operation (x);
4499 return simplify_set (x);
4504 return simplify_logical (x, last);
4507 /* (abs (neg <foo>)) -> (abs <foo>) */
4508 if (GET_CODE (XEXP (x, 0)) == NEG)
4509 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4511 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4513 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4516 /* If operand is something known to be positive, ignore the ABS. */
4517 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4518 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4519 <= HOST_BITS_PER_WIDE_INT)
4520 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4521 & ((HOST_WIDE_INT) 1
4522 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4526 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4527 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4528 return gen_rtx_NEG (mode, XEXP (x, 0));
4533 /* (ffs (*_extend <X>)) = (ffs <X>) */
4534 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4535 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4536 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4541 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4542 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4543 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4547 /* (float (sign_extend <X>)) = (float <X>). */
4548 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4549 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4557 /* If this is a shift by a constant amount, simplify it. */
4558 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4559 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4560 INTVAL (XEXP (x, 1)));
4562 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4564 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4566 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4573 rtx op0 = XEXP (x, 0);
4574 rtx op1 = XEXP (x, 1);
4577 if (GET_CODE (op1) != PARALLEL)
4579 len = XVECLEN (op1, 0);
4581 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4582 && GET_CODE (op0) == VEC_CONCAT)
4584 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4586 /* Try to find the element in the VEC_CONCAT. */
4589 if (GET_MODE (op0) == GET_MODE (x))
4591 if (GET_CODE (op0) == VEC_CONCAT)
4593 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4594 if (op0_size < offset)
4595 op0 = XEXP (op0, 0);
4599 op0 = XEXP (op0, 1);
4617 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4620 simplify_if_then_else (rtx x)
4622 enum machine_mode mode = GET_MODE (x);
4623 rtx cond = XEXP (x, 0);
4624 rtx true_rtx = XEXP (x, 1);
4625 rtx false_rtx = XEXP (x, 2);
4626 enum rtx_code true_code = GET_CODE (cond);
4627 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4630 enum rtx_code false_code;
4633 /* Simplify storing of the truth value. */
4634 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4635 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4637 /* Also when the truth value has to be reversed. */
4639 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4640 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4644 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4645 in it is being compared against certain values. Get the true and false
4646 comparisons and see if that says anything about the value of each arm. */
4649 && ((false_code = combine_reversed_comparison_code (cond))
4651 && GET_CODE (XEXP (cond, 0)) == REG)
4654 rtx from = XEXP (cond, 0);
4655 rtx true_val = XEXP (cond, 1);
4656 rtx false_val = true_val;
4659 /* If FALSE_CODE is EQ, swap the codes and arms. */
4661 if (false_code == EQ)
4663 swapped = 1, true_code = EQ, false_code = NE;
4664 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4667 /* If we are comparing against zero and the expression being tested has
4668 only a single bit that might be nonzero, that is its value when it is
4669 not equal to zero. Similarly if it is known to be -1 or 0. */
4671 if (true_code == EQ && true_val == const0_rtx
4672 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4673 false_code = EQ, false_val = GEN_INT (nzb);
4674 else if (true_code == EQ && true_val == const0_rtx
4675 && (num_sign_bit_copies (from, GET_MODE (from))
4676 == GET_MODE_BITSIZE (GET_MODE (from))))
4677 false_code = EQ, false_val = constm1_rtx;
4679 /* Now simplify an arm if we know the value of the register in the
4680 branch and it is used in the arm. Be careful due to the potential
4681 of locally-shared RTL. */
4683 if (reg_mentioned_p (from, true_rtx))
4684 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4686 pc_rtx, pc_rtx, 0, 0);
4687 if (reg_mentioned_p (from, false_rtx))
4688 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4690 pc_rtx, pc_rtx, 0, 0);
4692 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4693 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4695 true_rtx = XEXP (x, 1);
4696 false_rtx = XEXP (x, 2);
4697 true_code = GET_CODE (cond);
4700 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4701 reversed, do so to avoid needing two sets of patterns for
4702 subtract-and-branch insns. Similarly if we have a constant in the true
4703 arm, the false arm is the same as the first operand of the comparison, or
4704 the false arm is more complicated than the true arm. */
4707 && combine_reversed_comparison_code (cond) != UNKNOWN
4708 && (true_rtx == pc_rtx
4709 || (CONSTANT_P (true_rtx)
4710 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4711 || true_rtx == const0_rtx
4712 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4713 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4714 || (GET_CODE (true_rtx) == SUBREG
4715 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4716 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4717 || reg_mentioned_p (true_rtx, false_rtx)
4718 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4720 true_code = reversed_comparison_code (cond, NULL);
4722 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4725 SUBST (XEXP (x, 1), false_rtx);
4726 SUBST (XEXP (x, 2), true_rtx);
4728 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4731 /* It is possible that the conditional has been simplified out. */
4732 true_code = GET_CODE (cond);
4733 comparison_p = GET_RTX_CLASS (true_code) == '<';
4736 /* If the two arms are identical, we don't need the comparison. */
4738 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4741 /* Convert a == b ? b : a to "a". */
4742 if (true_code == EQ && ! side_effects_p (cond)
4743 && !HONOR_NANS (mode)
4744 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4745 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4747 else if (true_code == NE && ! side_effects_p (cond)
4748 && !HONOR_NANS (mode)
4749 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4750 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4753 /* Look for cases where we have (abs x) or (neg (abs X)). */
4755 if (GET_MODE_CLASS (mode) == MODE_INT
4756 && GET_CODE (false_rtx) == NEG
4757 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4759 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4760 && ! side_effects_p (true_rtx))
4765 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4769 simplify_gen_unary (NEG, mode,
4770 simplify_gen_unary (ABS, mode, true_rtx, mode),
4776 /* Look for MIN or MAX. */
4778 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4780 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4781 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4782 && ! side_effects_p (cond))
4787 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4790 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4793 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4796 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4801 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4802 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4803 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4804 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4805 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4806 neither 1 or -1, but it isn't worth checking for. */
4808 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4810 && GET_MODE_CLASS (mode) == MODE_INT
4811 && ! side_effects_p (x))
4813 rtx t = make_compound_operation (true_rtx, SET);
4814 rtx f = make_compound_operation (false_rtx, SET);
4815 rtx cond_op0 = XEXP (cond, 0);
4816 rtx cond_op1 = XEXP (cond, 1);
4817 enum rtx_code op = NIL, extend_op = NIL;
4818 enum machine_mode m = mode;
4819 rtx z = 0, c1 = NULL_RTX;
4821 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4822 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4823 || GET_CODE (t) == ASHIFT
4824 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4825 && rtx_equal_p (XEXP (t, 0), f))
4826 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4828 /* If an identity-zero op is commutative, check whether there
4829 would be a match if we swapped the operands. */
4830 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4831 || GET_CODE (t) == XOR)
4832 && rtx_equal_p (XEXP (t, 1), f))
4833 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4834 else if (GET_CODE (t) == SIGN_EXTEND
4835 && (GET_CODE (XEXP (t, 0)) == PLUS
4836 || GET_CODE (XEXP (t, 0)) == MINUS
4837 || GET_CODE (XEXP (t, 0)) == IOR
4838 || GET_CODE (XEXP (t, 0)) == XOR
4839 || GET_CODE (XEXP (t, 0)) == ASHIFT
4840 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4841 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4842 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4843 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4844 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4845 && (num_sign_bit_copies (f, GET_MODE (f))
4847 (GET_MODE_BITSIZE (mode)
4848 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4850 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4851 extend_op = SIGN_EXTEND;
4852 m = GET_MODE (XEXP (t, 0));
4854 else if (GET_CODE (t) == SIGN_EXTEND
4855 && (GET_CODE (XEXP (t, 0)) == PLUS
4856 || GET_CODE (XEXP (t, 0)) == IOR
4857 || GET_CODE (XEXP (t, 0)) == XOR)
4858 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4859 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4860 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4861 && (num_sign_bit_copies (f, GET_MODE (f))
4863 (GET_MODE_BITSIZE (mode)
4864 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4866 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4867 extend_op = SIGN_EXTEND;
4868 m = GET_MODE (XEXP (t, 0));
4870 else if (GET_CODE (t) == ZERO_EXTEND
4871 && (GET_CODE (XEXP (t, 0)) == PLUS
4872 || GET_CODE (XEXP (t, 0)) == MINUS
4873 || GET_CODE (XEXP (t, 0)) == IOR
4874 || GET_CODE (XEXP (t, 0)) == XOR
4875 || GET_CODE (XEXP (t, 0)) == ASHIFT
4876 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4877 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4878 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4879 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4880 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4881 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4882 && ((nonzero_bits (f, GET_MODE (f))
4883 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4886 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4887 extend_op = ZERO_EXTEND;
4888 m = GET_MODE (XEXP (t, 0));
4890 else if (GET_CODE (t) == ZERO_EXTEND
4891 && (GET_CODE (XEXP (t, 0)) == PLUS
4892 || GET_CODE (XEXP (t, 0)) == IOR
4893 || GET_CODE (XEXP (t, 0)) == XOR)
4894 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4895 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4896 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4897 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4898 && ((nonzero_bits (f, GET_MODE (f))
4899 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4902 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4903 extend_op = ZERO_EXTEND;
4904 m = GET_MODE (XEXP (t, 0));
4909 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4910 pc_rtx, pc_rtx, 0, 0);
4911 temp = gen_binary (MULT, m, temp,
4912 gen_binary (MULT, m, c1, const_true_rtx));
4913 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4914 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4916 if (extend_op != NIL)
4917 temp = simplify_gen_unary (extend_op, mode, temp, m);
4923 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4924 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4925 negation of a single bit, we can convert this operation to a shift. We
4926 can actually do this more generally, but it doesn't seem worth it. */
4928 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4929 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4930 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4931 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4932 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4933 == GET_MODE_BITSIZE (mode))
4934 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4936 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4937 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4939 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4940 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4941 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4942 && GET_MODE (XEXP (cond, 0)) == mode
4943 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
4944 == nonzero_bits (XEXP (cond, 0), mode)
4945 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
4946 return XEXP (cond, 0);
4951 /* Simplify X, a SET expression. Return the new expression. */
4954 simplify_set (rtx x)
4956 rtx src = SET_SRC (x);
4957 rtx dest = SET_DEST (x);
4958 enum machine_mode mode
4959 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4963 /* (set (pc) (return)) gets written as (return). */
4964 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4967 /* Now that we know for sure which bits of SRC we are using, see if we can
4968 simplify the expression for the object knowing that we only need the
4971 if (GET_MODE_CLASS (mode) == MODE_INT
4972 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4974 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4975 SUBST (SET_SRC (x), src);
4978 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4979 the comparison result and try to simplify it unless we already have used
4980 undobuf.other_insn. */
4981 if ((GET_MODE_CLASS (mode) == MODE_CC
4982 || GET_CODE (src) == COMPARE
4984 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4985 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4986 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4987 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4989 enum rtx_code old_code = GET_CODE (*cc_use);
4990 enum rtx_code new_code;
4992 int other_changed = 0;
4993 enum machine_mode compare_mode = GET_MODE (dest);
4994 enum machine_mode tmp_mode;
4996 if (GET_CODE (src) == COMPARE)
4997 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4999 op0 = src, op1 = const0_rtx;
5001 /* Check whether the comparison is known at compile time. */
5002 if (GET_MODE (op0) != VOIDmode)
5003 tmp_mode = GET_MODE (op0);
5004 else if (GET_MODE (op1) != VOIDmode)
5005 tmp_mode = GET_MODE (op1);
5007 tmp_mode = compare_mode;
5008 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5009 if (tmp != NULL_RTX)
5011 rtx pat = PATTERN (other_insn);
5012 undobuf.other_insn = other_insn;
5013 SUBST (*cc_use, tmp);
5015 /* Attempt to simplify CC user. */
5016 if (GET_CODE (pat) == SET)
5018 rtx new = simplify_rtx (SET_SRC (pat));
5019 if (new != NULL_RTX)
5020 SUBST (SET_SRC (pat), new);
5023 /* Convert X into a no-op move. */
5024 SUBST (SET_DEST (x), pc_rtx);
5025 SUBST (SET_SRC (x), pc_rtx);
5029 /* Simplify our comparison, if possible. */
5030 new_code = simplify_comparison (old_code, &op0, &op1);
5032 #ifdef SELECT_CC_MODE
5033 /* If this machine has CC modes other than CCmode, check to see if we
5034 need to use a different CC mode here. */
5035 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5038 /* If the mode changed, we have to change SET_DEST, the mode in the
5039 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5040 a hard register, just build new versions with the proper mode. If it
5041 is a pseudo, we lose unless it is only time we set the pseudo, in
5042 which case we can safely change its mode. */
5043 if (compare_mode != GET_MODE (dest))
5045 unsigned int regno = REGNO (dest);
5046 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5048 if (regno < FIRST_PSEUDO_REGISTER
5049 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5051 if (regno >= FIRST_PSEUDO_REGISTER)
5052 SUBST (regno_reg_rtx[regno], new_dest);
5054 SUBST (SET_DEST (x), new_dest);
5055 SUBST (XEXP (*cc_use, 0), new_dest);
5062 #endif /* SELECT_CC_MODE */
5064 /* If the code changed, we have to build a new comparison in
5065 undobuf.other_insn. */
5066 if (new_code != old_code)
5068 int other_changed_previously = other_changed;
5069 unsigned HOST_WIDE_INT mask;
5071 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5075 /* If the only change we made was to change an EQ into an NE or
5076 vice versa, OP0 has only one bit that might be nonzero, and OP1
5077 is zero, check if changing the user of the condition code will
5078 produce a valid insn. If it won't, we can keep the original code
5079 in that insn by surrounding our operation with an XOR. */
5081 if (((old_code == NE && new_code == EQ)
5082 || (old_code == EQ && new_code == NE))
5083 && ! other_changed_previously && op1 == const0_rtx
5084 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5085 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5087 rtx pat = PATTERN (other_insn), note = 0;
5089 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5090 && ! check_asm_operands (pat)))
5092 PUT_CODE (*cc_use, old_code);
5095 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5101 undobuf.other_insn = other_insn;
5104 /* If we are now comparing against zero, change our source if
5105 needed. If we do not use cc0, we always have a COMPARE. */
5106 if (op1 == const0_rtx && dest == cc0_rtx)
5108 SUBST (SET_SRC (x), op0);
5114 /* Otherwise, if we didn't previously have a COMPARE in the
5115 correct mode, we need one. */
5116 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5118 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5123 /* Otherwise, update the COMPARE if needed. */
5124 SUBST (XEXP (src, 0), op0);
5125 SUBST (XEXP (src, 1), op1);
5130 /* Get SET_SRC in a form where we have placed back any
5131 compound expressions. Then do the checks below. */
5132 src = make_compound_operation (src, SET);
5133 SUBST (SET_SRC (x), src);
5136 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5137 and X being a REG or (subreg (reg)), we may be able to convert this to
5138 (set (subreg:m2 x) (op)).
5140 We can always do this if M1 is narrower than M2 because that means that
5141 we only care about the low bits of the result.
5143 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5144 perform a narrower operation than requested since the high-order bits will
5145 be undefined. On machine where it is defined, this transformation is safe
5146 as long as M1 and M2 have the same number of words. */
5148 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5149 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5150 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5152 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5153 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5154 #ifndef WORD_REGISTER_OPERATIONS
5155 && (GET_MODE_SIZE (GET_MODE (src))
5156 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5158 #ifdef CANNOT_CHANGE_MODE_CLASS
5159 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5160 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5161 GET_MODE (SUBREG_REG (src)),
5164 && (GET_CODE (dest) == REG
5165 || (GET_CODE (dest) == SUBREG
5166 && GET_CODE (SUBREG_REG (dest)) == REG)))
5168 SUBST (SET_DEST (x),
5169 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5171 SUBST (SET_SRC (x), SUBREG_REG (src));
5173 src = SET_SRC (x), dest = SET_DEST (x);
5177 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5180 && GET_CODE (src) == SUBREG
5181 && subreg_lowpart_p (src)
5182 && (GET_MODE_BITSIZE (GET_MODE (src))
5183 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5185 rtx inner = SUBREG_REG (src);
5186 enum machine_mode inner_mode = GET_MODE (inner);
5188 /* Here we make sure that we don't have a sign bit on. */
5189 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5190 && (nonzero_bits (inner, inner_mode)
5191 < ((unsigned HOST_WIDE_INT) 1
5192 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5194 SUBST (SET_SRC (x), inner);
5200 #ifdef LOAD_EXTEND_OP
5201 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5202 would require a paradoxical subreg. Replace the subreg with a
5203 zero_extend to avoid the reload that would otherwise be required. */
5205 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5206 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5207 && SUBREG_BYTE (src) == 0
5208 && (GET_MODE_SIZE (GET_MODE (src))
5209 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5210 && GET_CODE (SUBREG_REG (src)) == MEM)
5213 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5214 GET_MODE (src), SUBREG_REG (src)));
5220 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5221 are comparing an item known to be 0 or -1 against 0, use a logical
5222 operation instead. Check for one of the arms being an IOR of the other
5223 arm with some value. We compute three terms to be IOR'ed together. In
5224 practice, at most two will be nonzero. Then we do the IOR's. */
5226 if (GET_CODE (dest) != PC
5227 && GET_CODE (src) == IF_THEN_ELSE
5228 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5229 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5230 && XEXP (XEXP (src, 0), 1) == const0_rtx
5231 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5232 #ifdef HAVE_conditional_move
5233 && ! can_conditionally_move_p (GET_MODE (src))
5235 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5236 GET_MODE (XEXP (XEXP (src, 0), 0)))
5237 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5238 && ! side_effects_p (src))
5240 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5241 ? XEXP (src, 1) : XEXP (src, 2));
5242 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5243 ? XEXP (src, 2) : XEXP (src, 1));
5244 rtx term1 = const0_rtx, term2, term3;
5246 if (GET_CODE (true_rtx) == IOR
5247 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5248 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5249 else if (GET_CODE (true_rtx) == IOR
5250 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5251 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5252 else if (GET_CODE (false_rtx) == IOR
5253 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5254 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5255 else if (GET_CODE (false_rtx) == IOR
5256 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5257 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5259 term2 = gen_binary (AND, GET_MODE (src),
5260 XEXP (XEXP (src, 0), 0), true_rtx);
5261 term3 = gen_binary (AND, GET_MODE (src),
5262 simplify_gen_unary (NOT, GET_MODE (src),
5263 XEXP (XEXP (src, 0), 0),
5268 gen_binary (IOR, GET_MODE (src),
5269 gen_binary (IOR, GET_MODE (src), term1, term2),
5275 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5276 whole thing fail. */
5277 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5279 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5282 /* Convert this into a field assignment operation, if possible. */
5283 return make_field_assignment (x);
5286 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5287 result. LAST is nonzero if this is the last retry. */
5290 simplify_logical (rtx x, int last)
5292 enum machine_mode mode = GET_MODE (x);
5293 rtx op0 = XEXP (x, 0);
5294 rtx op1 = XEXP (x, 1);
5297 switch (GET_CODE (x))
5300 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5301 insn (and may simplify more). */
5302 if (GET_CODE (op0) == XOR
5303 && rtx_equal_p (XEXP (op0, 0), op1)
5304 && ! side_effects_p (op1))
5305 x = gen_binary (AND, mode,
5306 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5309 if (GET_CODE (op0) == XOR
5310 && rtx_equal_p (XEXP (op0, 1), op1)
5311 && ! side_effects_p (op1))
5312 x = gen_binary (AND, mode,
5313 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5316 /* Similarly for (~(A ^ B)) & A. */
5317 if (GET_CODE (op0) == NOT
5318 && GET_CODE (XEXP (op0, 0)) == XOR
5319 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5320 && ! side_effects_p (op1))
5321 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5323 if (GET_CODE (op0) == NOT
5324 && GET_CODE (XEXP (op0, 0)) == XOR
5325 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5326 && ! side_effects_p (op1))
5327 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5329 /* We can call simplify_and_const_int only if we don't lose
5330 any (sign) bits when converting INTVAL (op1) to
5331 "unsigned HOST_WIDE_INT". */
5332 if (GET_CODE (op1) == CONST_INT
5333 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5334 || INTVAL (op1) > 0))
5336 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5338 /* If we have (ior (and (X C1) C2)) and the next restart would be
5339 the last, simplify this by making C1 as small as possible
5342 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5343 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5344 && GET_CODE (op1) == CONST_INT)
5345 return gen_binary (IOR, mode,
5346 gen_binary (AND, mode, XEXP (op0, 0),
5347 GEN_INT (INTVAL (XEXP (op0, 1))
5348 & ~INTVAL (op1))), op1);
5350 if (GET_CODE (x) != AND)
5353 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5354 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5355 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5358 /* Convert (A | B) & A to A. */
5359 if (GET_CODE (op0) == IOR
5360 && (rtx_equal_p (XEXP (op0, 0), op1)
5361 || rtx_equal_p (XEXP (op0, 1), op1))
5362 && ! side_effects_p (XEXP (op0, 0))
5363 && ! side_effects_p (XEXP (op0, 1)))
5366 /* In the following group of tests (and those in case IOR below),
5367 we start with some combination of logical operations and apply
5368 the distributive law followed by the inverse distributive law.
5369 Most of the time, this results in no change. However, if some of
5370 the operands are the same or inverses of each other, simplifications
5373 For example, (and (ior A B) (not B)) can occur as the result of
5374 expanding a bit field assignment. When we apply the distributive
5375 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5376 which then simplifies to (and (A (not B))).
5378 If we have (and (ior A B) C), apply the distributive law and then
5379 the inverse distributive law to see if things simplify. */
5381 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5383 x = apply_distributive_law
5384 (gen_binary (GET_CODE (op0), mode,
5385 gen_binary (AND, mode, XEXP (op0, 0), op1),
5386 gen_binary (AND, mode, XEXP (op0, 1),
5388 if (GET_CODE (x) != AND)
5392 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5393 return apply_distributive_law
5394 (gen_binary (GET_CODE (op1), mode,
5395 gen_binary (AND, mode, XEXP (op1, 0), op0),
5396 gen_binary (AND, mode, XEXP (op1, 1),
5399 /* Similarly, taking advantage of the fact that
5400 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5402 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5403 return apply_distributive_law
5404 (gen_binary (XOR, mode,
5405 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5406 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5409 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5410 return apply_distributive_law
5411 (gen_binary (XOR, mode,
5412 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5413 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5417 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5418 if (GET_CODE (op1) == CONST_INT
5419 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5420 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5423 /* Convert (A & B) | A to A. */
5424 if (GET_CODE (op0) == AND
5425 && (rtx_equal_p (XEXP (op0, 0), op1)
5426 || rtx_equal_p (XEXP (op0, 1), op1))
5427 && ! side_effects_p (XEXP (op0, 0))
5428 && ! side_effects_p (XEXP (op0, 1)))
5431 /* If we have (ior (and A B) C), apply the distributive law and then
5432 the inverse distributive law to see if things simplify. */
5434 if (GET_CODE (op0) == AND)
5436 x = apply_distributive_law
5437 (gen_binary (AND, mode,
5438 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5439 gen_binary (IOR, mode, XEXP (op0, 1),
5442 if (GET_CODE (x) != IOR)
5446 if (GET_CODE (op1) == AND)
5448 x = apply_distributive_law
5449 (gen_binary (AND, mode,
5450 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5451 gen_binary (IOR, mode, XEXP (op1, 1),
5454 if (GET_CODE (x) != IOR)
5458 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5459 mode size to (rotate A CX). */
5461 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5462 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5463 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5464 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5465 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5466 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5467 == GET_MODE_BITSIZE (mode)))
5468 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5469 (GET_CODE (op0) == ASHIFT
5470 ? XEXP (op0, 1) : XEXP (op1, 1)));
5472 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5473 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5474 does not affect any of the bits in OP1, it can really be done
5475 as a PLUS and we can associate. We do this by seeing if OP1
5476 can be safely shifted left C bits. */
5477 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5478 && GET_CODE (XEXP (op0, 0)) == PLUS
5479 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5480 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5481 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5483 int count = INTVAL (XEXP (op0, 1));
5484 HOST_WIDE_INT mask = INTVAL (op1) << count;
5486 if (mask >> count == INTVAL (op1)
5487 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5489 SUBST (XEXP (XEXP (op0, 0), 1),
5490 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5497 /* If we are XORing two things that have no bits in common,
5498 convert them into an IOR. This helps to detect rotation encoded
5499 using those methods and possibly other simplifications. */
5501 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5502 && (nonzero_bits (op0, mode)
5503 & nonzero_bits (op1, mode)) == 0)
5504 return (gen_binary (IOR, mode, op0, op1));
5506 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5507 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5510 int num_negated = 0;
5512 if (GET_CODE (op0) == NOT)
5513 num_negated++, op0 = XEXP (op0, 0);
5514 if (GET_CODE (op1) == NOT)
5515 num_negated++, op1 = XEXP (op1, 0);
5517 if (num_negated == 2)
5519 SUBST (XEXP (x, 0), op0);
5520 SUBST (XEXP (x, 1), op1);
5522 else if (num_negated == 1)
5524 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5528 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5529 correspond to a machine insn or result in further simplifications
5530 if B is a constant. */
5532 if (GET_CODE (op0) == AND
5533 && rtx_equal_p (XEXP (op0, 1), op1)
5534 && ! side_effects_p (op1))
5535 return gen_binary (AND, mode,
5536 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5539 else if (GET_CODE (op0) == AND
5540 && rtx_equal_p (XEXP (op0, 0), op1)
5541 && ! side_effects_p (op1))
5542 return gen_binary (AND, mode,
5543 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5546 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5547 comparison if STORE_FLAG_VALUE is 1. */
5548 if (STORE_FLAG_VALUE == 1
5549 && op1 == const1_rtx
5550 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5551 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5555 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5556 is (lt foo (const_int 0)), so we can perform the above
5557 simplification if STORE_FLAG_VALUE is 1. */
5559 if (STORE_FLAG_VALUE == 1
5560 && op1 == const1_rtx
5561 && GET_CODE (op0) == LSHIFTRT
5562 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5563 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5564 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5566 /* (xor (comparison foo bar) (const_int sign-bit))
5567 when STORE_FLAG_VALUE is the sign bit. */
5568 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5569 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5570 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5571 && op1 == const_true_rtx
5572 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5573 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5586 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5587 operations" because they can be replaced with two more basic operations.
5588 ZERO_EXTEND is also considered "compound" because it can be replaced with
5589 an AND operation, which is simpler, though only one operation.
5591 The function expand_compound_operation is called with an rtx expression
5592 and will convert it to the appropriate shifts and AND operations,
5593 simplifying at each stage.
5595 The function make_compound_operation is called to convert an expression
5596 consisting of shifts and ANDs into the equivalent compound expression.
5597 It is the inverse of this function, loosely speaking. */
5600 expand_compound_operation (rtx x)
5602 unsigned HOST_WIDE_INT pos = 0, len;
5604 unsigned int modewidth;
5607 switch (GET_CODE (x))
5612 /* We can't necessarily use a const_int for a multiword mode;
5613 it depends on implicitly extending the value.
5614 Since we don't know the right way to extend it,
5615 we can't tell whether the implicit way is right.
5617 Even for a mode that is no wider than a const_int,
5618 we can't win, because we need to sign extend one of its bits through
5619 the rest of it, and we don't know which bit. */
5620 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5623 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5624 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5625 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5626 reloaded. If not for that, MEM's would very rarely be safe.
5628 Reject MODEs bigger than a word, because we might not be able
5629 to reference a two-register group starting with an arbitrary register
5630 (and currently gen_lowpart might crash for a SUBREG). */
5632 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5635 /* Reject MODEs that aren't scalar integers because turning vector
5636 or complex modes into shifts causes problems. */
5638 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5641 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5642 /* If the inner object has VOIDmode (the only way this can happen
5643 is if it is an ASM_OPERANDS), we can't do anything since we don't
5644 know how much masking to do. */
5653 /* If the operand is a CLOBBER, just return it. */
5654 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5657 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5658 || GET_CODE (XEXP (x, 2)) != CONST_INT
5659 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5662 /* Reject MODEs that aren't scalar integers because turning vector
5663 or complex modes into shifts causes problems. */
5665 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5668 len = INTVAL (XEXP (x, 1));
5669 pos = INTVAL (XEXP (x, 2));
5671 /* If this goes outside the object being extracted, replace the object
5672 with a (use (mem ...)) construct that only combine understands
5673 and is used only for this purpose. */
5674 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5675 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5677 if (BITS_BIG_ENDIAN)
5678 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5685 /* Convert sign extension to zero extension, if we know that the high
5686 bit is not set, as this is easier to optimize. It will be converted
5687 back to cheaper alternative in make_extraction. */
5688 if (GET_CODE (x) == SIGN_EXTEND
5689 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5690 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5691 & ~(((unsigned HOST_WIDE_INT)
5692 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5696 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5697 rtx temp2 = expand_compound_operation (temp);
5699 /* Make sure this is a profitable operation. */
5700 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5702 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5708 /* We can optimize some special cases of ZERO_EXTEND. */
5709 if (GET_CODE (x) == ZERO_EXTEND)
5711 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5712 know that the last value didn't have any inappropriate bits
5714 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5715 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5716 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5717 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5718 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5719 return XEXP (XEXP (x, 0), 0);
5721 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5722 if (GET_CODE (XEXP (x, 0)) == SUBREG
5723 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5724 && subreg_lowpart_p (XEXP (x, 0))
5725 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5726 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5727 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5728 return SUBREG_REG (XEXP (x, 0));
5730 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5731 is a comparison and STORE_FLAG_VALUE permits. This is like
5732 the first case, but it works even when GET_MODE (x) is larger
5733 than HOST_WIDE_INT. */
5734 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5735 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5736 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5737 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5738 <= HOST_BITS_PER_WIDE_INT)
5739 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5740 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5741 return XEXP (XEXP (x, 0), 0);
5743 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5744 if (GET_CODE (XEXP (x, 0)) == SUBREG
5745 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5746 && subreg_lowpart_p (XEXP (x, 0))
5747 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5748 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5749 <= HOST_BITS_PER_WIDE_INT)
5750 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5751 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5752 return SUBREG_REG (XEXP (x, 0));
5756 /* If we reach here, we want to return a pair of shifts. The inner
5757 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5758 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5759 logical depending on the value of UNSIGNEDP.
5761 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5762 converted into an AND of a shift.
5764 We must check for the case where the left shift would have a negative
5765 count. This can happen in a case like (x >> 31) & 255 on machines
5766 that can't shift by a constant. On those machines, we would first
5767 combine the shift with the AND to produce a variable-position
5768 extraction. Then the constant of 31 would be substituted in to produce
5769 a such a position. */
5771 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5772 if (modewidth + len >= pos)
5773 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5775 simplify_shift_const (NULL_RTX, ASHIFT,
5778 modewidth - pos - len),
5781 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5782 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5783 simplify_shift_const (NULL_RTX, LSHIFTRT,
5786 ((HOST_WIDE_INT) 1 << len) - 1);
5788 /* Any other cases we can't handle. */
5791 /* If we couldn't do this for some reason, return the original
5793 if (GET_CODE (tem) == CLOBBER)
5799 /* X is a SET which contains an assignment of one object into
5800 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5801 or certain SUBREGS). If possible, convert it into a series of
5804 We half-heartedly support variable positions, but do not at all
5805 support variable lengths. */
5808 expand_field_assignment (rtx x)
5811 rtx pos; /* Always counts from low bit. */
5814 enum machine_mode compute_mode;
5816 /* Loop until we find something we can't simplify. */
5819 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5820 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5822 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5823 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5824 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5826 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5827 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5829 inner = XEXP (SET_DEST (x), 0);
5830 len = INTVAL (XEXP (SET_DEST (x), 1));
5831 pos = XEXP (SET_DEST (x), 2);
5833 /* If the position is constant and spans the width of INNER,
5834 surround INNER with a USE to indicate this. */
5835 if (GET_CODE (pos) == CONST_INT
5836 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5837 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5839 if (BITS_BIG_ENDIAN)
5841 if (GET_CODE (pos) == CONST_INT)
5842 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5844 else if (GET_CODE (pos) == MINUS
5845 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5846 && (INTVAL (XEXP (pos, 1))
5847 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5848 /* If position is ADJUST - X, new position is X. */
5849 pos = XEXP (pos, 0);
5851 pos = gen_binary (MINUS, GET_MODE (pos),
5852 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5858 /* A SUBREG between two modes that occupy the same numbers of words
5859 can be done by moving the SUBREG to the source. */
5860 else if (GET_CODE (SET_DEST (x)) == SUBREG
5861 /* We need SUBREGs to compute nonzero_bits properly. */
5862 && nonzero_sign_valid
5863 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5864 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5865 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5866 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5868 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5869 gen_lowpart_for_combine
5870 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5877 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5878 inner = SUBREG_REG (inner);
5880 compute_mode = GET_MODE (inner);
5882 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5883 if (! SCALAR_INT_MODE_P (compute_mode))
5885 enum machine_mode imode;
5887 /* Don't do anything for vector or complex integral types. */
5888 if (! FLOAT_MODE_P (compute_mode))
5891 /* Try to find an integral mode to pun with. */
5892 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5893 if (imode == BLKmode)
5896 compute_mode = imode;
5897 inner = gen_lowpart_for_combine (imode, inner);
5900 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5901 if (len < HOST_BITS_PER_WIDE_INT)
5902 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5906 /* Now compute the equivalent expression. Make a copy of INNER
5907 for the SET_DEST in case it is a MEM into which we will substitute;
5908 we don't want shared RTL in that case. */
5910 (VOIDmode, copy_rtx (inner),
5911 gen_binary (IOR, compute_mode,
5912 gen_binary (AND, compute_mode,
5913 simplify_gen_unary (NOT, compute_mode,
5919 gen_binary (ASHIFT, compute_mode,
5920 gen_binary (AND, compute_mode,
5921 gen_lowpart_for_combine
5922 (compute_mode, SET_SRC (x)),
5930 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5931 it is an RTX that represents a variable starting position; otherwise,
5932 POS is the (constant) starting bit position (counted from the LSB).
5934 INNER may be a USE. This will occur when we started with a bitfield
5935 that went outside the boundary of the object in memory, which is
5936 allowed on most machines. To isolate this case, we produce a USE
5937 whose mode is wide enough and surround the MEM with it. The only
5938 code that understands the USE is this routine. If it is not removed,
5939 it will cause the resulting insn not to match.
5941 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5944 IN_DEST is nonzero if this is a reference in the destination of a
5945 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5946 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5949 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5950 ZERO_EXTRACT should be built even for bits starting at bit 0.
5952 MODE is the desired mode of the result (if IN_DEST == 0).
5954 The result is an RTX for the extraction or NULL_RTX if the target
5958 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5959 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5960 int in_dest, int in_compare)
5962 /* This mode describes the size of the storage area
5963 to fetch the overall value from. Within that, we
5964 ignore the POS lowest bits, etc. */
5965 enum machine_mode is_mode = GET_MODE (inner);
5966 enum machine_mode inner_mode;
5967 enum machine_mode wanted_inner_mode = byte_mode;
5968 enum machine_mode wanted_inner_reg_mode = word_mode;
5969 enum machine_mode pos_mode = word_mode;
5970 enum machine_mode extraction_mode = word_mode;
5971 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5974 rtx orig_pos_rtx = pos_rtx;
5975 HOST_WIDE_INT orig_pos;
5977 /* Get some information about INNER and get the innermost object. */
5978 if (GET_CODE (inner) == USE)
5979 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5980 /* We don't need to adjust the position because we set up the USE
5981 to pretend that it was a full-word object. */
5982 spans_byte = 1, inner = XEXP (inner, 0);
5983 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5985 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5986 consider just the QI as the memory to extract from.
5987 The subreg adds or removes high bits; its mode is
5988 irrelevant to the meaning of this extraction,
5989 since POS and LEN count from the lsb. */
5990 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5991 is_mode = GET_MODE (SUBREG_REG (inner));
5992 inner = SUBREG_REG (inner);
5994 else if (GET_CODE (inner) == ASHIFT
5995 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5996 && pos_rtx == 0 && pos == 0
5997 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5999 /* We're extracting the least significant bits of an rtx
6000 (ashift X (const_int C)), where LEN > C. Extract the
6001 least significant (LEN - C) bits of X, giving an rtx
6002 whose mode is MODE, then shift it left C times. */
6003 new = make_extraction (mode, XEXP (inner, 0),
6004 0, 0, len - INTVAL (XEXP (inner, 1)),
6005 unsignedp, in_dest, in_compare);
6007 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6010 inner_mode = GET_MODE (inner);
6012 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6013 pos = INTVAL (pos_rtx), pos_rtx = 0;
6015 /* See if this can be done without an extraction. We never can if the
6016 width of the field is not the same as that of some integer mode. For
6017 registers, we can only avoid the extraction if the position is at the
6018 low-order bit and this is either not in the destination or we have the
6019 appropriate STRICT_LOW_PART operation available.
6021 For MEM, we can avoid an extract if the field starts on an appropriate
6022 boundary and we can change the mode of the memory reference. However,
6023 we cannot directly access the MEM if we have a USE and the underlying
6024 MEM is not TMODE. This combination means that MEM was being used in a
6025 context where bits outside its mode were being referenced; that is only
6026 valid in bit-field insns. */
6028 if (tmode != BLKmode
6029 && ! (spans_byte && inner_mode != tmode)
6030 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6031 && GET_CODE (inner) != MEM
6033 || (GET_CODE (inner) == REG
6034 && have_insn_for (STRICT_LOW_PART, tmode))))
6035 || (GET_CODE (inner) == MEM && pos_rtx == 0
6037 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6038 : BITS_PER_UNIT)) == 0
6039 /* We can't do this if we are widening INNER_MODE (it
6040 may not be aligned, for one thing). */
6041 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6042 && (inner_mode == tmode
6043 || (! mode_dependent_address_p (XEXP (inner, 0))
6044 && ! MEM_VOLATILE_P (inner))))))
6046 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6047 field. If the original and current mode are the same, we need not
6048 adjust the offset. Otherwise, we do if bytes big endian.
6050 If INNER is not a MEM, get a piece consisting of just the field
6051 of interest (in this case POS % BITS_PER_WORD must be 0). */
6053 if (GET_CODE (inner) == MEM)
6055 HOST_WIDE_INT offset;
6057 /* POS counts from lsb, but make OFFSET count in memory order. */
6058 if (BYTES_BIG_ENDIAN)
6059 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6061 offset = pos / BITS_PER_UNIT;
6063 new = adjust_address_nv (inner, tmode, offset);
6065 else if (GET_CODE (inner) == REG)
6067 if (tmode != inner_mode)
6069 /* We can't call gen_lowpart_for_combine in a DEST since we
6070 always want a SUBREG (see below) and it would sometimes
6071 return a new hard register. */
6074 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6076 if (WORDS_BIG_ENDIAN
6077 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6078 final_word = ((GET_MODE_SIZE (inner_mode)
6079 - GET_MODE_SIZE (tmode))
6080 / UNITS_PER_WORD) - final_word;
6082 final_word *= UNITS_PER_WORD;
6083 if (BYTES_BIG_ENDIAN &&
6084 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6085 final_word += (GET_MODE_SIZE (inner_mode)
6086 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6088 /* Avoid creating invalid subregs, for example when
6089 simplifying (x>>32)&255. */
6090 if (final_word >= GET_MODE_SIZE (inner_mode))
6093 new = gen_rtx_SUBREG (tmode, inner, final_word);
6096 new = gen_lowpart_for_combine (tmode, inner);
6102 new = force_to_mode (inner, tmode,
6103 len >= HOST_BITS_PER_WIDE_INT
6104 ? ~(unsigned HOST_WIDE_INT) 0
6105 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6108 /* If this extraction is going into the destination of a SET,
6109 make a STRICT_LOW_PART unless we made a MEM. */
6112 return (GET_CODE (new) == MEM ? new
6113 : (GET_CODE (new) != SUBREG
6114 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6115 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6120 if (GET_CODE (new) == CONST_INT)
6121 return gen_int_mode (INTVAL (new), mode);
6123 /* If we know that no extraneous bits are set, and that the high
6124 bit is not set, convert the extraction to the cheaper of
6125 sign and zero extension, that are equivalent in these cases. */
6126 if (flag_expensive_optimizations
6127 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6128 && ((nonzero_bits (new, tmode)
6129 & ~(((unsigned HOST_WIDE_INT)
6130 GET_MODE_MASK (tmode))
6134 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6135 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6137 /* Prefer ZERO_EXTENSION, since it gives more information to
6139 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6144 /* Otherwise, sign- or zero-extend unless we already are in the
6147 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6151 /* Unless this is a COMPARE or we have a funny memory reference,
6152 don't do anything with zero-extending field extracts starting at
6153 the low-order bit since they are simple AND operations. */
6154 if (pos_rtx == 0 && pos == 0 && ! in_dest
6155 && ! in_compare && ! spans_byte && unsignedp)
6158 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6159 we would be spanning bytes or if the position is not a constant and the
6160 length is not 1. In all other cases, we would only be going outside
6161 our object in cases when an original shift would have been
6163 if (! spans_byte && GET_CODE (inner) == MEM
6164 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6165 || (pos_rtx != 0 && len != 1)))
6168 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6169 and the mode for the result. */
6170 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6172 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6173 pos_mode = mode_for_extraction (EP_insv, 2);
6174 extraction_mode = mode_for_extraction (EP_insv, 3);
6177 if (! in_dest && unsignedp
6178 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6180 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6181 pos_mode = mode_for_extraction (EP_extzv, 3);
6182 extraction_mode = mode_for_extraction (EP_extzv, 0);
6185 if (! in_dest && ! unsignedp
6186 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6188 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6189 pos_mode = mode_for_extraction (EP_extv, 3);
6190 extraction_mode = mode_for_extraction (EP_extv, 0);
6193 /* Never narrow an object, since that might not be safe. */
6195 if (mode != VOIDmode
6196 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6197 extraction_mode = mode;
6199 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6200 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6201 pos_mode = GET_MODE (pos_rtx);
6203 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6204 if we have to change the mode of memory and cannot, the desired mode is
6206 if (GET_CODE (inner) != MEM)
6207 wanted_inner_mode = wanted_inner_reg_mode;
6208 else if (inner_mode != wanted_inner_mode
6209 && (mode_dependent_address_p (XEXP (inner, 0))
6210 || MEM_VOLATILE_P (inner)))
6211 wanted_inner_mode = extraction_mode;
6215 if (BITS_BIG_ENDIAN)
6217 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6218 BITS_BIG_ENDIAN style. If position is constant, compute new
6219 position. Otherwise, build subtraction.
6220 Note that POS is relative to the mode of the original argument.
6221 If it's a MEM we need to recompute POS relative to that.
6222 However, if we're extracting from (or inserting into) a register,
6223 we want to recompute POS relative to wanted_inner_mode. */
6224 int width = (GET_CODE (inner) == MEM
6225 ? GET_MODE_BITSIZE (is_mode)
6226 : GET_MODE_BITSIZE (wanted_inner_mode));
6229 pos = width - len - pos;
6232 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6233 /* POS may be less than 0 now, but we check for that below.
6234 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6237 /* If INNER has a wider mode, make it smaller. If this is a constant
6238 extract, try to adjust the byte to point to the byte containing
6240 if (wanted_inner_mode != VOIDmode
6241 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6242 && ((GET_CODE (inner) == MEM
6243 && (inner_mode == wanted_inner_mode
6244 || (! mode_dependent_address_p (XEXP (inner, 0))
6245 && ! MEM_VOLATILE_P (inner))))))
6249 /* The computations below will be correct if the machine is big
6250 endian in both bits and bytes or little endian in bits and bytes.
6251 If it is mixed, we must adjust. */
6253 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6254 adjust OFFSET to compensate. */
6255 if (BYTES_BIG_ENDIAN
6257 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6258 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6260 /* If this is a constant position, we can move to the desired byte. */
6263 offset += pos / BITS_PER_UNIT;
6264 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6267 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6269 && is_mode != wanted_inner_mode)
6270 offset = (GET_MODE_SIZE (is_mode)
6271 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6273 if (offset != 0 || inner_mode != wanted_inner_mode)
6274 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6277 /* If INNER is not memory, we can always get it into the proper mode. If we
6278 are changing its mode, POS must be a constant and smaller than the size
6280 else if (GET_CODE (inner) != MEM)
6282 if (GET_MODE (inner) != wanted_inner_mode
6284 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6287 inner = force_to_mode (inner, wanted_inner_mode,
6289 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6290 ? ~(unsigned HOST_WIDE_INT) 0
6291 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6296 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6297 have to zero extend. Otherwise, we can just use a SUBREG. */
6299 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6301 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6303 /* If we know that no extraneous bits are set, and that the high
6304 bit is not set, convert extraction to cheaper one - either
6305 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6307 if (flag_expensive_optimizations
6308 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6309 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6310 & ~(((unsigned HOST_WIDE_INT)
6311 GET_MODE_MASK (GET_MODE (pos_rtx)))
6315 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6317 /* Prefer ZERO_EXTENSION, since it gives more information to
6319 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6324 else if (pos_rtx != 0
6325 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6326 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6328 /* Make POS_RTX unless we already have it and it is correct. If we don't
6329 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6331 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6332 pos_rtx = orig_pos_rtx;
6334 else if (pos_rtx == 0)
6335 pos_rtx = GEN_INT (pos);
6337 /* Make the required operation. See if we can use existing rtx. */
6338 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6339 extraction_mode, inner, GEN_INT (len), pos_rtx);
6341 new = gen_lowpart_for_combine (mode, new);
6346 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6347 with any other operations in X. Return X without that shift if so. */
6350 extract_left_shift (rtx x, int count)
6352 enum rtx_code code = GET_CODE (x);
6353 enum machine_mode mode = GET_MODE (x);
6359 /* This is the shift itself. If it is wide enough, we will return
6360 either the value being shifted if the shift count is equal to
6361 COUNT or a shift for the difference. */
6362 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6363 && INTVAL (XEXP (x, 1)) >= count)
6364 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6365 INTVAL (XEXP (x, 1)) - count);
6369 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6370 return simplify_gen_unary (code, mode, tem, mode);
6374 case PLUS: case IOR: case XOR: case AND:
6375 /* If we can safely shift this constant and we find the inner shift,
6376 make a new operation. */
6377 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6378 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6379 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6380 return gen_binary (code, mode, tem,
6381 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6392 /* Look at the expression rooted at X. Look for expressions
6393 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6394 Form these expressions.
6396 Return the new rtx, usually just X.
6398 Also, for machines like the VAX that don't have logical shift insns,
6399 try to convert logical to arithmetic shift operations in cases where
6400 they are equivalent. This undoes the canonicalizations to logical
6401 shifts done elsewhere.
6403 We try, as much as possible, to re-use rtl expressions to save memory.
6405 IN_CODE says what kind of expression we are processing. Normally, it is
6406 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6407 being kludges), it is MEM. When processing the arguments of a comparison
6408 or a COMPARE against zero, it is COMPARE. */
6411 make_compound_operation (rtx x, enum rtx_code in_code)
6413 enum rtx_code code = GET_CODE (x);
6414 enum machine_mode mode = GET_MODE (x);
6415 int mode_width = GET_MODE_BITSIZE (mode);
6417 enum rtx_code next_code;
6423 /* Select the code to be used in recursive calls. Once we are inside an
6424 address, we stay there. If we have a comparison, set to COMPARE,
6425 but once inside, go back to our default of SET. */
6427 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6428 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6429 && XEXP (x, 1) == const0_rtx) ? COMPARE
6430 : in_code == COMPARE ? SET : in_code);
6432 /* Process depending on the code of this operation. If NEW is set
6433 nonzero, it will be returned. */
6438 /* Convert shifts by constants into multiplications if inside
6440 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6441 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6442 && INTVAL (XEXP (x, 1)) >= 0)
6444 new = make_compound_operation (XEXP (x, 0), next_code);
6445 new = gen_rtx_MULT (mode, new,
6446 GEN_INT ((HOST_WIDE_INT) 1
6447 << INTVAL (XEXP (x, 1))));
6452 /* If the second operand is not a constant, we can't do anything
6454 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6457 /* If the constant is a power of two minus one and the first operand
6458 is a logical right shift, make an extraction. */
6459 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6460 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6462 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6463 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6464 0, in_code == COMPARE);
6467 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6468 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6469 && subreg_lowpart_p (XEXP (x, 0))
6470 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6471 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6473 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6475 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6476 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6477 0, in_code == COMPARE);
6479 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6480 else if ((GET_CODE (XEXP (x, 0)) == XOR
6481 || GET_CODE (XEXP (x, 0)) == IOR)
6482 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6483 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6484 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6486 /* Apply the distributive law, and then try to make extractions. */
6487 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6488 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6490 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6492 new = make_compound_operation (new, in_code);
6495 /* If we are have (and (rotate X C) M) and C is larger than the number
6496 of bits in M, this is an extraction. */
6498 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6499 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6500 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6501 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6503 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6504 new = make_extraction (mode, new,
6505 (GET_MODE_BITSIZE (mode)
6506 - INTVAL (XEXP (XEXP (x, 0), 1))),
6507 NULL_RTX, i, 1, 0, in_code == COMPARE);
6510 /* On machines without logical shifts, if the operand of the AND is
6511 a logical shift and our mask turns off all the propagated sign
6512 bits, we can replace the logical shift with an arithmetic shift. */
6513 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6514 && !have_insn_for (LSHIFTRT, mode)
6515 && have_insn_for (ASHIFTRT, mode)
6516 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6517 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6518 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6519 && mode_width <= HOST_BITS_PER_WIDE_INT)
6521 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6523 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6524 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6526 gen_rtx_ASHIFTRT (mode,
6527 make_compound_operation
6528 (XEXP (XEXP (x, 0), 0), next_code),
6529 XEXP (XEXP (x, 0), 1)));
6532 /* If the constant is one less than a power of two, this might be
6533 representable by an extraction even if no shift is present.
6534 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6535 we are in a COMPARE. */
6536 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6537 new = make_extraction (mode,
6538 make_compound_operation (XEXP (x, 0),
6540 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6542 /* If we are in a comparison and this is an AND with a power of two,
6543 convert this into the appropriate bit extract. */
6544 else if (in_code == COMPARE
6545 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6546 new = make_extraction (mode,
6547 make_compound_operation (XEXP (x, 0),
6549 i, NULL_RTX, 1, 1, 0, 1);
6554 /* If the sign bit is known to be zero, replace this with an
6555 arithmetic shift. */
6556 if (have_insn_for (ASHIFTRT, mode)
6557 && ! have_insn_for (LSHIFTRT, mode)
6558 && mode_width <= HOST_BITS_PER_WIDE_INT
6559 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6561 new = gen_rtx_ASHIFTRT (mode,
6562 make_compound_operation (XEXP (x, 0),
6568 /* ... fall through ... */
6574 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6575 this is a SIGN_EXTRACT. */
6576 if (GET_CODE (rhs) == CONST_INT
6577 && GET_CODE (lhs) == ASHIFT
6578 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6579 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6581 new = make_compound_operation (XEXP (lhs, 0), next_code);
6582 new = make_extraction (mode, new,
6583 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6584 NULL_RTX, mode_width - INTVAL (rhs),
6585 code == LSHIFTRT, 0, in_code == COMPARE);
6589 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6590 If so, try to merge the shifts into a SIGN_EXTEND. We could
6591 also do this for some cases of SIGN_EXTRACT, but it doesn't
6592 seem worth the effort; the case checked for occurs on Alpha. */
6594 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6595 && ! (GET_CODE (lhs) == SUBREG
6596 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6597 && GET_CODE (rhs) == CONST_INT
6598 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6599 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6600 new = make_extraction (mode, make_compound_operation (new, next_code),
6601 0, NULL_RTX, mode_width - INTVAL (rhs),
6602 code == LSHIFTRT, 0, in_code == COMPARE);
6607 /* Call ourselves recursively on the inner expression. If we are
6608 narrowing the object and it has a different RTL code from
6609 what it originally did, do this SUBREG as a force_to_mode. */
6611 tem = make_compound_operation (SUBREG_REG (x), in_code);
6612 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6613 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6614 && subreg_lowpart_p (x))
6616 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6619 /* If we have something other than a SUBREG, we might have
6620 done an expansion, so rerun ourselves. */
6621 if (GET_CODE (newer) != SUBREG)
6622 newer = make_compound_operation (newer, in_code);
6627 /* If this is a paradoxical subreg, and the new code is a sign or
6628 zero extension, omit the subreg and widen the extension. If it
6629 is a regular subreg, we can still get rid of the subreg by not
6630 widening so much, or in fact removing the extension entirely. */
6631 if ((GET_CODE (tem) == SIGN_EXTEND
6632 || GET_CODE (tem) == ZERO_EXTEND)
6633 && subreg_lowpart_p (x))
6635 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6636 || (GET_MODE_SIZE (mode) >
6637 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6639 if (! SCALAR_INT_MODE_P (mode))
6641 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6644 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6655 x = gen_lowpart_for_combine (mode, new);
6656 code = GET_CODE (x);
6659 /* Now recursively process each operand of this operation. */
6660 fmt = GET_RTX_FORMAT (code);
6661 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6664 new = make_compound_operation (XEXP (x, i), next_code);
6665 SUBST (XEXP (x, i), new);
6671 /* Given M see if it is a value that would select a field of bits
6672 within an item, but not the entire word. Return -1 if not.
6673 Otherwise, return the starting position of the field, where 0 is the
6676 *PLEN is set to the length of the field. */
6679 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6681 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6682 int pos = exact_log2 (m & -m);
6688 /* Now shift off the low-order zero bits and see if we have a power of
6690 len = exact_log2 ((m >> pos) + 1);
6699 /* See if X can be simplified knowing that we will only refer to it in
6700 MODE and will only refer to those bits that are nonzero in MASK.
6701 If other bits are being computed or if masking operations are done
6702 that select a superset of the bits in MASK, they can sometimes be
6705 Return a possibly simplified expression, but always convert X to
6706 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6708 Also, if REG is nonzero and X is a register equal in value to REG,
6711 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6712 are all off in X. This is used when X will be complemented, by either
6713 NOT, NEG, or XOR. */
6716 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6717 rtx reg, int just_select)
6719 enum rtx_code code = GET_CODE (x);
6720 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6721 enum machine_mode op_mode;
6722 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6725 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6726 code below will do the wrong thing since the mode of such an
6727 expression is VOIDmode.
6729 Also do nothing if X is a CLOBBER; this can happen if X was
6730 the return value from a call to gen_lowpart_for_combine. */
6731 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6734 /* We want to perform the operation is its present mode unless we know
6735 that the operation is valid in MODE, in which case we do the operation
6737 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6738 && have_insn_for (code, mode))
6739 ? mode : GET_MODE (x));
6741 /* It is not valid to do a right-shift in a narrower mode
6742 than the one it came in with. */
6743 if ((code == LSHIFTRT || code == ASHIFTRT)
6744 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6745 op_mode = GET_MODE (x);
6747 /* Truncate MASK to fit OP_MODE. */
6749 mask &= GET_MODE_MASK (op_mode);
6751 /* When we have an arithmetic operation, or a shift whose count we
6752 do not know, we need to assume that all bits up to the highest-order
6753 bit in MASK will be needed. This is how we form such a mask. */
6754 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6755 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6757 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6760 /* Determine what bits of X are guaranteed to be (non)zero. */
6761 nonzero = nonzero_bits (x, mode);
6763 /* If none of the bits in X are needed, return a zero. */
6764 if (! just_select && (nonzero & mask) == 0)
6767 /* If X is a CONST_INT, return a new one. Do this here since the
6768 test below will fail. */
6769 if (GET_CODE (x) == CONST_INT)
6771 if (SCALAR_INT_MODE_P (mode))
6772 return gen_int_mode (INTVAL (x) & mask, mode);
6775 x = GEN_INT (INTVAL (x) & mask);
6776 return gen_lowpart_common (mode, x);
6780 /* If X is narrower than MODE and we want all the bits in X's mode, just
6781 get X in the proper mode. */
6782 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6783 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6784 return gen_lowpart_for_combine (mode, x);
6786 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6787 MASK are already known to be zero in X, we need not do anything. */
6788 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6794 /* If X is a (clobber (const_int)), return it since we know we are
6795 generating something that won't match. */
6799 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6800 spanned the boundary of the MEM. If we are now masking so it is
6801 within that boundary, we don't need the USE any more. */
6802 if (! BITS_BIG_ENDIAN
6803 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6804 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6811 x = expand_compound_operation (x);
6812 if (GET_CODE (x) != code)
6813 return force_to_mode (x, mode, mask, reg, next_select);
6817 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6818 || rtx_equal_p (reg, get_last_value (x))))
6823 if (subreg_lowpart_p (x)
6824 /* We can ignore the effect of this SUBREG if it narrows the mode or
6825 if the constant masks to zero all the bits the mode doesn't
6827 && ((GET_MODE_SIZE (GET_MODE (x))
6828 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6830 & GET_MODE_MASK (GET_MODE (x))
6831 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6832 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6836 /* If this is an AND with a constant, convert it into an AND
6837 whose constant is the AND of that constant with MASK. If it
6838 remains an AND of MASK, delete it since it is redundant. */
6840 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6842 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6843 mask & INTVAL (XEXP (x, 1)));
6845 /* If X is still an AND, see if it is an AND with a mask that
6846 is just some low-order bits. If so, and it is MASK, we don't
6849 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6850 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6854 /* If it remains an AND, try making another AND with the bits
6855 in the mode mask that aren't in MASK turned on. If the
6856 constant in the AND is wide enough, this might make a
6857 cheaper constant. */
6859 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6860 && GET_MODE_MASK (GET_MODE (x)) != mask
6861 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6863 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6864 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6865 int width = GET_MODE_BITSIZE (GET_MODE (x));
6868 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6869 number, sign extend it. */
6870 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6871 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6872 cval |= (HOST_WIDE_INT) -1 << width;
6874 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6875 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6885 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6886 low-order bits (as in an alignment operation) and FOO is already
6887 aligned to that boundary, mask C1 to that boundary as well.
6888 This may eliminate that PLUS and, later, the AND. */
6891 unsigned int width = GET_MODE_BITSIZE (mode);
6892 unsigned HOST_WIDE_INT smask = mask;
6894 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6895 number, sign extend it. */
6897 if (width < HOST_BITS_PER_WIDE_INT
6898 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6899 smask |= (HOST_WIDE_INT) -1 << width;
6901 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6902 && exact_log2 (- smask) >= 0
6903 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6904 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6905 return force_to_mode (plus_constant (XEXP (x, 0),
6906 (INTVAL (XEXP (x, 1)) & smask)),
6907 mode, smask, reg, next_select);
6910 /* ... fall through ... */
6913 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6914 most significant bit in MASK since carries from those bits will
6915 affect the bits we are interested in. */
6920 /* If X is (minus C Y) where C's least set bit is larger than any bit
6921 in the mask, then we may replace with (neg Y). */
6922 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6923 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6924 & -INTVAL (XEXP (x, 0))))
6927 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6929 return force_to_mode (x, mode, mask, reg, next_select);
6932 /* Similarly, if C contains every bit in the fuller_mask, then we may
6933 replace with (not Y). */
6934 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6935 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6936 == INTVAL (XEXP (x, 0))))
6938 x = simplify_gen_unary (NOT, GET_MODE (x),
6939 XEXP (x, 1), GET_MODE (x));
6940 return force_to_mode (x, mode, mask, reg, next_select);
6948 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6949 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6950 operation which may be a bitfield extraction. Ensure that the
6951 constant we form is not wider than the mode of X. */
6953 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6954 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6955 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6956 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6957 && GET_CODE (XEXP (x, 1)) == CONST_INT
6958 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6959 + floor_log2 (INTVAL (XEXP (x, 1))))
6960 < GET_MODE_BITSIZE (GET_MODE (x)))
6961 && (INTVAL (XEXP (x, 1))
6962 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6964 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6965 << INTVAL (XEXP (XEXP (x, 0), 1)));
6966 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6967 XEXP (XEXP (x, 0), 0), temp);
6968 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6969 XEXP (XEXP (x, 0), 1));
6970 return force_to_mode (x, mode, mask, reg, next_select);
6974 /* For most binary operations, just propagate into the operation and
6975 change the mode if we have an operation of that mode. */
6977 op0 = gen_lowpart_for_combine (op_mode,
6978 force_to_mode (XEXP (x, 0), mode, mask,
6980 op1 = gen_lowpart_for_combine (op_mode,
6981 force_to_mode (XEXP (x, 1), mode, mask,
6984 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6985 x = gen_binary (code, op_mode, op0, op1);
6989 /* For left shifts, do the same, but just for the first operand.
6990 However, we cannot do anything with shifts where we cannot
6991 guarantee that the counts are smaller than the size of the mode
6992 because such a count will have a different meaning in a
6995 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6996 && INTVAL (XEXP (x, 1)) >= 0
6997 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6998 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6999 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7000 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7003 /* If the shift count is a constant and we can do arithmetic in
7004 the mode of the shift, refine which bits we need. Otherwise, use the
7005 conservative form of the mask. */
7006 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7007 && INTVAL (XEXP (x, 1)) >= 0
7008 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7009 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7010 mask >>= INTVAL (XEXP (x, 1));
7014 op0 = gen_lowpart_for_combine (op_mode,
7015 force_to_mode (XEXP (x, 0), op_mode,
7016 mask, reg, next_select));
7018 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7019 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7023 /* Here we can only do something if the shift count is a constant,
7024 this shift constant is valid for the host, and we can do arithmetic
7027 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7028 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7029 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7031 rtx inner = XEXP (x, 0);
7032 unsigned HOST_WIDE_INT inner_mask;
7034 /* Select the mask of the bits we need for the shift operand. */
7035 inner_mask = mask << INTVAL (XEXP (x, 1));
7037 /* We can only change the mode of the shift if we can do arithmetic
7038 in the mode of the shift and INNER_MASK is no wider than the
7039 width of OP_MODE. */
7040 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7041 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7042 op_mode = GET_MODE (x);
7044 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7046 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7047 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7050 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7051 shift and AND produces only copies of the sign bit (C2 is one less
7052 than a power of two), we can do this with just a shift. */
7054 if (GET_CODE (x) == LSHIFTRT
7055 && GET_CODE (XEXP (x, 1)) == CONST_INT
7056 /* The shift puts one of the sign bit copies in the least significant
7058 && ((INTVAL (XEXP (x, 1))
7059 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7060 >= GET_MODE_BITSIZE (GET_MODE (x)))
7061 && exact_log2 (mask + 1) >= 0
7062 /* Number of bits left after the shift must be more than the mask
7064 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7065 <= GET_MODE_BITSIZE (GET_MODE (x)))
7066 /* Must be more sign bit copies than the mask needs. */
7067 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7068 >= exact_log2 (mask + 1)))
7069 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7070 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7071 - exact_log2 (mask + 1)));
7076 /* If we are just looking for the sign bit, we don't need this shift at
7077 all, even if it has a variable count. */
7078 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7079 && (mask == ((unsigned HOST_WIDE_INT) 1
7080 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7081 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7083 /* If this is a shift by a constant, get a mask that contains those bits
7084 that are not copies of the sign bit. We then have two cases: If
7085 MASK only includes those bits, this can be a logical shift, which may
7086 allow simplifications. If MASK is a single-bit field not within
7087 those bits, we are requesting a copy of the sign bit and hence can
7088 shift the sign bit to the appropriate location. */
7090 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7091 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7095 /* If the considered data is wider than HOST_WIDE_INT, we can't
7096 represent a mask for all its bits in a single scalar.
7097 But we only care about the lower bits, so calculate these. */
7099 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7101 nonzero = ~(HOST_WIDE_INT) 0;
7103 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7104 is the number of bits a full-width mask would have set.
7105 We need only shift if these are fewer than nonzero can
7106 hold. If not, we must keep all bits set in nonzero. */
7108 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7109 < HOST_BITS_PER_WIDE_INT)
7110 nonzero >>= INTVAL (XEXP (x, 1))
7111 + HOST_BITS_PER_WIDE_INT
7112 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7116 nonzero = GET_MODE_MASK (GET_MODE (x));
7117 nonzero >>= INTVAL (XEXP (x, 1));
7120 if ((mask & ~nonzero) == 0
7121 || (i = exact_log2 (mask)) >= 0)
7123 x = simplify_shift_const
7124 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7125 i < 0 ? INTVAL (XEXP (x, 1))
7126 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7128 if (GET_CODE (x) != ASHIFTRT)
7129 return force_to_mode (x, mode, mask, reg, next_select);
7133 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7134 even if the shift count isn't a constant. */
7136 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7140 /* If this is a zero- or sign-extension operation that just affects bits
7141 we don't care about, remove it. Be sure the call above returned
7142 something that is still a shift. */
7144 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7145 && GET_CODE (XEXP (x, 1)) == CONST_INT
7146 && INTVAL (XEXP (x, 1)) >= 0
7147 && (INTVAL (XEXP (x, 1))
7148 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7149 && GET_CODE (XEXP (x, 0)) == ASHIFT
7150 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7151 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7158 /* If the shift count is constant and we can do computations
7159 in the mode of X, compute where the bits we care about are.
7160 Otherwise, we can't do anything. Don't change the mode of
7161 the shift or propagate MODE into the shift, though. */
7162 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7163 && INTVAL (XEXP (x, 1)) >= 0)
7165 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7166 GET_MODE (x), GEN_INT (mask),
7168 if (temp && GET_CODE (temp) == CONST_INT)
7170 force_to_mode (XEXP (x, 0), GET_MODE (x),
7171 INTVAL (temp), reg, next_select));
7176 /* If we just want the low-order bit, the NEG isn't needed since it
7177 won't change the low-order bit. */
7179 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7181 /* We need any bits less significant than the most significant bit in
7182 MASK since carries from those bits will affect the bits we are
7188 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7189 same as the XOR case above. Ensure that the constant we form is not
7190 wider than the mode of X. */
7192 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7193 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7194 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7195 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7196 < GET_MODE_BITSIZE (GET_MODE (x)))
7197 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7199 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7201 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7202 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7204 return force_to_mode (x, mode, mask, reg, next_select);
7207 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7208 use the full mask inside the NOT. */
7212 op0 = gen_lowpart_for_combine (op_mode,
7213 force_to_mode (XEXP (x, 0), mode, mask,
7215 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7216 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7220 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7221 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7222 which is equal to STORE_FLAG_VALUE. */
7223 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7224 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7225 && (nonzero_bits (XEXP (x, 0), mode)
7226 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7227 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7232 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7233 written in a narrower mode. We play it safe and do not do so. */
7236 gen_lowpart_for_combine (GET_MODE (x),
7237 force_to_mode (XEXP (x, 1), mode,
7238 mask, reg, next_select)));
7240 gen_lowpart_for_combine (GET_MODE (x),
7241 force_to_mode (XEXP (x, 2), mode,
7242 mask, reg, next_select)));
7249 /* Ensure we return a value of the proper mode. */
7250 return gen_lowpart_for_combine (mode, x);
7253 /* Return nonzero if X is an expression that has one of two values depending on
7254 whether some other value is zero or nonzero. In that case, we return the
7255 value that is being tested, *PTRUE is set to the value if the rtx being
7256 returned has a nonzero value, and *PFALSE is set to the other alternative.
7258 If we return zero, we set *PTRUE and *PFALSE to X. */
7261 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7263 enum machine_mode mode = GET_MODE (x);
7264 enum rtx_code code = GET_CODE (x);
7265 rtx cond0, cond1, true0, true1, false0, false1;
7266 unsigned HOST_WIDE_INT nz;
7268 /* If we are comparing a value against zero, we are done. */
7269 if ((code == NE || code == EQ)
7270 && XEXP (x, 1) == const0_rtx)
7272 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7273 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7277 /* If this is a unary operation whose operand has one of two values, apply
7278 our opcode to compute those values. */
7279 else if (GET_RTX_CLASS (code) == '1'
7280 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7282 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7283 *pfalse = simplify_gen_unary (code, mode, false0,
7284 GET_MODE (XEXP (x, 0)));
7288 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7289 make can't possibly match and would suppress other optimizations. */
7290 else if (code == COMPARE)
7293 /* If this is a binary operation, see if either side has only one of two
7294 values. If either one does or if both do and they are conditional on
7295 the same value, compute the new true and false values. */
7296 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7297 || GET_RTX_CLASS (code) == '<')
7299 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7300 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7302 if ((cond0 != 0 || cond1 != 0)
7303 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7305 /* If if_then_else_cond returned zero, then true/false are the
7306 same rtl. We must copy one of them to prevent invalid rtl
7309 true0 = copy_rtx (true0);
7310 else if (cond1 == 0)
7311 true1 = copy_rtx (true1);
7313 *ptrue = gen_binary (code, mode, true0, true1);
7314 *pfalse = gen_binary (code, mode, false0, false1);
7315 return cond0 ? cond0 : cond1;
7318 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7319 operands is zero when the other is nonzero, and vice-versa,
7320 and STORE_FLAG_VALUE is 1 or -1. */
7322 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7323 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7325 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7327 rtx op0 = XEXP (XEXP (x, 0), 1);
7328 rtx op1 = XEXP (XEXP (x, 1), 1);
7330 cond0 = XEXP (XEXP (x, 0), 0);
7331 cond1 = XEXP (XEXP (x, 1), 0);
7333 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7334 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7335 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7336 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7337 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7338 || ((swap_condition (GET_CODE (cond0))
7339 == combine_reversed_comparison_code (cond1))
7340 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7341 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7342 && ! side_effects_p (x))
7344 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7345 *pfalse = gen_binary (MULT, mode,
7347 ? simplify_gen_unary (NEG, mode, op1,
7355 /* Similarly for MULT, AND and UMIN, except that for these the result
7357 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7358 && (code == MULT || code == AND || code == UMIN)
7359 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7361 cond0 = XEXP (XEXP (x, 0), 0);
7362 cond1 = XEXP (XEXP (x, 1), 0);
7364 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7365 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7366 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7367 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7368 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7369 || ((swap_condition (GET_CODE (cond0))
7370 == combine_reversed_comparison_code (cond1))
7371 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7372 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7373 && ! side_effects_p (x))
7375 *ptrue = *pfalse = const0_rtx;
7381 else if (code == IF_THEN_ELSE)
7383 /* If we have IF_THEN_ELSE already, extract the condition and
7384 canonicalize it if it is NE or EQ. */
7385 cond0 = XEXP (x, 0);
7386 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7387 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7388 return XEXP (cond0, 0);
7389 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7391 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7392 return XEXP (cond0, 0);
7398 /* If X is a SUBREG, we can narrow both the true and false values
7399 if the inner expression, if there is a condition. */
7400 else if (code == SUBREG
7401 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7404 true0 = simplify_gen_subreg (mode, true0,
7405 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7406 false0 = simplify_gen_subreg (mode, false0,
7407 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7408 if (true0 && false0)
7416 /* If X is a constant, this isn't special and will cause confusions
7417 if we treat it as such. Likewise if it is equivalent to a constant. */
7418 else if (CONSTANT_P (x)
7419 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7422 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7423 will be least confusing to the rest of the compiler. */
7424 else if (mode == BImode)
7426 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7430 /* If X is known to be either 0 or -1, those are the true and
7431 false values when testing X. */
7432 else if (x == constm1_rtx || x == const0_rtx
7433 || (mode != VOIDmode
7434 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7436 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7440 /* Likewise for 0 or a single bit. */
7441 else if (SCALAR_INT_MODE_P (mode)
7442 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7443 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7445 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7449 /* Otherwise fail; show no condition with true and false values the same. */
7450 *ptrue = *pfalse = x;
7454 /* Return the value of expression X given the fact that condition COND
7455 is known to be true when applied to REG as its first operand and VAL
7456 as its second. X is known to not be shared and so can be modified in
7459 We only handle the simplest cases, and specifically those cases that
7460 arise with IF_THEN_ELSE expressions. */
7463 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7465 enum rtx_code code = GET_CODE (x);
7470 if (side_effects_p (x))
7473 /* If either operand of the condition is a floating point value,
7474 then we have to avoid collapsing an EQ comparison. */
7476 && rtx_equal_p (x, reg)
7477 && ! FLOAT_MODE_P (GET_MODE (x))
7478 && ! FLOAT_MODE_P (GET_MODE (val)))
7481 if (cond == UNEQ && rtx_equal_p (x, reg))
7484 /* If X is (abs REG) and we know something about REG's relationship
7485 with zero, we may be able to simplify this. */
7487 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7490 case GE: case GT: case EQ:
7493 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7495 GET_MODE (XEXP (x, 0)));
7500 /* The only other cases we handle are MIN, MAX, and comparisons if the
7501 operands are the same as REG and VAL. */
7503 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7505 if (rtx_equal_p (XEXP (x, 0), val))
7506 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7508 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7510 if (GET_RTX_CLASS (code) == '<')
7512 if (comparison_dominates_p (cond, code))
7513 return const_true_rtx;
7515 code = combine_reversed_comparison_code (x);
7517 && comparison_dominates_p (cond, code))
7522 else if (code == SMAX || code == SMIN
7523 || code == UMIN || code == UMAX)
7525 int unsignedp = (code == UMIN || code == UMAX);
7527 /* Do not reverse the condition when it is NE or EQ.
7528 This is because we cannot conclude anything about
7529 the value of 'SMAX (x, y)' when x is not equal to y,
7530 but we can when x equals y. */
7531 if ((code == SMAX || code == UMAX)
7532 && ! (cond == EQ || cond == NE))
7533 cond = reverse_condition (cond);
7538 return unsignedp ? x : XEXP (x, 1);
7540 return unsignedp ? x : XEXP (x, 0);
7542 return unsignedp ? XEXP (x, 1) : x;
7544 return unsignedp ? XEXP (x, 0) : x;
7551 else if (code == SUBREG)
7553 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7554 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7556 if (SUBREG_REG (x) != r)
7558 /* We must simplify subreg here, before we lose track of the
7559 original inner_mode. */
7560 new = simplify_subreg (GET_MODE (x), r,
7561 inner_mode, SUBREG_BYTE (x));
7565 SUBST (SUBREG_REG (x), r);
7570 /* We don't have to handle SIGN_EXTEND here, because even in the
7571 case of replacing something with a modeless CONST_INT, a
7572 CONST_INT is already (supposed to be) a valid sign extension for
7573 its narrower mode, which implies it's already properly
7574 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7575 story is different. */
7576 else if (code == ZERO_EXTEND)
7578 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7579 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7581 if (XEXP (x, 0) != r)
7583 /* We must simplify the zero_extend here, before we lose
7584 track of the original inner_mode. */
7585 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7590 SUBST (XEXP (x, 0), r);
7596 fmt = GET_RTX_FORMAT (code);
7597 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7600 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7601 else if (fmt[i] == 'E')
7602 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7603 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7610 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7611 assignment as a field assignment. */
7614 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7616 if (x == y || rtx_equal_p (x, y))
7619 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7622 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7623 Note that all SUBREGs of MEM are paradoxical; otherwise they
7624 would have been rewritten. */
7625 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7626 && GET_CODE (SUBREG_REG (y)) == MEM
7627 && rtx_equal_p (SUBREG_REG (y),
7628 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7631 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7632 && GET_CODE (SUBREG_REG (x)) == MEM
7633 && rtx_equal_p (SUBREG_REG (x),
7634 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7637 /* We used to see if get_last_value of X and Y were the same but that's
7638 not correct. In one direction, we'll cause the assignment to have
7639 the wrong destination and in the case, we'll import a register into this
7640 insn that might have already have been dead. So fail if none of the
7641 above cases are true. */
7645 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7646 Return that assignment if so.
7648 We only handle the most common cases. */
7651 make_field_assignment (rtx x)
7653 rtx dest = SET_DEST (x);
7654 rtx src = SET_SRC (x);
7659 unsigned HOST_WIDE_INT len;
7661 enum machine_mode mode;
7663 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7664 a clear of a one-bit field. We will have changed it to
7665 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7668 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7669 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7670 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7671 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7673 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7676 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7680 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7681 && subreg_lowpart_p (XEXP (src, 0))
7682 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7683 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7684 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7685 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7686 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7687 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7689 assign = make_extraction (VOIDmode, dest, 0,
7690 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7693 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7697 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7699 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7700 && XEXP (XEXP (src, 0), 0) == const1_rtx
7701 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7703 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7706 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7710 /* The other case we handle is assignments into a constant-position
7711 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7712 a mask that has all one bits except for a group of zero bits and
7713 OTHER is known to have zeros where C1 has ones, this is such an
7714 assignment. Compute the position and length from C1. Shift OTHER
7715 to the appropriate position, force it to the required mode, and
7716 make the extraction. Check for the AND in both operands. */
7718 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7721 rhs = expand_compound_operation (XEXP (src, 0));
7722 lhs = expand_compound_operation (XEXP (src, 1));
7724 if (GET_CODE (rhs) == AND
7725 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7726 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7727 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7728 else if (GET_CODE (lhs) == AND
7729 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7730 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7731 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7735 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7736 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7737 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7738 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7741 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7745 /* The mode to use for the source is the mode of the assignment, or of
7746 what is inside a possible STRICT_LOW_PART. */
7747 mode = (GET_CODE (assign) == STRICT_LOW_PART
7748 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7750 /* Shift OTHER right POS places and make it the source, restricting it
7751 to the proper length and mode. */
7753 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7754 GET_MODE (src), other, pos),
7756 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7757 ? ~(unsigned HOST_WIDE_INT) 0
7758 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7761 /* If SRC is masked by an AND that does not make a difference in
7762 the value being stored, strip it. */
7763 if (GET_CODE (assign) == ZERO_EXTRACT
7764 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7765 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7766 && GET_CODE (src) == AND
7767 && GET_CODE (XEXP (src, 1)) == CONST_INT
7768 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7769 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7770 src = XEXP (src, 0);
7772 return gen_rtx_SET (VOIDmode, assign, src);
7775 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7779 apply_distributive_law (rtx x)
7781 enum rtx_code code = GET_CODE (x);
7782 enum rtx_code inner_code;
7783 rtx lhs, rhs, other;
7786 /* Distributivity is not true for floating point as it can change the
7787 value. So we don't do it unless -funsafe-math-optimizations. */
7788 if (FLOAT_MODE_P (GET_MODE (x))
7789 && ! flag_unsafe_math_optimizations)
7792 /* The outer operation can only be one of the following: */
7793 if (code != IOR && code != AND && code != XOR
7794 && code != PLUS && code != MINUS)
7800 /* If either operand is a primitive we can't do anything, so get out
7802 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7803 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7806 lhs = expand_compound_operation (lhs);
7807 rhs = expand_compound_operation (rhs);
7808 inner_code = GET_CODE (lhs);
7809 if (inner_code != GET_CODE (rhs))
7812 /* See if the inner and outer operations distribute. */
7819 /* These all distribute except over PLUS. */
7820 if (code == PLUS || code == MINUS)
7825 if (code != PLUS && code != MINUS)
7830 /* This is also a multiply, so it distributes over everything. */
7834 /* Non-paradoxical SUBREGs distributes over all operations, provided
7835 the inner modes and byte offsets are the same, this is an extraction
7836 of a low-order part, we don't convert an fp operation to int or
7837 vice versa, and we would not be converting a single-word
7838 operation into a multi-word operation. The latter test is not
7839 required, but it prevents generating unneeded multi-word operations.
7840 Some of the previous tests are redundant given the latter test, but
7841 are retained because they are required for correctness.
7843 We produce the result slightly differently in this case. */
7845 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7846 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7847 || ! subreg_lowpart_p (lhs)
7848 || (GET_MODE_CLASS (GET_MODE (lhs))
7849 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7850 || (GET_MODE_SIZE (GET_MODE (lhs))
7851 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7852 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7855 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7856 SUBREG_REG (lhs), SUBREG_REG (rhs));
7857 return gen_lowpart_for_combine (GET_MODE (x), tem);
7863 /* Set LHS and RHS to the inner operands (A and B in the example
7864 above) and set OTHER to the common operand (C in the example).
7865 These is only one way to do this unless the inner operation is
7867 if (GET_RTX_CLASS (inner_code) == 'c'
7868 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7869 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7870 else if (GET_RTX_CLASS (inner_code) == 'c'
7871 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7872 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7873 else if (GET_RTX_CLASS (inner_code) == 'c'
7874 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7875 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7876 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7877 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7881 /* Form the new inner operation, seeing if it simplifies first. */
7882 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7884 /* There is one exception to the general way of distributing:
7885 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7886 if (code == XOR && inner_code == IOR)
7889 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7892 /* We may be able to continuing distributing the result, so call
7893 ourselves recursively on the inner operation before forming the
7894 outer operation, which we return. */
7895 return gen_binary (inner_code, GET_MODE (x),
7896 apply_distributive_law (tem), other);
7899 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7902 Return an equivalent form, if different from X. Otherwise, return X. If
7903 X is zero, we are to always construct the equivalent form. */
7906 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7907 unsigned HOST_WIDE_INT constop)
7909 unsigned HOST_WIDE_INT nonzero;
7912 /* Simplify VAROP knowing that we will be only looking at some of the
7915 Note by passing in CONSTOP, we guarantee that the bits not set in
7916 CONSTOP are not significant and will never be examined. We must
7917 ensure that is the case by explicitly masking out those bits
7918 before returning. */
7919 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7921 /* If VAROP is a CLOBBER, we will fail so return it. */
7922 if (GET_CODE (varop) == CLOBBER)
7925 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7926 to VAROP and return the new constant. */
7927 if (GET_CODE (varop) == CONST_INT)
7928 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7930 /* See what bits may be nonzero in VAROP. Unlike the general case of
7931 a call to nonzero_bits, here we don't care about bits outside
7934 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7936 /* Turn off all bits in the constant that are known to already be zero.
7937 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7938 which is tested below. */
7942 /* If we don't have any bits left, return zero. */
7946 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7947 a power of two, we can replace this with an ASHIFT. */
7948 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7949 && (i = exact_log2 (constop)) >= 0)
7950 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7952 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7953 or XOR, then try to apply the distributive law. This may eliminate
7954 operations if either branch can be simplified because of the AND.
7955 It may also make some cases more complex, but those cases probably
7956 won't match a pattern either with or without this. */
7958 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7960 gen_lowpart_for_combine
7962 apply_distributive_law
7963 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7964 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7965 XEXP (varop, 0), constop),
7966 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7967 XEXP (varop, 1), constop))));
7969 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7970 the AND and see if one of the operands simplifies to zero. If so, we
7971 may eliminate it. */
7973 if (GET_CODE (varop) == PLUS
7974 && exact_log2 (constop + 1) >= 0)
7978 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7979 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7980 if (o0 == const0_rtx)
7982 if (o1 == const0_rtx)
7986 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7987 if we already had one (just check for the simplest cases). */
7988 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7989 && GET_MODE (XEXP (x, 0)) == mode
7990 && SUBREG_REG (XEXP (x, 0)) == varop)
7991 varop = XEXP (x, 0);
7993 varop = gen_lowpart_for_combine (mode, varop);
7995 /* If we can't make the SUBREG, try to return what we were given. */
7996 if (GET_CODE (varop) == CLOBBER)
7997 return x ? x : varop;
7999 /* If we are only masking insignificant bits, return VAROP. */
8000 if (constop == nonzero)
8004 /* Otherwise, return an AND. */
8005 constop = trunc_int_for_mode (constop, mode);
8006 /* See how much, if any, of X we can use. */
8007 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8008 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8012 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8013 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8014 SUBST (XEXP (x, 1), GEN_INT (constop));
8016 SUBST (XEXP (x, 0), varop);
8023 #define nonzero_bits_with_known(X, MODE) \
8024 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8026 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8027 It avoids exponential behavior in nonzero_bits1 when X has
8028 identical subexpressions on the first or the second level. */
8030 static unsigned HOST_WIDE_INT
8031 cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
8032 enum machine_mode known_mode,
8033 unsigned HOST_WIDE_INT known_ret)
8035 if (x == known_x && mode == known_mode)
8038 /* Try to find identical subexpressions. If found call
8039 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8040 precomputed value for the subexpression as KNOWN_RET. */
8042 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8043 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8045 rtx x0 = XEXP (x, 0);
8046 rtx x1 = XEXP (x, 1);
8048 /* Check the first level. */
8050 return nonzero_bits1 (x, mode, x0, mode,
8051 nonzero_bits_with_known (x0, mode));
8053 /* Check the second level. */
8054 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8055 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8056 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8057 return nonzero_bits1 (x, mode, x1, mode,
8058 nonzero_bits_with_known (x1, mode));
8060 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8061 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8062 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8063 return nonzero_bits1 (x, mode, x0, mode,
8064 nonzero_bits_with_known (x0, mode));
8067 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8070 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8071 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8072 is less useful. We can't allow both, because that results in exponential
8073 run time recursion. There is a nullstone testcase that triggered
8074 this. This macro avoids accidental uses of num_sign_bit_copies. */
8075 #define cached_num_sign_bit_copies()
8077 /* Given an expression, X, compute which bits in X can be nonzero.
8078 We don't care about bits outside of those defined in MODE.
8080 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8081 a shift, AND, or zero_extract, we can do better. */
8083 static unsigned HOST_WIDE_INT
8084 nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
8085 enum machine_mode known_mode,
8086 unsigned HOST_WIDE_INT known_ret)
8088 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8089 unsigned HOST_WIDE_INT inner_nz;
8091 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8094 /* For floating-point values, assume all bits are needed. */
8095 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8098 /* If X is wider than MODE, use its mode instead. */
8099 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8101 mode = GET_MODE (x);
8102 nonzero = GET_MODE_MASK (mode);
8103 mode_width = GET_MODE_BITSIZE (mode);
8106 if (mode_width > HOST_BITS_PER_WIDE_INT)
8107 /* Our only callers in this case look for single bit values. So
8108 just return the mode mask. Those tests will then be false. */
8111 #ifndef WORD_REGISTER_OPERATIONS
8112 /* If MODE is wider than X, but both are a single word for both the host
8113 and target machines, we can compute this from which bits of the
8114 object might be nonzero in its own mode, taking into account the fact
8115 that on many CISC machines, accessing an object in a wider mode
8116 causes the high-order bits to become undefined. So they are
8117 not known to be zero. */
8119 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8120 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8121 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8122 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8124 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8125 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8130 code = GET_CODE (x);
8134 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8135 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8136 all the bits above ptr_mode are known to be zero. */
8137 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8139 nonzero &= GET_MODE_MASK (ptr_mode);
8142 /* Include declared information about alignment of pointers. */
8143 /* ??? We don't properly preserve REG_POINTER changes across
8144 pointer-to-integer casts, so we can't trust it except for
8145 things that we know must be pointers. See execute/960116-1.c. */
8146 if ((x == stack_pointer_rtx
8147 || x == frame_pointer_rtx
8148 || x == arg_pointer_rtx)
8149 && REGNO_POINTER_ALIGN (REGNO (x)))
8151 unsigned HOST_WIDE_INT alignment
8152 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8154 #ifdef PUSH_ROUNDING
8155 /* If PUSH_ROUNDING is defined, it is possible for the
8156 stack to be momentarily aligned only to that amount,
8157 so we pick the least alignment. */
8158 if (x == stack_pointer_rtx && PUSH_ARGS)
8159 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1),
8163 nonzero &= ~(alignment - 1);
8166 /* If X is a register whose nonzero bits value is current, use it.
8167 Otherwise, if X is a register whose value we can find, use that
8168 value. Otherwise, use the previously-computed global nonzero bits
8169 for this register. */
8171 if (reg_last_set_value[REGNO (x)] != 0
8172 && (reg_last_set_mode[REGNO (x)] == mode
8173 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8174 && GET_MODE_CLASS (mode) == MODE_INT))
8175 && (reg_last_set_label[REGNO (x)] == label_tick
8176 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8177 && REG_N_SETS (REGNO (x)) == 1
8178 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8180 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8181 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8183 tem = get_last_value (x);
8187 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8188 /* If X is narrower than MODE and TEM is a non-negative
8189 constant that would appear negative in the mode of X,
8190 sign-extend it for use in reg_nonzero_bits because some
8191 machines (maybe most) will actually do the sign-extension
8192 and this is the conservative approach.
8194 ??? For 2.5, try to tighten up the MD files in this regard
8195 instead of this kludge. */
8197 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8198 && GET_CODE (tem) == CONST_INT
8200 && 0 != (INTVAL (tem)
8201 & ((HOST_WIDE_INT) 1
8202 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8203 tem = GEN_INT (INTVAL (tem)
8204 | ((HOST_WIDE_INT) (-1)
8205 << GET_MODE_BITSIZE (GET_MODE (x))));
8207 return nonzero_bits_with_known (tem, mode) & nonzero;
8209 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8211 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8213 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8214 /* We don't know anything about the upper bits. */
8215 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8216 return nonzero & mask;
8222 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8223 /* If X is negative in MODE, sign-extend the value. */
8224 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8225 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8226 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8232 #ifdef LOAD_EXTEND_OP
8233 /* In many, if not most, RISC machines, reading a byte from memory
8234 zeros the rest of the register. Noticing that fact saves a lot
8235 of extra zero-extends. */
8236 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8237 nonzero &= GET_MODE_MASK (GET_MODE (x));
8242 case UNEQ: case LTGT:
8243 case GT: case GTU: case UNGT:
8244 case LT: case LTU: case UNLT:
8245 case GE: case GEU: case UNGE:
8246 case LE: case LEU: case UNLE:
8247 case UNORDERED: case ORDERED:
8249 /* If this produces an integer result, we know which bits are set.
8250 Code here used to clear bits outside the mode of X, but that is
8253 if (GET_MODE_CLASS (mode) == MODE_INT
8254 && mode_width <= HOST_BITS_PER_WIDE_INT)
8255 nonzero = STORE_FLAG_VALUE;
8260 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8261 and num_sign_bit_copies. */
8262 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8263 == GET_MODE_BITSIZE (GET_MODE (x)))
8267 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8268 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8273 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8274 and num_sign_bit_copies. */
8275 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8276 == GET_MODE_BITSIZE (GET_MODE (x)))
8282 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8283 & GET_MODE_MASK (mode));
8287 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8288 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8289 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8293 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8294 Otherwise, show all the bits in the outer mode but not the inner
8296 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8297 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8299 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8301 & (((HOST_WIDE_INT) 1
8302 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8303 inner_nz |= (GET_MODE_MASK (mode)
8304 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8307 nonzero &= inner_nz;
8311 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8312 & nonzero_bits_with_known (XEXP (x, 1), mode));
8316 case UMIN: case UMAX: case SMIN: case SMAX:
8318 unsigned HOST_WIDE_INT nonzero0 =
8319 nonzero_bits_with_known (XEXP (x, 0), mode);
8321 /* Don't call nonzero_bits for the second time if it cannot change
8323 if ((nonzero & nonzero0) != nonzero)
8324 nonzero &= (nonzero0
8325 | nonzero_bits_with_known (XEXP (x, 1), mode));
8329 case PLUS: case MINUS:
8331 case DIV: case UDIV:
8332 case MOD: case UMOD:
8333 /* We can apply the rules of arithmetic to compute the number of
8334 high- and low-order zero bits of these operations. We start by
8335 computing the width (position of the highest-order nonzero bit)
8336 and the number of low-order zero bits for each value. */
8338 unsigned HOST_WIDE_INT nz0 =
8339 nonzero_bits_with_known (XEXP (x, 0), mode);
8340 unsigned HOST_WIDE_INT nz1 =
8341 nonzero_bits_with_known (XEXP (x, 1), mode);
8342 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8343 int width0 = floor_log2 (nz0) + 1;
8344 int width1 = floor_log2 (nz1) + 1;
8345 int low0 = floor_log2 (nz0 & -nz0);
8346 int low1 = floor_log2 (nz1 & -nz1);
8347 HOST_WIDE_INT op0_maybe_minusp
8348 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8349 HOST_WIDE_INT op1_maybe_minusp
8350 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8351 unsigned int result_width = mode_width;
8357 result_width = MAX (width0, width1) + 1;
8358 result_low = MIN (low0, low1);
8361 result_low = MIN (low0, low1);
8364 result_width = width0 + width1;
8365 result_low = low0 + low1;
8370 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8371 result_width = width0;
8376 result_width = width0;
8381 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8382 result_width = MIN (width0, width1);
8383 result_low = MIN (low0, low1);
8388 result_width = MIN (width0, width1);
8389 result_low = MIN (low0, low1);
8395 if (result_width < mode_width)
8396 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8399 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8401 #ifdef POINTERS_EXTEND_UNSIGNED
8402 /* If pointers extend unsigned and this is an addition or subtraction
8403 to a pointer in Pmode, all the bits above ptr_mode are known to be
8405 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8406 && (code == PLUS || code == MINUS)
8407 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8408 nonzero &= GET_MODE_MASK (ptr_mode);
8414 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8415 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8416 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8420 /* If this is a SUBREG formed for a promoted variable that has
8421 been zero-extended, we know that at least the high-order bits
8422 are zero, though others might be too. */
8424 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8425 nonzero = (GET_MODE_MASK (GET_MODE (x))
8426 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8428 /* If the inner mode is a single word for both the host and target
8429 machines, we can compute this from which bits of the inner
8430 object might be nonzero. */
8431 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8432 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8433 <= HOST_BITS_PER_WIDE_INT))
8435 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8437 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8438 /* If this is a typical RISC machine, we only have to worry
8439 about the way loads are extended. */
8440 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8442 & (((unsigned HOST_WIDE_INT) 1
8443 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8445 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8446 || GET_CODE (SUBREG_REG (x)) != MEM)
8449 /* On many CISC machines, accessing an object in a wider mode
8450 causes the high-order bits to become undefined. So they are
8451 not known to be zero. */
8452 if (GET_MODE_SIZE (GET_MODE (x))
8453 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8454 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8455 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8464 /* The nonzero bits are in two classes: any bits within MODE
8465 that aren't in GET_MODE (x) are always significant. The rest of the
8466 nonzero bits are those that are significant in the operand of
8467 the shift when shifted the appropriate number of bits. This
8468 shows that high-order bits are cleared by the right shift and
8469 low-order bits by left shifts. */
8470 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8471 && INTVAL (XEXP (x, 1)) >= 0
8472 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8474 enum machine_mode inner_mode = GET_MODE (x);
8475 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8476 int count = INTVAL (XEXP (x, 1));
8477 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8478 unsigned HOST_WIDE_INT op_nonzero =
8479 nonzero_bits_with_known (XEXP (x, 0), mode);
8480 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8481 unsigned HOST_WIDE_INT outer = 0;
8483 if (mode_width > width)
8484 outer = (op_nonzero & nonzero & ~mode_mask);
8486 if (code == LSHIFTRT)
8488 else if (code == ASHIFTRT)
8492 /* If the sign bit may have been nonzero before the shift, we
8493 need to mark all the places it could have been copied to
8494 by the shift as possibly nonzero. */
8495 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8496 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8498 else if (code == ASHIFT)
8501 inner = ((inner << (count % width)
8502 | (inner >> (width - (count % width)))) & mode_mask);
8504 nonzero &= (outer | inner);
8510 /* This is at most the number of bits in the mode. */
8511 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8515 /* If CLZ has a known value at zero, then the nonzero bits are
8516 that value, plus the number of bits in the mode minus one. */
8517 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8518 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8524 /* If CTZ has a known value at zero, then the nonzero bits are
8525 that value, plus the number of bits in the mode minus one. */
8526 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8527 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8537 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8538 | nonzero_bits_with_known (XEXP (x, 2), mode));
8548 /* See the macro definition above. */
8549 #undef cached_num_sign_bit_copies
8551 #define num_sign_bit_copies_with_known(X, M) \
8552 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8554 /* The function cached_num_sign_bit_copies is a wrapper around
8555 num_sign_bit_copies1. It avoids exponential behavior in
8556 num_sign_bit_copies1 when X has identical subexpressions on the
8557 first or the second level. */
8560 cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
8561 enum machine_mode known_mode,
8562 unsigned int known_ret)
8564 if (x == known_x && mode == known_mode)
8567 /* Try to find identical subexpressions. If found call
8568 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8569 the precomputed value for the subexpression as KNOWN_RET. */
8571 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8572 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8574 rtx x0 = XEXP (x, 0);
8575 rtx x1 = XEXP (x, 1);
8577 /* Check the first level. */
8580 num_sign_bit_copies1 (x, mode, x0, mode,
8581 num_sign_bit_copies_with_known (x0, mode));
8583 /* Check the second level. */
8584 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8585 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8586 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8588 num_sign_bit_copies1 (x, mode, x1, mode,
8589 num_sign_bit_copies_with_known (x1, mode));
8591 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8592 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8593 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8595 num_sign_bit_copies1 (x, mode, x0, mode,
8596 num_sign_bit_copies_with_known (x0, mode));
8599 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8602 /* Return the number of bits at the high-order end of X that are known to
8603 be equal to the sign bit. X will be used in mode MODE; if MODE is
8604 VOIDmode, X will be used in its own mode. The returned value will always
8605 be between 1 and the number of bits in MODE. */
8608 num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
8609 enum machine_mode known_mode,
8610 unsigned int known_ret)
8612 enum rtx_code code = GET_CODE (x);
8613 unsigned int bitwidth;
8614 int num0, num1, result;
8615 unsigned HOST_WIDE_INT nonzero;
8618 /* If we weren't given a mode, use the mode of X. If the mode is still
8619 VOIDmode, we don't know anything. Likewise if one of the modes is
8622 if (mode == VOIDmode)
8623 mode = GET_MODE (x);
8625 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8628 bitwidth = GET_MODE_BITSIZE (mode);
8630 /* For a smaller object, just ignore the high bits. */
8631 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8633 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8635 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8638 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8640 #ifndef WORD_REGISTER_OPERATIONS
8641 /* If this machine does not do all register operations on the entire
8642 register and MODE is wider than the mode of X, we can say nothing
8643 at all about the high-order bits. */
8646 /* Likewise on machines that do, if the mode of the object is smaller
8647 than a word and loads of that size don't sign extend, we can say
8648 nothing about the high order bits. */
8649 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8650 #ifdef LOAD_EXTEND_OP
8651 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8662 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8663 /* If pointers extend signed and this is a pointer in Pmode, say that
8664 all the bits above ptr_mode are known to be sign bit copies. */
8665 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8667 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8670 if (reg_last_set_value[REGNO (x)] != 0
8671 && reg_last_set_mode[REGNO (x)] == mode
8672 && (reg_last_set_label[REGNO (x)] == label_tick
8673 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8674 && REG_N_SETS (REGNO (x)) == 1
8675 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8677 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8678 return reg_last_set_sign_bit_copies[REGNO (x)];
8680 tem = get_last_value (x);
8682 return num_sign_bit_copies_with_known (tem, mode);
8684 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8685 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8686 return reg_sign_bit_copies[REGNO (x)];
8690 #ifdef LOAD_EXTEND_OP
8691 /* Some RISC machines sign-extend all loads of smaller than a word. */
8692 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8693 return MAX (1, ((int) bitwidth
8694 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8699 /* If the constant is negative, take its 1's complement and remask.
8700 Then see how many zero bits we have. */
8701 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8702 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8703 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8704 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8706 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8709 /* If this is a SUBREG for a promoted object that is sign-extended
8710 and we are looking at it in a wider mode, we know that at least the
8711 high-order bits are known to be sign bit copies. */
8713 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8715 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8716 return MAX ((int) bitwidth
8717 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8721 /* For a smaller object, just ignore the high bits. */
8722 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8724 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8725 return MAX (1, (num0
8726 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8730 #ifdef WORD_REGISTER_OPERATIONS
8731 #ifdef LOAD_EXTEND_OP
8732 /* For paradoxical SUBREGs on machines where all register operations
8733 affect the entire register, just look inside. Note that we are
8734 passing MODE to the recursive call, so the number of sign bit copies
8735 will remain relative to that mode, not the inner mode. */
8737 /* This works only if loads sign extend. Otherwise, if we get a
8738 reload for the inner part, it may be loaded from the stack, and
8739 then we lose all sign bit copies that existed before the store
8742 if ((GET_MODE_SIZE (GET_MODE (x))
8743 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8744 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8745 && GET_CODE (SUBREG_REG (x)) == MEM)
8746 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8752 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8753 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8757 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8758 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8761 /* For a smaller object, just ignore the high bits. */
8762 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8763 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8767 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8769 case ROTATE: case ROTATERT:
8770 /* If we are rotating left by a number of bits less than the number
8771 of sign bit copies, we can just subtract that amount from the
8773 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8774 && INTVAL (XEXP (x, 1)) >= 0
8775 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8777 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8778 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8779 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8784 /* In general, this subtracts one sign bit copy. But if the value
8785 is known to be positive, the number of sign bit copies is the
8786 same as that of the input. Finally, if the input has just one bit
8787 that might be nonzero, all the bits are copies of the sign bit. */
8788 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8789 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8790 return num0 > 1 ? num0 - 1 : 1;
8792 nonzero = nonzero_bits (XEXP (x, 0), mode);
8797 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8802 case IOR: case AND: case XOR:
8803 case SMIN: case SMAX: case UMIN: case UMAX:
8804 /* Logical operations will preserve the number of sign-bit copies.
8805 MIN and MAX operations always return one of the operands. */
8806 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8807 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8808 return MIN (num0, num1);
8810 case PLUS: case MINUS:
8811 /* For addition and subtraction, we can have a 1-bit carry. However,
8812 if we are subtracting 1 from a positive number, there will not
8813 be such a carry. Furthermore, if the positive number is known to
8814 be 0 or 1, we know the result is either -1 or 0. */
8816 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8817 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8819 nonzero = nonzero_bits (XEXP (x, 0), mode);
8820 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8821 return (nonzero == 1 || nonzero == 0 ? bitwidth
8822 : bitwidth - floor_log2 (nonzero) - 1);
8825 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8826 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8827 result = MAX (1, MIN (num0, num1) - 1);
8829 #ifdef POINTERS_EXTEND_UNSIGNED
8830 /* If pointers extend signed and this is an addition or subtraction
8831 to a pointer in Pmode, all the bits above ptr_mode are known to be
8833 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8834 && (code == PLUS || code == MINUS)
8835 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8836 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8837 - GET_MODE_BITSIZE (ptr_mode) + 1),
8843 /* The number of bits of the product is the sum of the number of
8844 bits of both terms. However, unless one of the terms if known
8845 to be positive, we must allow for an additional bit since negating
8846 a negative number can remove one sign bit copy. */
8848 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8849 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8851 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8853 && (bitwidth > HOST_BITS_PER_WIDE_INT
8854 || (((nonzero_bits (XEXP (x, 0), mode)
8855 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8856 && ((nonzero_bits (XEXP (x, 1), mode)
8857 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8860 return MAX (1, result);
8863 /* The result must be <= the first operand. If the first operand
8864 has the high bit set, we know nothing about the number of sign
8866 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8868 else if ((nonzero_bits (XEXP (x, 0), mode)
8869 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8872 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8875 /* The result must be <= the second operand. */
8876 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8879 /* Similar to unsigned division, except that we have to worry about
8880 the case where the divisor is negative, in which case we have
8882 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8884 && (bitwidth > HOST_BITS_PER_WIDE_INT
8885 || (nonzero_bits (XEXP (x, 1), mode)
8886 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8892 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8894 && (bitwidth > HOST_BITS_PER_WIDE_INT
8895 || (nonzero_bits (XEXP (x, 1), mode)
8896 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8902 /* Shifts by a constant add to the number of bits equal to the
8904 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8905 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8906 && INTVAL (XEXP (x, 1)) > 0)
8907 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8912 /* Left shifts destroy copies. */
8913 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8914 || INTVAL (XEXP (x, 1)) < 0
8915 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8918 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8919 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8922 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8923 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
8924 return MIN (num0, num1);
8926 case EQ: case NE: case GE: case GT: case LE: case LT:
8927 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8928 case GEU: case GTU: case LEU: case LTU:
8929 case UNORDERED: case ORDERED:
8930 /* If the constant is negative, take its 1's complement and remask.
8931 Then see how many zero bits we have. */
8932 nonzero = STORE_FLAG_VALUE;
8933 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8934 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8935 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8937 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8944 /* If we haven't been able to figure it out by one of the above rules,
8945 see if some of the high-order bits are known to be zero. If so,
8946 count those bits and return one less than that amount. If we can't
8947 safely compute the mask for this mode, always return BITWIDTH. */
8949 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8952 nonzero = nonzero_bits (x, mode);
8953 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8954 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8957 /* Return the number of "extended" bits there are in X, when interpreted
8958 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8959 unsigned quantities, this is the number of high-order zero bits.
8960 For signed quantities, this is the number of copies of the sign bit
8961 minus 1. In both case, this function returns the number of "spare"
8962 bits. For example, if two quantities for which this function returns
8963 at least 1 are added, the addition is known not to overflow.
8965 This function will always return 0 unless called during combine, which
8966 implies that it must be called from a define_split. */
8969 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8971 if (nonzero_sign_valid == 0)
8975 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8976 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8977 - floor_log2 (nonzero_bits (x, mode)))
8979 : num_sign_bit_copies (x, mode) - 1);
8982 /* This function is called from `simplify_shift_const' to merge two
8983 outer operations. Specifically, we have already found that we need
8984 to perform operation *POP0 with constant *PCONST0 at the outermost
8985 position. We would now like to also perform OP1 with constant CONST1
8986 (with *POP0 being done last).
8988 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8989 the resulting operation. *PCOMP_P is set to 1 if we would need to
8990 complement the innermost operand, otherwise it is unchanged.
8992 MODE is the mode in which the operation will be done. No bits outside
8993 the width of this mode matter. It is assumed that the width of this mode
8994 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8996 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8997 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8998 result is simply *PCONST0.
9000 If the resulting operation cannot be expressed as one operation, we
9001 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9004 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9006 enum rtx_code op0 = *pop0;
9007 HOST_WIDE_INT const0 = *pconst0;
9009 const0 &= GET_MODE_MASK (mode);
9010 const1 &= GET_MODE_MASK (mode);
9012 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9016 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9019 if (op1 == NIL || op0 == SET)
9022 else if (op0 == NIL)
9023 op0 = op1, const0 = const1;
9025 else if (op0 == op1)
9049 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9050 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9053 /* If the two constants aren't the same, we can't do anything. The
9054 remaining six cases can all be done. */
9055 else if (const0 != const1)
9063 /* (a & b) | b == b */
9065 else /* op1 == XOR */
9066 /* (a ^ b) | b == a | b */
9072 /* (a & b) ^ b == (~a) & b */
9073 op0 = AND, *pcomp_p = 1;
9074 else /* op1 == IOR */
9075 /* (a | b) ^ b == a & ~b */
9076 op0 = AND, const0 = ~const0;
9081 /* (a | b) & b == b */
9083 else /* op1 == XOR */
9084 /* (a ^ b) & b) == (~a) & b */
9091 /* Check for NO-OP cases. */
9092 const0 &= GET_MODE_MASK (mode);
9094 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9096 else if (const0 == 0 && op0 == AND)
9098 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9102 /* ??? Slightly redundant with the above mask, but not entirely.
9103 Moving this above means we'd have to sign-extend the mode mask
9104 for the final test. */
9105 const0 = trunc_int_for_mode (const0, mode);
9113 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9114 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9115 that we started with.
9117 The shift is normally computed in the widest mode we find in VAROP, as
9118 long as it isn't a different number of words than RESULT_MODE. Exceptions
9119 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9122 simplify_shift_const (rtx x, enum rtx_code code,
9123 enum machine_mode result_mode, rtx varop,
9126 enum rtx_code orig_code = code;
9129 enum machine_mode mode = result_mode;
9130 enum machine_mode shift_mode, tmode;
9131 unsigned int mode_words
9132 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9133 /* We form (outer_op (code varop count) (outer_const)). */
9134 enum rtx_code outer_op = NIL;
9135 HOST_WIDE_INT outer_const = 0;
9137 int complement_p = 0;
9140 /* Make sure and truncate the "natural" shift on the way in. We don't
9141 want to do this inside the loop as it makes it more difficult to
9143 if (SHIFT_COUNT_TRUNCATED)
9144 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9146 /* If we were given an invalid count, don't do anything except exactly
9147 what was requested. */
9149 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9154 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9159 /* Unless one of the branches of the `if' in this loop does a `continue',
9160 we will `break' the loop after the `if'. */
9164 /* If we have an operand of (clobber (const_int 0)), just return that
9166 if (GET_CODE (varop) == CLOBBER)
9169 /* If we discovered we had to complement VAROP, leave. Making a NOT
9170 here would cause an infinite loop. */
9174 /* Convert ROTATERT to ROTATE. */
9175 if (code == ROTATERT)
9177 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9179 if (VECTOR_MODE_P (result_mode))
9180 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9182 count = bitsize - count;
9185 /* We need to determine what mode we will do the shift in. If the
9186 shift is a right shift or a ROTATE, we must always do it in the mode
9187 it was originally done in. Otherwise, we can do it in MODE, the
9188 widest mode encountered. */
9190 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9191 ? result_mode : mode);
9193 /* Handle cases where the count is greater than the size of the mode
9194 minus 1. For ASHIFT, use the size minus one as the count (this can
9195 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9196 take the count modulo the size. For other shifts, the result is
9199 Since these shifts are being produced by the compiler by combining
9200 multiple operations, each of which are defined, we know what the
9201 result is supposed to be. */
9203 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9205 if (code == ASHIFTRT)
9206 count = GET_MODE_BITSIZE (shift_mode) - 1;
9207 else if (code == ROTATE || code == ROTATERT)
9208 count %= GET_MODE_BITSIZE (shift_mode);
9211 /* We can't simply return zero because there may be an
9219 /* An arithmetic right shift of a quantity known to be -1 or 0
9221 if (code == ASHIFTRT
9222 && (num_sign_bit_copies (varop, shift_mode)
9223 == GET_MODE_BITSIZE (shift_mode)))
9229 /* If we are doing an arithmetic right shift and discarding all but
9230 the sign bit copies, this is equivalent to doing a shift by the
9231 bitsize minus one. Convert it into that shift because it will often
9232 allow other simplifications. */
9234 if (code == ASHIFTRT
9235 && (count + num_sign_bit_copies (varop, shift_mode)
9236 >= GET_MODE_BITSIZE (shift_mode)))
9237 count = GET_MODE_BITSIZE (shift_mode) - 1;
9239 /* We simplify the tests below and elsewhere by converting
9240 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9241 `make_compound_operation' will convert it to an ASHIFTRT for
9242 those machines (such as VAX) that don't have an LSHIFTRT. */
9243 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9245 && ((nonzero_bits (varop, shift_mode)
9246 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9250 if (code == LSHIFTRT
9251 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9252 && !(nonzero_bits (varop, shift_mode) >> count))
9255 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9256 && !((nonzero_bits (varop, shift_mode) << count)
9257 & GET_MODE_MASK (shift_mode)))
9260 switch (GET_CODE (varop))
9266 new = expand_compound_operation (varop);
9275 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9276 minus the width of a smaller mode, we can do this with a
9277 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9278 if ((code == ASHIFTRT || code == LSHIFTRT)
9279 && ! mode_dependent_address_p (XEXP (varop, 0))
9280 && ! MEM_VOLATILE_P (varop)
9281 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9282 MODE_INT, 1)) != BLKmode)
9284 new = adjust_address_nv (varop, tmode,
9285 BYTES_BIG_ENDIAN ? 0
9286 : count / BITS_PER_UNIT);
9288 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9289 : ZERO_EXTEND, mode, new);
9296 /* Similar to the case above, except that we can only do this if
9297 the resulting mode is the same as that of the underlying
9298 MEM and adjust the address depending on the *bits* endianness
9299 because of the way that bit-field extract insns are defined. */
9300 if ((code == ASHIFTRT || code == LSHIFTRT)
9301 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9302 MODE_INT, 1)) != BLKmode
9303 && tmode == GET_MODE (XEXP (varop, 0)))
9305 if (BITS_BIG_ENDIAN)
9306 new = XEXP (varop, 0);
9309 new = copy_rtx (XEXP (varop, 0));
9310 SUBST (XEXP (new, 0),
9311 plus_constant (XEXP (new, 0),
9312 count / BITS_PER_UNIT));
9315 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9316 : ZERO_EXTEND, mode, new);
9323 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9324 the same number of words as what we've seen so far. Then store
9325 the widest mode in MODE. */
9326 if (subreg_lowpart_p (varop)
9327 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9328 > GET_MODE_SIZE (GET_MODE (varop)))
9329 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9330 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9333 varop = SUBREG_REG (varop);
9334 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9335 mode = GET_MODE (varop);
9341 /* Some machines use MULT instead of ASHIFT because MULT
9342 is cheaper. But it is still better on those machines to
9343 merge two shifts into one. */
9344 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9345 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9348 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9349 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9355 /* Similar, for when divides are cheaper. */
9356 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9357 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9360 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9361 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9367 /* If we are extracting just the sign bit of an arithmetic
9368 right shift, that shift is not needed. However, the sign
9369 bit of a wider mode may be different from what would be
9370 interpreted as the sign bit in a narrower mode, so, if
9371 the result is narrower, don't discard the shift. */
9372 if (code == LSHIFTRT
9373 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9374 && (GET_MODE_BITSIZE (result_mode)
9375 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9377 varop = XEXP (varop, 0);
9381 /* ... fall through ... */
9386 /* Here we have two nested shifts. The result is usually the
9387 AND of a new shift with a mask. We compute the result below. */
9388 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9389 && INTVAL (XEXP (varop, 1)) >= 0
9390 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9391 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9392 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9394 enum rtx_code first_code = GET_CODE (varop);
9395 unsigned int first_count = INTVAL (XEXP (varop, 1));
9396 unsigned HOST_WIDE_INT mask;
9399 /* We have one common special case. We can't do any merging if
9400 the inner code is an ASHIFTRT of a smaller mode. However, if
9401 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9402 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9403 we can convert it to
9404 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9405 This simplifies certain SIGN_EXTEND operations. */
9406 if (code == ASHIFT && first_code == ASHIFTRT
9407 && count == (unsigned int)
9408 (GET_MODE_BITSIZE (result_mode)
9409 - GET_MODE_BITSIZE (GET_MODE (varop))))
9411 /* C3 has the low-order C1 bits zero. */
9413 mask = (GET_MODE_MASK (mode)
9414 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9416 varop = simplify_and_const_int (NULL_RTX, result_mode,
9417 XEXP (varop, 0), mask);
9418 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9420 count = first_count;
9425 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9426 than C1 high-order bits equal to the sign bit, we can convert
9427 this to either an ASHIFT or an ASHIFTRT depending on the
9430 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9432 if (code == ASHIFTRT && first_code == ASHIFT
9433 && GET_MODE (varop) == shift_mode
9434 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9437 varop = XEXP (varop, 0);
9439 signed_count = count - first_count;
9440 if (signed_count < 0)
9441 count = -signed_count, code = ASHIFT;
9443 count = signed_count;
9448 /* There are some cases we can't do. If CODE is ASHIFTRT,
9449 we can only do this if FIRST_CODE is also ASHIFTRT.
9451 We can't do the case when CODE is ROTATE and FIRST_CODE is
9454 If the mode of this shift is not the mode of the outer shift,
9455 we can't do this if either shift is a right shift or ROTATE.
9457 Finally, we can't do any of these if the mode is too wide
9458 unless the codes are the same.
9460 Handle the case where the shift codes are the same
9463 if (code == first_code)
9465 if (GET_MODE (varop) != result_mode
9466 && (code == ASHIFTRT || code == LSHIFTRT
9470 count += first_count;
9471 varop = XEXP (varop, 0);
9475 if (code == ASHIFTRT
9476 || (code == ROTATE && first_code == ASHIFTRT)
9477 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9478 || (GET_MODE (varop) != result_mode
9479 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9480 || first_code == ROTATE
9481 || code == ROTATE)))
9484 /* To compute the mask to apply after the shift, shift the
9485 nonzero bits of the inner shift the same way the
9486 outer shift will. */
9488 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9491 = simplify_binary_operation (code, result_mode, mask_rtx,
9494 /* Give up if we can't compute an outer operation to use. */
9496 || GET_CODE (mask_rtx) != CONST_INT
9497 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9499 result_mode, &complement_p))
9502 /* If the shifts are in the same direction, we add the
9503 counts. Otherwise, we subtract them. */
9504 signed_count = count;
9505 if ((code == ASHIFTRT || code == LSHIFTRT)
9506 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9507 signed_count += first_count;
9509 signed_count -= first_count;
9511 /* If COUNT is positive, the new shift is usually CODE,
9512 except for the two exceptions below, in which case it is
9513 FIRST_CODE. If the count is negative, FIRST_CODE should
9515 if (signed_count > 0
9516 && ((first_code == ROTATE && code == ASHIFT)
9517 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9518 code = first_code, count = signed_count;
9519 else if (signed_count < 0)
9520 code = first_code, count = -signed_count;
9522 count = signed_count;
9524 varop = XEXP (varop, 0);
9528 /* If we have (A << B << C) for any shift, we can convert this to
9529 (A << C << B). This wins if A is a constant. Only try this if
9530 B is not a constant. */
9532 else if (GET_CODE (varop) == code
9533 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9535 = simplify_binary_operation (code, mode,
9539 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9546 /* Make this fit the case below. */
9547 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9548 GEN_INT (GET_MODE_MASK (mode)));
9554 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9555 with C the size of VAROP - 1 and the shift is logical if
9556 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9557 we have an (le X 0) operation. If we have an arithmetic shift
9558 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9559 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9561 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9562 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9563 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9564 && (code == LSHIFTRT || code == ASHIFTRT)
9565 && count == (unsigned int)
9566 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9567 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9570 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9573 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9574 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9579 /* If we have (shift (logical)), move the logical to the outside
9580 to allow it to possibly combine with another logical and the
9581 shift to combine with another shift. This also canonicalizes to
9582 what a ZERO_EXTRACT looks like. Also, some machines have
9583 (and (shift)) insns. */
9585 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9586 && (new = simplify_binary_operation (code, result_mode,
9588 GEN_INT (count))) != 0
9589 && GET_CODE (new) == CONST_INT
9590 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9591 INTVAL (new), result_mode, &complement_p))
9593 varop = XEXP (varop, 0);
9597 /* If we can't do that, try to simplify the shift in each arm of the
9598 logical expression, make a new logical expression, and apply
9599 the inverse distributive law. */
9601 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9602 XEXP (varop, 0), count);
9603 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9604 XEXP (varop, 1), count);
9606 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9607 varop = apply_distributive_law (varop);
9614 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9615 says that the sign bit can be tested, FOO has mode MODE, C is
9616 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9617 that may be nonzero. */
9618 if (code == LSHIFTRT
9619 && XEXP (varop, 1) == const0_rtx
9620 && GET_MODE (XEXP (varop, 0)) == result_mode
9621 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9622 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9623 && ((STORE_FLAG_VALUE
9624 & ((HOST_WIDE_INT) 1
9625 < (GET_MODE_BITSIZE (result_mode) - 1))))
9626 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9627 && merge_outer_ops (&outer_op, &outer_const, XOR,
9628 (HOST_WIDE_INT) 1, result_mode,
9631 varop = XEXP (varop, 0);
9638 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9639 than the number of bits in the mode is equivalent to A. */
9640 if (code == LSHIFTRT
9641 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9642 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9644 varop = XEXP (varop, 0);
9649 /* NEG commutes with ASHIFT since it is multiplication. Move the
9650 NEG outside to allow shifts to combine. */
9652 && merge_outer_ops (&outer_op, &outer_const, NEG,
9653 (HOST_WIDE_INT) 0, result_mode,
9656 varop = XEXP (varop, 0);
9662 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9663 is one less than the number of bits in the mode is
9664 equivalent to (xor A 1). */
9665 if (code == LSHIFTRT
9666 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9667 && XEXP (varop, 1) == constm1_rtx
9668 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9669 && merge_outer_ops (&outer_op, &outer_const, XOR,
9670 (HOST_WIDE_INT) 1, result_mode,
9674 varop = XEXP (varop, 0);
9678 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9679 that might be nonzero in BAR are those being shifted out and those
9680 bits are known zero in FOO, we can replace the PLUS with FOO.
9681 Similarly in the other operand order. This code occurs when
9682 we are computing the size of a variable-size array. */
9684 if ((code == ASHIFTRT || code == LSHIFTRT)
9685 && count < HOST_BITS_PER_WIDE_INT
9686 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9687 && (nonzero_bits (XEXP (varop, 1), result_mode)
9688 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9690 varop = XEXP (varop, 0);
9693 else if ((code == ASHIFTRT || code == LSHIFTRT)
9694 && count < HOST_BITS_PER_WIDE_INT
9695 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9696 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9698 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9699 & nonzero_bits (XEXP (varop, 1),
9702 varop = XEXP (varop, 1);
9706 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9708 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9709 && (new = simplify_binary_operation (ASHIFT, result_mode,
9711 GEN_INT (count))) != 0
9712 && GET_CODE (new) == CONST_INT
9713 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9714 INTVAL (new), result_mode, &complement_p))
9716 varop = XEXP (varop, 0);
9722 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9723 with C the size of VAROP - 1 and the shift is logical if
9724 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9725 we have a (gt X 0) operation. If the shift is arithmetic with
9726 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9727 we have a (neg (gt X 0)) operation. */
9729 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9730 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9731 && count == (unsigned int)
9732 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9733 && (code == LSHIFTRT || code == ASHIFTRT)
9734 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9735 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9737 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9740 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9743 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9744 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9751 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9752 if the truncate does not affect the value. */
9753 if (code == LSHIFTRT
9754 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9755 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9756 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9757 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9758 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9760 rtx varop_inner = XEXP (varop, 0);
9763 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9764 XEXP (varop_inner, 0),
9766 (count + INTVAL (XEXP (varop_inner, 1))));
9767 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9780 /* We need to determine what mode to do the shift in. If the shift is
9781 a right shift or ROTATE, we must always do it in the mode it was
9782 originally done in. Otherwise, we can do it in MODE, the widest mode
9783 encountered. The code we care about is that of the shift that will
9784 actually be done, not the shift that was originally requested. */
9786 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9787 ? result_mode : mode);
9789 /* We have now finished analyzing the shift. The result should be
9790 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9791 OUTER_OP is non-NIL, it is an operation that needs to be applied
9792 to the result of the shift. OUTER_CONST is the relevant constant,
9793 but we must turn off all bits turned off in the shift.
9795 If we were passed a value for X, see if we can use any pieces of
9796 it. If not, make new rtx. */
9798 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9799 && GET_CODE (XEXP (x, 1)) == CONST_INT
9800 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9801 const_rtx = XEXP (x, 1);
9803 const_rtx = GEN_INT (count);
9805 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9806 && GET_MODE (XEXP (x, 0)) == shift_mode
9807 && SUBREG_REG (XEXP (x, 0)) == varop)
9808 varop = XEXP (x, 0);
9809 else if (GET_MODE (varop) != shift_mode)
9810 varop = gen_lowpart_for_combine (shift_mode, varop);
9812 /* If we can't make the SUBREG, try to return what we were given. */
9813 if (GET_CODE (varop) == CLOBBER)
9814 return x ? x : varop;
9816 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9820 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9822 /* If we have an outer operation and we just made a shift, it is
9823 possible that we could have simplified the shift were it not
9824 for the outer operation. So try to do the simplification
9827 if (outer_op != NIL && GET_CODE (x) == code
9828 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9829 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9830 INTVAL (XEXP (x, 1)));
9832 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9833 turn off all the bits that the shift would have turned off. */
9834 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9835 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9836 GET_MODE_MASK (result_mode) >> orig_count);
9838 /* Do the remainder of the processing in RESULT_MODE. */
9839 x = gen_lowpart_for_combine (result_mode, x);
9841 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9844 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9846 if (outer_op != NIL)
9848 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9849 outer_const = trunc_int_for_mode (outer_const, result_mode);
9851 if (outer_op == AND)
9852 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9853 else if (outer_op == SET)
9854 /* This means that we have determined that the result is
9855 equivalent to a constant. This should be rare. */
9856 x = GEN_INT (outer_const);
9857 else if (GET_RTX_CLASS (outer_op) == '1')
9858 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9860 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9866 /* Like recog, but we receive the address of a pointer to a new pattern.
9867 We try to match the rtx that the pointer points to.
9868 If that fails, we may try to modify or replace the pattern,
9869 storing the replacement into the same pointer object.
9871 Modifications include deletion or addition of CLOBBERs.
9873 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9874 the CLOBBERs are placed.
9876 The value is the final insn code from the pattern ultimately matched,
9880 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9883 int insn_code_number;
9884 int num_clobbers_to_add = 0;
9887 rtx old_notes, old_pat;
9889 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9890 we use to indicate that something didn't match. If we find such a
9891 thing, force rejection. */
9892 if (GET_CODE (pat) == PARALLEL)
9893 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9894 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9895 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9898 old_pat = PATTERN (insn);
9899 old_notes = REG_NOTES (insn);
9900 PATTERN (insn) = pat;
9901 REG_NOTES (insn) = 0;
9903 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9905 /* If it isn't, there is the possibility that we previously had an insn
9906 that clobbered some register as a side effect, but the combined
9907 insn doesn't need to do that. So try once more without the clobbers
9908 unless this represents an ASM insn. */
9910 if (insn_code_number < 0 && ! check_asm_operands (pat)
9911 && GET_CODE (pat) == PARALLEL)
9915 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9916 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9919 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9923 SUBST_INT (XVECLEN (pat, 0), pos);
9926 pat = XVECEXP (pat, 0, 0);
9928 PATTERN (insn) = pat;
9929 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9931 PATTERN (insn) = old_pat;
9932 REG_NOTES (insn) = old_notes;
9934 /* Recognize all noop sets, these will be killed by followup pass. */
9935 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9936 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9938 /* If we had any clobbers to add, make a new pattern than contains
9939 them. Then check to make sure that all of them are dead. */
9940 if (num_clobbers_to_add)
9942 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9943 rtvec_alloc (GET_CODE (pat) == PARALLEL
9945 + num_clobbers_to_add)
9946 : num_clobbers_to_add + 1));
9948 if (GET_CODE (pat) == PARALLEL)
9949 for (i = 0; i < XVECLEN (pat, 0); i++)
9950 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9952 XVECEXP (newpat, 0, 0) = pat;
9954 add_clobbers (newpat, insn_code_number);
9956 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9957 i < XVECLEN (newpat, 0); i++)
9959 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9960 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9962 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9963 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9971 return insn_code_number;
9974 /* Like gen_lowpart but for use by combine. In combine it is not possible
9975 to create any new pseudoregs. However, it is safe to create
9976 invalid memory addresses, because combine will try to recognize
9977 them and all they will do is make the combine attempt fail.
9979 If for some reason this cannot do its job, an rtx
9980 (clobber (const_int 0)) is returned.
9981 An insn containing that will not be recognized. */
9986 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
9990 if (GET_MODE (x) == mode)
9993 /* Return identity if this is a CONST or symbolic
9996 && (GET_CODE (x) == CONST
9997 || GET_CODE (x) == SYMBOL_REF
9998 || GET_CODE (x) == LABEL_REF))
10001 /* We can only support MODE being wider than a word if X is a
10002 constant integer or has a mode the same size. */
10004 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
10005 && ! ((GET_MODE (x) == VOIDmode
10006 && (GET_CODE (x) == CONST_INT
10007 || GET_CODE (x) == CONST_DOUBLE))
10008 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10009 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10011 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10012 won't know what to do. So we will strip off the SUBREG here and
10013 process normally. */
10014 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10016 x = SUBREG_REG (x);
10017 if (GET_MODE (x) == mode)
10021 result = gen_lowpart_common (mode, x);
10022 #ifdef CANNOT_CHANGE_MODE_CLASS
10023 if (result != 0 && GET_CODE (result) == SUBREG)
10024 record_subregs_of_mode (result);
10030 if (GET_CODE (x) == MEM)
10034 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10036 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10037 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10039 /* If we want to refer to something bigger than the original memref,
10040 generate a perverse subreg instead. That will force a reload
10041 of the original memref X. */
10042 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10043 return gen_rtx_SUBREG (mode, x, 0);
10045 if (WORDS_BIG_ENDIAN)
10046 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10047 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10049 if (BYTES_BIG_ENDIAN)
10051 /* Adjust the address so that the address-after-the-data is
10053 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10054 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10057 return adjust_address_nv (x, mode, offset);
10060 /* If X is a comparison operator, rewrite it in a new mode. This
10061 probably won't match, but may allow further simplifications. */
10062 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10063 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10065 /* If we couldn't simplify X any other way, just enclose it in a
10066 SUBREG. Normally, this SUBREG won't match, but some patterns may
10067 include an explicit SUBREG or we may simplify it further in combine. */
10072 enum machine_mode sub_mode = GET_MODE (x);
10074 offset = subreg_lowpart_offset (mode, sub_mode);
10075 if (sub_mode == VOIDmode)
10077 sub_mode = int_mode_for_mode (mode);
10078 x = gen_lowpart_common (sub_mode, x);
10080 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
10082 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10085 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10089 /* These routines make binary and unary operations by first seeing if they
10090 fold; if not, a new expression is allocated. */
10093 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
10098 if (GET_CODE (op0) == CLOBBER)
10100 else if (GET_CODE (op1) == CLOBBER)
10103 if (GET_RTX_CLASS (code) == 'c'
10104 && swap_commutative_operands_p (op0, op1))
10105 tem = op0, op0 = op1, op1 = tem;
10107 if (GET_RTX_CLASS (code) == '<')
10109 enum machine_mode op_mode = GET_MODE (op0);
10111 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10112 just (REL_OP X Y). */
10113 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10115 op1 = XEXP (op0, 1);
10116 op0 = XEXP (op0, 0);
10117 op_mode = GET_MODE (op0);
10120 if (op_mode == VOIDmode)
10121 op_mode = GET_MODE (op1);
10122 result = simplify_relational_operation (code, op_mode, op0, op1);
10125 result = simplify_binary_operation (code, mode, op0, op1);
10130 /* Put complex operands first and constants second. */
10131 if (GET_RTX_CLASS (code) == 'c'
10132 && swap_commutative_operands_p (op0, op1))
10133 return gen_rtx_fmt_ee (code, mode, op1, op0);
10135 /* If we are turning off bits already known off in OP0, we need not do
10137 else if (code == AND && GET_CODE (op1) == CONST_INT
10138 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10139 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10142 return gen_rtx_fmt_ee (code, mode, op0, op1);
10145 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10146 comparison code that will be tested.
10148 The result is a possibly different comparison code to use. *POP0 and
10149 *POP1 may be updated.
10151 It is possible that we might detect that a comparison is either always
10152 true or always false. However, we do not perform general constant
10153 folding in combine, so this knowledge isn't useful. Such tautologies
10154 should have been detected earlier. Hence we ignore all such cases. */
10156 static enum rtx_code
10157 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10163 enum machine_mode mode, tmode;
10165 /* Try a few ways of applying the same transformation to both operands. */
10168 #ifndef WORD_REGISTER_OPERATIONS
10169 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10170 so check specially. */
10171 if (code != GTU && code != GEU && code != LTU && code != LEU
10172 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10173 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10174 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10175 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10176 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10177 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10178 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10179 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10180 && XEXP (op0, 1) == XEXP (op1, 1)
10181 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10182 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10183 && (INTVAL (XEXP (op0, 1))
10184 == (GET_MODE_BITSIZE (GET_MODE (op0))
10185 - (GET_MODE_BITSIZE
10186 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10188 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10189 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10193 /* If both operands are the same constant shift, see if we can ignore the
10194 shift. We can if the shift is a rotate or if the bits shifted out of
10195 this shift are known to be zero for both inputs and if the type of
10196 comparison is compatible with the shift. */
10197 if (GET_CODE (op0) == GET_CODE (op1)
10198 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10199 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10200 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10201 && (code != GT && code != LT && code != GE && code != LE))
10202 || (GET_CODE (op0) == ASHIFTRT
10203 && (code != GTU && code != LTU
10204 && code != GEU && code != LEU)))
10205 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10206 && INTVAL (XEXP (op0, 1)) >= 0
10207 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10208 && XEXP (op0, 1) == XEXP (op1, 1))
10210 enum machine_mode mode = GET_MODE (op0);
10211 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10212 int shift_count = INTVAL (XEXP (op0, 1));
10214 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10215 mask &= (mask >> shift_count) << shift_count;
10216 else if (GET_CODE (op0) == ASHIFT)
10217 mask = (mask & (mask << shift_count)) >> shift_count;
10219 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10220 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10221 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10226 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10227 SUBREGs are of the same mode, and, in both cases, the AND would
10228 be redundant if the comparison was done in the narrower mode,
10229 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10230 and the operand's possibly nonzero bits are 0xffffff01; in that case
10231 if we only care about QImode, we don't need the AND). This case
10232 occurs if the output mode of an scc insn is not SImode and
10233 STORE_FLAG_VALUE == 1 (e.g., the 386).
10235 Similarly, check for a case where the AND's are ZERO_EXTEND
10236 operations from some narrower mode even though a SUBREG is not
10239 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10240 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10241 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10243 rtx inner_op0 = XEXP (op0, 0);
10244 rtx inner_op1 = XEXP (op1, 0);
10245 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10246 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10249 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10250 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10251 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10252 && (GET_MODE (SUBREG_REG (inner_op0))
10253 == GET_MODE (SUBREG_REG (inner_op1)))
10254 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10255 <= HOST_BITS_PER_WIDE_INT)
10256 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10257 GET_MODE (SUBREG_REG (inner_op0)))))
10258 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10259 GET_MODE (SUBREG_REG (inner_op1))))))
10261 op0 = SUBREG_REG (inner_op0);
10262 op1 = SUBREG_REG (inner_op1);
10264 /* The resulting comparison is always unsigned since we masked
10265 off the original sign bit. */
10266 code = unsigned_condition (code);
10272 for (tmode = GET_CLASS_NARROWEST_MODE
10273 (GET_MODE_CLASS (GET_MODE (op0)));
10274 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10275 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10277 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10278 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10279 code = unsigned_condition (code);
10288 /* If both operands are NOT, we can strip off the outer operation
10289 and adjust the comparison code for swapped operands; similarly for
10290 NEG, except that this must be an equality comparison. */
10291 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10292 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10293 && (code == EQ || code == NE)))
10294 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10300 /* If the first operand is a constant, swap the operands and adjust the
10301 comparison code appropriately, but don't do this if the second operand
10302 is already a constant integer. */
10303 if (swap_commutative_operands_p (op0, op1))
10305 tem = op0, op0 = op1, op1 = tem;
10306 code = swap_condition (code);
10309 /* We now enter a loop during which we will try to simplify the comparison.
10310 For the most part, we only are concerned with comparisons with zero,
10311 but some things may really be comparisons with zero but not start
10312 out looking that way. */
10314 while (GET_CODE (op1) == CONST_INT)
10316 enum machine_mode mode = GET_MODE (op0);
10317 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10318 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10319 int equality_comparison_p;
10320 int sign_bit_comparison_p;
10321 int unsigned_comparison_p;
10322 HOST_WIDE_INT const_op;
10324 /* We only want to handle integral modes. This catches VOIDmode,
10325 CCmode, and the floating-point modes. An exception is that we
10326 can handle VOIDmode if OP0 is a COMPARE or a comparison
10329 if (GET_MODE_CLASS (mode) != MODE_INT
10330 && ! (mode == VOIDmode
10331 && (GET_CODE (op0) == COMPARE
10332 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10335 /* Get the constant we are comparing against and turn off all bits
10336 not on in our mode. */
10337 const_op = INTVAL (op1);
10338 if (mode != VOIDmode)
10339 const_op = trunc_int_for_mode (const_op, mode);
10340 op1 = GEN_INT (const_op);
10342 /* If we are comparing against a constant power of two and the value
10343 being compared can only have that single bit nonzero (e.g., it was
10344 `and'ed with that bit), we can replace this with a comparison
10347 && (code == EQ || code == NE || code == GE || code == GEU
10348 || code == LT || code == LTU)
10349 && mode_width <= HOST_BITS_PER_WIDE_INT
10350 && exact_log2 (const_op) >= 0
10351 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10353 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10354 op1 = const0_rtx, const_op = 0;
10357 /* Similarly, if we are comparing a value known to be either -1 or
10358 0 with -1, change it to the opposite comparison against zero. */
10361 && (code == EQ || code == NE || code == GT || code == LE
10362 || code == GEU || code == LTU)
10363 && num_sign_bit_copies (op0, mode) == mode_width)
10365 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10366 op1 = const0_rtx, const_op = 0;
10369 /* Do some canonicalizations based on the comparison code. We prefer
10370 comparisons against zero and then prefer equality comparisons.
10371 If we can reduce the size of a constant, we will do that too. */
10376 /* < C is equivalent to <= (C - 1) */
10380 op1 = GEN_INT (const_op);
10382 /* ... fall through to LE case below. */
10388 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10392 op1 = GEN_INT (const_op);
10396 /* If we are doing a <= 0 comparison on a value known to have
10397 a zero sign bit, we can replace this with == 0. */
10398 else if (const_op == 0
10399 && mode_width <= HOST_BITS_PER_WIDE_INT
10400 && (nonzero_bits (op0, mode)
10401 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10406 /* >= C is equivalent to > (C - 1). */
10410 op1 = GEN_INT (const_op);
10412 /* ... fall through to GT below. */
10418 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10422 op1 = GEN_INT (const_op);
10426 /* If we are doing a > 0 comparison on a value known to have
10427 a zero sign bit, we can replace this with != 0. */
10428 else if (const_op == 0
10429 && mode_width <= HOST_BITS_PER_WIDE_INT
10430 && (nonzero_bits (op0, mode)
10431 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10436 /* < C is equivalent to <= (C - 1). */
10440 op1 = GEN_INT (const_op);
10442 /* ... fall through ... */
10445 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10446 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10447 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10449 const_op = 0, op1 = const0_rtx;
10457 /* unsigned <= 0 is equivalent to == 0 */
10461 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10462 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10463 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10465 const_op = 0, op1 = const0_rtx;
10471 /* >= C is equivalent to < (C - 1). */
10475 op1 = GEN_INT (const_op);
10477 /* ... fall through ... */
10480 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10481 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10482 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10484 const_op = 0, op1 = const0_rtx;
10492 /* unsigned > 0 is equivalent to != 0 */
10496 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10497 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10498 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10500 const_op = 0, op1 = const0_rtx;
10509 /* Compute some predicates to simplify code below. */
10511 equality_comparison_p = (code == EQ || code == NE);
10512 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10513 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10516 /* If this is a sign bit comparison and we can do arithmetic in
10517 MODE, say that we will only be needing the sign bit of OP0. */
10518 if (sign_bit_comparison_p
10519 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10520 op0 = force_to_mode (op0, mode,
10522 << (GET_MODE_BITSIZE (mode) - 1)),
10525 /* Now try cases based on the opcode of OP0. If none of the cases
10526 does a "continue", we exit this loop immediately after the
10529 switch (GET_CODE (op0))
10532 /* If we are extracting a single bit from a variable position in
10533 a constant that has only a single bit set and are comparing it
10534 with zero, we can convert this into an equality comparison
10535 between the position and the location of the single bit. */
10536 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10537 have already reduced the shift count modulo the word size. */
10538 if (!SHIFT_COUNT_TRUNCATED
10539 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10540 && XEXP (op0, 1) == const1_rtx
10541 && equality_comparison_p && const_op == 0
10542 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10544 if (BITS_BIG_ENDIAN)
10546 enum machine_mode new_mode
10547 = mode_for_extraction (EP_extzv, 1);
10548 if (new_mode == MAX_MACHINE_MODE)
10549 i = BITS_PER_WORD - 1 - i;
10553 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10557 op0 = XEXP (op0, 2);
10561 /* Result is nonzero iff shift count is equal to I. */
10562 code = reverse_condition (code);
10566 /* ... fall through ... */
10569 tem = expand_compound_operation (op0);
10578 /* If testing for equality, we can take the NOT of the constant. */
10579 if (equality_comparison_p
10580 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10582 op0 = XEXP (op0, 0);
10587 /* If just looking at the sign bit, reverse the sense of the
10589 if (sign_bit_comparison_p)
10591 op0 = XEXP (op0, 0);
10592 code = (code == GE ? LT : GE);
10598 /* If testing for equality, we can take the NEG of the constant. */
10599 if (equality_comparison_p
10600 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10602 op0 = XEXP (op0, 0);
10607 /* The remaining cases only apply to comparisons with zero. */
10611 /* When X is ABS or is known positive,
10612 (neg X) is < 0 if and only if X != 0. */
10614 if (sign_bit_comparison_p
10615 && (GET_CODE (XEXP (op0, 0)) == ABS
10616 || (mode_width <= HOST_BITS_PER_WIDE_INT
10617 && (nonzero_bits (XEXP (op0, 0), mode)
10618 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10620 op0 = XEXP (op0, 0);
10621 code = (code == LT ? NE : EQ);
10625 /* If we have NEG of something whose two high-order bits are the
10626 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10627 if (num_sign_bit_copies (op0, mode) >= 2)
10629 op0 = XEXP (op0, 0);
10630 code = swap_condition (code);
10636 /* If we are testing equality and our count is a constant, we
10637 can perform the inverse operation on our RHS. */
10638 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10639 && (tem = simplify_binary_operation (ROTATERT, mode,
10640 op1, XEXP (op0, 1))) != 0)
10642 op0 = XEXP (op0, 0);
10647 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10648 a particular bit. Convert it to an AND of a constant of that
10649 bit. This will be converted into a ZERO_EXTRACT. */
10650 if (const_op == 0 && sign_bit_comparison_p
10651 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10652 && mode_width <= HOST_BITS_PER_WIDE_INT)
10654 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10657 - INTVAL (XEXP (op0, 1)))));
10658 code = (code == LT ? NE : EQ);
10662 /* Fall through. */
10665 /* ABS is ignorable inside an equality comparison with zero. */
10666 if (const_op == 0 && equality_comparison_p)
10668 op0 = XEXP (op0, 0);
10674 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10675 to (compare FOO CONST) if CONST fits in FOO's mode and we
10676 are either testing inequality or have an unsigned comparison
10677 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10678 if (! unsigned_comparison_p
10679 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10680 <= HOST_BITS_PER_WIDE_INT)
10681 && ((unsigned HOST_WIDE_INT) const_op
10682 < (((unsigned HOST_WIDE_INT) 1
10683 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10685 op0 = XEXP (op0, 0);
10691 /* Check for the case where we are comparing A - C1 with C2,
10692 both constants are smaller than 1/2 the maximum positive
10693 value in MODE, and the comparison is equality or unsigned.
10694 In that case, if A is either zero-extended to MODE or has
10695 sufficient sign bits so that the high-order bit in MODE
10696 is a copy of the sign in the inner mode, we can prove that it is
10697 safe to do the operation in the wider mode. This simplifies
10698 many range checks. */
10700 if (mode_width <= HOST_BITS_PER_WIDE_INT
10701 && subreg_lowpart_p (op0)
10702 && GET_CODE (SUBREG_REG (op0)) == PLUS
10703 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10704 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10705 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10706 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10707 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10708 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10709 GET_MODE (SUBREG_REG (op0)))
10710 & ~GET_MODE_MASK (mode))
10711 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10712 GET_MODE (SUBREG_REG (op0)))
10714 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10715 - GET_MODE_BITSIZE (mode)))))
10717 op0 = SUBREG_REG (op0);
10721 /* If the inner mode is narrower and we are extracting the low part,
10722 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10723 if (subreg_lowpart_p (op0)
10724 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10725 /* Fall through */ ;
10729 /* ... fall through ... */
10732 if ((unsigned_comparison_p || equality_comparison_p)
10733 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10734 <= HOST_BITS_PER_WIDE_INT)
10735 && ((unsigned HOST_WIDE_INT) const_op
10736 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10738 op0 = XEXP (op0, 0);
10744 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10745 this for equality comparisons due to pathological cases involving
10747 if (equality_comparison_p
10748 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10749 op1, XEXP (op0, 1))))
10751 op0 = XEXP (op0, 0);
10756 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10757 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10758 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10760 op0 = XEXP (XEXP (op0, 0), 0);
10761 code = (code == LT ? EQ : NE);
10767 /* We used to optimize signed comparisons against zero, but that
10768 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10769 arrive here as equality comparisons, or (GEU, LTU) are
10770 optimized away. No need to special-case them. */
10772 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10773 (eq B (minus A C)), whichever simplifies. We can only do
10774 this for equality comparisons due to pathological cases involving
10776 if (equality_comparison_p
10777 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10778 XEXP (op0, 1), op1)))
10780 op0 = XEXP (op0, 0);
10785 if (equality_comparison_p
10786 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10787 XEXP (op0, 0), op1)))
10789 op0 = XEXP (op0, 1);
10794 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10795 of bits in X minus 1, is one iff X > 0. */
10796 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10797 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10798 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10800 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10802 op0 = XEXP (op0, 1);
10803 code = (code == GE ? LE : GT);
10809 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10810 if C is zero or B is a constant. */
10811 if (equality_comparison_p
10812 && 0 != (tem = simplify_binary_operation (XOR, mode,
10813 XEXP (op0, 1), op1)))
10815 op0 = XEXP (op0, 0);
10822 case UNEQ: case LTGT:
10823 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10824 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10825 case UNORDERED: case ORDERED:
10826 /* We can't do anything if OP0 is a condition code value, rather
10827 than an actual data value. */
10829 || CC0_P (XEXP (op0, 0))
10830 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10833 /* Get the two operands being compared. */
10834 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10835 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10837 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10839 /* Check for the cases where we simply want the result of the
10840 earlier test or the opposite of that result. */
10841 if (code == NE || code == EQ
10842 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10843 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10844 && (STORE_FLAG_VALUE
10845 & (((HOST_WIDE_INT) 1
10846 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10847 && (code == LT || code == GE)))
10849 enum rtx_code new_code;
10850 if (code == LT || code == NE)
10851 new_code = GET_CODE (op0);
10853 new_code = combine_reversed_comparison_code (op0);
10855 if (new_code != UNKNOWN)
10866 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10868 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10869 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10870 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10872 op0 = XEXP (op0, 1);
10873 code = (code == GE ? GT : LE);
10879 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10880 will be converted to a ZERO_EXTRACT later. */
10881 if (const_op == 0 && equality_comparison_p
10882 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10883 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10885 op0 = simplify_and_const_int
10886 (op0, mode, gen_rtx_LSHIFTRT (mode,
10888 XEXP (XEXP (op0, 0), 1)),
10889 (HOST_WIDE_INT) 1);
10893 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10894 zero and X is a comparison and C1 and C2 describe only bits set
10895 in STORE_FLAG_VALUE, we can compare with X. */
10896 if (const_op == 0 && equality_comparison_p
10897 && mode_width <= HOST_BITS_PER_WIDE_INT
10898 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10899 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10900 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10901 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10902 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10904 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10905 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10906 if ((~STORE_FLAG_VALUE & mask) == 0
10907 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10908 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10909 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10911 op0 = XEXP (XEXP (op0, 0), 0);
10916 /* If we are doing an equality comparison of an AND of a bit equal
10917 to the sign bit, replace this with a LT or GE comparison of
10918 the underlying value. */
10919 if (equality_comparison_p
10921 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10922 && mode_width <= HOST_BITS_PER_WIDE_INT
10923 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10924 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10926 op0 = XEXP (op0, 0);
10927 code = (code == EQ ? GE : LT);
10931 /* If this AND operation is really a ZERO_EXTEND from a narrower
10932 mode, the constant fits within that mode, and this is either an
10933 equality or unsigned comparison, try to do this comparison in
10934 the narrower mode. */
10935 if ((equality_comparison_p || unsigned_comparison_p)
10936 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10937 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10938 & GET_MODE_MASK (mode))
10940 && const_op >> i == 0
10941 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10943 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10947 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10948 fits in both M1 and M2 and the SUBREG is either paradoxical
10949 or represents the low part, permute the SUBREG and the AND
10951 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10953 unsigned HOST_WIDE_INT c1;
10954 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10955 /* Require an integral mode, to avoid creating something like
10957 if (SCALAR_INT_MODE_P (tmode)
10958 /* It is unsafe to commute the AND into the SUBREG if the
10959 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10960 not defined. As originally written the upper bits
10961 have a defined value due to the AND operation.
10962 However, if we commute the AND inside the SUBREG then
10963 they no longer have defined values and the meaning of
10964 the code has been changed. */
10966 #ifdef WORD_REGISTER_OPERATIONS
10967 || (mode_width > GET_MODE_BITSIZE (tmode)
10968 && mode_width <= BITS_PER_WORD)
10970 || (mode_width <= GET_MODE_BITSIZE (tmode)
10971 && subreg_lowpart_p (XEXP (op0, 0))))
10972 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10973 && mode_width <= HOST_BITS_PER_WIDE_INT
10974 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10975 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10976 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10978 && c1 != GET_MODE_MASK (tmode))
10980 op0 = gen_binary (AND, tmode,
10981 SUBREG_REG (XEXP (op0, 0)),
10982 gen_int_mode (c1, tmode));
10983 op0 = gen_lowpart_for_combine (mode, op0);
10988 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10989 if (const_op == 0 && equality_comparison_p
10990 && XEXP (op0, 1) == const1_rtx
10991 && GET_CODE (XEXP (op0, 0)) == NOT)
10993 op0 = simplify_and_const_int
10994 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10995 code = (code == NE ? EQ : NE);
10999 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11000 (eq (and (lshiftrt X) 1) 0).
11001 Also handle the case where (not X) is expressed using xor. */
11002 if (const_op == 0 && equality_comparison_p
11003 && XEXP (op0, 1) == const1_rtx
11004 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11006 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11007 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11009 if (GET_CODE (shift_op) == NOT
11010 || (GET_CODE (shift_op) == XOR
11011 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
11012 && GET_CODE (shift_count) == CONST_INT
11013 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11014 && (INTVAL (XEXP (shift_op, 1))
11015 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11017 op0 = simplify_and_const_int
11019 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11020 (HOST_WIDE_INT) 1);
11021 code = (code == NE ? EQ : NE);
11028 /* If we have (compare (ashift FOO N) (const_int C)) and
11029 the high order N bits of FOO (N+1 if an inequality comparison)
11030 are known to be zero, we can do this by comparing FOO with C
11031 shifted right N bits so long as the low-order N bits of C are
11033 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11034 && INTVAL (XEXP (op0, 1)) >= 0
11035 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11036 < HOST_BITS_PER_WIDE_INT)
11038 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11039 && mode_width <= HOST_BITS_PER_WIDE_INT
11040 && (nonzero_bits (XEXP (op0, 0), mode)
11041 & ~(mask >> (INTVAL (XEXP (op0, 1))
11042 + ! equality_comparison_p))) == 0)
11044 /* We must perform a logical shift, not an arithmetic one,
11045 as we want the top N bits of C to be zero. */
11046 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11048 temp >>= INTVAL (XEXP (op0, 1));
11049 op1 = gen_int_mode (temp, mode);
11050 op0 = XEXP (op0, 0);
11054 /* If we are doing a sign bit comparison, it means we are testing
11055 a particular bit. Convert it to the appropriate AND. */
11056 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11057 && mode_width <= HOST_BITS_PER_WIDE_INT)
11059 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11062 - INTVAL (XEXP (op0, 1)))));
11063 code = (code == LT ? NE : EQ);
11067 /* If this an equality comparison with zero and we are shifting
11068 the low bit to the sign bit, we can convert this to an AND of the
11070 if (const_op == 0 && equality_comparison_p
11071 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11072 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11075 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11076 (HOST_WIDE_INT) 1);
11082 /* If this is an equality comparison with zero, we can do this
11083 as a logical shift, which might be much simpler. */
11084 if (equality_comparison_p && const_op == 0
11085 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11087 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11089 INTVAL (XEXP (op0, 1)));
11093 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11094 do the comparison in a narrower mode. */
11095 if (! unsigned_comparison_p
11096 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11097 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11098 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11099 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11100 MODE_INT, 1)) != BLKmode
11101 && (((unsigned HOST_WIDE_INT) const_op
11102 + (GET_MODE_MASK (tmode) >> 1) + 1)
11103 <= GET_MODE_MASK (tmode)))
11105 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11109 /* Likewise if OP0 is a PLUS of a sign extension with a
11110 constant, which is usually represented with the PLUS
11111 between the shifts. */
11112 if (! unsigned_comparison_p
11113 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11114 && GET_CODE (XEXP (op0, 0)) == PLUS
11115 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11116 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11117 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11118 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11119 MODE_INT, 1)) != BLKmode
11120 && (((unsigned HOST_WIDE_INT) const_op
11121 + (GET_MODE_MASK (tmode) >> 1) + 1)
11122 <= GET_MODE_MASK (tmode)))
11124 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11125 rtx add_const = XEXP (XEXP (op0, 0), 1);
11126 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11129 op0 = gen_binary (PLUS, tmode,
11130 gen_lowpart_for_combine (tmode, inner),
11135 /* ... fall through ... */
11137 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11138 the low order N bits of FOO are known to be zero, we can do this
11139 by comparing FOO with C shifted left N bits so long as no
11140 overflow occurs. */
11141 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11142 && INTVAL (XEXP (op0, 1)) >= 0
11143 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11144 && mode_width <= HOST_BITS_PER_WIDE_INT
11145 && (nonzero_bits (XEXP (op0, 0), mode)
11146 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11147 && (((unsigned HOST_WIDE_INT) const_op
11148 + (GET_CODE (op0) != LSHIFTRT
11149 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11152 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11154 /* If the shift was logical, then we must make the condition
11156 if (GET_CODE (op0) == LSHIFTRT)
11157 code = unsigned_condition (code);
11159 const_op <<= INTVAL (XEXP (op0, 1));
11160 op1 = GEN_INT (const_op);
11161 op0 = XEXP (op0, 0);
11165 /* If we are using this shift to extract just the sign bit, we
11166 can replace this with an LT or GE comparison. */
11168 && (equality_comparison_p || sign_bit_comparison_p)
11169 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11170 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11173 op0 = XEXP (op0, 0);
11174 code = (code == NE || code == GT ? LT : GE);
11186 /* Now make any compound operations involved in this comparison. Then,
11187 check for an outmost SUBREG on OP0 that is not doing anything or is
11188 paradoxical. The latter transformation must only be performed when
11189 it is known that the "extra" bits will be the same in op0 and op1 or
11190 that they don't matter. There are three cases to consider:
11192 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11193 care bits and we can assume they have any convenient value. So
11194 making the transformation is safe.
11196 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11197 In this case the upper bits of op0 are undefined. We should not make
11198 the simplification in that case as we do not know the contents of
11201 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11202 NIL. In that case we know those bits are zeros or ones. We must
11203 also be sure that they are the same as the upper bits of op1.
11205 We can never remove a SUBREG for a non-equality comparison because
11206 the sign bit is in a different place in the underlying object. */
11208 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11209 op1 = make_compound_operation (op1, SET);
11211 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11212 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11213 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11214 && (code == NE || code == EQ))
11216 if (GET_MODE_SIZE (GET_MODE (op0))
11217 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11219 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11221 if (GET_CODE (SUBREG_REG (op0)) == REG)
11223 op0 = SUBREG_REG (op0);
11224 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11227 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11228 <= HOST_BITS_PER_WIDE_INT)
11229 && (nonzero_bits (SUBREG_REG (op0),
11230 GET_MODE (SUBREG_REG (op0)))
11231 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11233 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11235 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11236 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11237 op0 = SUBREG_REG (op0), op1 = tem;
11241 /* We now do the opposite procedure: Some machines don't have compare
11242 insns in all modes. If OP0's mode is an integer mode smaller than a
11243 word and we can't do a compare in that mode, see if there is a larger
11244 mode for which we can do the compare. There are a number of cases in
11245 which we can use the wider mode. */
11247 mode = GET_MODE (op0);
11248 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11249 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11250 && ! have_insn_for (COMPARE, mode))
11251 for (tmode = GET_MODE_WIDER_MODE (mode);
11253 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11254 tmode = GET_MODE_WIDER_MODE (tmode))
11255 if (have_insn_for (COMPARE, tmode))
11259 /* If the only nonzero bits in OP0 and OP1 are those in the
11260 narrower mode and this is an equality or unsigned comparison,
11261 we can use the wider mode. Similarly for sign-extended
11262 values, in which case it is true for all comparisons. */
11263 zero_extended = ((code == EQ || code == NE
11264 || code == GEU || code == GTU
11265 || code == LEU || code == LTU)
11266 && (nonzero_bits (op0, tmode)
11267 & ~GET_MODE_MASK (mode)) == 0
11268 && ((GET_CODE (op1) == CONST_INT
11269 || (nonzero_bits (op1, tmode)
11270 & ~GET_MODE_MASK (mode)) == 0)));
11273 || ((num_sign_bit_copies (op0, tmode)
11274 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11275 - GET_MODE_BITSIZE (mode)))
11276 && (num_sign_bit_copies (op1, tmode)
11277 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11278 - GET_MODE_BITSIZE (mode)))))
11280 /* If OP0 is an AND and we don't have an AND in MODE either,
11281 make a new AND in the proper mode. */
11282 if (GET_CODE (op0) == AND
11283 && !have_insn_for (AND, mode))
11284 op0 = gen_binary (AND, tmode,
11285 gen_lowpart_for_combine (tmode,
11287 gen_lowpart_for_combine (tmode,
11290 op0 = gen_lowpart_for_combine (tmode, op0);
11291 if (zero_extended && GET_CODE (op1) == CONST_INT)
11292 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11293 op1 = gen_lowpart_for_combine (tmode, op1);
11297 /* If this is a test for negative, we can make an explicit
11298 test of the sign bit. */
11300 if (op1 == const0_rtx && (code == LT || code == GE)
11301 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11303 op0 = gen_binary (AND, tmode,
11304 gen_lowpart_for_combine (tmode, op0),
11305 GEN_INT ((HOST_WIDE_INT) 1
11306 << (GET_MODE_BITSIZE (mode) - 1)));
11307 code = (code == LT) ? NE : EQ;
11312 #ifdef CANONICALIZE_COMPARISON
11313 /* If this machine only supports a subset of valid comparisons, see if we
11314 can convert an unsupported one into a supported one. */
11315 CANONICALIZE_COMPARISON (code, op0, op1);
11324 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11325 searching backward. */
11326 static enum rtx_code
11327 combine_reversed_comparison_code (rtx exp)
11329 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11332 if (code1 != UNKNOWN
11333 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11335 /* Otherwise try and find where the condition codes were last set and
11337 x = get_last_value (XEXP (exp, 0));
11338 if (!x || GET_CODE (x) != COMPARE)
11340 return reversed_comparison_code_parts (GET_CODE (exp),
11341 XEXP (x, 0), XEXP (x, 1), NULL);
11344 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11345 Return NULL_RTX in case we fail to do the reversal. */
11347 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
11349 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11350 if (reversed_code == UNKNOWN)
11353 return gen_binary (reversed_code, mode, op0, op1);
11356 /* Utility function for following routine. Called when X is part of a value
11357 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11358 for each register mentioned. Similar to mention_regs in cse.c */
11361 update_table_tick (rtx x)
11363 enum rtx_code code = GET_CODE (x);
11364 const char *fmt = GET_RTX_FORMAT (code);
11369 unsigned int regno = REGNO (x);
11370 unsigned int endregno
11371 = regno + (regno < FIRST_PSEUDO_REGISTER
11372 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11375 for (r = regno; r < endregno; r++)
11376 reg_last_set_table_tick[r] = label_tick;
11381 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11382 /* Note that we can't have an "E" in values stored; see
11383 get_last_value_validate. */
11386 /* Check for identical subexpressions. If x contains
11387 identical subexpression we only have to traverse one of
11390 && (GET_RTX_CLASS (code) == '2'
11391 || GET_RTX_CLASS (code) == 'c'))
11393 /* Note that at this point x1 has already been
11395 rtx x0 = XEXP (x, 0);
11396 rtx x1 = XEXP (x, 1);
11398 /* If x0 and x1 are identical then there is no need to
11403 /* If x0 is identical to a subexpression of x1 then while
11404 processing x1, x0 has already been processed. Thus we
11405 are done with x. */
11406 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11407 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11408 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11411 /* If x1 is identical to a subexpression of x0 then we
11412 still have to process the rest of x0. */
11413 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11414 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11415 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11417 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11422 update_table_tick (XEXP (x, i));
11426 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11427 are saying that the register is clobbered and we no longer know its
11428 value. If INSN is zero, don't update reg_last_set; this is only permitted
11429 with VALUE also zero and is used to invalidate the register. */
11432 record_value_for_reg (rtx reg, rtx insn, rtx value)
11434 unsigned int regno = REGNO (reg);
11435 unsigned int endregno
11436 = regno + (regno < FIRST_PSEUDO_REGISTER
11437 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11440 /* If VALUE contains REG and we have a previous value for REG, substitute
11441 the previous value. */
11442 if (value && insn && reg_overlap_mentioned_p (reg, value))
11446 /* Set things up so get_last_value is allowed to see anything set up to
11448 subst_low_cuid = INSN_CUID (insn);
11449 tem = get_last_value (reg);
11451 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11452 it isn't going to be useful and will take a lot of time to process,
11453 so just use the CLOBBER. */
11457 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11458 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11459 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11460 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11461 tem = XEXP (tem, 0);
11463 value = replace_rtx (copy_rtx (value), reg, tem);
11467 /* For each register modified, show we don't know its value, that
11468 we don't know about its bitwise content, that its value has been
11469 updated, and that we don't know the location of the death of the
11471 for (i = regno; i < endregno; i++)
11474 reg_last_set[i] = insn;
11476 reg_last_set_value[i] = 0;
11477 reg_last_set_mode[i] = 0;
11478 reg_last_set_nonzero_bits[i] = 0;
11479 reg_last_set_sign_bit_copies[i] = 0;
11480 reg_last_death[i] = 0;
11483 /* Mark registers that are being referenced in this value. */
11485 update_table_tick (value);
11487 /* Now update the status of each register being set.
11488 If someone is using this register in this block, set this register
11489 to invalid since we will get confused between the two lives in this
11490 basic block. This makes using this register always invalid. In cse, we
11491 scan the table to invalidate all entries using this register, but this
11492 is too much work for us. */
11494 for (i = regno; i < endregno; i++)
11496 reg_last_set_label[i] = label_tick;
11497 if (value && reg_last_set_table_tick[i] == label_tick)
11498 reg_last_set_invalid[i] = 1;
11500 reg_last_set_invalid[i] = 0;
11503 /* The value being assigned might refer to X (like in "x++;"). In that
11504 case, we must replace it with (clobber (const_int 0)) to prevent
11506 if (value && ! get_last_value_validate (&value, insn,
11507 reg_last_set_label[regno], 0))
11509 value = copy_rtx (value);
11510 if (! get_last_value_validate (&value, insn,
11511 reg_last_set_label[regno], 1))
11515 /* For the main register being modified, update the value, the mode, the
11516 nonzero bits, and the number of sign bit copies. */
11518 reg_last_set_value[regno] = value;
11522 enum machine_mode mode = GET_MODE (reg);
11523 subst_low_cuid = INSN_CUID (insn);
11524 reg_last_set_mode[regno] = mode;
11525 if (GET_MODE_CLASS (mode) == MODE_INT
11526 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11527 mode = nonzero_bits_mode;
11528 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11529 reg_last_set_sign_bit_copies[regno]
11530 = num_sign_bit_copies (value, GET_MODE (reg));
11534 /* Called via note_stores from record_dead_and_set_regs to handle one
11535 SET or CLOBBER in an insn. DATA is the instruction in which the
11536 set is occurring. */
11539 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11541 rtx record_dead_insn = (rtx) data;
11543 if (GET_CODE (dest) == SUBREG)
11544 dest = SUBREG_REG (dest);
11546 if (GET_CODE (dest) == REG)
11548 /* If we are setting the whole register, we know its value. Otherwise
11549 show that we don't know the value. We can handle SUBREG in
11551 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11552 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11553 else if (GET_CODE (setter) == SET
11554 && GET_CODE (SET_DEST (setter)) == SUBREG
11555 && SUBREG_REG (SET_DEST (setter)) == dest
11556 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11557 && subreg_lowpart_p (SET_DEST (setter)))
11558 record_value_for_reg (dest, record_dead_insn,
11559 gen_lowpart_for_combine (GET_MODE (dest),
11560 SET_SRC (setter)));
11562 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11564 else if (GET_CODE (dest) == MEM
11565 /* Ignore pushes, they clobber nothing. */
11566 && ! push_operand (dest, GET_MODE (dest)))
11567 mem_last_set = INSN_CUID (record_dead_insn);
11570 /* Update the records of when each REG was most recently set or killed
11571 for the things done by INSN. This is the last thing done in processing
11572 INSN in the combiner loop.
11574 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11575 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11576 and also the similar information mem_last_set (which insn most recently
11577 modified memory) and last_call_cuid (which insn was the most recent
11578 subroutine call). */
11581 record_dead_and_set_regs (rtx insn)
11586 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11588 if (REG_NOTE_KIND (link) == REG_DEAD
11589 && GET_CODE (XEXP (link, 0)) == REG)
11591 unsigned int regno = REGNO (XEXP (link, 0));
11592 unsigned int endregno
11593 = regno + (regno < FIRST_PSEUDO_REGISTER
11594 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11597 for (i = regno; i < endregno; i++)
11598 reg_last_death[i] = insn;
11600 else if (REG_NOTE_KIND (link) == REG_INC)
11601 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11604 if (GET_CODE (insn) == CALL_INSN)
11606 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11607 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11609 reg_last_set_value[i] = 0;
11610 reg_last_set_mode[i] = 0;
11611 reg_last_set_nonzero_bits[i] = 0;
11612 reg_last_set_sign_bit_copies[i] = 0;
11613 reg_last_death[i] = 0;
11616 last_call_cuid = mem_last_set = INSN_CUID (insn);
11618 /* Don't bother recording what this insn does. It might set the
11619 return value register, but we can't combine into a call
11620 pattern anyway, so there's no point trying (and it may cause
11621 a crash, if e.g. we wind up asking for last_set_value of a
11622 SUBREG of the return value register). */
11626 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11629 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11630 register present in the SUBREG, so for each such SUBREG go back and
11631 adjust nonzero and sign bit information of the registers that are
11632 known to have some zero/sign bits set.
11634 This is needed because when combine blows the SUBREGs away, the
11635 information on zero/sign bits is lost and further combines can be
11636 missed because of that. */
11639 record_promoted_value (rtx insn, rtx subreg)
11642 unsigned int regno = REGNO (SUBREG_REG (subreg));
11643 enum machine_mode mode = GET_MODE (subreg);
11645 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11648 for (links = LOG_LINKS (insn); links;)
11650 insn = XEXP (links, 0);
11651 set = single_set (insn);
11653 if (! set || GET_CODE (SET_DEST (set)) != REG
11654 || REGNO (SET_DEST (set)) != regno
11655 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11657 links = XEXP (links, 1);
11661 if (reg_last_set[regno] == insn)
11663 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11664 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11667 if (GET_CODE (SET_SRC (set)) == REG)
11669 regno = REGNO (SET_SRC (set));
11670 links = LOG_LINKS (insn);
11677 /* Scan X for promoted SUBREGs. For each one found,
11678 note what it implies to the registers used in it. */
11681 check_promoted_subreg (rtx insn, rtx x)
11683 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11684 && GET_CODE (SUBREG_REG (x)) == REG)
11685 record_promoted_value (insn, x);
11688 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11691 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11695 check_promoted_subreg (insn, XEXP (x, i));
11699 if (XVEC (x, i) != 0)
11700 for (j = 0; j < XVECLEN (x, i); j++)
11701 check_promoted_subreg (insn, XVECEXP (x, i, j));
11707 /* Utility routine for the following function. Verify that all the registers
11708 mentioned in *LOC are valid when *LOC was part of a value set when
11709 label_tick == TICK. Return 0 if some are not.
11711 If REPLACE is nonzero, replace the invalid reference with
11712 (clobber (const_int 0)) and return 1. This replacement is useful because
11713 we often can get useful information about the form of a value (e.g., if
11714 it was produced by a shift that always produces -1 or 0) even though
11715 we don't know exactly what registers it was produced from. */
11718 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11721 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11722 int len = GET_RTX_LENGTH (GET_CODE (x));
11725 if (GET_CODE (x) == REG)
11727 unsigned int regno = REGNO (x);
11728 unsigned int endregno
11729 = regno + (regno < FIRST_PSEUDO_REGISTER
11730 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11733 for (j = regno; j < endregno; j++)
11734 if (reg_last_set_invalid[j]
11735 /* If this is a pseudo-register that was only set once and not
11736 live at the beginning of the function, it is always valid. */
11737 || (! (regno >= FIRST_PSEUDO_REGISTER
11738 && REG_N_SETS (regno) == 1
11739 && (! REGNO_REG_SET_P
11740 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11741 && reg_last_set_label[j] > tick))
11744 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11750 /* If this is a memory reference, make sure that there were
11751 no stores after it that might have clobbered the value. We don't
11752 have alias info, so we assume any store invalidates it. */
11753 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11754 && INSN_CUID (insn) <= mem_last_set)
11757 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11761 for (i = 0; i < len; i++)
11765 /* Check for identical subexpressions. If x contains
11766 identical subexpression we only have to traverse one of
11769 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11770 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11772 /* Note that at this point x0 has already been checked
11773 and found valid. */
11774 rtx x0 = XEXP (x, 0);
11775 rtx x1 = XEXP (x, 1);
11777 /* If x0 and x1 are identical then x is also valid. */
11781 /* If x1 is identical to a subexpression of x0 then
11782 while checking x0, x1 has already been checked. Thus
11783 it is valid and so as x. */
11784 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11785 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11786 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11789 /* If x0 is identical to a subexpression of x1 then x is
11790 valid iff the rest of x1 is valid. */
11791 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11792 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11793 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11795 get_last_value_validate (&XEXP (x1,
11796 x0 == XEXP (x1, 0) ? 1 : 0),
11797 insn, tick, replace);
11800 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11804 /* Don't bother with these. They shouldn't occur anyway. */
11805 else if (fmt[i] == 'E')
11809 /* If we haven't found a reason for it to be invalid, it is valid. */
11813 /* Get the last value assigned to X, if known. Some registers
11814 in the value may be replaced with (clobber (const_int 0)) if their value
11815 is known longer known reliably. */
11818 get_last_value (rtx x)
11820 unsigned int regno;
11823 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11824 then convert it to the desired mode. If this is a paradoxical SUBREG,
11825 we cannot predict what values the "extra" bits might have. */
11826 if (GET_CODE (x) == SUBREG
11827 && subreg_lowpart_p (x)
11828 && (GET_MODE_SIZE (GET_MODE (x))
11829 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11830 && (value = get_last_value (SUBREG_REG (x))) != 0)
11831 return gen_lowpart_for_combine (GET_MODE (x), value);
11833 if (GET_CODE (x) != REG)
11837 value = reg_last_set_value[regno];
11839 /* If we don't have a value, or if it isn't for this basic block and
11840 it's either a hard register, set more than once, or it's a live
11841 at the beginning of the function, return 0.
11843 Because if it's not live at the beginning of the function then the reg
11844 is always set before being used (is never used without being set).
11845 And, if it's set only once, and it's always set before use, then all
11846 uses must have the same last value, even if it's not from this basic
11850 || (reg_last_set_label[regno] != label_tick
11851 && (regno < FIRST_PSEUDO_REGISTER
11852 || REG_N_SETS (regno) != 1
11853 || (REGNO_REG_SET_P
11854 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11857 /* If the value was set in a later insn than the ones we are processing,
11858 we can't use it even if the register was only set once. */
11859 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11862 /* If the value has all its registers valid, return it. */
11863 if (get_last_value_validate (&value, reg_last_set[regno],
11864 reg_last_set_label[regno], 0))
11867 /* Otherwise, make a copy and replace any invalid register with
11868 (clobber (const_int 0)). If that fails for some reason, return 0. */
11870 value = copy_rtx (value);
11871 if (get_last_value_validate (&value, reg_last_set[regno],
11872 reg_last_set_label[regno], 1))
11878 /* Return nonzero if expression X refers to a REG or to memory
11879 that is set in an instruction more recent than FROM_CUID. */
11882 use_crosses_set_p (rtx x, int from_cuid)
11886 enum rtx_code code = GET_CODE (x);
11890 unsigned int regno = REGNO (x);
11891 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11892 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11894 #ifdef PUSH_ROUNDING
11895 /* Don't allow uses of the stack pointer to be moved,
11896 because we don't know whether the move crosses a push insn. */
11897 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11900 for (; regno < endreg; regno++)
11901 if (reg_last_set[regno]
11902 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11907 if (code == MEM && mem_last_set > from_cuid)
11910 fmt = GET_RTX_FORMAT (code);
11912 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11917 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11918 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11921 else if (fmt[i] == 'e'
11922 && use_crosses_set_p (XEXP (x, i), from_cuid))
11928 /* Define three variables used for communication between the following
11931 static unsigned int reg_dead_regno, reg_dead_endregno;
11932 static int reg_dead_flag;
11934 /* Function called via note_stores from reg_dead_at_p.
11936 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11937 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11940 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11942 unsigned int regno, endregno;
11944 if (GET_CODE (dest) != REG)
11947 regno = REGNO (dest);
11948 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11949 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11951 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11952 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11955 /* Return nonzero if REG is known to be dead at INSN.
11957 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11958 referencing REG, it is dead. If we hit a SET referencing REG, it is
11959 live. Otherwise, see if it is live or dead at the start of the basic
11960 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11961 must be assumed to be always live. */
11964 reg_dead_at_p (rtx reg, rtx insn)
11969 /* Set variables for reg_dead_at_p_1. */
11970 reg_dead_regno = REGNO (reg);
11971 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11972 ? HARD_REGNO_NREGS (reg_dead_regno,
11978 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11979 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11981 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11982 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11986 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11987 beginning of function. */
11988 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11989 insn = prev_nonnote_insn (insn))
11991 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11993 return reg_dead_flag == 1 ? 1 : 0;
11995 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11999 /* Get the basic block that we were in. */
12001 block = ENTRY_BLOCK_PTR->next_bb;
12004 FOR_EACH_BB (block)
12005 if (insn == BB_HEAD (block))
12008 if (block == EXIT_BLOCK_PTR)
12012 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12013 if (REGNO_REG_SET_P (block->global_live_at_start, i))
12019 /* Note hard registers in X that are used. This code is similar to
12020 that in flow.c, but much simpler since we don't care about pseudos. */
12023 mark_used_regs_combine (rtx x)
12025 RTX_CODE code = GET_CODE (x);
12026 unsigned int regno;
12039 case ADDR_DIFF_VEC:
12042 /* CC0 must die in the insn after it is set, so we don't need to take
12043 special note of it here. */
12049 /* If we are clobbering a MEM, mark any hard registers inside the
12050 address as used. */
12051 if (GET_CODE (XEXP (x, 0)) == MEM)
12052 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12057 /* A hard reg in a wide mode may really be multiple registers.
12058 If so, mark all of them just like the first. */
12059 if (regno < FIRST_PSEUDO_REGISTER)
12061 unsigned int endregno, r;
12063 /* None of this applies to the stack, frame or arg pointers. */
12064 if (regno == STACK_POINTER_REGNUM
12065 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12066 || regno == HARD_FRAME_POINTER_REGNUM
12068 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12069 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12071 || regno == FRAME_POINTER_REGNUM)
12074 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12075 for (r = regno; r < endregno; r++)
12076 SET_HARD_REG_BIT (newpat_used_regs, r);
12082 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12084 rtx testreg = SET_DEST (x);
12086 while (GET_CODE (testreg) == SUBREG
12087 || GET_CODE (testreg) == ZERO_EXTRACT
12088 || GET_CODE (testreg) == SIGN_EXTRACT
12089 || GET_CODE (testreg) == STRICT_LOW_PART)
12090 testreg = XEXP (testreg, 0);
12092 if (GET_CODE (testreg) == MEM)
12093 mark_used_regs_combine (XEXP (testreg, 0));
12095 mark_used_regs_combine (SET_SRC (x));
12103 /* Recursively scan the operands of this expression. */
12106 const char *fmt = GET_RTX_FORMAT (code);
12108 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12111 mark_used_regs_combine (XEXP (x, i));
12112 else if (fmt[i] == 'E')
12116 for (j = 0; j < XVECLEN (x, i); j++)
12117 mark_used_regs_combine (XVECEXP (x, i, j));
12123 /* Remove register number REGNO from the dead registers list of INSN.
12125 Return the note used to record the death, if there was one. */
12128 remove_death (unsigned int regno, rtx insn)
12130 rtx note = find_regno_note (insn, REG_DEAD, regno);
12134 REG_N_DEATHS (regno)--;
12135 remove_note (insn, note);
12141 /* For each register (hardware or pseudo) used within expression X, if its
12142 death is in an instruction with cuid between FROM_CUID (inclusive) and
12143 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12144 list headed by PNOTES.
12146 That said, don't move registers killed by maybe_kill_insn.
12148 This is done when X is being merged by combination into TO_INSN. These
12149 notes will then be distributed as needed. */
12152 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
12157 enum rtx_code code = GET_CODE (x);
12161 unsigned int regno = REGNO (x);
12162 rtx where_dead = reg_last_death[regno];
12163 rtx before_dead, after_dead;
12165 /* Don't move the register if it gets killed in between from and to. */
12166 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12167 && ! reg_referenced_p (x, maybe_kill_insn))
12170 /* WHERE_DEAD could be a USE insn made by combine, so first we
12171 make sure that we have insns with valid INSN_CUID values. */
12172 before_dead = where_dead;
12173 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12174 before_dead = PREV_INSN (before_dead);
12176 after_dead = where_dead;
12177 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12178 after_dead = NEXT_INSN (after_dead);
12180 if (before_dead && after_dead
12181 && INSN_CUID (before_dead) >= from_cuid
12182 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12183 || (where_dead != after_dead
12184 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12186 rtx note = remove_death (regno, where_dead);
12188 /* It is possible for the call above to return 0. This can occur
12189 when reg_last_death points to I2 or I1 that we combined with.
12190 In that case make a new note.
12192 We must also check for the case where X is a hard register
12193 and NOTE is a death note for a range of hard registers
12194 including X. In that case, we must put REG_DEAD notes for
12195 the remaining registers in place of NOTE. */
12197 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12198 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12199 > GET_MODE_SIZE (GET_MODE (x))))
12201 unsigned int deadregno = REGNO (XEXP (note, 0));
12202 unsigned int deadend
12203 = (deadregno + HARD_REGNO_NREGS (deadregno,
12204 GET_MODE (XEXP (note, 0))));
12205 unsigned int ourend
12206 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12209 for (i = deadregno; i < deadend; i++)
12210 if (i < regno || i >= ourend)
12211 REG_NOTES (where_dead)
12212 = gen_rtx_EXPR_LIST (REG_DEAD,
12214 REG_NOTES (where_dead));
12217 /* If we didn't find any note, or if we found a REG_DEAD note that
12218 covers only part of the given reg, and we have a multi-reg hard
12219 register, then to be safe we must check for REG_DEAD notes
12220 for each register other than the first. They could have
12221 their own REG_DEAD notes lying around. */
12222 else if ((note == 0
12224 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12225 < GET_MODE_SIZE (GET_MODE (x)))))
12226 && regno < FIRST_PSEUDO_REGISTER
12227 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12229 unsigned int ourend
12230 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12231 unsigned int i, offset;
12235 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12239 for (i = regno + offset; i < ourend; i++)
12240 move_deaths (regno_reg_rtx[i],
12241 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12244 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12246 XEXP (note, 1) = *pnotes;
12250 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12252 REG_N_DEATHS (regno)++;
12258 else if (GET_CODE (x) == SET)
12260 rtx dest = SET_DEST (x);
12262 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12264 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12265 that accesses one word of a multi-word item, some
12266 piece of everything register in the expression is used by
12267 this insn, so remove any old death. */
12268 /* ??? So why do we test for equality of the sizes? */
12270 if (GET_CODE (dest) == ZERO_EXTRACT
12271 || GET_CODE (dest) == STRICT_LOW_PART
12272 || (GET_CODE (dest) == SUBREG
12273 && (((GET_MODE_SIZE (GET_MODE (dest))
12274 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12275 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12276 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12278 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12282 /* If this is some other SUBREG, we know it replaces the entire
12283 value, so use that as the destination. */
12284 if (GET_CODE (dest) == SUBREG)
12285 dest = SUBREG_REG (dest);
12287 /* If this is a MEM, adjust deaths of anything used in the address.
12288 For a REG (the only other possibility), the entire value is
12289 being replaced so the old value is not used in this insn. */
12291 if (GET_CODE (dest) == MEM)
12292 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12297 else if (GET_CODE (x) == CLOBBER)
12300 len = GET_RTX_LENGTH (code);
12301 fmt = GET_RTX_FORMAT (code);
12303 for (i = 0; i < len; i++)
12308 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12309 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12312 else if (fmt[i] == 'e')
12313 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12317 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12318 pattern of an insn. X must be a REG. */
12321 reg_bitfield_target_p (rtx x, rtx body)
12325 if (GET_CODE (body) == SET)
12327 rtx dest = SET_DEST (body);
12329 unsigned int regno, tregno, endregno, endtregno;
12331 if (GET_CODE (dest) == ZERO_EXTRACT)
12332 target = XEXP (dest, 0);
12333 else if (GET_CODE (dest) == STRICT_LOW_PART)
12334 target = SUBREG_REG (XEXP (dest, 0));
12338 if (GET_CODE (target) == SUBREG)
12339 target = SUBREG_REG (target);
12341 if (GET_CODE (target) != REG)
12344 tregno = REGNO (target), regno = REGNO (x);
12345 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12346 return target == x;
12348 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12349 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12351 return endregno > tregno && regno < endtregno;
12354 else if (GET_CODE (body) == PARALLEL)
12355 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12356 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12362 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12363 as appropriate. I3 and I2 are the insns resulting from the combination
12364 insns including FROM (I2 may be zero).
12366 Each note in the list is either ignored or placed on some insns, depending
12367 on the type of note. */
12370 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
12372 rtx note, next_note;
12375 for (note = notes; note; note = next_note)
12377 rtx place = 0, place2 = 0;
12379 /* If this NOTE references a pseudo register, ensure it references
12380 the latest copy of that register. */
12381 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12382 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12383 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12385 next_note = XEXP (note, 1);
12386 switch (REG_NOTE_KIND (note))
12390 /* Doesn't matter much where we put this, as long as it's somewhere.
12391 It is preferable to keep these notes on branches, which is most
12392 likely to be i3. */
12396 case REG_VALUE_PROFILE:
12397 /* Just get rid of this note, as it is unused later anyway. */
12400 case REG_VTABLE_REF:
12401 /* ??? Should remain with *a particular* memory load. Given the
12402 nature of vtable data, the last insn seems relatively safe. */
12406 case REG_NON_LOCAL_GOTO:
12407 if (GET_CODE (i3) == JUMP_INSN)
12409 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12415 case REG_EH_REGION:
12416 /* These notes must remain with the call or trapping instruction. */
12417 if (GET_CODE (i3) == CALL_INSN)
12419 else if (i2 && GET_CODE (i2) == CALL_INSN)
12421 else if (flag_non_call_exceptions)
12423 if (may_trap_p (i3))
12425 else if (i2 && may_trap_p (i2))
12427 /* ??? Otherwise assume we've combined things such that we
12428 can now prove that the instructions can't trap. Drop the
12429 note in this case. */
12435 case REG_ALWAYS_RETURN:
12438 /* These notes must remain with the call. It should not be
12439 possible for both I2 and I3 to be a call. */
12440 if (GET_CODE (i3) == CALL_INSN)
12442 else if (i2 && GET_CODE (i2) == CALL_INSN)
12449 /* Any clobbers for i3 may still exist, and so we must process
12450 REG_UNUSED notes from that insn.
12452 Any clobbers from i2 or i1 can only exist if they were added by
12453 recog_for_combine. In that case, recog_for_combine created the
12454 necessary REG_UNUSED notes. Trying to keep any original
12455 REG_UNUSED notes from these insns can cause incorrect output
12456 if it is for the same register as the original i3 dest.
12457 In that case, we will notice that the register is set in i3,
12458 and then add a REG_UNUSED note for the destination of i3, which
12459 is wrong. However, it is possible to have REG_UNUSED notes from
12460 i2 or i1 for register which were both used and clobbered, so
12461 we keep notes from i2 or i1 if they will turn into REG_DEAD
12464 /* If this register is set or clobbered in I3, put the note there
12465 unless there is one already. */
12466 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12468 if (from_insn != i3)
12471 if (! (GET_CODE (XEXP (note, 0)) == REG
12472 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12473 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12476 /* Otherwise, if this register is used by I3, then this register
12477 now dies here, so we must put a REG_DEAD note here unless there
12479 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12480 && ! (GET_CODE (XEXP (note, 0)) == REG
12481 ? find_regno_note (i3, REG_DEAD,
12482 REGNO (XEXP (note, 0)))
12483 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12485 PUT_REG_NOTE_KIND (note, REG_DEAD);
12493 /* These notes say something about results of an insn. We can
12494 only support them if they used to be on I3 in which case they
12495 remain on I3. Otherwise they are ignored.
12497 If the note refers to an expression that is not a constant, we
12498 must also ignore the note since we cannot tell whether the
12499 equivalence is still true. It might be possible to do
12500 slightly better than this (we only have a problem if I2DEST
12501 or I1DEST is present in the expression), but it doesn't
12502 seem worth the trouble. */
12504 if (from_insn == i3
12505 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12510 case REG_NO_CONFLICT:
12511 /* These notes say something about how a register is used. They must
12512 be present on any use of the register in I2 or I3. */
12513 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12516 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12526 /* This can show up in several ways -- either directly in the
12527 pattern, or hidden off in the constant pool with (or without?)
12528 a REG_EQUAL note. */
12529 /* ??? Ignore the without-reg_equal-note problem for now. */
12530 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12531 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12532 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12533 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12537 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12538 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12539 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12540 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12548 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12549 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12550 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12552 if (JUMP_LABEL (place) != XEXP (note, 0))
12554 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12555 LABEL_NUSES (JUMP_LABEL (place))--;
12558 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12560 if (JUMP_LABEL (place2) != XEXP (note, 0))
12562 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12563 LABEL_NUSES (JUMP_LABEL (place2))--;
12569 /* This note says something about the value of a register prior
12570 to the execution of an insn. It is too much trouble to see
12571 if the note is still correct in all situations. It is better
12572 to simply delete it. */
12576 /* If the insn previously containing this note still exists,
12577 put it back where it was. Otherwise move it to the previous
12578 insn. Adjust the corresponding REG_LIBCALL note. */
12579 if (GET_CODE (from_insn) != NOTE)
12583 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12584 place = prev_real_insn (from_insn);
12586 XEXP (tem, 0) = place;
12587 /* If we're deleting the last remaining instruction of a
12588 libcall sequence, don't add the notes. */
12589 else if (XEXP (note, 0) == from_insn)
12591 /* Don't add the dangling REG_RETVAL note. */
12598 /* This is handled similarly to REG_RETVAL. */
12599 if (GET_CODE (from_insn) != NOTE)
12603 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12604 place = next_real_insn (from_insn);
12606 XEXP (tem, 0) = place;
12607 /* If we're deleting the last remaining instruction of a
12608 libcall sequence, don't add the notes. */
12609 else if (XEXP (note, 0) == from_insn)
12611 /* Don't add the dangling REG_LIBCALL note. */
12618 /* If the register is used as an input in I3, it dies there.
12619 Similarly for I2, if it is nonzero and adjacent to I3.
12621 If the register is not used as an input in either I3 or I2
12622 and it is not one of the registers we were supposed to eliminate,
12623 there are two possibilities. We might have a non-adjacent I2
12624 or we might have somehow eliminated an additional register
12625 from a computation. For example, we might have had A & B where
12626 we discover that B will always be zero. In this case we will
12627 eliminate the reference to A.
12629 In both cases, we must search to see if we can find a previous
12630 use of A and put the death note there. */
12633 && GET_CODE (from_insn) == CALL_INSN
12634 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12636 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12638 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12639 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12644 basic_block bb = this_basic_block;
12646 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12648 if (! INSN_P (tem))
12650 if (tem == BB_HEAD (bb))
12655 /* If the register is being set at TEM, see if that is all
12656 TEM is doing. If so, delete TEM. Otherwise, make this
12657 into a REG_UNUSED note instead. Don't delete sets to
12658 global register vars. */
12659 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12660 || !global_regs[REGNO (XEXP (note, 0))])
12661 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12663 rtx set = single_set (tem);
12664 rtx inner_dest = 0;
12666 rtx cc0_setter = NULL_RTX;
12670 for (inner_dest = SET_DEST (set);
12671 (GET_CODE (inner_dest) == STRICT_LOW_PART
12672 || GET_CODE (inner_dest) == SUBREG
12673 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12674 inner_dest = XEXP (inner_dest, 0))
12677 /* Verify that it was the set, and not a clobber that
12678 modified the register.
12680 CC0 targets must be careful to maintain setter/user
12681 pairs. If we cannot delete the setter due to side
12682 effects, mark the user with an UNUSED note instead
12685 if (set != 0 && ! side_effects_p (SET_SRC (set))
12686 && rtx_equal_p (XEXP (note, 0), inner_dest)
12688 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12689 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12690 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12694 /* Move the notes and links of TEM elsewhere.
12695 This might delete other dead insns recursively.
12696 First set the pattern to something that won't use
12698 rtx old_notes = REG_NOTES (tem);
12700 PATTERN (tem) = pc_rtx;
12701 REG_NOTES (tem) = NULL;
12703 distribute_notes (old_notes, tem, tem, NULL_RTX);
12704 distribute_links (LOG_LINKS (tem));
12706 PUT_CODE (tem, NOTE);
12707 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12708 NOTE_SOURCE_FILE (tem) = 0;
12711 /* Delete the setter too. */
12714 PATTERN (cc0_setter) = pc_rtx;
12715 old_notes = REG_NOTES (cc0_setter);
12716 REG_NOTES (cc0_setter) = NULL;
12718 distribute_notes (old_notes, cc0_setter,
12719 cc0_setter, NULL_RTX);
12720 distribute_links (LOG_LINKS (cc0_setter));
12722 PUT_CODE (cc0_setter, NOTE);
12723 NOTE_LINE_NUMBER (cc0_setter)
12724 = NOTE_INSN_DELETED;
12725 NOTE_SOURCE_FILE (cc0_setter) = 0;
12729 /* If the register is both set and used here, put the
12730 REG_DEAD note here, but place a REG_UNUSED note
12731 here too unless there already is one. */
12732 else if (reg_referenced_p (XEXP (note, 0),
12737 if (! find_regno_note (tem, REG_UNUSED,
12738 REGNO (XEXP (note, 0))))
12740 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12745 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12747 /* If there isn't already a REG_UNUSED note, put one
12749 if (! find_regno_note (tem, REG_UNUSED,
12750 REGNO (XEXP (note, 0))))
12755 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12756 || (GET_CODE (tem) == CALL_INSN
12757 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12761 /* If we are doing a 3->2 combination, and we have a
12762 register which formerly died in i3 and was not used
12763 by i2, which now no longer dies in i3 and is used in
12764 i2 but does not die in i2, and place is between i2
12765 and i3, then we may need to move a link from place to
12767 if (i2 && INSN_UID (place) <= max_uid_cuid
12768 && INSN_CUID (place) > INSN_CUID (i2)
12770 && INSN_CUID (from_insn) > INSN_CUID (i2)
12771 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12773 rtx links = LOG_LINKS (place);
12774 LOG_LINKS (place) = 0;
12775 distribute_links (links);
12780 if (tem == BB_HEAD (bb))
12784 /* We haven't found an insn for the death note and it
12785 is still a REG_DEAD note, but we have hit the beginning
12786 of the block. If the existing life info says the reg
12787 was dead, there's nothing left to do. Otherwise, we'll
12788 need to do a global life update after combine. */
12789 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12790 && REGNO_REG_SET_P (bb->global_live_at_start,
12791 REGNO (XEXP (note, 0))))
12792 SET_BIT (refresh_blocks, this_basic_block->index);
12795 /* If the register is set or already dead at PLACE, we needn't do
12796 anything with this note if it is still a REG_DEAD note.
12797 We can here if it is set at all, not if is it totally replace,
12798 which is what `dead_or_set_p' checks, so also check for it being
12801 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12803 unsigned int regno = REGNO (XEXP (note, 0));
12805 /* Similarly, if the instruction on which we want to place
12806 the note is a noop, we'll need do a global live update
12807 after we remove them in delete_noop_moves. */
12808 if (noop_move_p (place))
12809 SET_BIT (refresh_blocks, this_basic_block->index);
12811 if (dead_or_set_p (place, XEXP (note, 0))
12812 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12814 /* Unless the register previously died in PLACE, clear
12815 reg_last_death. [I no longer understand why this is
12817 if (reg_last_death[regno] != place)
12818 reg_last_death[regno] = 0;
12822 reg_last_death[regno] = place;
12824 /* If this is a death note for a hard reg that is occupying
12825 multiple registers, ensure that we are still using all
12826 parts of the object. If we find a piece of the object
12827 that is unused, we must arrange for an appropriate REG_DEAD
12828 note to be added for it. However, we can't just emit a USE
12829 and tag the note to it, since the register might actually
12830 be dead; so we recourse, and the recursive call then finds
12831 the previous insn that used this register. */
12833 if (place && regno < FIRST_PSEUDO_REGISTER
12834 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12836 unsigned int endregno
12837 = regno + HARD_REGNO_NREGS (regno,
12838 GET_MODE (XEXP (note, 0)));
12842 for (i = regno; i < endregno; i++)
12843 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12844 && ! find_regno_fusage (place, USE, i))
12845 || dead_or_set_regno_p (place, i))
12850 /* Put only REG_DEAD notes for pieces that are
12851 not already dead or set. */
12853 for (i = regno; i < endregno;
12854 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12856 rtx piece = regno_reg_rtx[i];
12857 basic_block bb = this_basic_block;
12859 if (! dead_or_set_p (place, piece)
12860 && ! reg_bitfield_target_p (piece,
12864 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12866 distribute_notes (new_note, place, place,
12869 else if (! refers_to_regno_p (i, i + 1,
12870 PATTERN (place), 0)
12871 && ! find_regno_fusage (place, USE, i))
12872 for (tem = PREV_INSN (place); ;
12873 tem = PREV_INSN (tem))
12875 if (! INSN_P (tem))
12877 if (tem == BB_HEAD (bb))
12879 SET_BIT (refresh_blocks,
12880 this_basic_block->index);
12885 if (dead_or_set_p (tem, piece)
12886 || reg_bitfield_target_p (piece,
12890 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12905 /* Any other notes should not be present at this point in the
12912 XEXP (note, 1) = REG_NOTES (place);
12913 REG_NOTES (place) = note;
12915 else if ((REG_NOTE_KIND (note) == REG_DEAD
12916 || REG_NOTE_KIND (note) == REG_UNUSED)
12917 && GET_CODE (XEXP (note, 0)) == REG)
12918 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12922 if ((REG_NOTE_KIND (note) == REG_DEAD
12923 || REG_NOTE_KIND (note) == REG_UNUSED)
12924 && GET_CODE (XEXP (note, 0)) == REG)
12925 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12927 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12928 REG_NOTE_KIND (note),
12930 REG_NOTES (place2));
12935 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12936 I3, I2, and I1 to new locations. This is also called to add a link
12937 pointing at I3 when I3's destination is changed. */
12940 distribute_links (rtx links)
12942 rtx link, next_link;
12944 for (link = links; link; link = next_link)
12950 next_link = XEXP (link, 1);
12952 /* If the insn that this link points to is a NOTE or isn't a single
12953 set, ignore it. In the latter case, it isn't clear what we
12954 can do other than ignore the link, since we can't tell which
12955 register it was for. Such links wouldn't be used by combine
12958 It is not possible for the destination of the target of the link to
12959 have been changed by combine. The only potential of this is if we
12960 replace I3, I2, and I1 by I3 and I2. But in that case the
12961 destination of I2 also remains unchanged. */
12963 if (GET_CODE (XEXP (link, 0)) == NOTE
12964 || (set = single_set (XEXP (link, 0))) == 0)
12967 reg = SET_DEST (set);
12968 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12969 || GET_CODE (reg) == SIGN_EXTRACT
12970 || GET_CODE (reg) == STRICT_LOW_PART)
12971 reg = XEXP (reg, 0);
12973 /* A LOG_LINK is defined as being placed on the first insn that uses
12974 a register and points to the insn that sets the register. Start
12975 searching at the next insn after the target of the link and stop
12976 when we reach a set of the register or the end of the basic block.
12978 Note that this correctly handles the link that used to point from
12979 I3 to I2. Also note that not much searching is typically done here
12980 since most links don't point very far away. */
12982 for (insn = NEXT_INSN (XEXP (link, 0));
12983 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12984 || BB_HEAD (this_basic_block->next_bb) != insn));
12985 insn = NEXT_INSN (insn))
12986 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12988 if (reg_referenced_p (reg, PATTERN (insn)))
12992 else if (GET_CODE (insn) == CALL_INSN
12993 && find_reg_fusage (insn, USE, reg))
12998 else if (INSN_P (insn) && reg_set_p (reg, insn))
13001 /* If we found a place to put the link, place it there unless there
13002 is already a link to the same insn as LINK at that point. */
13008 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13009 if (XEXP (link2, 0) == XEXP (link, 0))
13014 XEXP (link, 1) = LOG_LINKS (place);
13015 LOG_LINKS (place) = link;
13017 /* Set added_links_insn to the earliest insn we added a
13019 if (added_links_insn == 0
13020 || INSN_CUID (added_links_insn) > INSN_CUID (place))
13021 added_links_insn = place;
13027 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13030 insn_cuid (rtx insn)
13032 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13033 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13034 insn = NEXT_INSN (insn);
13036 if (INSN_UID (insn) > max_uid_cuid)
13039 return INSN_CUID (insn);
13043 dump_combine_stats (FILE *file)
13047 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13048 combine_attempts, combine_merges, combine_extras, combine_successes);
13052 dump_combine_total_stats (FILE *file)
13056 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13057 total_attempts, total_merges, total_extras, total_successes);