2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2004, Scott Long <scottl@kfreebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/i386/pci/pci_cfgreg.c,v 1.124.2.3 2009/05/04 21:04:29 jhb
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/thread2.h>
39 #include <sys/spinlock.h>
40 #include <sys/spinlock2.h>
41 #include <sys/queue.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
44 #include "pci_cfgreg.h"
45 #include <machine/pc/bios.h>
48 #include <vm/vm_param.h>
49 #include <vm/vm_kern.h>
50 #include <vm/vm_extern.h>
52 #include <machine/pmap.h>
54 #if defined(__DragonFly__)
55 #define mtx_init(a, b, c, d) spin_init(a)
56 #define mtx_lock_spin(a) spin_lock(a)
57 #define mtx_unlock_spin(a) spin_unlock(a)
60 #define PRVERB(a) do { \
66 struct pcie_cfg_elem {
67 TAILQ_ENTRY(pcie_cfg_elem) elem;
79 static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
80 static uint64_t pcie_base;
81 static int pcie_minbus, pcie_maxbus;
82 static uint32_t pcie_badslots;
85 #if defined(__DragonFly__)
86 static struct spinlock pcicfg_mtx;
88 static struct mtx pcicfg_mtx;
90 static int mcfg_enable = 0;
92 TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
94 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg, int bytes);
95 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
96 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
97 static int pcireg_cfgopen(void);
99 static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
100 unsigned reg, unsigned bytes);
101 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
102 unsigned reg, int data, unsigned bytes);
107 * Some BIOS writers seem to want to ignore the spec and put
108 * 0 in the intline rather than 255 to indicate none. Some use
109 * numbers in the range 128-254 to indicate something strange and
110 * apparently undocumented anywhere. Assume these are completely bogus
111 * and map them to 255, which means "none".
114 pci_i386_map_intline(int line)
116 if (line == 0 || line >= 128)
117 return (PCI_INVALID_IRQ);
124 pcibios_get_version(void)
126 struct bios_regs args;
128 if (PCIbios.ventry == 0) {
129 PRVERB(("pcibios: No call entry point\n"));
132 args.eax = PCIBIOS_BIOS_PRESENT;
133 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
134 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
137 if (args.edx != 0x20494350) {
138 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
141 return (args.ebx & 0xffff);
147 * Initialise access to PCI configuration space
152 static int opened = 0;
161 if (pcireg_cfgopen() == 0)
165 v = pcibios_get_version();
167 PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
169 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
172 /* $PIR requires PCI BIOS 2.10 or greater. */
176 if (cfgmech == CFGMECH_PCIE)
180 * Grope around in the PCI config space to see if this is a
181 * chipset that is capable of doing memory-mapped config cycles.
182 * This also implies that it can do PCIe extended config cycles.
185 /* Check for supported chipsets */
186 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
187 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
193 /* Intel 7520 or 7320 */
194 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
195 pcie_cfgregopen(pciebar, 0, 255);
200 /* Intel 915, 925, or 915GM */
201 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
202 pcie_cfgregopen(pciebar, 0, 255);
214 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
217 if (cfgmech == CFGMECH_PCIE &&
218 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
219 (bus != 0 || !(1 << slot & pcie_badslots)))
220 return (pciereg_cfgread(bus, slot, func, reg, bytes));
222 return (pcireg_cfgread(bus, slot, func, reg, bytes));
226 * Read configuration space register
229 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
234 * Some BIOS writers seem to want to ignore the spec and put
235 * 0 in the intline rather than 255 to indicate none. The rest of
236 * the code uses 255 as an invalid IRQ.
238 if (reg == PCIR_INTLINE && bytes == 1) {
239 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
240 return (pci_i386_map_intline(line));
242 return (pci_docfgregread(bus, slot, func, reg, bytes));
246 * Write configuration space register
249 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
252 if (cfgmech == CFGMECH_PCIE &&
253 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
254 (bus != 0 || !(1 << slot & pcie_badslots)))
255 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
257 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
261 * Configuration space access using direct register operations
264 /* enable configuration space accesses and return data port address */
266 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
271 if (arch_i386_is_xbox) {
273 * The Xbox MCPX chipset is a derivative of the nForce 1
274 * chipset. It almost has the same bus layout; some devices
275 * cannot be used, because they have been removed.
279 * Devices 00:00.1 and 00:00.2 used to be memory controllers on
280 * the nForce chipset, but on the Xbox, using them will lockup
283 if (bus == 0 && slot == 0 && (func == 1 || func == 2))
287 * Bus 1 only contains a VGA controller at 01:00.0. When you try
288 * to probe beyond that device, you only get garbage, which
289 * could cause lockups.
291 if (bus == 1 && (slot != 0 || func != 0))
295 * Bus 2 used to contain the AGP controller, but the Xbox MCPX
296 * doesn't have one. Probing it can cause lockups.
303 if (bus <= PCI_BUSMAX
305 && func <= PCI_FUNCMAX
308 && (unsigned) bytes <= 4
309 && (reg & (bytes - 1)) == 0) {
313 outl(CONF1_ADDR_PORT, (1 << 31)
314 | (bus << 16) | (slot << 11)
315 | (func << 8) | (reg & ~0x03));
316 dataport = CONF1_DATA_PORT + (reg & 0x03);
319 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
320 outb(CONF2_FORWARD_PORT, bus);
321 dataport = 0xc000 | (slot << 8) | reg;
328 /* disable configuration space accesses */
336 * Do nothing for the config mechanism 1 case.
337 * Writing a 0 to the address port can apparently
338 * confuse some bridges and cause spurious
343 outb(CONF2_ENABLE_PORT, 0);
349 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
354 mtx_lock_spin(&pcicfg_mtx);
355 port = pci_cfgenable(bus, slot, func, reg, bytes);
370 mtx_unlock_spin(&pcicfg_mtx);
375 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
379 mtx_lock_spin(&pcicfg_mtx);
380 port = pci_cfgenable(bus, slot, func, reg, bytes);
395 mtx_unlock_spin(&pcicfg_mtx);
398 /* check whether the configuration mechanism has been correctly identified */
400 pci_cfgcheck(int maxdev)
408 kprintf("pci_cfgcheck:\tdevice ");
410 for (device = 0; device < maxdev; device++) {
412 kprintf("%d ", device);
414 port = pci_cfgenable(0, device, 0, 0, 4);
416 if (id == 0 || id == 0xffffffff)
419 port = pci_cfgenable(0, device, 0, 8, 4);
420 class = inl(port) >> 8;
422 kprintf("[class=%06x] ", class);
423 if (class == 0 || (class & 0xf870ff) != 0)
426 port = pci_cfgenable(0, device, 0, 14, 1);
429 kprintf("[hdr=%02x] ", header);
430 if ((header & 0x7e) != 0)
434 kprintf("is there (id=%08x)\n", id);
440 kprintf("-- nothing found\n");
449 uint32_t mode1res, oldval1;
450 uint8_t mode2res, oldval2;
452 /* Check for type #1 first. */
453 oldval1 = inl(CONF1_ADDR_PORT);
456 kprintf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
463 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
465 mode1res = inl(CONF1_ADDR_PORT);
466 outl(CONF1_ADDR_PORT, oldval1);
469 kprintf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
473 if (pci_cfgcheck(32))
477 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
478 mode1res = inl(CONF1_ADDR_PORT);
479 outl(CONF1_ADDR_PORT, oldval1);
482 kprintf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
485 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
486 if (pci_cfgcheck(32))
490 /* Type #1 didn't work, so try type #2. */
491 oldval2 = inb(CONF2_ENABLE_PORT);
494 kprintf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
498 if ((oldval2 & 0xf0) == 0) {
503 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
504 mode2res = inb(CONF2_ENABLE_PORT);
505 outb(CONF2_ENABLE_PORT, oldval2);
508 kprintf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
509 mode2res, CONF2_ENABLE_CHK);
511 if (mode2res == CONF2_ENABLE_RES) {
513 kprintf("pci_open(2a):\tnow trying mechanism 2\n");
515 if (pci_cfgcheck(16))
520 /* Nothing worked, so punt. */
521 cfgmech = CFGMECH_NONE;
527 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
530 struct pcie_cfg_list *pcielist;
531 struct pcie_cfg_elem *pcie_array, *elem;
545 if (base >= 0x100000000) {
548 "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
554 kprintf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
558 SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
562 pcie_array = kmalloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
564 if (pcie_array == NULL)
567 va = kmem_alloc_nofault(&kernel_map, PCIE_CACHE * PAGE_SIZE,
570 kfree(pcie_array, M_DEVBUF);
575 pcielist = &pcie_list[pc->pc_cpuid];
577 pcielist = &pcie_list[0];
579 TAILQ_INIT(pcielist);
580 for (i = 0; i < PCIE_CACHE; i++) {
581 elem = &pcie_array[i];
582 elem->vapage = va + (i * PAGE_SIZE);
584 TAILQ_INSERT_HEAD(pcielist, elem, elem);
589 pcie_minbus = minbus;
590 pcie_maxbus = maxbus;
591 cfgmech = CFGMECH_PCIE;
595 * On some AMD systems, some of the devices on bus 0 are
596 * inaccessible using memory-mapped PCI config access. Walk
597 * bus 0 looking for such devices. For these devices, we will
598 * fall back to using type 1 config access instead.
600 if (pci_cfgregopen() != 0) {
601 for (slot = 0; slot < 32; slot++) {
602 val1 = pcireg_cfgread(0, slot, 0, 0, 4);
603 if (val1 == 0xffffffff)
606 val2 = pciereg_cfgread(0, slot, 0, 0, 4);
608 pcie_badslots |= (1 << slot);
613 #else /* !PCIE_CFG_MECH */
615 #endif /* PCIE_CFG_MECH */
618 #define PCIE_PADDR(bar, reg, bus, slot, func) \
620 (((bus) & 0xff) << 20) | \
621 (((slot) & 0x1f) << 15) | \
622 (((func) & 0x7) << 12) | \
626 * Find an element in the cache that matches the physical page desired, or
627 * create a new mapping from the least recently used element.
628 * A very simple LRU algorithm is used here, does it need to be more
631 static __inline struct pcie_cfg_elem *
632 pciereg_findelem(vm_paddr_t papage)
634 struct pcie_cfg_list *pcielist;
635 struct pcie_cfg_elem *elem;
636 pcielist = &pcie_list[mycpuid];
637 TAILQ_FOREACH(elem, pcielist, elem) {
638 if (elem->papage == papage)
643 elem = TAILQ_LAST(pcielist, pcie_cfg_list);
644 if (elem->papage != 0) {
645 pmap_kremove(elem->vapage);
646 cpu_invlpg(&elem->vapage);
648 pmap_kenter(elem->vapage, papage);
649 elem->papage = papage;
652 if (elem != TAILQ_FIRST(pcielist)) {
653 TAILQ_REMOVE(pcielist, elem, elem);
654 TAILQ_INSERT_HEAD(pcielist, elem, elem);
660 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
663 struct pcie_cfg_elem *elem;
664 volatile vm_offset_t va;
665 vm_paddr_t pa, papage;
668 if (bus < pcie_minbus || bus > pcie_maxbus || slot >= 32 ||
669 func > PCI_FUNCMAX || reg >= 0x1000 || bytes > 4 || bytes == 3)
673 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
674 papage = pa & ~PAGE_MASK;
675 elem = pciereg_findelem(papage);
676 va = elem->vapage | (pa & PAGE_MASK);
680 data = *(volatile uint32_t *)(va);
683 data = *(volatile uint16_t *)(va);
686 data = *(volatile uint8_t *)(va);
695 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data, unsigned bytes)
697 struct pcie_cfg_elem *elem;
698 volatile vm_offset_t va;
699 vm_paddr_t pa, papage;
702 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
703 papage = pa & ~PAGE_MASK;
704 elem = pciereg_findelem(papage);
705 va = elem->vapage | (pa & PAGE_MASK);
709 *(volatile uint32_t *)(va) = data;
712 *(volatile uint16_t *)(va) = data;
715 *(volatile uint8_t *)(va) = data;