2 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/globaldata.h>
39 #include <machine/md_var.h>
40 #include <machine/cpufunc.h>
41 #include <machine/cpufreq.h>
44 #include "acpi_cpu_pstate.h"
46 #define AMD_APMI_HWPSTATE 0x80
48 #define AMD_MSR_PSTATE_CSR_MASK 0x7ULL
49 #define AMD1X_MSR_PSTATE_CTL 0xc0010062
50 #define AMD1X_MSR_PSTATE_ST 0xc0010063
52 #define AMD_MSR_PSTATE_EN 0x8000000000000000ULL
54 #define AMD10_MSR_PSTATE_START 0xc0010064
55 #define AMD10_MSR_PSTATE_COUNT 5
57 #define AMD0F_PST_CTL_FID(cval) (((cval) >> 0) & 0x3f)
58 #define AMD0F_PST_CTL_VID(cval) (((cval) >> 6) & 0x1f)
59 #define AMD0F_PST_CTL_VST(cval) (((cval) >> 11) & 0x7f)
60 #define AMD0F_PST_CTL_MVS(cval) (((cval) >> 18) & 0x3)
61 #define AMD0F_PST_CTL_PLLTIME(cval) (((cval) >> 20) & 0x7f)
62 #define AMD0F_PST_CTL_RVO(cval) (((cval) >> 28) & 0x3)
63 #define AMD0F_PST_CTL_IRT(cval) (((cval) >> 30) & 0x3)
65 #define AMD0F_PST_ST_FID(sval) (((sval) >> 0) & 0x3f)
66 #define AMD0F_PST_ST_VID(sval) (((sval) >> 6) & 0x3f)
68 static const struct acpi_pst_md *
69 acpi_pst_amd_probe(void);
70 static int acpi_pst_amd_check_csr(const struct acpi_pst_res *,
71 const struct acpi_pst_res *);
72 static int acpi_pst_amd1x_check_pstates(const struct acpi_pstate *, int,
74 static int acpi_pst_amd10_check_pstates(const struct acpi_pstate *, int);
75 static int acpi_pst_amd0f_check_pstates(const struct acpi_pstate *, int);
76 static int acpi_pst_amd1x_set_pstate(const struct acpi_pst_res *,
77 const struct acpi_pst_res *, const struct acpi_pstate *);
78 static int acpi_pst_amd0f_set_pstate(const struct acpi_pst_res *,
79 const struct acpi_pst_res *, const struct acpi_pstate *);
80 static const struct acpi_pstate *
81 acpi_pst_amd1x_get_pstate(const struct acpi_pst_res *,
82 const struct acpi_pstate *, int);
83 static const struct acpi_pstate *
84 acpi_pst_amd0f_get_pstate(const struct acpi_pst_res *,
85 const struct acpi_pstate *, int);
87 static const struct acpi_pst_md acpi_pst_amd10 = {
88 .pmd_check_csr = acpi_pst_amd_check_csr,
89 .pmd_check_pstates = acpi_pst_amd10_check_pstates,
90 .pmd_set_pstate = acpi_pst_amd1x_set_pstate,
91 .pmd_get_pstate = acpi_pst_amd1x_get_pstate
94 static const struct acpi_pst_md acpi_pst_amd0f = {
95 .pmd_check_csr = acpi_pst_amd_check_csr,
96 .pmd_check_pstates = acpi_pst_amd0f_check_pstates,
97 .pmd_set_pstate = acpi_pst_amd0f_set_pstate,
98 .pmd_get_pstate = acpi_pst_amd0f_get_pstate
101 const struct acpi_pst_md *
102 acpi_pst_md_probe(void)
104 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
105 return acpi_pst_amd_probe();
109 static const struct acpi_pst_md *
110 acpi_pst_amd_probe(void)
112 uint32_t regs[4], ext_family;
114 if ((cpu_id & 0x00000f00) != 0x00000f00)
117 /* Check whether APMI exists */
118 do_cpuid(0x80000000, regs);
119 if (regs[0] < 0x80000007)
123 do_cpuid(0x80000007, regs);
125 ext_family = cpu_id & 0x0ff00000;
126 switch (ext_family) {
127 case 0x00000000: /* Family 0fh */
128 if ((regs[3] & 0x06) == 0x06)
129 return &acpi_pst_amd0f;
132 case 0x00100000: /* Family 10h */
134 return &acpi_pst_amd10;
144 acpi_pst_amd_check_csr(const struct acpi_pst_res *ctrl,
145 const struct acpi_pst_res *status)
147 if (ctrl->pr_gas.SpaceId != ACPI_ADR_SPACE_FIXED_HARDWARE) {
148 kprintf("cpu%d: Invalid P-State control register\n", mycpuid);
151 if (status->pr_gas.SpaceId != ACPI_ADR_SPACE_FIXED_HARDWARE) {
152 kprintf("cpu%d: Invalid P-State status register\n", mycpuid);
159 acpi_pst_amd1x_check_pstates(const struct acpi_pstate *pstates, int npstates,
160 uint32_t msr_start, uint32_t msr_end)
165 * Make sure that related MSR P-State registers are enabled.
168 * We don't check status register value here;
169 * it will not be used.
171 for (i = 0; i < npstates; ++i) {
176 (pstates[i].st_cval & AMD_MSR_PSTATE_CSR_MASK);
177 if (msr >= msr_end) {
178 kprintf("cpu%d: MSR P-State register %#08x "
179 "does not exist\n", mycpuid, msr);
184 if ((pstate & AMD_MSR_PSTATE_EN) == 0) {
185 kprintf("cpu%d: MSR P-State register %#08x "
186 "is not enabled\n", mycpuid, msr);
194 acpi_pst_amd10_check_pstates(const struct acpi_pstate *pstates, int npstates)
196 /* Only P0-P4 are supported */
197 if (npstates > AMD10_MSR_PSTATE_COUNT) {
198 kprintf("cpu%d: only P0-P4 is allowed\n", mycpuid);
202 return acpi_pst_amd1x_check_pstates(pstates, npstates,
203 AMD10_MSR_PSTATE_START,
204 AMD10_MSR_PSTATE_START + AMD10_MSR_PSTATE_COUNT);
208 acpi_pst_amd1x_set_pstate(const struct acpi_pst_res *ctrl __unused,
209 const struct acpi_pst_res *status __unused,
210 const struct acpi_pstate *pstate)
214 cval = pstate->st_cval & AMD_MSR_PSTATE_CSR_MASK;
215 wrmsr(AMD1X_MSR_PSTATE_CTL, cval);
218 * Don't check AMD1X_MSR_PSTATE_ST here, since it is
219 * affected by various P-State limits.
222 * AMD Family 10h Processor BKDG Rev 3.20 (#31116)
223 * 2.4.2.4 P-state Transition Behavior
229 static const struct acpi_pstate *
230 acpi_pst_amd1x_get_pstate(const struct acpi_pst_res *status __unused,
231 const struct acpi_pstate *pstates, int npstates)
236 sval = rdmsr(AMD1X_MSR_PSTATE_ST) & AMD_MSR_PSTATE_CSR_MASK;
237 for (i = 0; i < npstates; ++i) {
238 if ((pstates[i].st_sval & AMD_MSR_PSTATE_CSR_MASK) == sval)
245 acpi_pst_amd0f_check_pstates(const struct acpi_pstate *pstates, int npstates)
247 struct amd0f_fidvid fv_max, fv_min;
250 amd0f_fidvid_limit(&fv_min, &fv_max);
252 for (i = 0; i < npstates; ++i) {
253 const struct acpi_pstate *p = &pstates[i];
254 uint32_t fid, vid, mvs, rvo;
257 fid = AMD0F_PST_CTL_FID(p->st_cval);
258 vid = AMD0F_PST_CTL_VID(p->st_cval);
260 if (fid > fv_max.fid || fid < fv_min.fid) {
261 kprintf("cpu%d: Invalid FID %#x [%#x, %#x]\n",
262 mycpuid, fid, fv_min.fid, fv_max.fid);
265 if (vid < fv_max.vid || vid > fv_min.vid) {
266 kprintf("cpu%d: Invalid VID %#x [%#x, %#x]\n",
267 mycpuid, vid, fv_max.vid, fv_min.fid);
271 mvs = AMD0F_PST_CTL_MVS(p->st_cval);
272 rvo = AMD0F_PST_CTL_RVO(p->st_cval);
274 /* Only 0 is allowed, i.e. 25mV stepping */
276 kprintf("cpu%d: Invalid MVS %#x\n", mycpuid, mvs);
281 mvs_mv = 25 * (1 << mvs);
283 if (rvo_mv % mvs_mv != 0) {
284 kprintf("cpu%d: Invalid MVS/RVO (%#x/%#x)\n",
293 acpi_pst_amd0f_set_pstate(const struct acpi_pst_res *ctrl __unused,
294 const struct acpi_pst_res *status __unused,
295 const struct acpi_pstate *pstate)
297 struct amd0f_fidvid fv;
298 struct amd0f_xsit xsit;
300 fv.fid = AMD0F_PST_CTL_FID(pstate->st_cval);
301 fv.vid = AMD0F_PST_CTL_VID(pstate->st_cval);
303 xsit.rvo = AMD0F_PST_CTL_RVO(pstate->st_cval);
304 xsit.mvs = AMD0F_PST_CTL_MVS(pstate->st_cval);
305 xsit.vst = AMD0F_PST_CTL_VST(pstate->st_cval);
306 xsit.pll_time = AMD0F_PST_CTL_PLLTIME(pstate->st_cval);
307 xsit.irt = AMD0F_PST_CTL_IRT(pstate->st_cval);
309 return amd0f_set_fidvid(&fv, &xsit);
312 static const struct acpi_pstate *
313 acpi_pst_amd0f_get_pstate(const struct acpi_pst_res *status __unused,
314 const struct acpi_pstate *pstates, int npstates)
316 struct amd0f_fidvid fv;
319 error = amd0f_get_fidvid(&fv);
323 for (i = 0; i < npstates; ++i) {
324 const struct acpi_pstate *p = &pstates[i];
326 if (fv.fid == AMD0F_PST_ST_FID(p->st_sval) &&
327 fv.vid == AMD0F_PST_ST_VID(p->st_sval))