1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Gareth Hughes <gareth@valinux.com>
31 * $DragonFly: src/sys/dev/drm/r128_cce.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
39 #define R128_FIFO_DEBUG 0
41 /* CCE microcode (from ATI) */
42 static u32 r128_cce_microcode[] = {
43 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
44 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
45 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
46 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
47 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
48 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
49 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
50 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
51 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
52 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
53 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
54 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
55 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
56 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
57 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
58 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
59 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
60 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
61 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
62 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
63 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
64 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
65 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
66 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
67 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
68 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
69 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
70 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
71 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
72 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
73 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
74 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
75 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
76 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
77 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
86 static int R128_READ_PLL(struct drm_device * dev, int addr)
88 drm_r128_private_t *dev_priv = dev->dev_private;
90 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
91 return R128_READ(R128_CLOCK_CNTL_DATA);
95 static void r128_status(drm_r128_private_t * dev_priv)
97 printk("GUI_STAT = 0x%08x\n",
98 (unsigned int)R128_READ(R128_GUI_STAT));
99 printk("PM4_STAT = 0x%08x\n",
100 (unsigned int)R128_READ(R128_PM4_STAT));
101 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
102 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
103 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
104 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
105 printk("PM4_MICRO_CNTL = 0x%08x\n",
106 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
107 printk("PM4_BUFFER_CNTL = 0x%08x\n",
108 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
112 /* ================================================================
113 * Engine, FIFO control
116 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
121 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
122 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
124 for (i = 0; i < dev_priv->usec_timeout; i++) {
125 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
132 DRM_ERROR("failed!\n");
137 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
141 for (i = 0; i < dev_priv->usec_timeout; i++) {
142 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
143 if (slots >= entries)
149 DRM_ERROR("failed!\n");
154 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
158 ret = r128_do_wait_for_fifo(dev_priv, 64);
162 for (i = 0; i < dev_priv->usec_timeout; i++) {
163 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
164 r128_do_pixcache_flush(dev_priv);
171 DRM_ERROR("failed!\n");
176 /* ================================================================
177 * CCE control, initialization
180 /* Load the microcode for the CCE */
181 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
187 r128_do_wait_for_idle(dev_priv);
189 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
190 for (i = 0; i < 256; i++) {
191 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
192 R128_WRITE(R128_PM4_MICROCODE_DATAL,
193 r128_cce_microcode[i * 2 + 1]);
197 /* Flush any pending commands to the CCE. This should only be used just
198 * prior to a wait for idle, as it informs the engine that the command
201 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
205 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
206 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
209 /* Wait for the CCE to go idle.
211 int r128_do_cce_idle(drm_r128_private_t * dev_priv)
215 for (i = 0; i < dev_priv->usec_timeout; i++) {
216 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
217 int pm4stat = R128_READ(R128_PM4_STAT);
218 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
219 dev_priv->cce_fifo_size) &&
220 !(pm4stat & (R128_PM4_BUSY |
221 R128_PM4_GUI_ACTIVE))) {
222 return r128_do_pixcache_flush(dev_priv);
229 DRM_ERROR("failed!\n");
230 r128_status(dev_priv);
235 /* Start the Concurrent Command Engine.
237 static void r128_do_cce_start(drm_r128_private_t * dev_priv)
239 r128_do_wait_for_idle(dev_priv);
241 R128_WRITE(R128_PM4_BUFFER_CNTL,
242 dev_priv->cce_mode | dev_priv->ring.size_l2qw
243 | R128_PM4_BUFFER_CNTL_NOUPDATE);
244 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
245 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
247 dev_priv->cce_running = 1;
250 /* Reset the Concurrent Command Engine. This will not flush any pending
251 * commands, so you must wait for the CCE command stream to complete
252 * before calling this routine.
254 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
256 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
257 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
258 dev_priv->ring.tail = 0;
261 /* Stop the Concurrent Command Engine. This will not flush any pending
262 * commands, so you must flush the command stream and wait for the CCE
263 * to go idle before calling this routine.
265 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
267 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
268 R128_WRITE(R128_PM4_BUFFER_CNTL,
269 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
271 dev_priv->cce_running = 0;
274 /* Reset the engine. This will stop the CCE if it is running.
276 static int r128_do_engine_reset(struct drm_device * dev)
278 drm_r128_private_t *dev_priv = dev->dev_private;
279 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
281 r128_do_pixcache_flush(dev_priv);
283 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
284 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
286 R128_WRITE_PLL(R128_MCLK_CNTL,
287 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
289 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
291 /* Taken from the sample code - do not change */
292 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
293 R128_READ(R128_GEN_RESET_CNTL);
294 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
295 R128_READ(R128_GEN_RESET_CNTL);
297 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
298 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
299 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
301 /* Reset the CCE ring */
302 r128_do_cce_reset(dev_priv);
304 /* The CCE is no longer running after an engine reset */
305 dev_priv->cce_running = 0;
307 /* Reset any pending vertex, indirect buffers */
308 r128_freelist_reset(dev);
313 static void r128_cce_init_ring_buffer(struct drm_device * dev,
314 drm_r128_private_t * dev_priv)
321 /* The manual (p. 2) says this address is in "VM space". This
322 * means it's an offset from the start of AGP space.
325 if (!dev_priv->is_pci)
326 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
329 ring_start = dev_priv->cce_ring->offset -
330 (unsigned long)dev->sg->virtual;
332 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
334 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
335 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
337 /* Set watermark control */
338 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
339 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
340 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
341 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
342 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
344 /* Force read. Why? Because it's in the examples... */
345 R128_READ(R128_PM4_BUFFER_ADDR);
347 /* Turn on bus mastering */
348 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
349 R128_WRITE(R128_BUS_CNTL, tmp);
352 static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
354 drm_r128_private_t *dev_priv;
358 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
359 if (dev_priv == NULL)
362 memset(dev_priv, 0, sizeof(drm_r128_private_t));
364 dev_priv->is_pci = init->is_pci;
366 if (dev_priv->is_pci && !dev->sg) {
367 DRM_ERROR("PCI GART memory not allocated!\n");
368 dev->dev_private = (void *)dev_priv;
369 r128_do_cleanup_cce(dev);
373 dev_priv->usec_timeout = init->usec_timeout;
374 if (dev_priv->usec_timeout < 1 ||
375 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
376 DRM_DEBUG("TIMEOUT problem!\n");
377 dev->dev_private = (void *)dev_priv;
378 r128_do_cleanup_cce(dev);
382 dev_priv->cce_mode = init->cce_mode;
384 /* GH: Simple idle check.
386 atomic_set(&dev_priv->idle_count, 0);
388 /* We don't support anything other than bus-mastering ring mode,
389 * but the ring can be in either AGP or PCI space for the ring
392 if ((init->cce_mode != R128_PM4_192BM) &&
393 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
394 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
395 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
396 DRM_DEBUG("Bad cce_mode!\n");
397 dev->dev_private = (void *)dev_priv;
398 r128_do_cleanup_cce(dev);
402 switch (init->cce_mode) {
403 case R128_PM4_NONPM4:
404 dev_priv->cce_fifo_size = 0;
406 case R128_PM4_192PIO:
408 dev_priv->cce_fifo_size = 192;
410 case R128_PM4_128PIO_64INDBM:
411 case R128_PM4_128BM_64INDBM:
412 dev_priv->cce_fifo_size = 128;
414 case R128_PM4_64PIO_128INDBM:
415 case R128_PM4_64BM_128INDBM:
416 case R128_PM4_64PIO_64VCBM_64INDBM:
417 case R128_PM4_64BM_64VCBM_64INDBM:
418 case R128_PM4_64PIO_64VCPIO_64INDPIO:
419 dev_priv->cce_fifo_size = 64;
423 switch (init->fb_bpp) {
425 dev_priv->color_fmt = R128_DATATYPE_RGB565;
429 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
432 dev_priv->front_offset = init->front_offset;
433 dev_priv->front_pitch = init->front_pitch;
434 dev_priv->back_offset = init->back_offset;
435 dev_priv->back_pitch = init->back_pitch;
437 switch (init->depth_bpp) {
439 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
444 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
447 dev_priv->depth_offset = init->depth_offset;
448 dev_priv->depth_pitch = init->depth_pitch;
449 dev_priv->span_offset = init->span_offset;
451 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
452 (dev_priv->front_offset >> 5));
453 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
454 (dev_priv->back_offset >> 5));
455 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
456 (dev_priv->depth_offset >> 5) |
458 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
459 (dev_priv->span_offset >> 5));
461 dev_priv->sarea = drm_getsarea(dev);
462 if (!dev_priv->sarea) {
463 DRM_ERROR("could not find sarea!\n");
464 dev->dev_private = (void *)dev_priv;
465 r128_do_cleanup_cce(dev);
469 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
470 if (!dev_priv->mmio) {
471 DRM_ERROR("could not find mmio region!\n");
472 dev->dev_private = (void *)dev_priv;
473 r128_do_cleanup_cce(dev);
476 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
477 if (!dev_priv->cce_ring) {
478 DRM_ERROR("could not find cce ring region!\n");
479 dev->dev_private = (void *)dev_priv;
480 r128_do_cleanup_cce(dev);
483 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
484 if (!dev_priv->ring_rptr) {
485 DRM_ERROR("could not find ring read pointer!\n");
486 dev->dev_private = (void *)dev_priv;
487 r128_do_cleanup_cce(dev);
490 dev->agp_buffer_token = init->buffers_offset;
491 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
492 if (!dev->agp_buffer_map) {
493 DRM_ERROR("could not find dma buffer region!\n");
494 dev->dev_private = (void *)dev_priv;
495 r128_do_cleanup_cce(dev);
499 if (!dev_priv->is_pci) {
500 dev_priv->agp_textures =
501 drm_core_findmap(dev, init->agp_textures_offset);
502 if (!dev_priv->agp_textures) {
503 DRM_ERROR("could not find agp texture region!\n");
504 dev->dev_private = (void *)dev_priv;
505 r128_do_cleanup_cce(dev);
510 dev_priv->sarea_priv =
511 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
512 init->sarea_priv_offset);
515 if (!dev_priv->is_pci) {
516 drm_core_ioremap(dev_priv->cce_ring, dev);
517 drm_core_ioremap(dev_priv->ring_rptr, dev);
518 drm_core_ioremap(dev->agp_buffer_map, dev);
519 if (!dev_priv->cce_ring->handle ||
520 !dev_priv->ring_rptr->handle ||
521 !dev->agp_buffer_map->handle) {
522 DRM_ERROR("Could not ioremap agp regions!\n");
523 dev->dev_private = (void *)dev_priv;
524 r128_do_cleanup_cce(dev);
530 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
531 dev_priv->ring_rptr->handle =
532 (void *)dev_priv->ring_rptr->offset;
533 dev->agp_buffer_map->handle =
534 (void *)dev->agp_buffer_map->offset;
538 if (!dev_priv->is_pci)
539 dev_priv->cce_buffers_offset = dev->agp->base;
542 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
544 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
545 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
546 + init->ring_size / sizeof(u32));
547 dev_priv->ring.size = init->ring_size;
548 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
550 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
552 dev_priv->ring.high_mark = 128;
554 dev_priv->sarea_priv->last_frame = 0;
555 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
557 dev_priv->sarea_priv->last_dispatch = 0;
558 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
561 if (dev_priv->is_pci) {
563 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
564 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
565 dev_priv->gart_info.addr = NULL;
566 dev_priv->gart_info.bus_addr = 0;
567 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
568 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
569 DRM_ERROR("failed to init PCI GART!\n");
570 dev->dev_private = (void *)dev_priv;
571 r128_do_cleanup_cce(dev);
574 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
579 r128_cce_init_ring_buffer(dev, dev_priv);
580 r128_cce_load_microcode(dev_priv);
582 dev->dev_private = (void *)dev_priv;
584 r128_do_engine_reset(dev);
589 int r128_do_cleanup_cce(struct drm_device * dev)
592 /* Make sure interrupts are disabled here because the uninstall ioctl
593 * may not have been called from userspace and after dev_private
594 * is freed, it's too late.
596 if (dev->irq_enabled)
597 drm_irq_uninstall(dev);
599 if (dev->dev_private) {
600 drm_r128_private_t *dev_priv = dev->dev_private;
603 if (!dev_priv->is_pci) {
604 if (dev_priv->cce_ring != NULL)
605 drm_core_ioremapfree(dev_priv->cce_ring, dev);
606 if (dev_priv->ring_rptr != NULL)
607 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
608 if (dev->agp_buffer_map != NULL) {
609 drm_core_ioremapfree(dev->agp_buffer_map, dev);
610 dev->agp_buffer_map = NULL;
615 if (dev_priv->gart_info.bus_addr)
616 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
617 DRM_ERROR("failed to cleanup PCI GART!\n");
620 drm_free(dev->dev_private, sizeof(drm_r128_private_t),
622 dev->dev_private = NULL;
628 int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
630 drm_r128_init_t *init = data;
634 LOCK_TEST_WITH_RETURN(dev, file_priv);
636 switch (init->func) {
638 return r128_do_init_cce(dev, init);
639 case R128_CLEANUP_CCE:
640 return r128_do_cleanup_cce(dev);
646 int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
648 drm_r128_private_t *dev_priv = dev->dev_private;
651 LOCK_TEST_WITH_RETURN(dev, file_priv);
653 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
654 DRM_DEBUG("while CCE running\n");
658 r128_do_cce_start(dev_priv);
663 /* Stop the CCE. The engine must have been idled before calling this
666 int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
668 drm_r128_private_t *dev_priv = dev->dev_private;
669 drm_r128_cce_stop_t *stop = data;
673 LOCK_TEST_WITH_RETURN(dev, file_priv);
675 /* Flush any pending CCE commands. This ensures any outstanding
676 * commands are exectuted by the engine before we turn it off.
679 r128_do_cce_flush(dev_priv);
682 /* If we fail to make the engine go idle, we return an error
683 * code so that the DRM ioctl wrapper can try again.
686 ret = r128_do_cce_idle(dev_priv);
691 /* Finally, we can turn off the CCE. If the engine isn't idle,
692 * we will get some dropped triangles as they won't be fully
693 * rendered before the CCE is shut down.
695 r128_do_cce_stop(dev_priv);
697 /* Reset the engine */
698 r128_do_engine_reset(dev);
703 /* Just reset the CCE ring. Called as part of an X Server engine reset.
705 int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
707 drm_r128_private_t *dev_priv = dev->dev_private;
710 LOCK_TEST_WITH_RETURN(dev, file_priv);
713 DRM_DEBUG("called before init done\n");
717 r128_do_cce_reset(dev_priv);
719 /* The CCE is no longer running after an engine reset */
720 dev_priv->cce_running = 0;
725 int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
727 drm_r128_private_t *dev_priv = dev->dev_private;
730 LOCK_TEST_WITH_RETURN(dev, file_priv);
732 if (dev_priv->cce_running) {
733 r128_do_cce_flush(dev_priv);
736 return r128_do_cce_idle(dev_priv);
739 int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
743 LOCK_TEST_WITH_RETURN(dev, file_priv);
745 return r128_do_engine_reset(dev);
748 int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
753 /* ================================================================
754 * Freelist management
756 #define R128_BUFFER_USED 0xffffffff
757 #define R128_BUFFER_FREE 0
760 static int r128_freelist_init(struct drm_device * dev)
762 struct drm_device_dma *dma = dev->dma;
763 drm_r128_private_t *dev_priv = dev->dev_private;
765 drm_r128_buf_priv_t *buf_priv;
766 drm_r128_freelist_t *entry;
769 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
770 if (dev_priv->head == NULL)
773 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
774 dev_priv->head->age = R128_BUFFER_USED;
776 for (i = 0; i < dma->buf_count; i++) {
777 buf = dma->buflist[i];
778 buf_priv = buf->dev_private;
780 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
784 entry->age = R128_BUFFER_FREE;
786 entry->prev = dev_priv->head;
787 entry->next = dev_priv->head->next;
789 dev_priv->tail = entry;
791 buf_priv->discard = 0;
792 buf_priv->dispatched = 0;
793 buf_priv->list_entry = entry;
795 dev_priv->head->next = entry;
797 if (dev_priv->head->next)
798 dev_priv->head->next->prev = entry;
806 static struct drm_buf *r128_freelist_get(struct drm_device * dev)
808 struct drm_device_dma *dma = dev->dma;
809 drm_r128_private_t *dev_priv = dev->dev_private;
810 drm_r128_buf_priv_t *buf_priv;
814 /* FIXME: Optimize -- use freelist code */
816 for (i = 0; i < dma->buf_count; i++) {
817 buf = dma->buflist[i];
818 buf_priv = buf->dev_private;
819 if (buf->file_priv == 0)
823 for (t = 0; t < dev_priv->usec_timeout; t++) {
824 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
826 for (i = 0; i < dma->buf_count; i++) {
827 buf = dma->buflist[i];
828 buf_priv = buf->dev_private;
829 if (buf->pending && buf_priv->age <= done_age) {
830 /* The buffer has been processed, so it
840 DRM_DEBUG("returning NULL!\n");
844 void r128_freelist_reset(struct drm_device * dev)
846 struct drm_device_dma *dma = dev->dma;
849 for (i = 0; i < dma->buf_count; i++) {
850 struct drm_buf *buf = dma->buflist[i];
851 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
856 /* ================================================================
857 * CCE command submission
860 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
862 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
865 for (i = 0; i < dev_priv->usec_timeout; i++) {
866 r128_update_ring_snapshot(dev_priv);
867 if (ring->space >= n)
872 /* FIXME: This is being ignored... */
873 DRM_ERROR("failed!\n");
877 static int r128_cce_get_buffers(struct drm_device * dev,
878 struct drm_file *file_priv,
884 for (i = d->granted_count; i < d->request_count; i++) {
885 buf = r128_freelist_get(dev);
889 buf->file_priv = file_priv;
891 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
894 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
903 int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
905 struct drm_device_dma *dma = dev->dma;
907 struct drm_dma *d = data;
909 LOCK_TEST_WITH_RETURN(dev, file_priv);
911 /* Please don't send us buffers.
913 if (d->send_count != 0) {
914 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
915 DRM_CURRENTPID, d->send_count);
919 /* We'll send you buffers.
921 if (d->request_count < 0 || d->request_count > dma->buf_count) {
922 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
923 DRM_CURRENTPID, d->request_count, dma->buf_count);
927 d->granted_count = 0;
929 if (d->request_count) {
930 ret = r128_cce_get_buffers(dev, file_priv, d);