1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
30 * $DragonFly: src/sys/dev/drm/radeon_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
33 #ifndef __RADEON_DRV_H__
34 #define __RADEON_DRV_H__
36 /* General customization:
39 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
41 #define DRIVER_NAME "radeon"
42 #define DRIVER_DESC "ATI Radeon"
43 #define DRIVER_DATE "20060524"
48 * 1.2 - Add vertex2 ioctl (keith)
49 * - Add stencil capability to clear ioctl (gareth, keith)
50 * - Increase MAX_TEXTURE_LEVELS (brian)
51 * 1.3 - Add cmdbuf ioctl (keith)
52 * - Add support for new radeon packets (keith)
53 * - Add getparam ioctl (keith)
54 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
55 * 1.4 - Add scratch registers to get_param ioctl.
56 * 1.5 - Add r200 packets to cmdbuf ioctl
57 * - Add r200 function to init ioctl
58 * - Add 'scalar2' instruction to cmdbuf
59 * 1.6 - Add static GART memory manager
60 * Add irq handler (won't be turned on unless X server knows to)
61 * Add irq ioctls and irq_active getparam.
62 * Add wait command for cmdbuf ioctl
63 * Add GART offset query for getparam
64 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
65 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
66 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
67 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
68 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
69 * Add 'GET' queries for starting additional clients on different VT's.
70 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
71 * Add texture rectangle support for r100.
72 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
73 * clients use to tell the DRM where they think the framebuffer is
74 * located in the card's address space
75 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
76 * and GL_EXT_blend_[func|equation]_separate on r200
77 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
78 * (No 3D support yet - just microcode loading).
79 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
80 * - Add hyperz support, add hyperz flags to clear ioctl.
81 * 1.14- Add support for color tiling
82 * - Add R100/R200 surface allocation/free support
83 * 1.15- Add support for texture micro tiling
84 * - Add support for r100 cube maps
85 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
86 * texture filtering on r200
87 * 1.17- Add initial support for R300 (3D).
88 * 1.18- Add support for GL_ATI_fragment_shader, new packets
89 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
90 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
91 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
92 * 1.19- Add support for gart table in FB memory and PCIE r300
93 * 1.20- Add support for r300 texrect
94 * 1.21- Add support for card type getparam
95 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
96 * 1.23- Add new radeon memory map work from benh
97 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
98 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
100 * 1.26- Add support for variable size PCI(E) gart aperture
101 * 1.27- Add support for IGP GART
102 * 1.28- Add support for VBL on CRTC2
105 #define DRIVER_MAJOR 1
106 #define DRIVER_MINOR 28
107 #define DRIVER_PATCHLEVEL 0
110 * Radeon chip families
138 enum radeon_cp_microcode_version {
147 enum radeon_chip_flags {
148 RADEON_FAMILY_MASK = 0x0000ffffUL,
149 RADEON_FLAGS_MASK = 0xffff0000UL,
150 RADEON_IS_MOBILITY = 0x00010000UL,
151 RADEON_IS_IGP = 0x00020000UL,
152 RADEON_SINGLE_CRTC = 0x00040000UL,
153 RADEON_IS_AGP = 0x00080000UL,
154 RADEON_HAS_HIERZ = 0x00100000UL,
155 RADEON_IS_PCIE = 0x00200000UL,
156 RADEON_NEW_MEMMAP = 0x00400000UL,
157 RADEON_IS_PCI = 0x00800000UL,
158 RADEON_IS_IGPGART = 0x01000000UL,
161 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
162 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
163 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
165 typedef struct drm_radeon_freelist {
168 struct drm_radeon_freelist *next;
169 struct drm_radeon_freelist *prev;
170 } drm_radeon_freelist_t;
172 typedef struct drm_radeon_ring_buffer {
175 int size; /* Double Words */
176 int size_l2qw; /* log2 Quad Words */
178 int rptr_update; /* Double Words */
179 int rptr_update_l2qw; /* log2 Quad Words */
181 int fetch_size; /* Double Words */
182 int fetch_size_l2ow; /* log2 Oct Words */
189 } drm_radeon_ring_buffer_t;
191 typedef struct drm_radeon_depth_clear_t {
193 u32 rb3d_zstencilcntl;
195 } drm_radeon_depth_clear_t;
197 struct drm_radeon_driver_file_fields {
198 int64_t radeon_fb_delta;
202 struct mem_block *next;
203 struct mem_block *prev;
206 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
209 struct radeon_surface {
216 struct radeon_virt_surface {
221 struct drm_file *file_priv;
224 typedef struct drm_radeon_private {
226 drm_radeon_ring_buffer_t ring;
227 drm_radeon_sarea_t *sarea_priv;
235 unsigned long gart_buffers_offset;
240 drm_radeon_freelist_t *head;
241 drm_radeon_freelist_t *tail;
243 volatile u32 *scratch;
248 int microcode_version;
252 int freelist_timeouts;
255 int last_frame_reads;
256 int last_clear_reads;
265 unsigned int front_offset;
266 unsigned int front_pitch;
267 unsigned int back_offset;
268 unsigned int back_pitch;
271 unsigned int depth_offset;
272 unsigned int depth_pitch;
274 u32 front_pitch_offset;
275 u32 back_pitch_offset;
276 u32 depth_pitch_offset;
278 drm_radeon_depth_clear_t depth_clear;
280 unsigned long ring_offset;
281 unsigned long ring_rptr_offset;
282 unsigned long buffers_offset;
283 unsigned long gart_textures_offset;
285 drm_local_map_t *sarea;
286 drm_local_map_t *mmio;
287 drm_local_map_t *cp_ring;
288 drm_local_map_t *ring_rptr;
289 drm_local_map_t *gart_textures;
291 struct mem_block *gart_heap;
292 struct mem_block *fb_heap;
295 wait_queue_head_t swi_queue;
296 atomic_t swi_emitted;
298 uint32_t irq_enable_reg;
301 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
302 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
304 unsigned long pcigart_offset;
305 unsigned int pcigart_offset_set;
306 struct drm_ati_pcigart_info gart_info;
310 /* starting from here on, data is preserved accross an open */
311 uint32_t flags; /* see radeon_chip_flags */
312 unsigned long fb_aper_offset;
314 } drm_radeon_private_t;
316 typedef struct drm_radeon_buf_priv {
318 } drm_radeon_buf_priv_t;
320 typedef struct drm_radeon_kcmd_buffer {
324 struct drm_clip_rect __user *boxes;
325 } drm_radeon_kcmd_buffer_t;
327 extern int radeon_no_wb;
328 extern struct drm_ioctl_desc radeon_ioctls[];
329 extern int radeon_max_ioctl;
331 /* Check whether the given hardware address is inside the framebuffer or the
334 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
337 u32 fb_start = dev_priv->fb_location;
338 u32 fb_end = fb_start + dev_priv->fb_size - 1;
339 u32 gart_start = dev_priv->gart_vm_start;
340 u32 gart_end = gart_start + dev_priv->gart_size - 1;
342 return ((off >= fb_start && off <= fb_end) ||
343 (off >= gart_start && off <= gart_end));
347 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
348 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
349 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
350 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
351 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
352 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
353 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
354 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
355 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
356 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
358 extern void radeon_freelist_reset(struct drm_device * dev);
359 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
361 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
363 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
365 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
366 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
367 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
368 extern void radeon_mem_takedown(struct mem_block **heap);
369 extern void radeon_mem_release(struct drm_file *file_priv,
370 struct mem_block *heap);
373 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
374 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
376 extern void radeon_do_release(struct drm_device * dev);
377 extern int radeon_driver_vblank_wait(struct drm_device * dev,
378 unsigned int *sequence);
379 extern int radeon_driver_vblank_wait2(struct drm_device * dev,
380 unsigned int *sequence);
381 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
382 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
383 extern void radeon_driver_irq_postinstall(struct drm_device * dev);
384 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
385 extern int radeon_vblank_crtc_get(struct drm_device *dev);
386 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
388 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
389 extern int radeon_driver_unload(struct drm_device *dev);
390 extern int radeon_driver_firstopen(struct drm_device *dev);
391 extern void radeon_driver_preclose(struct drm_device * dev,
392 struct drm_file *file_priv);
393 extern void radeon_driver_postclose(struct drm_device * dev,
394 struct drm_file *file_priv);
395 extern void radeon_driver_lastclose(struct drm_device * dev);
396 extern int radeon_driver_open(struct drm_device * dev,
397 struct drm_file * file_priv);
398 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
402 extern void r300_init_reg_flags(struct drm_device *dev);
404 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
405 struct drm_file *file_priv,
406 drm_radeon_kcmd_buffer_t *cmdbuf);
408 /* Flags for stats.boxes
410 #define RADEON_BOX_DMA_IDLE 0x1
411 #define RADEON_BOX_RING_FULL 0x2
412 #define RADEON_BOX_FLIP 0x4
413 #define RADEON_BOX_WAIT_IDLE 0x8
414 #define RADEON_BOX_TEXTURE_LOAD 0x10
416 /* Register definitions, register access macros and drmAddMap constants
417 * for Radeon kernel driver.
419 #define RADEON_AGP_COMMAND 0x0f60
420 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
421 # define RADEON_AGP_ENABLE (1<<8)
422 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
423 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
424 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
425 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
426 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
427 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
428 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
430 #define RADEON_BUS_CNTL 0x0030
431 # define RADEON_BUS_MASTER_DIS (1 << 6)
433 #define RADEON_CLOCK_CNTL_DATA 0x000c
434 # define RADEON_PLL_WR_EN (1 << 7)
435 #define RADEON_CLOCK_CNTL_INDEX 0x0008
436 #define RADEON_CONFIG_APER_SIZE 0x0108
437 #define RADEON_CONFIG_MEMSIZE 0x00f8
438 #define RADEON_CRTC_OFFSET 0x0224
439 #define RADEON_CRTC_OFFSET_CNTL 0x0228
440 # define RADEON_CRTC_TILE_EN (1 << 15)
441 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
442 #define RADEON_CRTC2_OFFSET 0x0324
443 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
445 #define RADEON_PCIE_INDEX 0x0030
446 #define RADEON_PCIE_DATA 0x0034
447 #define RADEON_PCIE_TX_GART_CNTL 0x10
448 # define RADEON_PCIE_TX_GART_EN (1 << 0)
449 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
450 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
451 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
452 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
453 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
454 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
455 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
456 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
457 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
458 #define RADEON_PCIE_TX_GART_BASE 0x13
459 #define RADEON_PCIE_TX_GART_START_LO 0x14
460 #define RADEON_PCIE_TX_GART_START_HI 0x15
461 #define RADEON_PCIE_TX_GART_END_LO 0x16
462 #define RADEON_PCIE_TX_GART_END_HI 0x17
464 #define RADEON_IGPGART_INDEX 0x168
465 #define RADEON_IGPGART_DATA 0x16c
466 #define RADEON_IGPGART_UNK_18 0x18
467 #define RADEON_IGPGART_CTRL 0x2b
468 #define RADEON_IGPGART_BASE_ADDR 0x2c
469 #define RADEON_IGPGART_FLUSH 0x2e
470 #define RADEON_IGPGART_ENABLE 0x38
471 #define RADEON_IGPGART_UNK_39 0x39
473 #define R520_MC_IND_INDEX 0x70
474 #define R520_MC_IND_WR_EN (1<<24)
475 #define R520_MC_IND_DATA 0x74
477 #define RV515_MC_FB_LOCATION 0x01
478 #define RV515_MC_AGP_LOCATION 0x02
480 #define R520_MC_FB_LOCATION 0x04
481 #define R520_MC_AGP_LOCATION 0x05
483 #define RADEON_MPP_TB_CONFIG 0x01c0
484 #define RADEON_MEM_CNTL 0x0140
485 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
486 #define RADEON_AGP_BASE 0x0170
488 #define RADEON_RB3D_COLOROFFSET 0x1c40
489 #define RADEON_RB3D_COLORPITCH 0x1c48
491 #define RADEON_SRC_X_Y 0x1590
493 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
494 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
495 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
496 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
497 # define RADEON_GMC_BRUSH_NONE (15 << 4)
498 # define RADEON_GMC_DST_16BPP (4 << 8)
499 # define RADEON_GMC_DST_24BPP (5 << 8)
500 # define RADEON_GMC_DST_32BPP (6 << 8)
501 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
502 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
503 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
504 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
505 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
506 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
507 # define RADEON_ROP3_S 0x00cc0000
508 # define RADEON_ROP3_P 0x00f00000
509 #define RADEON_DP_WRITE_MASK 0x16cc
510 #define RADEON_SRC_PITCH_OFFSET 0x1428
511 #define RADEON_DST_PITCH_OFFSET 0x142c
512 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
513 # define RADEON_DST_TILE_LINEAR (0 << 30)
514 # define RADEON_DST_TILE_MACRO (1 << 30)
515 # define RADEON_DST_TILE_MICRO (2 << 30)
516 # define RADEON_DST_TILE_BOTH (3 << 30)
518 #define RADEON_SCRATCH_REG0 0x15e0
519 #define RADEON_SCRATCH_REG1 0x15e4
520 #define RADEON_SCRATCH_REG2 0x15e8
521 #define RADEON_SCRATCH_REG3 0x15ec
522 #define RADEON_SCRATCH_REG4 0x15f0
523 #define RADEON_SCRATCH_REG5 0x15f4
524 #define RADEON_SCRATCH_UMSK 0x0770
525 #define RADEON_SCRATCH_ADDR 0x0774
527 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
529 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
530 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
531 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
533 #define RADEON_GEN_INT_CNTL 0x0040
534 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
535 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
536 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
537 # define RADEON_SW_INT_ENABLE (1 << 25)
539 #define RADEON_GEN_INT_STATUS 0x0044
540 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
541 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
542 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
543 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
544 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
545 # define RADEON_SW_INT_TEST (1 << 25)
546 # define RADEON_SW_INT_TEST_ACK (1 << 25)
547 # define RADEON_SW_INT_FIRE (1 << 26)
549 #define RADEON_HOST_PATH_CNTL 0x0130
550 # define RADEON_HDP_SOFT_RESET (1 << 26)
551 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
552 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
554 #define RADEON_ISYNC_CNTL 0x1724
555 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
556 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
557 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
558 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
559 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
560 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
562 #define RADEON_RBBM_GUICNTL 0x172c
563 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
564 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
565 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
566 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
568 #define RADEON_MC_AGP_LOCATION 0x014c
569 #define RADEON_MC_FB_LOCATION 0x0148
570 #define RADEON_MCLK_CNTL 0x0012
571 # define RADEON_FORCEON_MCLKA (1 << 16)
572 # define RADEON_FORCEON_MCLKB (1 << 17)
573 # define RADEON_FORCEON_YCLKA (1 << 18)
574 # define RADEON_FORCEON_YCLKB (1 << 19)
575 # define RADEON_FORCEON_MC (1 << 20)
576 # define RADEON_FORCEON_AIC (1 << 21)
578 #define RADEON_PP_BORDER_COLOR_0 0x1d40
579 #define RADEON_PP_BORDER_COLOR_1 0x1d44
580 #define RADEON_PP_BORDER_COLOR_2 0x1d48
581 #define RADEON_PP_CNTL 0x1c38
582 # define RADEON_SCISSOR_ENABLE (1 << 1)
583 #define RADEON_PP_LUM_MATRIX 0x1d00
584 #define RADEON_PP_MISC 0x1c14
585 #define RADEON_PP_ROT_MATRIX_0 0x1d58
586 #define RADEON_PP_TXFILTER_0 0x1c54
587 #define RADEON_PP_TXOFFSET_0 0x1c5c
588 #define RADEON_PP_TXFILTER_1 0x1c6c
589 #define RADEON_PP_TXFILTER_2 0x1c84
591 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
592 # define RADEON_RB2D_DC_FLUSH (3 << 0)
593 # define RADEON_RB2D_DC_FREE (3 << 2)
594 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
595 # define RADEON_RB2D_DC_BUSY (1 << 31)
596 #define RADEON_RB3D_CNTL 0x1c3c
597 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
598 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
599 # define RADEON_DITHER_ENABLE (1 << 2)
600 # define RADEON_ROUND_ENABLE (1 << 3)
601 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
602 # define RADEON_DITHER_INIT (1 << 5)
603 # define RADEON_ROP_ENABLE (1 << 6)
604 # define RADEON_STENCIL_ENABLE (1 << 7)
605 # define RADEON_Z_ENABLE (1 << 8)
606 # define RADEON_ZBLOCK16 (1 << 15)
607 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
608 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
609 #define RADEON_RB3D_DEPTHPITCH 0x1c28
610 #define RADEON_RB3D_PLANEMASK 0x1d84
611 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
612 #define RADEON_RB3D_ZCACHE_MODE 0x3250
613 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
614 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
615 # define RADEON_RB3D_ZC_FREE (1 << 2)
616 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
617 # define RADEON_RB3D_ZC_BUSY (1 << 31)
618 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
619 # define RADEON_RB3D_DC_FLUSH (3 << 0)
620 # define RADEON_RB3D_DC_FREE (3 << 2)
621 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
622 # define RADEON_RB3D_DC_BUSY (1 << 31)
623 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
624 # define RADEON_Z_TEST_MASK (7 << 4)
625 # define RADEON_Z_TEST_ALWAYS (7 << 4)
626 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
627 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
628 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
629 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
630 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
631 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
632 # define RADEON_FORCE_Z_DIRTY (1 << 29)
633 # define RADEON_Z_WRITE_ENABLE (1 << 30)
634 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
635 #define RADEON_RBBM_SOFT_RESET 0x00f0
636 # define RADEON_SOFT_RESET_CP (1 << 0)
637 # define RADEON_SOFT_RESET_HI (1 << 1)
638 # define RADEON_SOFT_RESET_SE (1 << 2)
639 # define RADEON_SOFT_RESET_RE (1 << 3)
640 # define RADEON_SOFT_RESET_PP (1 << 4)
641 # define RADEON_SOFT_RESET_E2 (1 << 5)
642 # define RADEON_SOFT_RESET_RB (1 << 6)
643 # define RADEON_SOFT_RESET_HDP (1 << 7)
645 * 6:0 Available slots in the FIFO
646 * 8 Host Interface active
647 * 9 CP request active
648 * 10 FIFO request active
649 * 11 Host Interface retry active
651 * 13 FIFO retry active
652 * 14 FIFO pipeline busy
653 * 15 Event engine busy
654 * 16 CP command stream busy
656 * 18 2D portion of render backend busy
657 * 20 3D setup engine busy
659 * 27 CBA 2D engine busy
660 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
661 * command stream queue not empty or Ring Buffer not empty
663 #define RADEON_RBBM_STATUS 0x0e40
664 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
665 /* #define RADEON_RBBM_STATUS 0x1740 */
666 /* bits 6:0 are dword slots available in the cmd fifo */
667 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
668 # define RADEON_HIRQ_ON_RBB (1 << 8)
669 # define RADEON_CPRQ_ON_RBB (1 << 9)
670 # define RADEON_CFRQ_ON_RBB (1 << 10)
671 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
672 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
673 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
674 # define RADEON_PIPE_BUSY (1 << 14)
675 # define RADEON_ENG_EV_BUSY (1 << 15)
676 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
677 # define RADEON_E2_BUSY (1 << 17)
678 # define RADEON_RB2D_BUSY (1 << 18)
679 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
680 # define RADEON_VAP_BUSY (1 << 20)
681 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
682 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
683 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
684 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
685 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
686 # define RADEON_GA_BUSY (1 << 26)
687 # define RADEON_CBA2D_BUSY (1 << 27)
688 # define RADEON_RBBM_ACTIVE (1 << 31)
689 #define RADEON_RE_LINE_PATTERN 0x1cd0
690 #define RADEON_RE_MISC 0x26c4
691 #define RADEON_RE_TOP_LEFT 0x26c0
692 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
693 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
694 #define RADEON_RE_STIPPLE_DATA 0x1ccc
696 #define RADEON_SCISSOR_TL_0 0x1cd8
697 #define RADEON_SCISSOR_BR_0 0x1cdc
698 #define RADEON_SCISSOR_TL_1 0x1ce0
699 #define RADEON_SCISSOR_BR_1 0x1ce4
700 #define RADEON_SCISSOR_TL_2 0x1ce8
701 #define RADEON_SCISSOR_BR_2 0x1cec
702 #define RADEON_SE_COORD_FMT 0x1c50
703 #define RADEON_SE_CNTL 0x1c4c
704 # define RADEON_FFACE_CULL_CW (0 << 0)
705 # define RADEON_BFACE_SOLID (3 << 1)
706 # define RADEON_FFACE_SOLID (3 << 3)
707 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
708 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
709 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
710 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
711 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
712 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
713 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
714 # define RADEON_FOG_SHADE_FLAT (1 << 14)
715 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
716 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
717 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
718 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
719 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
720 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
721 #define RADEON_SE_CNTL_STATUS 0x2140
722 #define RADEON_SE_LINE_WIDTH 0x1db8
723 #define RADEON_SE_VPORT_XSCALE 0x1d98
724 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
725 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
726 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
727 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
728 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
729 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
730 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
731 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
732 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
733 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
734 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
735 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
736 #define RADEON_SURFACE_CNTL 0x0b00
737 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
738 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
739 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
740 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
741 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
742 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
743 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
744 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
745 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
746 #define RADEON_SURFACE0_INFO 0x0b0c
747 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
748 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
749 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
750 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
751 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
752 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
753 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
754 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
755 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
756 #define RADEON_SURFACE1_INFO 0x0b1c
757 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
758 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
759 #define RADEON_SURFACE2_INFO 0x0b2c
760 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
761 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
762 #define RADEON_SURFACE3_INFO 0x0b3c
763 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
764 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
765 #define RADEON_SURFACE4_INFO 0x0b4c
766 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
767 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
768 #define RADEON_SURFACE5_INFO 0x0b5c
769 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
770 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
771 #define RADEON_SURFACE6_INFO 0x0b6c
772 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
773 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
774 #define RADEON_SURFACE7_INFO 0x0b7c
775 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
776 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
777 #define RADEON_SW_SEMAPHORE 0x013c
779 #define RADEON_WAIT_UNTIL 0x1720
780 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
781 # define RADEON_WAIT_2D_IDLE (1 << 14)
782 # define RADEON_WAIT_3D_IDLE (1 << 15)
783 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
784 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
785 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
787 #define RADEON_RB3D_ZMASKOFFSET 0x3234
788 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
789 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
790 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
793 #define RADEON_CP_ME_RAM_ADDR 0x07d4
794 #define RADEON_CP_ME_RAM_RADDR 0x07d8
795 #define RADEON_CP_ME_RAM_DATAH 0x07dc
796 #define RADEON_CP_ME_RAM_DATAL 0x07e0
798 #define RADEON_CP_RB_BASE 0x0700
799 #define RADEON_CP_RB_CNTL 0x0704
800 # define RADEON_BUF_SWAP_32BIT (2 << 16)
801 # define RADEON_RB_NO_UPDATE (1 << 27)
802 #define RADEON_CP_RB_RPTR_ADDR 0x070c
803 #define RADEON_CP_RB_RPTR 0x0710
804 #define RADEON_CP_RB_WPTR 0x0714
806 #define RADEON_CP_RB_WPTR_DELAY 0x0718
807 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
808 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
810 #define RADEON_CP_IB_BASE 0x0738
812 #define RADEON_CP_CSQ_CNTL 0x0740
813 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
814 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
815 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
816 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
817 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
818 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
819 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
821 #define RADEON_AIC_CNTL 0x01d0
822 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
823 #define RADEON_AIC_STAT 0x01d4
824 #define RADEON_AIC_PT_BASE 0x01d8
825 #define RADEON_AIC_LO_ADDR 0x01dc
826 #define RADEON_AIC_HI_ADDR 0x01e0
827 #define RADEON_AIC_TLB_ADDR 0x01e4
828 #define RADEON_AIC_TLB_DATA 0x01e8
830 /* CP command packets */
831 #define RADEON_CP_PACKET0 0x00000000
832 # define RADEON_ONE_REG_WR (1 << 15)
833 #define RADEON_CP_PACKET1 0x40000000
834 #define RADEON_CP_PACKET2 0x80000000
835 #define RADEON_CP_PACKET3 0xC0000000
836 # define RADEON_CP_NOP 0x00001000
837 # define RADEON_CP_NEXT_CHAR 0x00001900
838 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
839 # define RADEON_CP_SET_SCISSORS 0x00001E00
840 /* GEN_INDX_PRIM is unsupported starting with R300 */
841 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
842 # define RADEON_WAIT_FOR_IDLE 0x00002600
843 # define RADEON_3D_DRAW_VBUF 0x00002800
844 # define RADEON_3D_DRAW_IMMD 0x00002900
845 # define RADEON_3D_DRAW_INDX 0x00002A00
846 # define RADEON_CP_LOAD_PALETTE 0x00002C00
847 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
848 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
849 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
850 # define RADEON_3D_CLEAR_ZMASK 0x00003200
851 # define RADEON_CP_INDX_BUFFER 0x00003300
852 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
853 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
854 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
855 # define RADEON_3D_CLEAR_HIZ 0x00003700
856 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
857 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
858 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
859 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
860 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
862 #define RADEON_CP_PACKET_MASK 0xC0000000
863 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
864 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
865 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
866 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
868 #define RADEON_VTX_Z_PRESENT (1 << 31)
869 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
871 #define RADEON_PRIM_TYPE_NONE (0 << 0)
872 #define RADEON_PRIM_TYPE_POINT (1 << 0)
873 #define RADEON_PRIM_TYPE_LINE (2 << 0)
874 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
875 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
876 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
877 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
878 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
879 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
880 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
881 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
882 #define RADEON_PRIM_TYPE_MASK 0xf
883 #define RADEON_PRIM_WALK_IND (1 << 4)
884 #define RADEON_PRIM_WALK_LIST (2 << 4)
885 #define RADEON_PRIM_WALK_RING (3 << 4)
886 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
887 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
888 #define RADEON_MAOS_ENABLE (1 << 7)
889 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
890 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
891 #define RADEON_NUM_VERTICES_SHIFT 16
893 #define RADEON_COLOR_FORMAT_CI8 2
894 #define RADEON_COLOR_FORMAT_ARGB1555 3
895 #define RADEON_COLOR_FORMAT_RGB565 4
896 #define RADEON_COLOR_FORMAT_ARGB8888 6
897 #define RADEON_COLOR_FORMAT_RGB332 7
898 #define RADEON_COLOR_FORMAT_RGB8 9
899 #define RADEON_COLOR_FORMAT_ARGB4444 15
901 #define RADEON_TXFORMAT_I8 0
902 #define RADEON_TXFORMAT_AI88 1
903 #define RADEON_TXFORMAT_RGB332 2
904 #define RADEON_TXFORMAT_ARGB1555 3
905 #define RADEON_TXFORMAT_RGB565 4
906 #define RADEON_TXFORMAT_ARGB4444 5
907 #define RADEON_TXFORMAT_ARGB8888 6
908 #define RADEON_TXFORMAT_RGBA8888 7
909 #define RADEON_TXFORMAT_Y8 8
910 #define RADEON_TXFORMAT_VYUY422 10
911 #define RADEON_TXFORMAT_YVYU422 11
912 #define RADEON_TXFORMAT_DXT1 12
913 #define RADEON_TXFORMAT_DXT23 14
914 #define RADEON_TXFORMAT_DXT45 15
916 #define R200_PP_TXCBLEND_0 0x2f00
917 #define R200_PP_TXCBLEND_1 0x2f10
918 #define R200_PP_TXCBLEND_2 0x2f20
919 #define R200_PP_TXCBLEND_3 0x2f30
920 #define R200_PP_TXCBLEND_4 0x2f40
921 #define R200_PP_TXCBLEND_5 0x2f50
922 #define R200_PP_TXCBLEND_6 0x2f60
923 #define R200_PP_TXCBLEND_7 0x2f70
924 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
925 #define R200_PP_TFACTOR_0 0x2ee0
926 #define R200_SE_VTX_FMT_0 0x2088
927 #define R200_SE_VAP_CNTL 0x2080
928 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
929 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
930 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
931 #define R200_PP_TXFILTER_5 0x2ca0
932 #define R200_PP_TXFILTER_4 0x2c80
933 #define R200_PP_TXFILTER_3 0x2c60
934 #define R200_PP_TXFILTER_2 0x2c40
935 #define R200_PP_TXFILTER_1 0x2c20
936 #define R200_PP_TXFILTER_0 0x2c00
937 #define R200_PP_TXOFFSET_5 0x2d78
938 #define R200_PP_TXOFFSET_4 0x2d60
939 #define R200_PP_TXOFFSET_3 0x2d48
940 #define R200_PP_TXOFFSET_2 0x2d30
941 #define R200_PP_TXOFFSET_1 0x2d18
942 #define R200_PP_TXOFFSET_0 0x2d00
944 #define R200_PP_CUBIC_FACES_0 0x2c18
945 #define R200_PP_CUBIC_FACES_1 0x2c38
946 #define R200_PP_CUBIC_FACES_2 0x2c58
947 #define R200_PP_CUBIC_FACES_3 0x2c78
948 #define R200_PP_CUBIC_FACES_4 0x2c98
949 #define R200_PP_CUBIC_FACES_5 0x2cb8
950 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
951 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
952 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
953 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
954 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
955 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
956 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
957 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
958 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
959 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
960 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
961 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
962 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
963 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
964 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
965 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
966 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
967 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
968 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
969 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
970 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
971 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
972 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
973 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
974 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
975 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
976 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
977 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
978 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
979 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
981 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
982 #define R200_SE_VTE_CNTL 0x20b0
983 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
984 #define R200_PP_TAM_DEBUG3 0x2d9c
985 #define R200_PP_CNTL_X 0x2cc4
986 #define R200_SE_VAP_CNTL_STATUS 0x2140
987 #define R200_RE_SCISSOR_TL_0 0x1cd8
988 #define R200_RE_SCISSOR_TL_1 0x1ce0
989 #define R200_RE_SCISSOR_TL_2 0x1ce8
990 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
991 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
992 #define R200_SE_VTX_STATE_CNTL 0x2180
993 #define R200_RE_POINTSIZE 0x2648
994 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
996 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
997 #define RADEON_PP_TEX_SIZE_1 0x1d0c
998 #define RADEON_PP_TEX_SIZE_2 0x1d14
1000 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1001 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1002 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1003 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1004 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1005 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1007 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1009 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1010 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1011 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1012 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1013 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1014 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1015 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1016 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1017 #define R200_3D_DRAW_IMMD_2 0xC0003500
1018 #define R200_SE_VTX_FMT_1 0x208c
1019 #define R200_RE_CNTL 0x1c50
1021 #define R200_RB3D_BLENDCOLOR 0x3218
1023 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1025 #define R200_PP_TRI_PERF 0x2cf8
1027 #define R200_PP_AFS_0 0x2f80
1028 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1030 #define R200_VAP_PVS_CNTL_1 0x22D0
1032 /* MPEG settings from VHA code */
1033 #define RADEON_VHA_SETTO16_1 0x2694
1034 #define RADEON_VHA_SETTO16_2 0x2680
1035 #define RADEON_VHA_SETTO0_1 0x1840
1036 #define RADEON_VHA_FB_OFFSET 0x19e4
1037 #define RADEON_VHA_SETTO1AND70S 0x19d8
1038 #define RADEON_VHA_DST_PITCH 0x1408
1040 /* set as reference header */
1041 #define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840
1042 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844
1043 #define RADEON_VHA_BACKFRAME0_OFF_U 0x1848
1044 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c
1045 #define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850
1046 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854
1047 #define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858
1048 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c
1049 #define RADEON_VHA_FORWFRAME0_OFF_U 0x1860
1050 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864
1051 #define RADEON_VHA_FORWFRAME0_OFF_V 0x1868
1052 #define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880
1053 #define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884
1054 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888
1055 #define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c
1056 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890
1057 #define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894
1058 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898
1063 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1065 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1066 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1067 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1068 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1069 #define RADEON_LAST_DISPATCH 1
1071 #define RADEON_MAX_VB_AGE 0x7fffffff
1072 #define RADEON_MAX_VB_VERTS (0xffff)
1074 #define RADEON_RING_HIGH_MARK 128
1076 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1078 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1079 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1080 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1081 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1083 #define RADEON_WRITE_PLL( addr, val ) \
1085 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
1086 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1087 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
1090 #define RADEON_WRITE_IGPGART( addr, val ) \
1092 RADEON_WRITE( RADEON_IGPGART_INDEX, \
1093 ((addr) & 0x7f) | (1 << 8)); \
1094 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
1095 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
1098 #define RADEON_WRITE_PCIE( addr, val ) \
1100 RADEON_WRITE8( RADEON_PCIE_INDEX, \
1102 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
1105 #define RADEON_WRITE_MCIND( addr, val ) \
1107 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1108 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1109 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1112 #define CP_PACKET0( reg, n ) \
1113 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1114 #define CP_PACKET0_TABLE( reg, n ) \
1115 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1116 #define CP_PACKET1( reg0, reg1 ) \
1117 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1118 #define CP_PACKET2() \
1120 #define CP_PACKET3( pkt, n ) \
1121 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1123 /* ================================================================
1124 * Engine control helper macros
1127 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1128 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1129 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1130 RADEON_WAIT_HOST_IDLECLEAN) ); \
1133 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1134 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1135 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1136 RADEON_WAIT_HOST_IDLECLEAN) ); \
1139 #define RADEON_WAIT_UNTIL_IDLE() do { \
1140 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1141 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1142 RADEON_WAIT_3D_IDLECLEAN | \
1143 RADEON_WAIT_HOST_IDLECLEAN) ); \
1146 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1147 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1148 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1151 #define RADEON_FLUSH_CACHE() do { \
1152 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1153 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1156 #define RADEON_PURGE_CACHE() do { \
1157 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1158 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1161 #define RADEON_FLUSH_ZCACHE() do { \
1162 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1163 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1166 #define RADEON_PURGE_ZCACHE() do { \
1167 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1168 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1171 /* ================================================================
1172 * Misc helper macros
1175 /* Perfbox functionality only.
1177 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1179 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1180 u32 head = GET_RING_HEAD( dev_priv ); \
1181 if (head == dev_priv->ring.tail) \
1182 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1186 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1188 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1189 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1190 int __ret = radeon_do_cp_idle( dev_priv ); \
1191 if ( __ret ) return __ret; \
1192 sarea_priv->last_dispatch = 0; \
1193 radeon_freelist_reset( dev ); \
1197 #define RADEON_DISPATCH_AGE( age ) do { \
1198 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1202 #define RADEON_FRAME_AGE( age ) do { \
1203 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1207 #define RADEON_CLEAR_AGE( age ) do { \
1208 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1212 /* ================================================================
1216 #define RADEON_VERBOSE 0
1218 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1220 #define BEGIN_RING( n ) do { \
1221 if ( RADEON_VERBOSE ) { \
1222 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1224 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1226 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1228 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1229 ring = dev_priv->ring.start; \
1230 write = dev_priv->ring.tail; \
1231 mask = dev_priv->ring.tail_mask; \
1234 #define ADVANCE_RING() do { \
1235 if ( RADEON_VERBOSE ) { \
1236 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1237 write, dev_priv->ring.tail ); \
1239 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1241 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1242 ((dev_priv->ring.tail + _nr) & mask), \
1245 dev_priv->ring.tail = write; \
1248 #define COMMIT_RING() do { \
1249 /* Flush writes to ring */ \
1250 DRM_MEMORYBARRIER(); \
1251 GET_RING_HEAD( dev_priv ); \
1252 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1253 /* read from PCI bus to ensure correct posting */ \
1254 RADEON_READ( RADEON_CP_RB_RPTR ); \
1257 #define OUT_RING( x ) do { \
1258 if ( RADEON_VERBOSE ) { \
1259 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1260 (unsigned int)(x), write ); \
1262 ring[write++] = (x); \
1266 #define OUT_RING_REG( reg, val ) do { \
1267 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1271 #define OUT_RING_TABLE( tab, sz ) do { \
1273 int *_tab = (int *)(tab); \
1275 if (write + _size > mask) { \
1276 int _i = (mask+1) - write; \
1279 *(int *)(ring + write) = *_tab++; \
1286 while (_size > 0) { \
1287 *(ring + write) = *_tab++; \
1294 #endif /* __RADEON_DRV_H__ */