sys/dev/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <uapi_drm/radeon_drm.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "atom.h"
  36 #include "rv770_dpm.h"
  37 #include "ni_dpm.h"
  38
  39 /*
  40  * Registers accessors functions.
  41  */
  42 /**
  43  * radeon_invalid_rreg - dummy reg read function
  44  *
  45  * @rdev: radeon device pointer
  46  * @reg: offset of register
  47  *
  48  * Dummy register read function.  Used for register blocks
  49  * that certain asics don't have (all asics).
  50  * Returns the value in the register.
  51  */
  52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  53 {
  54         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  55         BUG_ON(1);
  56         return 0;
  57 }
  58
  59 /**
  60  * radeon_invalid_wreg - dummy reg write function
  61  *
  62  * @rdev: radeon device pointer
  63  * @reg: offset of register
  64  * @v: value to write to the register
  65  *
  66  * Dummy register read function.  Used for register blocks
  67  * that certain asics don't have (all asics).
  68  */
  69 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  70 {
  71         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  72                   reg, v);
  73         BUG_ON(1);
  74 }
  75
  76 /**
  77  * radeon_register_accessor_init - sets up the register accessor callbacks
  78  *
  79  * @rdev: radeon device pointer
  80  *
  81  * Sets up the register accessor callbacks for various register
  82  * apertures.  Not all asics have all apertures (all asics).
  83  */
  84 static void radeon_register_accessor_init(struct radeon_device *rdev)
  85 {
  86         rdev->mc_rreg = &radeon_invalid_rreg;
  87         rdev->mc_wreg = &radeon_invalid_wreg;
  88         rdev->pll_rreg = &radeon_invalid_rreg;
  89         rdev->pll_wreg = &radeon_invalid_wreg;
  90         rdev->pciep_rreg = &radeon_invalid_rreg;
  91         rdev->pciep_wreg = &radeon_invalid_wreg;
  92
  93         /* Don't change order as we are overridding accessor. */
  94         if (rdev->family < CHIP_RV515) {
  95                 rdev->pcie_reg_mask = 0xff;
  96         } else {
  97                 rdev->pcie_reg_mask = 0x7ff;
  98         }
  99         /* FIXME: not sure here */
 100         if (rdev->family <= CHIP_R580) {
 101                 rdev->pll_rreg = &r100_pll_rreg;
 102                 rdev->pll_wreg = &r100_pll_wreg;
 103         }
 104         if (rdev->family >= CHIP_R420) {
 105                 rdev->mc_rreg = &r420_mc_rreg;
 106                 rdev->mc_wreg = &r420_mc_wreg;
 107         }
 108         if (rdev->family >= CHIP_RV515) {
 109                 rdev->mc_rreg = &rv515_mc_rreg;
 110                 rdev->mc_wreg = &rv515_mc_wreg;
 111         }
 112         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 113                 rdev->mc_rreg = &rs400_mc_rreg;
 114                 rdev->mc_wreg = &rs400_mc_wreg;
 115         }
 116         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 117                 rdev->mc_rreg = &rs690_mc_rreg;
 118                 rdev->mc_wreg = &rs690_mc_wreg;
 119         }
 120         if (rdev->family == CHIP_RS600) {
 121                 rdev->mc_rreg = &rs600_mc_rreg;
 122                 rdev->mc_wreg = &rs600_mc_wreg;
 123         }
 124         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 125                 rdev->mc_rreg = &rs780_mc_rreg;
 126                 rdev->mc_wreg = &rs780_mc_wreg;
 127         }
 128
 129         if (rdev->family >= CHIP_BONAIRE) {
 130                 rdev->pciep_rreg = &cik_pciep_rreg;
 131                 rdev->pciep_wreg = &cik_pciep_wreg;
 132         } else if (rdev->family >= CHIP_R600) {
 133                 rdev->pciep_rreg = &r600_pciep_rreg;
 134                 rdev->pciep_wreg = &r600_pciep_wreg;
 135         }
 136 }
 137
 138
 139 /* helper to disable agp */
 140 /**
 141  * radeon_agp_disable - AGP disable helper function
 142  *
 143  * @rdev: radeon device pointer
 144  *
 145  * Removes AGP flags and changes the gart callbacks on AGP
 146  * cards when using the internal gart rather than AGP (all asics).
 147  */
 148 void radeon_agp_disable(struct radeon_device *rdev)
 149 {
 150         rdev->flags &= ~RADEON_IS_AGP;
 151         if (rdev->family >= CHIP_R600) {
 152                 DRM_INFO("Forcing AGP to PCIE mode\n");
 153                 rdev->flags |= RADEON_IS_PCIE;
 154         } else if (rdev->family >= CHIP_RV515 ||
 155                         rdev->family == CHIP_RV380 ||
 156                         rdev->family == CHIP_RV410 ||
 157                         rdev->family == CHIP_R423) {
 158                 DRM_INFO("Forcing AGP to PCIE mode\n");
 159                 rdev->flags |= RADEON_IS_PCIE;
 160                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 161                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 162         } else {
 163                 DRM_INFO("Forcing AGP to PCI mode\n");
 164                 rdev->flags |= RADEON_IS_PCI;
 165                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 166                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 167         }
 168         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 169 }
 170
 171 /*
 172  * ASIC
 173  */
 174
 175 static struct radeon_asic_ring r100_gfx_ring = {
 176         .ib_execute = &r100_ring_ib_execute,
 177         .emit_fence = &r100_fence_ring_emit,
 178         .emit_semaphore = &r100_semaphore_ring_emit,
 179         .cs_parse = &r100_cs_parse,
 180         .ring_start = &r100_ring_start,
 181         .ring_test = &r100_ring_test,
 182         .ib_test = &r100_ib_test,
 183         .is_lockup = &r100_gpu_is_lockup,
 184         .get_rptr = &radeon_ring_generic_get_rptr,
 185         .get_wptr = &radeon_ring_generic_get_wptr,
 186         .set_wptr = &radeon_ring_generic_set_wptr,
 187 };
 188
 189 static struct radeon_asic r100_asic = {
 190         .init = &r100_init,
 191         .fini = &r100_fini,
 192         .suspend = &r100_suspend,
 193         .resume = &r100_resume,
 194         .vga_set_state = &r100_vga_set_state,
 195         .asic_reset = &r100_asic_reset,
 196         .ioctl_wait_idle = NULL,
 197         .gui_idle = &r100_gui_idle,
 198         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 199         .gart = {
 200                 .tlb_flush = &r100_pci_gart_tlb_flush,
 201                 .set_page = &r100_pci_gart_set_page,
 202         },
 203         .ring = {
 204                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 205         },
 206         .irq = {
 207                 .set = &r100_irq_set,
 208                 .process = &r100_irq_process,
 209         },
 210         .display = {
 211                 .bandwidth_update = &r100_bandwidth_update,
 212                 .get_vblank_counter = &r100_get_vblank_counter,
 213                 .wait_for_vblank = &r100_wait_for_vblank,
 214                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 215                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 216         },
 217         .copy = {
 218                 .blit = &r100_copy_blit,
 219                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 220                 .dma = NULL,
 221                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 222                 .copy = &r100_copy_blit,
 223                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 224         },
 225         .surface = {
 226                 .set_reg = r100_set_surface_reg,
 227                 .clear_reg = r100_clear_surface_reg,
 228         },
 229         .hpd = {
 230                 .init = &r100_hpd_init,
 231                 .fini = &r100_hpd_fini,
 232                 .sense = &r100_hpd_sense,
 233                 .set_polarity = &r100_hpd_set_polarity,
 234         },
 235         .pm = {
 236                 .misc = &r100_pm_misc,
 237                 .prepare = &r100_pm_prepare,
 238                 .finish = &r100_pm_finish,
 239                 .init_profile = &r100_pm_init_profile,
 240                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 241                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 242                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 243                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 244                 .set_memory_clock = NULL,
 245                 .get_pcie_lanes = NULL,
 246                 .set_pcie_lanes = NULL,
 247                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 248         },
 249         .pflip = {
 250                 .pre_page_flip = &r100_pre_page_flip,
 251                 .page_flip = &r100_page_flip,
 252                 .post_page_flip = &r100_post_page_flip,
 253         },
 254 };
 255
 256 static struct radeon_asic r200_asic = {
 257         .init = &r100_init,
 258         .fini = &r100_fini,
 259         .suspend = &r100_suspend,
 260         .resume = &r100_resume,
 261         .vga_set_state = &r100_vga_set_state,
 262         .asic_reset = &r100_asic_reset,
 263         .ioctl_wait_idle = NULL,
 264         .gui_idle = &r100_gui_idle,
 265         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 266         .gart = {
 267                 .tlb_flush = &r100_pci_gart_tlb_flush,
 268                 .set_page = &r100_pci_gart_set_page,
 269         },
 270         .ring = {
 271                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 272         },
 273         .irq = {
 274                 .set = &r100_irq_set,
 275                 .process = &r100_irq_process,
 276         },
 277         .display = {
 278                 .bandwidth_update = &r100_bandwidth_update,
 279                 .get_vblank_counter = &r100_get_vblank_counter,
 280                 .wait_for_vblank = &r100_wait_for_vblank,
 281                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 282                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 283         },
 284         .copy = {
 285                 .blit = &r100_copy_blit,
 286                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 287                 .dma = &r200_copy_dma,
 288                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 289                 .copy = &r100_copy_blit,
 290                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 291         },
 292         .surface = {
 293                 .set_reg = r100_set_surface_reg,
 294                 .clear_reg = r100_clear_surface_reg,
 295         },
 296         .hpd = {
 297                 .init = &r100_hpd_init,
 298                 .fini = &r100_hpd_fini,
 299                 .sense = &r100_hpd_sense,
 300                 .set_polarity = &r100_hpd_set_polarity,
 301         },
 302         .pm = {
 303                 .misc = &r100_pm_misc,
 304                 .prepare = &r100_pm_prepare,
 305                 .finish = &r100_pm_finish,
 306                 .init_profile = &r100_pm_init_profile,
 307                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 308                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 309                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 310                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 311                 .set_memory_clock = NULL,
 312                 .get_pcie_lanes = NULL,
 313                 .set_pcie_lanes = NULL,
 314                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 315         },
 316         .pflip = {
 317                 .pre_page_flip = &r100_pre_page_flip,
 318                 .page_flip = &r100_page_flip,
 319                 .post_page_flip = &r100_post_page_flip,
 320         },
 321 };
 322
 323 static struct radeon_asic_ring r300_gfx_ring = {
 324         .ib_execute = &r100_ring_ib_execute,
 325         .emit_fence = &r300_fence_ring_emit,
 326         .emit_semaphore = &r100_semaphore_ring_emit,
 327         .cs_parse = &r300_cs_parse,
 328         .ring_start = &r300_ring_start,
 329         .ring_test = &r100_ring_test,
 330         .ib_test = &r100_ib_test,
 331         .is_lockup = &r100_gpu_is_lockup,
 332         .get_rptr = &radeon_ring_generic_get_rptr,
 333         .get_wptr = &radeon_ring_generic_get_wptr,
 334         .set_wptr = &radeon_ring_generic_set_wptr,
 335 };
 336
 337 static struct radeon_asic r300_asic = {
 338         .init = &r300_init,
 339         .fini = &r300_fini,
 340         .suspend = &r300_suspend,
 341         .resume = &r300_resume,
 342         .vga_set_state = &r100_vga_set_state,
 343         .asic_reset = &r300_asic_reset,
 344         .ioctl_wait_idle = NULL,
 345         .gui_idle = &r100_gui_idle,
 346         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 347         .gart = {
 348                 .tlb_flush = &r100_pci_gart_tlb_flush,
 349                 .set_page = &r100_pci_gart_set_page,
 350         },
 351         .ring = {
 352                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 353         },
 354         .irq = {
 355                 .set = &r100_irq_set,
 356                 .process = &r100_irq_process,
 357         },
 358         .display = {
 359                 .bandwidth_update = &r100_bandwidth_update,
 360                 .get_vblank_counter = &r100_get_vblank_counter,
 361                 .wait_for_vblank = &r100_wait_for_vblank,
 362                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 363                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 364         },
 365         .copy = {
 366                 .blit = &r100_copy_blit,
 367                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 368                 .dma = &r200_copy_dma,
 369                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 370                 .copy = &r100_copy_blit,
 371                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 372         },
 373         .surface = {
 374                 .set_reg = r100_set_surface_reg,
 375                 .clear_reg = r100_clear_surface_reg,
 376         },
 377         .hpd = {
 378                 .init = &r100_hpd_init,
 379                 .fini = &r100_hpd_fini,
 380                 .sense = &r100_hpd_sense,
 381                 .set_polarity = &r100_hpd_set_polarity,
 382         },
 383         .pm = {
 384                 .misc = &r100_pm_misc,
 385                 .prepare = &r100_pm_prepare,
 386                 .finish = &r100_pm_finish,
 387                 .init_profile = &r100_pm_init_profile,
 388                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 389                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 390                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 391                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 392                 .set_memory_clock = NULL,
 393                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 394                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 395                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 396         },
 397         .pflip = {
 398                 .pre_page_flip = &r100_pre_page_flip,
 399                 .page_flip = &r100_page_flip,
 400                 .post_page_flip = &r100_post_page_flip,
 401         },
 402 };
 403
 404 static struct radeon_asic r300_asic_pcie = {
 405         .init = &r300_init,
 406         .fini = &r300_fini,
 407         .suspend = &r300_suspend,
 408         .resume = &r300_resume,
 409         .vga_set_state = &r100_vga_set_state,
 410         .asic_reset = &r300_asic_reset,
 411         .ioctl_wait_idle = NULL,
 412         .gui_idle = &r100_gui_idle,
 413         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 414         .gart = {
 415                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 416                 .set_page = &rv370_pcie_gart_set_page,
 417         },
 418         .ring = {
 419                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 420         },
 421         .irq = {
 422                 .set = &r100_irq_set,
 423                 .process = &r100_irq_process,
 424         },
 425         .display = {
 426                 .bandwidth_update = &r100_bandwidth_update,
 427                 .get_vblank_counter = &r100_get_vblank_counter,
 428                 .wait_for_vblank = &r100_wait_for_vblank,
 429                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 430                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 431         },
 432         .copy = {
 433                 .blit = &r100_copy_blit,
 434                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 435                 .dma = &r200_copy_dma,
 436                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 437                 .copy = &r100_copy_blit,
 438                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 439         },
 440         .surface = {
 441                 .set_reg = r100_set_surface_reg,
 442                 .clear_reg = r100_clear_surface_reg,
 443         },
 444         .hpd = {
 445                 .init = &r100_hpd_init,
 446                 .fini = &r100_hpd_fini,
 447                 .sense = &r100_hpd_sense,
 448                 .set_polarity = &r100_hpd_set_polarity,
 449         },
 450         .pm = {
 451                 .misc = &r100_pm_misc,
 452                 .prepare = &r100_pm_prepare,
 453                 .finish = &r100_pm_finish,
 454                 .init_profile = &r100_pm_init_profile,
 455                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 456                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 457                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 458                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 459                 .set_memory_clock = NULL,
 460                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 461                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 462                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 463         },
 464         .pflip = {
 465                 .pre_page_flip = &r100_pre_page_flip,
 466                 .page_flip = &r100_page_flip,
 467                 .post_page_flip = &r100_post_page_flip,
 468         },
 469 };
 470
 471 static struct radeon_asic r420_asic = {
 472         .init = &r420_init,
 473         .fini = &r420_fini,
 474         .suspend = &r420_suspend,
 475         .resume = &r420_resume,
 476         .vga_set_state = &r100_vga_set_state,
 477         .asic_reset = &r300_asic_reset,
 478         .ioctl_wait_idle = NULL,
 479         .gui_idle = &r100_gui_idle,
 480         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 481         .gart = {
 482                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 483                 .set_page = &rv370_pcie_gart_set_page,
 484         },
 485         .ring = {
 486                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 487         },
 488         .irq = {
 489                 .set = &r100_irq_set,
 490                 .process = &r100_irq_process,
 491         },
 492         .display = {
 493                 .bandwidth_update = &r100_bandwidth_update,
 494                 .get_vblank_counter = &r100_get_vblank_counter,
 495                 .wait_for_vblank = &r100_wait_for_vblank,
 496                 .set_backlight_level = &atombios_set_backlight_level,
 497                 .get_backlight_level = &atombios_get_backlight_level,
 498         },
 499         .copy = {
 500                 .blit = &r100_copy_blit,
 501                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 502                 .dma = &r200_copy_dma,
 503                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 504                 .copy = &r100_copy_blit,
 505                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 506         },
 507         .surface = {
 508                 .set_reg = r100_set_surface_reg,
 509                 .clear_reg = r100_clear_surface_reg,
 510         },
 511         .hpd = {
 512                 .init = &r100_hpd_init,
 513                 .fini = &r100_hpd_fini,
 514                 .sense = &r100_hpd_sense,
 515                 .set_polarity = &r100_hpd_set_polarity,
 516         },
 517         .pm = {
 518                 .misc = &r100_pm_misc,
 519                 .prepare = &r100_pm_prepare,
 520                 .finish = &r100_pm_finish,
 521                 .init_profile = &r420_pm_init_profile,
 522                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 523                 .get_engine_clock = &radeon_atom_get_engine_clock,
 524                 .set_engine_clock = &radeon_atom_set_engine_clock,
 525                 .get_memory_clock = &radeon_atom_get_memory_clock,
 526                 .set_memory_clock = &radeon_atom_set_memory_clock,
 527                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 528                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 529                 .set_clock_gating = &radeon_atom_set_clock_gating,
 530         },
 531         .pflip = {
 532                 .pre_page_flip = &r100_pre_page_flip,
 533                 .page_flip = &r100_page_flip,
 534                 .post_page_flip = &r100_post_page_flip,
 535         },
 536 };
 537
 538 static struct radeon_asic rs400_asic = {
 539         .init = &rs400_init,
 540         .fini = &rs400_fini,
 541         .suspend = &rs400_suspend,
 542         .resume = &rs400_resume,
 543         .vga_set_state = &r100_vga_set_state,
 544         .asic_reset = &r300_asic_reset,
 545         .ioctl_wait_idle = NULL,
 546         .gui_idle = &r100_gui_idle,
 547         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 548         .gart = {
 549                 .tlb_flush = &rs400_gart_tlb_flush,
 550                 .set_page = &rs400_gart_set_page,
 551         },
 552         .ring = {
 553                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 554         },
 555         .irq = {
 556                 .set = &r100_irq_set,
 557                 .process = &r100_irq_process,
 558         },
 559         .display = {
 560                 .bandwidth_update = &r100_bandwidth_update,
 561                 .get_vblank_counter = &r100_get_vblank_counter,
 562                 .wait_for_vblank = &r100_wait_for_vblank,
 563                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 564                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 565         },
 566         .copy = {
 567                 .blit = &r100_copy_blit,
 568                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 569                 .dma = &r200_copy_dma,
 570                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 571                 .copy = &r100_copy_blit,
 572                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 573         },
 574         .surface = {
 575                 .set_reg = r100_set_surface_reg,
 576                 .clear_reg = r100_clear_surface_reg,
 577         },
 578         .hpd = {
 579                 .init = &r100_hpd_init,
 580                 .fini = &r100_hpd_fini,
 581                 .sense = &r100_hpd_sense,
 582                 .set_polarity = &r100_hpd_set_polarity,
 583         },
 584         .pm = {
 585                 .misc = &r100_pm_misc,
 586                 .prepare = &r100_pm_prepare,
 587                 .finish = &r100_pm_finish,
 588                 .init_profile = &r100_pm_init_profile,
 589                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 590                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 591                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 592                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 593                 .set_memory_clock = NULL,
 594                 .get_pcie_lanes = NULL,
 595                 .set_pcie_lanes = NULL,
 596                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 597         },
 598         .pflip = {
 599                 .pre_page_flip = &r100_pre_page_flip,
 600                 .page_flip = &r100_page_flip,
 601                 .post_page_flip = &r100_post_page_flip,
 602         },
 603 };
 604
 605 static struct radeon_asic rs600_asic = {
 606         .init = &rs600_init,
 607         .fini = &rs600_fini,
 608         .suspend = &rs600_suspend,
 609         .resume = &rs600_resume,
 610         .vga_set_state = &r100_vga_set_state,
 611         .asic_reset = &rs600_asic_reset,
 612         .ioctl_wait_idle = NULL,
 613         .gui_idle = &r100_gui_idle,
 614         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 615         .gart = {
 616                 .tlb_flush = &rs600_gart_tlb_flush,
 617                 .set_page = &rs600_gart_set_page,
 618         },
 619         .ring = {
 620                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 621         },
 622         .irq = {
 623                 .set = &rs600_irq_set,
 624                 .process = &rs600_irq_process,
 625         },
 626         .display = {
 627                 .bandwidth_update = &rs600_bandwidth_update,
 628                 .get_vblank_counter = &rs600_get_vblank_counter,
 629                 .wait_for_vblank = &avivo_wait_for_vblank,
 630                 .set_backlight_level = &atombios_set_backlight_level,
 631                 .get_backlight_level = &atombios_get_backlight_level,
 632                 .hdmi_enable = &r600_hdmi_enable,
 633                 .hdmi_setmode = &r600_hdmi_setmode,
 634         },
 635         .copy = {
 636                 .blit = &r100_copy_blit,
 637                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 638                 .dma = &r200_copy_dma,
 639                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 640                 .copy = &r100_copy_blit,
 641                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 642         },
 643         .surface = {
 644                 .set_reg = r100_set_surface_reg,
 645                 .clear_reg = r100_clear_surface_reg,
 646         },
 647         .hpd = {
 648                 .init = &rs600_hpd_init,
 649                 .fini = &rs600_hpd_fini,
 650                 .sense = &rs600_hpd_sense,
 651                 .set_polarity = &rs600_hpd_set_polarity,
 652         },
 653         .pm = {
 654                 .misc = &rs600_pm_misc,
 655                 .prepare = &rs600_pm_prepare,
 656                 .finish = &rs600_pm_finish,
 657                 .init_profile = &r420_pm_init_profile,
 658                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 659                 .get_engine_clock = &radeon_atom_get_engine_clock,
 660                 .set_engine_clock = &radeon_atom_set_engine_clock,
 661                 .get_memory_clock = &radeon_atom_get_memory_clock,
 662                 .set_memory_clock = &radeon_atom_set_memory_clock,
 663                 .get_pcie_lanes = NULL,
 664                 .set_pcie_lanes = NULL,
 665                 .set_clock_gating = &radeon_atom_set_clock_gating,
 666         },
 667         .pflip = {
 668                 .pre_page_flip = &rs600_pre_page_flip,
 669                 .page_flip = &rs600_page_flip,
 670                 .post_page_flip = &rs600_post_page_flip,
 671         },
 672 };
 673
 674 static struct radeon_asic rs690_asic = {
 675         .init = &rs690_init,
 676         .fini = &rs690_fini,
 677         .suspend = &rs690_suspend,
 678         .resume = &rs690_resume,
 679         .vga_set_state = &r100_vga_set_state,
 680         .asic_reset = &rs600_asic_reset,
 681         .ioctl_wait_idle = NULL,
 682         .gui_idle = &r100_gui_idle,
 683         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 684         .gart = {
 685                 .tlb_flush = &rs400_gart_tlb_flush,
 686                 .set_page = &rs400_gart_set_page,
 687         },
 688         .ring = {
 689                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 690         },
 691         .irq = {
 692                 .set = &rs600_irq_set,
 693                 .process = &rs600_irq_process,
 694         },
 695         .display = {
 696                 .get_vblank_counter = &rs600_get_vblank_counter,
 697                 .bandwidth_update = &rs690_bandwidth_update,
 698                 .wait_for_vblank = &avivo_wait_for_vblank,
 699                 .set_backlight_level = &atombios_set_backlight_level,
 700                 .get_backlight_level = &atombios_get_backlight_level,
 701                 .hdmi_enable = &r600_hdmi_enable,
 702                 .hdmi_setmode = &r600_hdmi_setmode,
 703         },
 704         .copy = {
 705                 .blit = &r100_copy_blit,
 706                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 707                 .dma = &r200_copy_dma,
 708                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 709                 .copy = &r200_copy_dma,
 710                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 711         },
 712         .surface = {
 713                 .set_reg = r100_set_surface_reg,
 714                 .clear_reg = r100_clear_surface_reg,
 715         },
 716         .hpd = {
 717                 .init = &rs600_hpd_init,
 718                 .fini = &rs600_hpd_fini,
 719                 .sense = &rs600_hpd_sense,
 720                 .set_polarity = &rs600_hpd_set_polarity,
 721         },
 722         .pm = {
 723                 .misc = &rs600_pm_misc,
 724                 .prepare = &rs600_pm_prepare,
 725                 .finish = &rs600_pm_finish,
 726                 .init_profile = &r420_pm_init_profile,
 727                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 728                 .get_engine_clock = &radeon_atom_get_engine_clock,
 729                 .set_engine_clock = &radeon_atom_set_engine_clock,
 730                 .get_memory_clock = &radeon_atom_get_memory_clock,
 731                 .set_memory_clock = &radeon_atom_set_memory_clock,
 732                 .get_pcie_lanes = NULL,
 733                 .set_pcie_lanes = NULL,
 734                 .set_clock_gating = &radeon_atom_set_clock_gating,
 735         },
 736         .pflip = {
 737                 .pre_page_flip = &rs600_pre_page_flip,
 738                 .page_flip = &rs600_page_flip,
 739                 .post_page_flip = &rs600_post_page_flip,
 740         },
 741 };
 742
 743 static struct radeon_asic rv515_asic = {
 744         .init = &rv515_init,
 745         .fini = &rv515_fini,
 746         .suspend = &rv515_suspend,
 747         .resume = &rv515_resume,
 748         .vga_set_state = &r100_vga_set_state,
 749         .asic_reset = &rs600_asic_reset,
 750         .ioctl_wait_idle = NULL,
 751         .gui_idle = &r100_gui_idle,
 752         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 753         .gart = {
 754                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 755                 .set_page = &rv370_pcie_gart_set_page,
 756         },
 757         .ring = {
 758                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 759         },
 760         .irq = {
 761                 .set = &rs600_irq_set,
 762                 .process = &rs600_irq_process,
 763         },
 764         .display = {
 765                 .get_vblank_counter = &rs600_get_vblank_counter,
 766                 .bandwidth_update = &rv515_bandwidth_update,
 767                 .wait_for_vblank = &avivo_wait_for_vblank,
 768                 .set_backlight_level = &atombios_set_backlight_level,
 769                 .get_backlight_level = &atombios_get_backlight_level,
 770         },
 771         .copy = {
 772                 .blit = &r100_copy_blit,
 773                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 774                 .dma = &r200_copy_dma,
 775                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 776                 .copy = &r100_copy_blit,
 777                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 778         },
 779         .surface = {
 780                 .set_reg = r100_set_surface_reg,
 781                 .clear_reg = r100_clear_surface_reg,
 782         },
 783         .hpd = {
 784                 .init = &rs600_hpd_init,
 785                 .fini = &rs600_hpd_fini,
 786                 .sense = &rs600_hpd_sense,
 787                 .set_polarity = &rs600_hpd_set_polarity,
 788         },
 789         .pm = {
 790                 .misc = &rs600_pm_misc,
 791                 .prepare = &rs600_pm_prepare,
 792                 .finish = &rs600_pm_finish,
 793                 .init_profile = &r420_pm_init_profile,
 794                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 795                 .get_engine_clock = &radeon_atom_get_engine_clock,
 796                 .set_engine_clock = &radeon_atom_set_engine_clock,
 797                 .get_memory_clock = &radeon_atom_get_memory_clock,
 798                 .set_memory_clock = &radeon_atom_set_memory_clock,
 799                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 800                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 801                 .set_clock_gating = &radeon_atom_set_clock_gating,
 802         },
 803         .pflip = {
 804                 .pre_page_flip = &rs600_pre_page_flip,
 805                 .page_flip = &rs600_page_flip,
 806                 .post_page_flip = &rs600_post_page_flip,
 807         },
 808 };
 809
 810 static struct radeon_asic r520_asic = {
 811         .init = &r520_init,
 812         .fini = &rv515_fini,
 813         .suspend = &rv515_suspend,
 814         .resume = &r520_resume,
 815         .vga_set_state = &r100_vga_set_state,
 816         .asic_reset = &rs600_asic_reset,
 817         .ioctl_wait_idle = NULL,
 818         .gui_idle = &r100_gui_idle,
 819         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 820         .gart = {
 821                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 822                 .set_page = &rv370_pcie_gart_set_page,
 823         },
 824         .ring = {
 825                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 826         },
 827         .irq = {
 828                 .set = &rs600_irq_set,
 829                 .process = &rs600_irq_process,
 830         },
 831         .display = {
 832                 .bandwidth_update = &rv515_bandwidth_update,
 833                 .get_vblank_counter = &rs600_get_vblank_counter,
 834                 .wait_for_vblank = &avivo_wait_for_vblank,
 835                 .set_backlight_level = &atombios_set_backlight_level,
 836                 .get_backlight_level = &atombios_get_backlight_level,
 837         },
 838         .copy = {
 839                 .blit = &r100_copy_blit,
 840                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 841                 .dma = &r200_copy_dma,
 842                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 843                 .copy = &r100_copy_blit,
 844                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 845         },
 846         .surface = {
 847                 .set_reg = r100_set_surface_reg,
 848                 .clear_reg = r100_clear_surface_reg,
 849         },
 850         .hpd = {
 851                 .init = &rs600_hpd_init,
 852                 .fini = &rs600_hpd_fini,
 853                 .sense = &rs600_hpd_sense,
 854                 .set_polarity = &rs600_hpd_set_polarity,
 855         },
 856         .pm = {
 857                 .misc = &rs600_pm_misc,
 858                 .prepare = &rs600_pm_prepare,
 859                 .finish = &rs600_pm_finish,
 860                 .init_profile = &r420_pm_init_profile,
 861                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 862                 .get_engine_clock = &radeon_atom_get_engine_clock,
 863                 .set_engine_clock = &radeon_atom_set_engine_clock,
 864                 .get_memory_clock = &radeon_atom_get_memory_clock,
 865                 .set_memory_clock = &radeon_atom_set_memory_clock,
 866                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 867                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 868                 .set_clock_gating = &radeon_atom_set_clock_gating,
 869         },
 870         .pflip = {
 871                 .pre_page_flip = &rs600_pre_page_flip,
 872                 .page_flip = &rs600_page_flip,
 873                 .post_page_flip = &rs600_post_page_flip,
 874         },
 875 };
 876
 877 static struct radeon_asic_ring r600_gfx_ring = {
 878         .ib_execute = &r600_ring_ib_execute,
 879         .emit_fence = &r600_fence_ring_emit,
 880         .emit_semaphore = &r600_semaphore_ring_emit,
 881         .cs_parse = &r600_cs_parse,
 882         .ring_test = &r600_ring_test,
 883         .ib_test = &r600_ib_test,
 884         .is_lockup = &r600_gfx_is_lockup,
 885         .get_rptr = &radeon_ring_generic_get_rptr,
 886         .get_wptr = &radeon_ring_generic_get_wptr,
 887         .set_wptr = &radeon_ring_generic_set_wptr,
 888 };
 889
 890 static struct radeon_asic_ring r600_dma_ring = {
 891         .ib_execute = &r600_dma_ring_ib_execute,
 892         .emit_fence = &r600_dma_fence_ring_emit,
 893         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 894         .cs_parse = &r600_dma_cs_parse,
 895         .ring_test = &r600_dma_ring_test,
 896         .ib_test = &r600_dma_ib_test,
 897         .is_lockup = &r600_dma_is_lockup,
 898         .get_rptr = &r600_dma_get_rptr,
 899         .get_wptr = &r600_dma_get_wptr,
 900         .set_wptr = &r600_dma_set_wptr,
 901 };
 902
 903 static struct radeon_asic r600_asic = {
 904         .init = &r600_init,
 905         .fini = &r600_fini,
 906         .suspend = &r600_suspend,
 907         .resume = &r600_resume,
 908         .vga_set_state = &r600_vga_set_state,
 909         .asic_reset = &r600_asic_reset,
 910         .ioctl_wait_idle = r600_ioctl_wait_idle,
 911         .gui_idle = &r600_gui_idle,
 912         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 913         .get_xclk = &r600_get_xclk,
 914         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 915         .gart = {
 916                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 917                 .set_page = &rs600_gart_set_page,
 918         },
 919         .ring = {
 920                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 921                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 922         },
 923         .irq = {
 924                 .set = &r600_irq_set,
 925                 .process = &r600_irq_process,
 926         },
 927         .display = {
 928                 .bandwidth_update = &rv515_bandwidth_update,
 929                 .get_vblank_counter = &rs600_get_vblank_counter,
 930                 .wait_for_vblank = &avivo_wait_for_vblank,
 931                 .set_backlight_level = &atombios_set_backlight_level,
 932                 .get_backlight_level = &atombios_get_backlight_level,
 933                 .hdmi_enable = &r600_hdmi_enable,
 934                 .hdmi_setmode = &r600_hdmi_setmode,
 935         },
 936         .copy = {
 937                 .blit = &r600_copy_cpdma,
 938                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 939                 .dma = &r600_copy_dma,
 940                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 941                 .copy = &r600_copy_cpdma,
 942                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 943         },
 944         .surface = {
 945                 .set_reg = r600_set_surface_reg,
 946                 .clear_reg = r600_clear_surface_reg,
 947         },
 948         .hpd = {
 949                 .init = &r600_hpd_init,
 950                 .fini = &r600_hpd_fini,
 951                 .sense = &r600_hpd_sense,
 952                 .set_polarity = &r600_hpd_set_polarity,
 953         },
 954         .pm = {
 955                 .misc = &r600_pm_misc,
 956                 .prepare = &rs600_pm_prepare,
 957                 .finish = &rs600_pm_finish,
 958                 .init_profile = &r600_pm_init_profile,
 959                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 960                 .get_engine_clock = &radeon_atom_get_engine_clock,
 961                 .set_engine_clock = &radeon_atom_set_engine_clock,
 962                 .get_memory_clock = &radeon_atom_get_memory_clock,
 963                 .set_memory_clock = &radeon_atom_set_memory_clock,
 964                 .get_pcie_lanes = &r600_get_pcie_lanes,
 965                 .set_pcie_lanes = &r600_set_pcie_lanes,
 966                 .set_clock_gating = NULL,
 967                 .get_temperature = &rv6xx_get_temp,
 968         },
 969         .pflip = {
 970                 .pre_page_flip = &rs600_pre_page_flip,
 971                 .page_flip = &rs600_page_flip,
 972                 .post_page_flip = &rs600_post_page_flip,
 973         },
 974 };
 975
 976 static struct radeon_asic rv6xx_asic = {
 977         .init = &r600_init,
 978         .fini = &r600_fini,
 979         .suspend = &r600_suspend,
 980         .resume = &r600_resume,
 981         .vga_set_state = &r600_vga_set_state,
 982         .asic_reset = &r600_asic_reset,
 983         .ioctl_wait_idle = r600_ioctl_wait_idle,
 984         .gui_idle = &r600_gui_idle,
 985         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 986         .get_xclk = &r600_get_xclk,
 987         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 988         .gart = {
 989                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 990                 .set_page = &rs600_gart_set_page,
 991         },
 992         .ring = {
 993                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 994                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 995         },
 996         .irq = {
 997                 .set = &r600_irq_set,
 998                 .process = &r600_irq_process,
 999         },
1000         .display = {
1001                 .bandwidth_update = &rv515_bandwidth_update,
1002                 .get_vblank_counter = &rs600_get_vblank_counter,
1003                 .wait_for_vblank = &avivo_wait_for_vblank,
1004                 .set_backlight_level = &atombios_set_backlight_level,
1005                 .get_backlight_level = &atombios_get_backlight_level,
1006                 .hdmi_enable = &r600_hdmi_enable,
1007                 .hdmi_setmode = &r600_hdmi_setmode,
1008         },
1009         .copy = {
1010                 .blit = &r600_copy_cpdma,
1011                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1012                 .dma = &r600_copy_dma,
1013                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1014                 .copy = &r600_copy_cpdma,
1015                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1016         },
1017         .surface = {
1018                 .set_reg = r600_set_surface_reg,
1019                 .clear_reg = r600_clear_surface_reg,
1020         },
1021         .hpd = {
1022                 .init = &r600_hpd_init,
1023                 .fini = &r600_hpd_fini,
1024                 .sense = &r600_hpd_sense,
1025                 .set_polarity = &r600_hpd_set_polarity,
1026         },
1027         .pm = {
1028                 .misc = &r600_pm_misc,
1029                 .prepare = &rs600_pm_prepare,
1030                 .finish = &rs600_pm_finish,
1031                 .init_profile = &r600_pm_init_profile,
1032                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1033                 .get_engine_clock = &radeon_atom_get_engine_clock,
1034                 .set_engine_clock = &radeon_atom_set_engine_clock,
1035                 .get_memory_clock = &radeon_atom_get_memory_clock,
1036                 .set_memory_clock = &radeon_atom_set_memory_clock,
1037                 .get_pcie_lanes = &r600_get_pcie_lanes,
1038                 .set_pcie_lanes = &r600_set_pcie_lanes,
1039                 .set_clock_gating = NULL,
1040                 .get_temperature = &rv6xx_get_temp,
1041                 .set_uvd_clocks = &r600_set_uvd_clocks,
1042         },
1043         .dpm = {
1044                 .init = &rv6xx_dpm_init,
1045                 .setup_asic = &rv6xx_setup_asic,
1046                 .enable = &rv6xx_dpm_enable,
1047                 .disable = &rv6xx_dpm_disable,
1048                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1049                 .set_power_state = &rv6xx_dpm_set_power_state,
1050                 .post_set_power_state = &r600_dpm_post_set_power_state,
1051                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1052                 .fini = &rv6xx_dpm_fini,
1053                 .get_sclk = &rv6xx_dpm_get_sclk,
1054                 .get_mclk = &rv6xx_dpm_get_mclk,
1055                 .print_power_state = &rv6xx_dpm_print_power_state,
1056                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1057                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1058         },
1059         .pflip = {
1060                 .pre_page_flip = &rs600_pre_page_flip,
1061                 .page_flip = &rs600_page_flip,
1062                 .post_page_flip = &rs600_post_page_flip,
1063         },
1064 };
1065
1066 static struct radeon_asic rs780_asic = {
1067         .init = &r600_init,
1068         .fini = &r600_fini,
1069         .suspend = &r600_suspend,
1070         .resume = &r600_resume,
1071         .vga_set_state = &r600_vga_set_state,
1072         .asic_reset = &r600_asic_reset,
1073         .ioctl_wait_idle = r600_ioctl_wait_idle,
1074         .gui_idle = &r600_gui_idle,
1075         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1076         .get_xclk = &r600_get_xclk,
1077         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1078         .gart = {
1079                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1080                 .set_page = &rs600_gart_set_page,
1081         },
1082         .ring = {
1083                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1084                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1085         },
1086         .irq = {
1087                 .set = &r600_irq_set,
1088                 .process = &r600_irq_process,
1089         },
1090         .display = {
1091                 .bandwidth_update = &rs690_bandwidth_update,
1092                 .get_vblank_counter = &rs600_get_vblank_counter,
1093                 .wait_for_vblank = &avivo_wait_for_vblank,
1094                 .set_backlight_level = &atombios_set_backlight_level,
1095                 .get_backlight_level = &atombios_get_backlight_level,
1096                 .hdmi_enable = &r600_hdmi_enable,
1097                 .hdmi_setmode = &r600_hdmi_setmode,
1098         },
1099         .copy = {
1100                 .blit = &r600_copy_cpdma,
1101                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1102                 .dma = &r600_copy_dma,
1103                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1104                 .copy = &r600_copy_cpdma,
1105                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1106         },
1107         .surface = {
1108                 .set_reg = r600_set_surface_reg,
1109                 .clear_reg = r600_clear_surface_reg,
1110         },
1111         .hpd = {
1112                 .init = &r600_hpd_init,
1113                 .fini = &r600_hpd_fini,
1114                 .sense = &r600_hpd_sense,
1115                 .set_polarity = &r600_hpd_set_polarity,
1116         },
1117         .pm = {
1118                 .misc = &r600_pm_misc,
1119                 .prepare = &rs600_pm_prepare,
1120                 .finish = &rs600_pm_finish,
1121                 .init_profile = &rs780_pm_init_profile,
1122                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1123                 .get_engine_clock = &radeon_atom_get_engine_clock,
1124                 .set_engine_clock = &radeon_atom_set_engine_clock,
1125                 .get_memory_clock = NULL,
1126                 .set_memory_clock = NULL,
1127                 .get_pcie_lanes = NULL,
1128                 .set_pcie_lanes = NULL,
1129                 .set_clock_gating = NULL,
1130                 .get_temperature = &rv6xx_get_temp,
1131                 .set_uvd_clocks = &r600_set_uvd_clocks,
1132         },
1133         .dpm = {
1134                 .init = &rs780_dpm_init,
1135                 .setup_asic = &rs780_dpm_setup_asic,
1136                 .enable = &rs780_dpm_enable,
1137                 .disable = &rs780_dpm_disable,
1138                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1139                 .set_power_state = &rs780_dpm_set_power_state,
1140                 .post_set_power_state = &r600_dpm_post_set_power_state,
1141                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1142                 .fini = &rs780_dpm_fini,
1143                 .get_sclk = &rs780_dpm_get_sclk,
1144                 .get_mclk = &rs780_dpm_get_mclk,
1145                 .print_power_state = &rs780_dpm_print_power_state,
1146                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1147                 .force_performance_level = &rs780_dpm_force_performance_level,
1148         },
1149         .pflip = {
1150                 .pre_page_flip = &rs600_pre_page_flip,
1151                 .page_flip = &rs600_page_flip,
1152                 .post_page_flip = &rs600_post_page_flip,
1153         },
1154 };
1155
1156 static struct radeon_asic_ring rv770_uvd_ring = {
1157         .ib_execute = &uvd_v1_0_ib_execute,
1158         .emit_fence = &uvd_v2_2_fence_emit,
1159         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1160         .cs_parse = &radeon_uvd_cs_parse,
1161         .ring_test = &uvd_v1_0_ring_test,
1162         .ib_test = &uvd_v1_0_ib_test,
1163         .is_lockup = &radeon_ring_test_lockup,
1164         .get_rptr = &uvd_v1_0_get_rptr,
1165         .get_wptr = &uvd_v1_0_get_wptr,
1166         .set_wptr = &uvd_v1_0_set_wptr,
1167 };
1168
1169 static struct radeon_asic rv770_asic = {
1170         .init = &rv770_init,
1171         .fini = &rv770_fini,
1172         .suspend = &rv770_suspend,
1173         .resume = &rv770_resume,
1174         .asic_reset = &r600_asic_reset,
1175         .vga_set_state = &r600_vga_set_state,
1176         .ioctl_wait_idle = r600_ioctl_wait_idle,
1177         .gui_idle = &r600_gui_idle,
1178         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1179         .get_xclk = &rv770_get_xclk,
1180         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1181         .gart = {
1182                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1183                 .set_page = &rs600_gart_set_page,
1184         },
1185         .ring = {
1186                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1187                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1188                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1189         },
1190         .irq = {
1191                 .set = &r600_irq_set,
1192                 .process = &r600_irq_process,
1193         },
1194         .display = {
1195                 .bandwidth_update = &rv515_bandwidth_update,
1196                 .get_vblank_counter = &rs600_get_vblank_counter,
1197                 .wait_for_vblank = &avivo_wait_for_vblank,
1198                 .set_backlight_level = &atombios_set_backlight_level,
1199                 .get_backlight_level = &atombios_get_backlight_level,
1200                 .hdmi_enable = &r600_hdmi_enable,
1201                 .hdmi_setmode = &r600_hdmi_setmode,
1202         },
1203         .copy = {
1204                 .blit = &r600_copy_cpdma,
1205                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1206                 .dma = &rv770_copy_dma,
1207                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1208                 .copy = &rv770_copy_dma,
1209                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1210         },
1211         .surface = {
1212                 .set_reg = r600_set_surface_reg,
1213                 .clear_reg = r600_clear_surface_reg,
1214         },
1215         .hpd = {
1216                 .init = &r600_hpd_init,
1217                 .fini = &r600_hpd_fini,
1218                 .sense = &r600_hpd_sense,
1219                 .set_polarity = &r600_hpd_set_polarity,
1220         },
1221         .pm = {
1222                 .misc = &rv770_pm_misc,
1223                 .prepare = &rs600_pm_prepare,
1224                 .finish = &rs600_pm_finish,
1225                 .init_profile = &r600_pm_init_profile,
1226                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1227                 .get_engine_clock = &radeon_atom_get_engine_clock,
1228                 .set_engine_clock = &radeon_atom_set_engine_clock,
1229                 .get_memory_clock = &radeon_atom_get_memory_clock,
1230                 .set_memory_clock = &radeon_atom_set_memory_clock,
1231                 .get_pcie_lanes = &r600_get_pcie_lanes,
1232                 .set_pcie_lanes = &r600_set_pcie_lanes,
1233                 .set_clock_gating = &radeon_atom_set_clock_gating,
1234                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1235                 .get_temperature = &rv770_get_temp,
1236         },
1237         .dpm = {
1238                 .init = &rv770_dpm_init,
1239                 .setup_asic = &rv770_dpm_setup_asic,
1240                 .enable = &rv770_dpm_enable,
1241                 .disable = &rv770_dpm_disable,
1242                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1243                 .set_power_state = &rv770_dpm_set_power_state,
1244                 .post_set_power_state = &r600_dpm_post_set_power_state,
1245                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1246                 .fini = &rv770_dpm_fini,
1247                 .get_sclk = &rv770_dpm_get_sclk,
1248                 .get_mclk = &rv770_dpm_get_mclk,
1249                 .print_power_state = &rv770_dpm_print_power_state,
1250                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1251                 .force_performance_level = &rv770_dpm_force_performance_level,
1252                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1253         },
1254         .pflip = {
1255                 .pre_page_flip = &rs600_pre_page_flip,
1256                 .page_flip = &rv770_page_flip,
1257                 .post_page_flip = &rs600_post_page_flip,
1258         },
1259 };
1260
1261 static struct radeon_asic_ring evergreen_gfx_ring = {
1262         .ib_execute = &evergreen_ring_ib_execute,
1263         .emit_fence = &r600_fence_ring_emit,
1264         .emit_semaphore = &r600_semaphore_ring_emit,
1265         .cs_parse = &evergreen_cs_parse,
1266         .ring_test = &r600_ring_test,
1267         .ib_test = &r600_ib_test,
1268         .is_lockup = &evergreen_gfx_is_lockup,
1269         .get_rptr = &radeon_ring_generic_get_rptr,
1270         .get_wptr = &radeon_ring_generic_get_wptr,
1271         .set_wptr = &radeon_ring_generic_set_wptr,
1272 };
1273
1274 static struct radeon_asic_ring evergreen_dma_ring = {
1275         .ib_execute = &evergreen_dma_ring_ib_execute,
1276         .emit_fence = &evergreen_dma_fence_ring_emit,
1277         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1278         .cs_parse = &evergreen_dma_cs_parse,
1279         .ring_test = &r600_dma_ring_test,
1280         .ib_test = &r600_dma_ib_test,
1281         .is_lockup = &evergreen_dma_is_lockup,
1282         .get_rptr = &r600_dma_get_rptr,
1283         .get_wptr = &r600_dma_get_wptr,
1284         .set_wptr = &r600_dma_set_wptr,
1285 };
1286
1287 static struct radeon_asic evergreen_asic = {
1288         .init = &evergreen_init,
1289         .fini = &evergreen_fini,
1290         .suspend = &evergreen_suspend,
1291         .resume = &evergreen_resume,
1292         .asic_reset = &evergreen_asic_reset,
1293         .vga_set_state = &r600_vga_set_state,
1294         .ioctl_wait_idle = r600_ioctl_wait_idle,
1295         .gui_idle = &r600_gui_idle,
1296         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1297         .get_xclk = &rv770_get_xclk,
1298         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1299         .gart = {
1300                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1301                 .set_page = &rs600_gart_set_page,
1302         },
1303         .ring = {
1304                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1305                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1306                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1307         },
1308         .irq = {
1309                 .set = &evergreen_irq_set,
1310                 .process = &evergreen_irq_process,
1311         },
1312         .display = {
1313                 .bandwidth_update = &evergreen_bandwidth_update,
1314                 .get_vblank_counter = &evergreen_get_vblank_counter,
1315                 .wait_for_vblank = &dce4_wait_for_vblank,
1316                 .set_backlight_level = &atombios_set_backlight_level,
1317                 .get_backlight_level = &atombios_get_backlight_level,
1318                 .hdmi_enable = &evergreen_hdmi_enable,
1319                 .hdmi_setmode = &evergreen_hdmi_setmode,
1320         },
1321         .copy = {
1322                 .blit = &r600_copy_cpdma,
1323                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1324                 .dma = &evergreen_copy_dma,
1325                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1326                 .copy = &evergreen_copy_dma,
1327                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1328         },
1329         .surface = {
1330                 .set_reg = r600_set_surface_reg,
1331                 .clear_reg = r600_clear_surface_reg,
1332         },
1333         .hpd = {
1334                 .init = &evergreen_hpd_init,
1335                 .fini = &evergreen_hpd_fini,
1336                 .sense = &evergreen_hpd_sense,
1337                 .set_polarity = &evergreen_hpd_set_polarity,
1338         },
1339         .pm = {
1340                 .misc = &evergreen_pm_misc,
1341                 .prepare = &evergreen_pm_prepare,
1342                 .finish = &evergreen_pm_finish,
1343                 .init_profile = &r600_pm_init_profile,
1344                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1345                 .get_engine_clock = &radeon_atom_get_engine_clock,
1346                 .set_engine_clock = &radeon_atom_set_engine_clock,
1347                 .get_memory_clock = &radeon_atom_get_memory_clock,
1348                 .set_memory_clock = &radeon_atom_set_memory_clock,
1349                 .get_pcie_lanes = &r600_get_pcie_lanes,
1350                 .set_pcie_lanes = &r600_set_pcie_lanes,
1351                 .set_clock_gating = NULL,
1352                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1353                 .get_temperature = &evergreen_get_temp,
1354         },
1355         .dpm = {
1356                 .init = &cypress_dpm_init,
1357                 .setup_asic = &cypress_dpm_setup_asic,
1358                 .enable = &cypress_dpm_enable,
1359                 .disable = &cypress_dpm_disable,
1360                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1361                 .set_power_state = &cypress_dpm_set_power_state,
1362                 .post_set_power_state = &r600_dpm_post_set_power_state,
1363                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1364                 .fini = &cypress_dpm_fini,
1365                 .get_sclk = &rv770_dpm_get_sclk,
1366                 .get_mclk = &rv770_dpm_get_mclk,
1367                 .print_power_state = &rv770_dpm_print_power_state,
1368                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1369                 .force_performance_level = &rv770_dpm_force_performance_level,
1370                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1371         },
1372         .pflip = {
1373                 .pre_page_flip = &evergreen_pre_page_flip,
1374                 .page_flip = &evergreen_page_flip,
1375                 .post_page_flip = &evergreen_post_page_flip,
1376         },
1377 };
1378
1379 static struct radeon_asic sumo_asic = {
1380         .init = &evergreen_init,
1381         .fini = &evergreen_fini,
1382         .suspend = &evergreen_suspend,
1383         .resume = &evergreen_resume,
1384         .asic_reset = &evergreen_asic_reset,
1385         .vga_set_state = &r600_vga_set_state,
1386         .ioctl_wait_idle = r600_ioctl_wait_idle,
1387         .gui_idle = &r600_gui_idle,
1388         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1389         .get_xclk = &r600_get_xclk,
1390         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1391         .gart = {
1392                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1393                 .set_page = &rs600_gart_set_page,
1394         },
1395         .ring = {
1396                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1397                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1398                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1399         },
1400         .irq = {
1401                 .set = &evergreen_irq_set,
1402                 .process = &evergreen_irq_process,
1403         },
1404         .display = {
1405                 .bandwidth_update = &evergreen_bandwidth_update,
1406                 .get_vblank_counter = &evergreen_get_vblank_counter,
1407                 .wait_for_vblank = &dce4_wait_for_vblank,
1408                 .set_backlight_level = &atombios_set_backlight_level,
1409                 .get_backlight_level = &atombios_get_backlight_level,
1410                 .hdmi_enable = &evergreen_hdmi_enable,
1411                 .hdmi_setmode = &evergreen_hdmi_setmode,
1412         },
1413         .copy = {
1414                 .blit = &r600_copy_cpdma,
1415                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1416                 .dma = &evergreen_copy_dma,
1417                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1418                 .copy = &evergreen_copy_dma,
1419                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1420         },
1421         .surface = {
1422                 .set_reg = r600_set_surface_reg,
1423                 .clear_reg = r600_clear_surface_reg,
1424         },
1425         .hpd = {
1426                 .init = &evergreen_hpd_init,
1427                 .fini = &evergreen_hpd_fini,
1428                 .sense = &evergreen_hpd_sense,
1429                 .set_polarity = &evergreen_hpd_set_polarity,
1430         },
1431         .pm = {
1432                 .misc = &evergreen_pm_misc,
1433                 .prepare = &evergreen_pm_prepare,
1434                 .finish = &evergreen_pm_finish,
1435                 .init_profile = &sumo_pm_init_profile,
1436                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1437                 .get_engine_clock = &radeon_atom_get_engine_clock,
1438                 .set_engine_clock = &radeon_atom_set_engine_clock,
1439                 .get_memory_clock = NULL,
1440                 .set_memory_clock = NULL,
1441                 .get_pcie_lanes = NULL,
1442                 .set_pcie_lanes = NULL,
1443                 .set_clock_gating = NULL,
1444                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1445                 .get_temperature = &sumo_get_temp,
1446         },
1447         .dpm = {
1448                 .init = &sumo_dpm_init,
1449                 .setup_asic = &sumo_dpm_setup_asic,
1450                 .enable = &sumo_dpm_enable,
1451                 .disable = &sumo_dpm_disable,
1452                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1453                 .set_power_state = &sumo_dpm_set_power_state,
1454                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1455                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1456                 .fini = &sumo_dpm_fini,
1457                 .get_sclk = &sumo_dpm_get_sclk,
1458                 .get_mclk = &sumo_dpm_get_mclk,
1459                 .print_power_state = &sumo_dpm_print_power_state,
1460                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1461                 .force_performance_level = &sumo_dpm_force_performance_level,
1462         },
1463         .pflip = {
1464                 .pre_page_flip = &evergreen_pre_page_flip,
1465                 .page_flip = &evergreen_page_flip,
1466                 .post_page_flip = &evergreen_post_page_flip,
1467         },
1468 };
1469
1470 static struct radeon_asic btc_asic = {
1471         .init = &evergreen_init,
1472         .fini = &evergreen_fini,
1473         .suspend = &evergreen_suspend,
1474         .resume = &evergreen_resume,
1475         .asic_reset = &evergreen_asic_reset,
1476         .vga_set_state = &r600_vga_set_state,
1477         .ioctl_wait_idle = r600_ioctl_wait_idle,
1478         .gui_idle = &r600_gui_idle,
1479         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1480         .get_xclk = &rv770_get_xclk,
1481         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1482         .gart = {
1483                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1484                 .set_page = &rs600_gart_set_page,
1485         },
1486         .ring = {
1487                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1488                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1489                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1490         },
1491         .irq = {
1492                 .set = &evergreen_irq_set,
1493                 .process = &evergreen_irq_process,
1494         },
1495         .display = {
1496                 .bandwidth_update = &evergreen_bandwidth_update,
1497                 .get_vblank_counter = &evergreen_get_vblank_counter,
1498                 .wait_for_vblank = &dce4_wait_for_vblank,
1499                 .set_backlight_level = &atombios_set_backlight_level,
1500                 .get_backlight_level = &atombios_get_backlight_level,
1501                 .hdmi_enable = &evergreen_hdmi_enable,
1502                 .hdmi_setmode = &evergreen_hdmi_setmode,
1503         },
1504         .copy = {
1505                 .blit = &r600_copy_cpdma,
1506                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1507                 .dma = &evergreen_copy_dma,
1508                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1509                 .copy = &evergreen_copy_dma,
1510                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1511         },
1512         .surface = {
1513                 .set_reg = r600_set_surface_reg,
1514                 .clear_reg = r600_clear_surface_reg,
1515         },
1516         .hpd = {
1517                 .init = &evergreen_hpd_init,
1518                 .fini = &evergreen_hpd_fini,
1519                 .sense = &evergreen_hpd_sense,
1520                 .set_polarity = &evergreen_hpd_set_polarity,
1521         },
1522         .pm = {
1523                 .misc = &evergreen_pm_misc,
1524                 .prepare = &evergreen_pm_prepare,
1525                 .finish = &evergreen_pm_finish,
1526                 .init_profile = &btc_pm_init_profile,
1527                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1528                 .get_engine_clock = &radeon_atom_get_engine_clock,
1529                 .set_engine_clock = &radeon_atom_set_engine_clock,
1530                 .get_memory_clock = &radeon_atom_get_memory_clock,
1531                 .set_memory_clock = &radeon_atom_set_memory_clock,
1532                 .get_pcie_lanes = &r600_get_pcie_lanes,
1533                 .set_pcie_lanes = &r600_set_pcie_lanes,
1534                 .set_clock_gating = NULL,
1535                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1536                 .get_temperature = &evergreen_get_temp,
1537         },
1538         .dpm = {
1539                 .init = &btc_dpm_init,
1540                 .setup_asic = &btc_dpm_setup_asic,
1541                 .enable = &btc_dpm_enable,
1542                 .disable = &btc_dpm_disable,
1543                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1544                 .set_power_state = &btc_dpm_set_power_state,
1545                 .post_set_power_state = &btc_dpm_post_set_power_state,
1546                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1547                 .fini = &btc_dpm_fini,
1548                 .get_sclk = &btc_dpm_get_sclk,
1549                 .get_mclk = &btc_dpm_get_mclk,
1550                 .print_power_state = &rv770_dpm_print_power_state,
1551                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1552                 .force_performance_level = &rv770_dpm_force_performance_level,
1553                 .vblank_too_short = &btc_dpm_vblank_too_short,
1554         },
1555         .pflip = {
1556                 .pre_page_flip = &evergreen_pre_page_flip,
1557                 .page_flip = &evergreen_page_flip,
1558                 .post_page_flip = &evergreen_post_page_flip,
1559         },
1560 };
1561
1562 static struct radeon_asic_ring cayman_gfx_ring = {
1563         .ib_execute = &cayman_ring_ib_execute,
1564         .ib_parse = &evergreen_ib_parse,
1565         .emit_fence = &cayman_fence_ring_emit,
1566         .emit_semaphore = &r600_semaphore_ring_emit,
1567         .cs_parse = &evergreen_cs_parse,
1568         .ring_test = &r600_ring_test,
1569         .ib_test = &r600_ib_test,
1570         .is_lockup = &cayman_gfx_is_lockup,
1571         .vm_flush = &cayman_vm_flush,
1572         .get_rptr = &radeon_ring_generic_get_rptr,
1573         .get_wptr = &radeon_ring_generic_get_wptr,
1574         .set_wptr = &radeon_ring_generic_set_wptr,
1575 };
1576
1577 static struct radeon_asic_ring cayman_dma_ring = {
1578         .ib_execute = &cayman_dma_ring_ib_execute,
1579         .ib_parse = &evergreen_dma_ib_parse,
1580         .emit_fence = &evergreen_dma_fence_ring_emit,
1581         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1582         .cs_parse = &evergreen_dma_cs_parse,
1583         .ring_test = &r600_dma_ring_test,
1584         .ib_test = &r600_dma_ib_test,
1585         .is_lockup = &cayman_dma_is_lockup,
1586         .vm_flush = &cayman_dma_vm_flush,
1587         .get_rptr = &r600_dma_get_rptr,
1588         .get_wptr = &r600_dma_get_wptr,
1589         .set_wptr = &r600_dma_set_wptr
1590 };
1591
1592 static struct radeon_asic_ring cayman_uvd_ring = {
1593         .ib_execute = &uvd_v1_0_ib_execute,
1594         .emit_fence = &uvd_v2_2_fence_emit,
1595         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1596         .cs_parse = &radeon_uvd_cs_parse,
1597         .ring_test = &uvd_v1_0_ring_test,
1598         .ib_test = &uvd_v1_0_ib_test,
1599         .is_lockup = &radeon_ring_test_lockup,
1600         .get_rptr = &uvd_v1_0_get_rptr,
1601         .get_wptr = &uvd_v1_0_get_wptr,
1602         .set_wptr = &uvd_v1_0_set_wptr,
1603 };
1604
1605 static struct radeon_asic cayman_asic = {
1606         .init = &cayman_init,
1607         .fini = &cayman_fini,
1608         .suspend = &cayman_suspend,
1609         .resume = &cayman_resume,
1610         .asic_reset = &cayman_asic_reset,
1611         .vga_set_state = &r600_vga_set_state,
1612         .ioctl_wait_idle = r600_ioctl_wait_idle,
1613         .gui_idle = &r600_gui_idle,
1614         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1615         .get_xclk = &rv770_get_xclk,
1616         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1617         .gart = {
1618                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1619                 .set_page = &rs600_gart_set_page,
1620         },
1621         .vm = {
1622                 .init = &cayman_vm_init,
1623                 .fini = &cayman_vm_fini,
1624                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1625                 .set_page = &cayman_vm_set_page,
1626         },
1627         .ring = {
1628                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1629                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1630                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1631                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1632                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1633                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1634         },
1635         .irq = {
1636                 .set = &evergreen_irq_set,
1637                 .process = &evergreen_irq_process,
1638         },
1639         .display = {
1640                 .bandwidth_update = &evergreen_bandwidth_update,
1641                 .get_vblank_counter = &evergreen_get_vblank_counter,
1642                 .wait_for_vblank = &dce4_wait_for_vblank,
1643                 .set_backlight_level = &atombios_set_backlight_level,
1644                 .get_backlight_level = &atombios_get_backlight_level,
1645                 .hdmi_enable = &evergreen_hdmi_enable,
1646                 .hdmi_setmode = &evergreen_hdmi_setmode,
1647         },
1648         .copy = {
1649                 .blit = &r600_copy_cpdma,
1650                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1651                 .dma = &evergreen_copy_dma,
1652                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1653                 .copy = &evergreen_copy_dma,
1654                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1655         },
1656         .surface = {
1657                 .set_reg = r600_set_surface_reg,
1658                 .clear_reg = r600_clear_surface_reg,
1659         },
1660         .hpd = {
1661                 .init = &evergreen_hpd_init,
1662                 .fini = &evergreen_hpd_fini,
1663                 .sense = &evergreen_hpd_sense,
1664                 .set_polarity = &evergreen_hpd_set_polarity,
1665         },
1666         .pm = {
1667                 .misc = &evergreen_pm_misc,
1668                 .prepare = &evergreen_pm_prepare,
1669                 .finish = &evergreen_pm_finish,
1670                 .init_profile = &btc_pm_init_profile,
1671                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1672                 .get_engine_clock = &radeon_atom_get_engine_clock,
1673                 .set_engine_clock = &radeon_atom_set_engine_clock,
1674                 .get_memory_clock = &radeon_atom_get_memory_clock,
1675                 .set_memory_clock = &radeon_atom_set_memory_clock,
1676                 .get_pcie_lanes = &r600_get_pcie_lanes,
1677                 .set_pcie_lanes = &r600_set_pcie_lanes,
1678                 .set_clock_gating = NULL,
1679                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1680                 .get_temperature = &evergreen_get_temp,
1681         },
1682         .dpm = {
1683                 .init = &ni_dpm_init,
1684                 .setup_asic = &ni_dpm_setup_asic,
1685                 .enable = &ni_dpm_enable,
1686                 .disable = &ni_dpm_disable,
1687                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1688                 .set_power_state = &ni_dpm_set_power_state,
1689                 .post_set_power_state = &ni_dpm_post_set_power_state,
1690                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1691                 .fini = &ni_dpm_fini,
1692                 .get_sclk = &ni_dpm_get_sclk,
1693                 .get_mclk = &ni_dpm_get_mclk,
1694                 .print_power_state = &ni_dpm_print_power_state,
1695                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1696                 .force_performance_level = &ni_dpm_force_performance_level,
1697                 .vblank_too_short = &ni_dpm_vblank_too_short,
1698         },
1699         .pflip = {
1700                 .pre_page_flip = &evergreen_pre_page_flip,
1701                 .page_flip = &evergreen_page_flip,
1702                 .post_page_flip = &evergreen_post_page_flip,
1703         },
1704 };
1705
1706 static struct radeon_asic trinity_asic = {
1707         .init = &cayman_init,
1708         .fini = &cayman_fini,
1709         .suspend = &cayman_suspend,
1710         .resume = &cayman_resume,
1711         .asic_reset = &cayman_asic_reset,
1712         .vga_set_state = &r600_vga_set_state,
1713         .ioctl_wait_idle = r600_ioctl_wait_idle,
1714         .gui_idle = &r600_gui_idle,
1715         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1716         .get_xclk = &r600_get_xclk,
1717         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1718         .gart = {
1719                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1720                 .set_page = &rs600_gart_set_page,
1721         },
1722         .vm = {
1723                 .init = &cayman_vm_init,
1724                 .fini = &cayman_vm_fini,
1725                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1726                 .set_page = &cayman_vm_set_page,
1727         },
1728         .ring = {
1729                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1730                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1731                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1732                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1733                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1734                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1735         },
1736         .irq = {
1737                 .set = &evergreen_irq_set,
1738                 .process = &evergreen_irq_process,
1739         },
1740         .display = {
1741                 .bandwidth_update = &dce6_bandwidth_update,
1742                 .get_vblank_counter = &evergreen_get_vblank_counter,
1743                 .wait_for_vblank = &dce4_wait_for_vblank,
1744                 .set_backlight_level = &atombios_set_backlight_level,
1745                 .get_backlight_level = &atombios_get_backlight_level,
1746                 .hdmi_enable = &evergreen_hdmi_enable,
1747                 .hdmi_setmode = &evergreen_hdmi_setmode,
1748         },
1749         .copy = {
1750                 .blit = &r600_copy_cpdma,
1751                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1752                 .dma = &evergreen_copy_dma,
1753                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1754                 .copy = &evergreen_copy_dma,
1755                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1756         },
1757         .surface = {
1758                 .set_reg = r600_set_surface_reg,
1759                 .clear_reg = r600_clear_surface_reg,
1760         },
1761         .hpd = {
1762                 .init = &evergreen_hpd_init,
1763                 .fini = &evergreen_hpd_fini,
1764                 .sense = &evergreen_hpd_sense,
1765                 .set_polarity = &evergreen_hpd_set_polarity,
1766         },
1767         .pm = {
1768                 .misc = &evergreen_pm_misc,
1769                 .prepare = &evergreen_pm_prepare,
1770                 .finish = &evergreen_pm_finish,
1771                 .init_profile = &sumo_pm_init_profile,
1772                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1773                 .get_engine_clock = &radeon_atom_get_engine_clock,
1774                 .set_engine_clock = &radeon_atom_set_engine_clock,
1775                 .get_memory_clock = NULL,
1776                 .set_memory_clock = NULL,
1777                 .get_pcie_lanes = NULL,
1778                 .set_pcie_lanes = NULL,
1779                 .set_clock_gating = NULL,
1780                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1781                 .get_temperature = &tn_get_temp,
1782         },
1783         .dpm = {
1784                 .init = &trinity_dpm_init,
1785                 .setup_asic = &trinity_dpm_setup_asic,
1786                 .enable = &trinity_dpm_enable,
1787                 .disable = &trinity_dpm_disable,
1788                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1789                 .set_power_state = &trinity_dpm_set_power_state,
1790                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1791                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1792                 .fini = &trinity_dpm_fini,
1793                 .get_sclk = &trinity_dpm_get_sclk,
1794                 .get_mclk = &trinity_dpm_get_mclk,
1795                 .print_power_state = &trinity_dpm_print_power_state,
1796                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1797                 .force_performance_level = &trinity_dpm_force_performance_level,
1798                 .enable_bapm = &trinity_dpm_enable_bapm,
1799         },
1800         .pflip = {
1801                 .pre_page_flip = &evergreen_pre_page_flip,
1802                 .page_flip = &evergreen_page_flip,
1803                 .post_page_flip = &evergreen_post_page_flip,
1804         },
1805 };
1806
1807 static struct radeon_asic_ring si_gfx_ring = {
1808         .ib_execute = &si_ring_ib_execute,
1809         .ib_parse = &si_ib_parse,
1810         .emit_fence = &si_fence_ring_emit,
1811         .emit_semaphore = &r600_semaphore_ring_emit,
1812         .cs_parse = NULL,
1813         .ring_test = &r600_ring_test,
1814         .ib_test = &r600_ib_test,
1815         .is_lockup = &si_gfx_is_lockup,
1816         .vm_flush = &si_vm_flush,
1817         .get_rptr = &radeon_ring_generic_get_rptr,
1818         .get_wptr = &radeon_ring_generic_get_wptr,
1819         .set_wptr = &radeon_ring_generic_set_wptr,
1820 };
1821
1822 static struct radeon_asic_ring si_dma_ring = {
1823         .ib_execute = &cayman_dma_ring_ib_execute,
1824         .ib_parse = &evergreen_dma_ib_parse,
1825         .emit_fence = &evergreen_dma_fence_ring_emit,
1826         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1827         .cs_parse = NULL,
1828         .ring_test = &r600_dma_ring_test,
1829         .ib_test = &r600_dma_ib_test,
1830         .is_lockup = &si_dma_is_lockup,
1831         .vm_flush = &si_dma_vm_flush,
1832         .get_rptr = &r600_dma_get_rptr,
1833         .get_wptr = &r600_dma_get_wptr,
1834         .set_wptr = &r600_dma_set_wptr,
1835 };
1836
1837 static struct radeon_asic si_asic = {
1838         .init = &si_init,
1839         .fini = &si_fini,
1840         .suspend = &si_suspend,
1841         .resume = &si_resume,
1842         .asic_reset = &si_asic_reset,
1843         .vga_set_state = &r600_vga_set_state,
1844         .ioctl_wait_idle = r600_ioctl_wait_idle,
1845         .gui_idle = &r600_gui_idle,
1846         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1847         .get_xclk = &si_get_xclk,
1848         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1849         .gart = {
1850                 .tlb_flush = &si_pcie_gart_tlb_flush,
1851                 .set_page = &rs600_gart_set_page,
1852         },
1853         .vm = {
1854                 .init = &si_vm_init,
1855                 .fini = &si_vm_fini,
1856                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1857                 .set_page = &si_vm_set_page,
1858         },
1859         .ring = {
1860                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1861                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1862                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1863                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1864                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1865                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1866         },
1867         .irq = {
1868                 .set = &si_irq_set,
1869                 .process = &si_irq_process,
1870         },
1871         .display = {
1872                 .bandwidth_update = &dce6_bandwidth_update,
1873                 .get_vblank_counter = &evergreen_get_vblank_counter,
1874                 .wait_for_vblank = &dce4_wait_for_vblank,
1875                 .set_backlight_level = &atombios_set_backlight_level,
1876                 .get_backlight_level = &atombios_get_backlight_level,
1877                 .hdmi_enable = &evergreen_hdmi_enable,
1878                 .hdmi_setmode = &evergreen_hdmi_setmode,
1879         },
1880         .copy = {
1881                 .blit = NULL,
1882                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1883                 .dma = &si_copy_dma,
1884                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1885                 .copy = &si_copy_dma,
1886                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1887         },
1888         .surface = {
1889                 .set_reg = r600_set_surface_reg,
1890                 .clear_reg = r600_clear_surface_reg,
1891         },
1892         .hpd = {
1893                 .init = &evergreen_hpd_init,
1894                 .fini = &evergreen_hpd_fini,
1895                 .sense = &evergreen_hpd_sense,
1896                 .set_polarity = &evergreen_hpd_set_polarity,
1897         },
1898         .pm = {
1899                 .misc = &evergreen_pm_misc,
1900                 .prepare = &evergreen_pm_prepare,
1901                 .finish = &evergreen_pm_finish,
1902                 .init_profile = &sumo_pm_init_profile,
1903                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1904                 .get_engine_clock = &radeon_atom_get_engine_clock,
1905                 .set_engine_clock = &radeon_atom_set_engine_clock,
1906                 .get_memory_clock = &radeon_atom_get_memory_clock,
1907                 .set_memory_clock = &radeon_atom_set_memory_clock,
1908                 .get_pcie_lanes = &r600_get_pcie_lanes,
1909                 .set_pcie_lanes = &r600_set_pcie_lanes,
1910                 .set_clock_gating = NULL,
1911                 .set_uvd_clocks = &si_set_uvd_clocks,
1912                 .get_temperature = &si_get_temp,
1913         },
1914         .dpm = {
1915                 .init = &si_dpm_init,
1916                 .setup_asic = &si_dpm_setup_asic,
1917                 .enable = &si_dpm_enable,
1918                 .disable = &si_dpm_disable,
1919                 .pre_set_power_state = &si_dpm_pre_set_power_state,
1920                 .set_power_state = &si_dpm_set_power_state,
1921                 .post_set_power_state = &si_dpm_post_set_power_state,
1922                 .display_configuration_changed = &si_dpm_display_configuration_changed,
1923                 .fini = &si_dpm_fini,
1924                 .get_sclk = &ni_dpm_get_sclk,
1925                 .get_mclk = &ni_dpm_get_mclk,
1926                 .print_power_state = &ni_dpm_print_power_state,
1927                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1928                 .force_performance_level = &si_dpm_force_performance_level,
1929                 .vblank_too_short = &ni_dpm_vblank_too_short,
1930         },
1931         .pflip = {
1932                 .pre_page_flip = &evergreen_pre_page_flip,
1933                 .page_flip = &evergreen_page_flip,
1934                 .post_page_flip = &evergreen_post_page_flip,
1935         },
1936 };
1937
1938 static struct radeon_asic_ring ci_gfx_ring = {
1939         .ib_execute = &cik_ring_ib_execute,
1940         .ib_parse = &cik_ib_parse,
1941         .emit_fence = &cik_fence_gfx_ring_emit,
1942         .emit_semaphore = &cik_semaphore_ring_emit,
1943         .cs_parse = NULL,
1944         .ring_test = &cik_ring_test,
1945         .ib_test = &cik_ib_test,
1946         .is_lockup = &cik_gfx_is_lockup,
1947         .vm_flush = &cik_vm_flush,
1948         .get_rptr = &radeon_ring_generic_get_rptr,
1949         .get_wptr = &radeon_ring_generic_get_wptr,
1950         .set_wptr = &radeon_ring_generic_set_wptr,
1951 };
1952
1953 static struct radeon_asic_ring ci_cp_ring = {
1954         .ib_execute = &cik_ring_ib_execute,
1955         .ib_parse = &cik_ib_parse,
1956         .emit_fence = &cik_fence_compute_ring_emit,
1957         .emit_semaphore = &cik_semaphore_ring_emit,
1958         .cs_parse = NULL,
1959         .ring_test = &cik_ring_test,
1960         .ib_test = &cik_ib_test,
1961         .is_lockup = &cik_gfx_is_lockup,
1962         .vm_flush = &cik_vm_flush,
1963         .get_rptr = &cik_compute_ring_get_rptr,
1964         .get_wptr = &cik_compute_ring_get_wptr,
1965         .set_wptr = &cik_compute_ring_set_wptr,
1966 };
1967
1968 static struct radeon_asic_ring ci_dma_ring = {
1969         .ib_execute = &cik_sdma_ring_ib_execute,
1970         .ib_parse = &cik_ib_parse,
1971         .emit_fence = &cik_sdma_fence_ring_emit,
1972         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1973         .cs_parse = NULL,
1974         .ring_test = &cik_sdma_ring_test,
1975         .ib_test = &cik_sdma_ib_test,
1976         .is_lockup = &cik_sdma_is_lockup,
1977         .vm_flush = &cik_dma_vm_flush,
1978         .get_rptr = &r600_dma_get_rptr,
1979         .get_wptr = &r600_dma_get_wptr,
1980         .set_wptr = &r600_dma_set_wptr,
1981 };
1982
1983 static struct radeon_asic ci_asic = {
1984         .init = &cik_init,
1985         .fini = &cik_fini,
1986         .suspend = &cik_suspend,
1987         .resume = &cik_resume,
1988         .asic_reset = &cik_asic_reset,
1989         .vga_set_state = &r600_vga_set_state,
1990         .ioctl_wait_idle = NULL,
1991         .gui_idle = &r600_gui_idle,
1992         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1993         .get_xclk = &cik_get_xclk,
1994         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
1995         .gart = {
1996                 .tlb_flush = &cik_pcie_gart_tlb_flush,
1997                 .set_page = &rs600_gart_set_page,
1998         },
1999         .vm = {
2000                 .init = &cik_vm_init,
2001                 .fini = &cik_vm_fini,
2002                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2003                 .set_page = &cik_vm_set_page,
2004         },
2005         .ring = {
2006                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2007                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2008                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2009                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2010                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2011                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2012         },
2013         .irq = {
2014                 .set = &cik_irq_set,
2015                 .process = &cik_irq_process,
2016         },
2017         .display = {
2018                 .bandwidth_update = &dce8_bandwidth_update,
2019                 .get_vblank_counter = &evergreen_get_vblank_counter,
2020                 .wait_for_vblank = &dce4_wait_for_vblank,
2021                 .hdmi_enable = &evergreen_hdmi_enable,
2022                 .hdmi_setmode = &evergreen_hdmi_setmode,
2023         },
2024         .copy = {
2025                 .blit = NULL,
2026                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2027                 .dma = &cik_copy_dma,
2028                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2029                 .copy = &cik_copy_dma,
2030                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2031         },
2032         .surface = {
2033                 .set_reg = r600_set_surface_reg,
2034                 .clear_reg = r600_clear_surface_reg,
2035         },
2036         .hpd = {
2037                 .init = &evergreen_hpd_init,
2038                 .fini = &evergreen_hpd_fini,
2039                 .sense = &evergreen_hpd_sense,
2040                 .set_polarity = &evergreen_hpd_set_polarity,
2041         },
2042         .pm = {
2043                 .misc = &evergreen_pm_misc,
2044                 .prepare = &evergreen_pm_prepare,
2045                 .finish = &evergreen_pm_finish,
2046                 .init_profile = &sumo_pm_init_profile,
2047                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2048                 .get_engine_clock = &radeon_atom_get_engine_clock,
2049                 .set_engine_clock = &radeon_atom_set_engine_clock,
2050                 .get_memory_clock = &radeon_atom_get_memory_clock,
2051                 .set_memory_clock = &radeon_atom_set_memory_clock,
2052                 .get_pcie_lanes = NULL,
2053                 .set_pcie_lanes = NULL,
2054                 .set_clock_gating = NULL,
2055                 .set_uvd_clocks = &cik_set_uvd_clocks,
2056                 .get_temperature = &ci_get_temp,
2057         },
2058         .dpm = {
2059                 .init = &ci_dpm_init,
2060                 .setup_asic = &ci_dpm_setup_asic,
2061                 .enable = &ci_dpm_enable,
2062                 .disable = &ci_dpm_disable,
2063                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2064                 .set_power_state = &ci_dpm_set_power_state,
2065                 .post_set_power_state = &ci_dpm_post_set_power_state,
2066                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2067                 .fini = &ci_dpm_fini,
2068                 .get_sclk = &ci_dpm_get_sclk,
2069                 .get_mclk = &ci_dpm_get_mclk,
2070                 .print_power_state = &ci_dpm_print_power_state,
2071                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2072                 .force_performance_level = &ci_dpm_force_performance_level,
2073                 .vblank_too_short = &ci_dpm_vblank_too_short,
2074                 .powergate_uvd = &ci_dpm_powergate_uvd,
2075         },
2076         .pflip = {
2077                 .pre_page_flip = &evergreen_pre_page_flip,
2078                 .page_flip = &evergreen_page_flip,
2079                 .post_page_flip = &evergreen_post_page_flip,
2080         },
2081 };
2082
2083 static struct radeon_asic kv_asic = {
2084         .init = &cik_init,
2085         .fini = &cik_fini,
2086         .suspend = &cik_suspend,
2087         .resume = &cik_resume,
2088         .asic_reset = &cik_asic_reset,
2089         .vga_set_state = &r600_vga_set_state,
2090         .ioctl_wait_idle = NULL,
2091         .gui_idle = &r600_gui_idle,
2092         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2093         .get_xclk = &cik_get_xclk,
2094         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2095         .gart = {
2096                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2097                 .set_page = &rs600_gart_set_page,
2098         },
2099         .vm = {
2100                 .init = &cik_vm_init,
2101                 .fini = &cik_vm_fini,
2102                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2103                 .set_page = &cik_vm_set_page,
2104         },
2105         .ring = {
2106                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2107                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2108                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2109                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2110                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2111                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2112         },
2113         .irq = {
2114                 .set = &cik_irq_set,
2115                 .process = &cik_irq_process,
2116         },
2117         .display = {
2118                 .bandwidth_update = &dce8_bandwidth_update,
2119                 .get_vblank_counter = &evergreen_get_vblank_counter,
2120                 .wait_for_vblank = &dce4_wait_for_vblank,
2121                 .hdmi_enable = &evergreen_hdmi_enable,
2122                 .hdmi_setmode = &evergreen_hdmi_setmode,
2123         },
2124         .copy = {
2125                 .blit = NULL,
2126                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2127                 .dma = &cik_copy_dma,
2128                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2129                 .copy = &cik_copy_dma,
2130                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2131         },
2132         .surface = {
2133                 .set_reg = r600_set_surface_reg,
2134                 .clear_reg = r600_clear_surface_reg,
2135         },
2136         .hpd = {
2137                 .init = &evergreen_hpd_init,
2138                 .fini = &evergreen_hpd_fini,
2139                 .sense = &evergreen_hpd_sense,
2140                 .set_polarity = &evergreen_hpd_set_polarity,
2141         },
2142         .pm = {
2143                 .misc = &evergreen_pm_misc,
2144                 .prepare = &evergreen_pm_prepare,
2145                 .finish = &evergreen_pm_finish,
2146                 .init_profile = &sumo_pm_init_profile,
2147                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2148                 .get_engine_clock = &radeon_atom_get_engine_clock,
2149                 .set_engine_clock = &radeon_atom_set_engine_clock,
2150                 .get_memory_clock = &radeon_atom_get_memory_clock,
2151                 .set_memory_clock = &radeon_atom_set_memory_clock,
2152                 .get_pcie_lanes = NULL,
2153                 .set_pcie_lanes = NULL,
2154                 .set_clock_gating = NULL,
2155                 .set_uvd_clocks = &cik_set_uvd_clocks,
2156                 .get_temperature = &kv_get_temp,
2157         },
2158         .dpm = {
2159                 .init = &kv_dpm_init,
2160                 .setup_asic = &kv_dpm_setup_asic,
2161                 .enable = &kv_dpm_enable,
2162                 .disable = &kv_dpm_disable,
2163                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2164                 .set_power_state = &kv_dpm_set_power_state,
2165                 .post_set_power_state = &kv_dpm_post_set_power_state,
2166                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2167                 .fini = &kv_dpm_fini,
2168                 .get_sclk = &kv_dpm_get_sclk,
2169                 .get_mclk = &kv_dpm_get_mclk,
2170                 .print_power_state = &kv_dpm_print_power_state,
2171                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2172                 .force_performance_level = &kv_dpm_force_performance_level,
2173                 .powergate_uvd = &kv_dpm_powergate_uvd,
2174                 .enable_bapm = &kv_dpm_enable_bapm,
2175         },
2176         .pflip = {
2177                 .pre_page_flip = &evergreen_pre_page_flip,
2178                 .page_flip = &evergreen_page_flip,
2179                 .post_page_flip = &evergreen_post_page_flip,
2180         },
2181 };
2182
2183 /**
2184  * radeon_asic_init - register asic specific callbacks
2185  *
2186  * @rdev: radeon device pointer
2187  *
2188  * Registers the appropriate asic specific callbacks for each
2189  * chip family.  Also sets other asics specific info like the number
2190  * of crtcs and the register aperture accessors (all asics).
2191  * Returns 0 for success.
2192  */
2193 int radeon_asic_init(struct radeon_device *rdev)
2194 {
2195         radeon_register_accessor_init(rdev);
2196
2197         /* set the number of crtcs */
2198         if (rdev->flags & RADEON_SINGLE_CRTC)
2199                 rdev->num_crtc = 1;
2200         else
2201                 rdev->num_crtc = 2;
2202
2203         rdev->has_uvd = false;
2204
2205         switch (rdev->family) {
2206         case CHIP_R100:
2207         case CHIP_RV100:
2208         case CHIP_RS100:
2209         case CHIP_RV200:
2210         case CHIP_RS200:
2211                 rdev->asic = &r100_asic;
2212                 break;
2213         case CHIP_R200:
2214         case CHIP_RV250:
2215         case CHIP_RS300:
2216         case CHIP_RV280:
2217                 rdev->asic = &r200_asic;
2218                 break;
2219         case CHIP_R300:
2220         case CHIP_R350:
2221         case CHIP_RV350:
2222         case CHIP_RV380:
2223                 if (rdev->flags & RADEON_IS_PCIE)
2224                         rdev->asic = &r300_asic_pcie;
2225                 else
2226                         rdev->asic = &r300_asic;
2227                 break;
2228         case CHIP_R420:
2229         case CHIP_R423:
2230         case CHIP_RV410:
2231                 rdev->asic = &r420_asic;
2232                 /* handle macs */
2233                 if (rdev->bios == NULL) {
2234                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2235                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2236                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2237                         rdev->asic->pm.set_memory_clock = NULL;
2238                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2239                 }
2240                 break;
2241         case CHIP_RS400:
2242         case CHIP_RS480:
2243                 rdev->asic = &rs400_asic;
2244                 break;
2245         case CHIP_RS600:
2246                 rdev->asic = &rs600_asic;
2247                 break;
2248         case CHIP_RS690:
2249         case CHIP_RS740:
2250                 rdev->asic = &rs690_asic;
2251                 break;
2252         case CHIP_RV515:
2253                 rdev->asic = &rv515_asic;
2254                 break;
2255         case CHIP_R520:
2256         case CHIP_RV530:
2257         case CHIP_RV560:
2258         case CHIP_RV570:
2259         case CHIP_R580:
2260                 rdev->asic = &r520_asic;
2261                 break;
2262         case CHIP_R600:
2263                 rdev->asic = &r600_asic;
2264                 break;
2265         case CHIP_RV610:
2266         case CHIP_RV630:
2267         case CHIP_RV620:
2268         case CHIP_RV635:
2269         case CHIP_RV670:
2270                 rdev->asic = &rv6xx_asic;
2271                 rdev->has_uvd = true;
2272                 break;
2273         case CHIP_RS780:
2274         case CHIP_RS880:
2275                 rdev->asic = &rs780_asic;
2276                 rdev->has_uvd = true;
2277                 break;
2278         case CHIP_RV770:
2279         case CHIP_RV730:
2280         case CHIP_RV710:
2281         case CHIP_RV740:
2282                 rdev->asic = &rv770_asic;
2283                 rdev->has_uvd = true;
2284                 break;
2285         case CHIP_CEDAR:
2286         case CHIP_REDWOOD:
2287         case CHIP_JUNIPER:
2288         case CHIP_CYPRESS:
2289         case CHIP_HEMLOCK:
2290                 /* set num crtcs */
2291                 if (rdev->family == CHIP_CEDAR)
2292                         rdev->num_crtc = 4;
2293                 else
2294                         rdev->num_crtc = 6;
2295                 rdev->asic = &evergreen_asic;
2296                 rdev->has_uvd = true;
2297                 break;
2298         case CHIP_PALM:
2299         case CHIP_SUMO:
2300         case CHIP_SUMO2:
2301                 rdev->asic = &sumo_asic;
2302                 rdev->has_uvd = true;
2303                 break;
2304         case CHIP_BARTS:
2305         case CHIP_TURKS:
2306         case CHIP_CAICOS:
2307                 /* set num crtcs */
2308                 if (rdev->family == CHIP_CAICOS)
2309                         rdev->num_crtc = 4;
2310                 else
2311                         rdev->num_crtc = 6;
2312                 rdev->asic = &btc_asic;
2313                 rdev->has_uvd = true;
2314                 break;
2315         case CHIP_CAYMAN:
2316                 rdev->asic = &cayman_asic;
2317                 /* set num crtcs */
2318                 rdev->num_crtc = 6;
2319                 rdev->has_uvd = true;
2320                 break;
2321         case CHIP_ARUBA:
2322                 rdev->asic = &trinity_asic;
2323                 /* set num crtcs */
2324                 rdev->num_crtc = 4;
2325                 rdev->has_uvd = true;
2326                 break;
2327         case CHIP_TAHITI:
2328         case CHIP_PITCAIRN:
2329         case CHIP_VERDE:
2330         case CHIP_OLAND:
2331         case CHIP_HAINAN:
2332                 rdev->asic = &si_asic;
2333                 /* set num crtcs */
2334                 if (rdev->family == CHIP_HAINAN)
2335                         rdev->num_crtc = 0;
2336                 else if (rdev->family == CHIP_OLAND)
2337                         rdev->num_crtc = 2;
2338                 else
2339                         rdev->num_crtc = 6;
2340                 if (rdev->family == CHIP_HAINAN)
2341                         rdev->has_uvd = false;
2342                 else
2343                         rdev->has_uvd = true;
2344                 switch (rdev->family) {
2345                 case CHIP_TAHITI:
2346                         rdev->cg_flags =
2347                                 RADEON_CG_SUPPORT_GFX_MGCG |
2348                                 RADEON_CG_SUPPORT_GFX_MGLS |
2349                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2350                                 RADEON_CG_SUPPORT_GFX_CGLS |
2351                                 RADEON_CG_SUPPORT_GFX_CGTS |
2352                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2353                                 RADEON_CG_SUPPORT_MC_MGCG |
2354                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2355                                 RADEON_CG_SUPPORT_BIF_LS |
2356                                 RADEON_CG_SUPPORT_VCE_MGCG |
2357                                 RADEON_CG_SUPPORT_UVD_MGCG |
2358                                 RADEON_CG_SUPPORT_HDP_LS |
2359                                 RADEON_CG_SUPPORT_HDP_MGCG;
2360                         rdev->pg_flags = 0;
2361                         break;
2362                 case CHIP_PITCAIRN:
2363                         rdev->cg_flags =
2364                                 RADEON_CG_SUPPORT_GFX_MGCG |
2365                                 RADEON_CG_SUPPORT_GFX_MGLS |
2366                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2367                                 RADEON_CG_SUPPORT_GFX_CGLS |
2368                                 RADEON_CG_SUPPORT_GFX_CGTS |
2369                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2370                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2371                                 RADEON_CG_SUPPORT_MC_LS |
2372                                 RADEON_CG_SUPPORT_MC_MGCG |
2373                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2374                                 RADEON_CG_SUPPORT_BIF_LS |
2375                                 RADEON_CG_SUPPORT_VCE_MGCG |
2376                                 RADEON_CG_SUPPORT_UVD_MGCG |
2377                                 RADEON_CG_SUPPORT_HDP_LS |
2378                                 RADEON_CG_SUPPORT_HDP_MGCG;
2379                         rdev->pg_flags = 0;
2380                         break;
2381                 case CHIP_VERDE:
2382                         rdev->cg_flags =
2383                                 RADEON_CG_SUPPORT_GFX_MGCG |
2384                                 RADEON_CG_SUPPORT_GFX_MGLS |
2385                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2386                                 RADEON_CG_SUPPORT_GFX_CGLS |
2387                                 RADEON_CG_SUPPORT_GFX_CGTS |
2388                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2389                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2390                                 RADEON_CG_SUPPORT_MC_LS |
2391                                 RADEON_CG_SUPPORT_MC_MGCG |
2392                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2393                                 RADEON_CG_SUPPORT_BIF_LS |
2394                                 RADEON_CG_SUPPORT_VCE_MGCG |
2395                                 RADEON_CG_SUPPORT_UVD_MGCG |
2396                                 RADEON_CG_SUPPORT_HDP_LS |
2397                                 RADEON_CG_SUPPORT_HDP_MGCG;
2398                         rdev->pg_flags = 0 |
2399                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2400                                 RADEON_PG_SUPPORT_SDMA;
2401                         break;
2402                 case CHIP_OLAND:
2403                         rdev->cg_flags =
2404                                 RADEON_CG_SUPPORT_GFX_MGCG |
2405                                 RADEON_CG_SUPPORT_GFX_MGLS |
2406                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2407                                 RADEON_CG_SUPPORT_GFX_CGLS |
2408                                 RADEON_CG_SUPPORT_GFX_CGTS |
2409                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2410                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2411                                 RADEON_CG_SUPPORT_MC_LS |
2412                                 RADEON_CG_SUPPORT_MC_MGCG |
2413                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2414                                 RADEON_CG_SUPPORT_BIF_LS |
2415                                 RADEON_CG_SUPPORT_UVD_MGCG |
2416                                 RADEON_CG_SUPPORT_HDP_LS |
2417                                 RADEON_CG_SUPPORT_HDP_MGCG;
2418                         rdev->pg_flags = 0;
2419                         break;
2420                 case CHIP_HAINAN:
2421                         rdev->cg_flags =
2422                                 RADEON_CG_SUPPORT_GFX_MGCG |
2423                                 RADEON_CG_SUPPORT_GFX_MGLS |
2424                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2425                                 RADEON_CG_SUPPORT_GFX_CGLS |
2426                                 RADEON_CG_SUPPORT_GFX_CGTS |
2427                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2428                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2429                                 RADEON_CG_SUPPORT_MC_LS |
2430                                 RADEON_CG_SUPPORT_MC_MGCG |
2431                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2432                                 RADEON_CG_SUPPORT_BIF_LS |
2433                                 RADEON_CG_SUPPORT_HDP_LS |
2434                                 RADEON_CG_SUPPORT_HDP_MGCG;
2435                         rdev->pg_flags = 0;
2436                         break;
2437                 default:
2438                         rdev->cg_flags = 0;
2439                         rdev->pg_flags = 0;
2440                         break;
2441                 }
2442                 break;
2443         case CHIP_BONAIRE:
2444                 rdev->asic = &ci_asic;
2445                 rdev->num_crtc = 6;
2446                 rdev->has_uvd = true;
2447                 rdev->cg_flags =
2448                         RADEON_CG_SUPPORT_GFX_MGCG |
2449                         RADEON_CG_SUPPORT_GFX_MGLS |
2450                         /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2451                         RADEON_CG_SUPPORT_GFX_CGLS |
2452                         RADEON_CG_SUPPORT_GFX_CGTS |
2453                         RADEON_CG_SUPPORT_GFX_CGTS_LS |
2454                         RADEON_CG_SUPPORT_GFX_CP_LS |
2455                         RADEON_CG_SUPPORT_MC_LS |
2456                         RADEON_CG_SUPPORT_MC_MGCG |
2457                         RADEON_CG_SUPPORT_SDMA_MGCG |
2458                         RADEON_CG_SUPPORT_SDMA_LS |
2459                         RADEON_CG_SUPPORT_BIF_LS |
2460                         RADEON_CG_SUPPORT_VCE_MGCG |
2461                         RADEON_CG_SUPPORT_UVD_MGCG |
2462                         RADEON_CG_SUPPORT_HDP_LS |
2463                         RADEON_CG_SUPPORT_HDP_MGCG;
2464                 rdev->pg_flags = 0;
2465                 break;
2466         case CHIP_KAVERI:
2467         case CHIP_KABINI:
2468                 rdev->asic = &kv_asic;
2469                 /* set num crtcs */
2470                 if (rdev->family == CHIP_KAVERI) {
2471                         rdev->num_crtc = 4;
2472                         rdev->cg_flags =
2473                                 RADEON_CG_SUPPORT_GFX_MGCG |
2474                                 RADEON_CG_SUPPORT_GFX_MGLS |
2475                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2476                                 RADEON_CG_SUPPORT_GFX_CGLS |
2477                                 RADEON_CG_SUPPORT_GFX_CGTS |
2478                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2479                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2480                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2481                                 RADEON_CG_SUPPORT_SDMA_LS |
2482                                 RADEON_CG_SUPPORT_BIF_LS |
2483                                 RADEON_CG_SUPPORT_VCE_MGCG |
2484                                 RADEON_CG_SUPPORT_UVD_MGCG |
2485                                 RADEON_CG_SUPPORT_HDP_LS |
2486                                 RADEON_CG_SUPPORT_HDP_MGCG;
2487                         rdev->pg_flags = 0;
2488                                 /*RADEON_PG_SUPPORT_GFX_PG |
2489                                 RADEON_PG_SUPPORT_GFX_SMG |
2490                                 RADEON_PG_SUPPORT_GFX_DMG |
2491                                 RADEON_PG_SUPPORT_UVD |
2492                                 RADEON_PG_SUPPORT_VCE |
2493                                 RADEON_PG_SUPPORT_CP |
2494                                 RADEON_PG_SUPPORT_GDS |
2495                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2496                                 RADEON_PG_SUPPORT_ACP |
2497                                 RADEON_PG_SUPPORT_SAMU;*/
2498                 } else {
2499                         rdev->num_crtc = 2;
2500                         rdev->cg_flags =
2501                                 RADEON_CG_SUPPORT_GFX_MGCG |
2502                                 RADEON_CG_SUPPORT_GFX_MGLS |
2503                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2504                                 RADEON_CG_SUPPORT_GFX_CGLS |
2505                                 RADEON_CG_SUPPORT_GFX_CGTS |
2506                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2507                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2508                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2509                                 RADEON_CG_SUPPORT_SDMA_LS |
2510                                 RADEON_CG_SUPPORT_BIF_LS |
2511                                 RADEON_CG_SUPPORT_VCE_MGCG |
2512                                 RADEON_CG_SUPPORT_UVD_MGCG |
2513                                 RADEON_CG_SUPPORT_HDP_LS |
2514                                 RADEON_CG_SUPPORT_HDP_MGCG;
2515                         rdev->pg_flags = 0;
2516                                 /*RADEON_PG_SUPPORT_GFX_PG |
2517                                 RADEON_PG_SUPPORT_GFX_SMG |
2518                                 RADEON_PG_SUPPORT_UVD |
2519                                 RADEON_PG_SUPPORT_VCE |
2520                                 RADEON_PG_SUPPORT_CP |
2521                                 RADEON_PG_SUPPORT_GDS |
2522                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2523                                 RADEON_PG_SUPPORT_SAMU;*/
2524                 }
2525                 rdev->has_uvd = true;
2526                 break;
2527         default:
2528                 /* FIXME: not supported yet */
2529                 return -EINVAL;
2530         }
2531
2532         if (rdev->flags & RADEON_IS_IGP) {
2533                 rdev->asic->pm.get_memory_clock = NULL;
2534                 rdev->asic->pm.set_memory_clock = NULL;
2535         }
2536
2537         return 0;
2538 }
2539