2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/md_var.h>
36 #include <machine/pmap.h>
37 #include <machine_base/apic/lapic.h>
38 #include <machine_base/apic/ioapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
40 #include <machine/segments.h>
41 #include <sys/thread2.h>
43 #include <machine/cputypes.h>
44 #include <machine/intr_machdep.h>
50 volatile lapic_t *lapic;
52 static void lapic_timer_calibrate(void);
53 static void lapic_timer_set_divisor(int);
54 static void lapic_timer_fixup_handler(void *);
55 static void lapic_timer_restart_handler(void *);
57 void lapic_timer_process(void);
58 void lapic_timer_process_frame(struct intrframe *);
59 void lapic_timer_always(struct intrframe *);
61 static int lapic_timer_enable = 1;
62 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
64 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
65 static void lapic_timer_intr_enable(struct cputimer_intr *);
66 static void lapic_timer_intr_restart(struct cputimer_intr *);
67 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
69 static struct cputimer_intr lapic_cputimer_intr = {
71 .reload = lapic_timer_intr_reload,
72 .enable = lapic_timer_intr_enable,
73 .config = cputimer_intr_default_config,
74 .restart = lapic_timer_intr_restart,
75 .pmfixup = lapic_timer_intr_pmfixup,
76 .initclock = cputimer_intr_default_initclock,
77 .next = SLIST_ENTRY_INITIALIZER,
79 .type = CPUTIMER_INTR_LAPIC,
80 .prio = CPUTIMER_INTR_PRIO_LAPIC,
81 .caps = CPUTIMER_INTR_CAP_NONE
84 static int lapic_timer_divisor_idx = -1;
85 static const uint32_t lapic_timer_divisors[] = {
86 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
87 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
89 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
92 * APIC ID <-> CPU ID mapping structures.
94 int cpu_id_to_apic_id[NAPICID];
95 int apic_id_to_cpu_id[NAPICID];
106 * Enable LAPIC, configure interrupts.
109 lapic_init(boolean_t bsp)
117 * Since IDT is shared between BSP and APs, these vectors
118 * only need to be installed once; we do it on BSP.
121 /* Install a 'Spurious INTerrupt' vector */
122 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
123 SDT_SYSIGT, SEL_KPL, 0);
125 /* Install an inter-CPU IPI for TLB invalidation */
126 setidt(XINVLTLB_OFFSET, Xinvltlb,
127 SDT_SYSIGT, SEL_KPL, 0);
129 /* Install an inter-CPU IPI for IPIQ messaging */
130 setidt(XIPIQ_OFFSET, Xipiq,
131 SDT_SYSIGT, SEL_KPL, 0);
133 /* Install a timer vector */
134 setidt(XTIMER_OFFSET, Xtimer,
135 SDT_SYSIGT, SEL_KPL, 0);
137 /* Install an inter-CPU IPI for CPU stop/restart */
138 setidt(XCPUSTOP_OFFSET, Xcpustop,
139 SDT_SYSIGT, SEL_KPL, 0);
143 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
144 * aggregate interrupt input from the 8259. The INTA cycle
145 * will be routed to the external controller (the 8259) which
146 * is expected to supply the vector.
148 * Must be setup edge triggered, active high.
150 * Disable LINT0 on BSP, if I/O APIC is enabled.
152 * Disable LINT0 on the APs. It doesn't matter what delivery
153 * mode we use because we leave it masked.
155 temp = lapic->lvt_lint0;
156 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
157 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
159 temp |= APIC_LVT_DM_EXTINT;
161 temp |= APIC_LVT_MASKED;
163 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
165 lapic->lvt_lint0 = temp;
168 * Setup LINT1 as NMI.
170 * Must be setup edge trigger, active high.
172 * Enable LINT1 on BSP, if I/O APIC is enabled.
174 * Disable LINT1 on the APs.
176 temp = lapic->lvt_lint1;
177 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
178 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
179 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
180 if (bsp && ioapic_enable)
181 temp &= ~APIC_LVT_MASKED;
182 lapic->lvt_lint1 = temp;
185 * Mask the LAPIC error interrupt, LAPIC performance counter
188 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
189 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
192 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
194 timer = lapic->lvt_timer;
195 timer &= ~APIC_LVTT_VECTOR;
196 timer |= XTIMER_OFFSET;
197 timer |= APIC_LVTT_MASKED;
198 lapic->lvt_timer = timer;
201 * Set the Task Priority Register as needed. At the moment allow
202 * interrupts on all cpus (the APs will remain CLId until they are
206 temp &= ~APIC_TPR_PRIO; /* clear priority field */
213 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
214 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
217 * Set the spurious interrupt vector. The low 4 bits of the vector
220 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
221 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
222 temp &= ~APIC_SVR_VECTOR;
223 temp |= XSPURIOUSINT_OFFSET;
228 * Pump out a few EOIs to clean out interrupts that got through
229 * before we were able to set the TPR.
236 lapic_timer_calibrate();
237 if (lapic_timer_enable) {
238 cputimer_intr_register(&lapic_cputimer_intr);
239 cputimer_intr_select(&lapic_cputimer_intr, 0);
242 lapic_timer_set_divisor(lapic_timer_divisor_idx);
246 apic_dump("apic_initialize()");
250 lapic_timer_set_divisor(int divisor_idx)
252 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
253 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
257 lapic_timer_oneshot(u_int count)
261 value = lapic->lvt_timer;
262 value &= ~APIC_LVTT_PERIODIC;
263 lapic->lvt_timer = value;
264 lapic->icr_timer = count;
268 lapic_timer_oneshot_quick(u_int count)
270 lapic->icr_timer = count;
274 lapic_timer_calibrate(void)
278 /* Try to calibrate the local APIC timer. */
279 for (lapic_timer_divisor_idx = 0;
280 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
281 lapic_timer_divisor_idx++) {
282 lapic_timer_set_divisor(lapic_timer_divisor_idx);
283 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
285 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
286 if (value != APIC_TIMER_MAX_COUNT)
289 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
290 panic("lapic: no proper timer divisor?!\n");
291 lapic_cputimer_intr.freq = value / 2;
293 kprintf("lapic: divisor index %d, frequency %u Hz\n",
294 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
298 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
302 gd->gd_timer_running = 0;
304 count = sys_cputimer->count();
305 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
306 systimer_intr(&count, 0, frame);
310 lapic_timer_process(void)
312 lapic_timer_process_oncpu(mycpu, NULL);
316 lapic_timer_process_frame(struct intrframe *frame)
318 lapic_timer_process_oncpu(mycpu, frame);
322 * This manual debugging code is called unconditionally from Xtimer
323 * (the lapic timer interrupt) whether the current thread is in a
324 * critical section or not) and can be useful in tracking down lockups.
326 * NOTE: MANUAL DEBUG CODE
329 static int saveticks[SMP_MAXCPU];
330 static int savecounts[SMP_MAXCPU];
334 lapic_timer_always(struct intrframe *frame)
337 globaldata_t gd = mycpu;
338 int cpu = gd->gd_cpuid;
344 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
345 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
348 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
349 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
351 for (i = 0; buf[i]; ++i) {
352 gptr[i] = 0x0700 | (unsigned char)buf[i];
356 if (saveticks[gd->gd_cpuid] != ticks) {
357 saveticks[gd->gd_cpuid] = ticks;
358 savecounts[gd->gd_cpuid] = 0;
360 ++savecounts[gd->gd_cpuid];
361 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
362 panic("cpud %d panicing on ticks failure",
365 for (i = 0; i < ncpus; ++i) {
367 if (saveticks[i] && panicstr == NULL) {
368 delta = saveticks[i] - ticks;
369 if (delta < -10 || delta > 10) {
370 panic("cpu %d panicing on cpu %d watchdog",
380 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
382 struct globaldata *gd = mycpu;
384 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
388 if (gd->gd_timer_running) {
389 if (reload < lapic->ccr_timer)
390 lapic_timer_oneshot_quick(reload);
392 gd->gd_timer_running = 1;
393 lapic_timer_oneshot_quick(reload);
398 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
402 timer = lapic->lvt_timer;
403 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
404 lapic->lvt_timer = timer;
406 lapic_timer_fixup_handler(NULL);
410 lapic_timer_fixup_handler(void *arg)
417 if (cpu_vendor_id == CPU_VENDOR_AMD) {
419 * Detect the presence of C1E capability mostly on latest
420 * dual-cores (or future) k8 family. This feature renders
421 * the local APIC timer dead, so we disable it by reading
422 * the Interrupt Pending Message register and clearing both
423 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
426 * "BIOS and Kernel Developer's Guide for AMD NPT
427 * Family 0Fh Processors"
428 * #32559 revision 3.00
430 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
431 (cpu_id & 0x0fff0000) >= 0x00040000) {
434 msr = rdmsr(0xc0010055);
435 if (msr & 0x18000000) {
436 struct globaldata *gd = mycpu;
438 kprintf("cpu%d: AMD C1E detected\n",
440 wrmsr(0xc0010055, msr & ~0x18000000ULL);
443 * We are kinda stalled;
446 gd->gd_timer_running = 1;
447 lapic_timer_oneshot_quick(2);
457 lapic_timer_restart_handler(void *dummy __unused)
461 lapic_timer_fixup_handler(&started);
463 struct globaldata *gd = mycpu;
465 gd->gd_timer_running = 1;
466 lapic_timer_oneshot_quick(2);
471 * This function is called only by ACPI-CA code currently:
472 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
473 * module controls PM. So once ACPI-CA is attached, we try
474 * to apply the fixup to prevent LAPIC timer from hanging.
477 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
479 lwkt_send_ipiq_mask(smp_active_mask,
480 lapic_timer_fixup_handler, NULL);
484 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
486 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
491 * dump contents of local APIC registers
496 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
497 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
498 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
502 * Inter Processor Interrupt functions.
506 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
508 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
509 * vector is any valid SYSTEM INT vector
510 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
512 * A backlog of requests can create a deadlock between cpus. To avoid this
513 * we have to be able to accept IPIs at the same time we are trying to send
514 * them. The critical section prevents us from attempting to send additional
515 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
516 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
517 * to occur but fortunately it does not happen too often.
520 apic_ipi(int dest_type, int vector, int delivery_mode)
525 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
526 unsigned long rflags = read_rflags();
528 DEBUG_PUSH_INFO("apic_ipi");
529 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
533 write_rflags(rflags);
536 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
537 delivery_mode | vector;
538 lapic->icr_lo = icr_lo;
544 single_apic_ipi(int cpu, int vector, int delivery_mode)
550 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
551 unsigned long rflags = read_rflags();
553 DEBUG_PUSH_INFO("single_apic_ipi");
554 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
558 write_rflags(rflags);
560 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
561 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
562 lapic->icr_hi = icr_hi;
565 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
566 | APIC_DEST_DESTFLD | delivery_mode | vector;
569 lapic->icr_lo = icr_lo;
576 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
578 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
579 * to the target, and the scheduler does not 'poll' for IPI messages.
582 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
588 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
592 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
593 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
594 lapic->icr_hi = icr_hi;
597 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
598 | APIC_DEST_DESTFLD | delivery_mode | vector;
601 lapic->icr_lo = icr_lo;
609 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
611 * target is a bitmask of destination cpus. Vector is any
612 * valid system INT vector. Delivery mode may be either
613 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
616 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
620 int n = BSFCPUMASK(target);
621 target &= ~CPUMASK(n);
622 single_apic_ipi(n, vector, delivery_mode);
628 * Timer code, in development...
629 * - suggested by rgrimes@gndrsh.aac.dev.com
632 get_apic_timer_frequency(void)
634 return(lapic_cputimer_intr.freq);
638 * Load a 'downcount time' in uSeconds.
641 set_apic_timer(int us)
646 * When we reach here, lapic timer's frequency
647 * must have been calculated as well as the
648 * divisor (lapic->dcr_timer is setup during the
649 * divisor calculation).
651 KKASSERT(lapic_cputimer_intr.freq != 0 &&
652 lapic_timer_divisor_idx >= 0);
654 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
655 lapic_timer_oneshot(count);
660 * Read remaining time in timer.
663 read_apic_timer(void)
666 /** XXX FIXME: we need to return the actual remaining time,
667 * for now we just return the remaining count.
670 return lapic->ccr_timer;
676 * Spin-style delay, set delay time in uS, spin till it drains.
681 set_apic_timer(count);
682 while (read_apic_timer())
687 lapic_unused_apic_id(int start)
691 for (i = start; i < NAPICID; ++i) {
692 if (APICID_TO_CPUID(i) == -1)
699 lapic_map(vm_offset_t lapic_addr)
701 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
703 kprintf("lapic: at 0x%08lx\n", lapic_addr);
706 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
707 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
712 struct lapic_enumerator *e;
713 int error, i, ap_max;
715 KKASSERT(lapic_enable);
717 for (i = 0; i < NAPICID; ++i)
718 APICID_TO_CPUID(i) = -1;
720 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
721 error = e->lapic_probe(e);
726 kprintf("LAPIC: Can't find LAPIC\n");
730 e->lapic_enumerate(e);
733 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
734 if (ap_max > MAXCPU - 1)
738 kprintf("LAPIC: Warning use only %d out of %d "
748 lapic_enumerator_register(struct lapic_enumerator *ne)
750 struct lapic_enumerator *e;
752 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
753 if (e->lapic_prio < ne->lapic_prio) {
754 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
758 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
762 lapic_set_cpuid(int cpu_id, int apic_id)
764 CPUID_TO_APICID(cpu_id) = apic_id;
765 APICID_TO_CPUID(apic_id) = cpu_id;
769 lapic_fixup_noioapic(void)
773 /* Only allowed on BSP */
774 KKASSERT(mycpuid == 0);
775 KKASSERT(!ioapic_enable);
777 temp = lapic->lvt_lint0;
778 temp &= ~APIC_LVT_MASKED;
779 lapic->lvt_lint0 = temp;
781 temp = lapic->lvt_lint1;
782 temp |= APIC_LVT_MASKED;
783 lapic->lvt_lint1 = temp;