2 * Copyright (c) 1997, 2001 Hellmuth Michaelis. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 *---------------------------------------------------------------------------
27 * i4b - Siemens HSCX chip (B-channel) handling
28 * --------------------------------------------
30 * $FreeBSD: src/sys/i4b/layer1/isic/i4b_hscx.c,v 1.7.2.1 2001/08/10 14:08:38 obrien Exp $
31 * $DragonFly: src/sys/net/i4b/layer1/isic/i4b_hscx.c,v 1.6 2006/12/22 23:44:56 swildner Exp $
33 * last edit-date: [Wed Jan 24 09:09:42 2001]
35 *---------------------------------------------------------------------------*/
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/socket.h>
48 #include <net/i4b/include/machine/i4b_debug.h>
49 #include <net/i4b/include/machine/i4b_ioctl.h>
50 #include <net/i4b/include/machine/i4b_trace.h>
55 #include "../i4b_l1.h"
57 #include "../../include/i4b_global.h"
58 #include "../../include/i4b_mbuf.h"
60 /*---------------------------------------------------------------------------*
62 *---------------------------------------------------------------------------*/
64 isic_hscx_irq(struct l1_softc *sc, u_char ista, int h_chan, u_char ex_irq)
66 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
71 NDBGL1(L1_H_IRQ, "%#x", ista);
75 /* get channel extended irq reg */
77 exir = HSCX_READ(h_chan, H_EXIR);
79 if(exir & HSCX_EXIR_RFO)
82 NDBGL1(L1_H_XFRERR, "ex_irq: receive data overflow");
85 if((exir & HSCX_EXIR_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
88 NDBGL1(L1_H_XFRERR, "ex_irq: xmit data underrun");
89 isic_hscx_cmd(sc, h_chan, HSCX_CMDR_XRES);
91 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
93 i4b_Bfreembuf(chan->out_mbuf_head);
94 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
100 /* rx message end, end of frame */
102 if(ista & HSCX_ISTA_RME)
108 rsta = HSCX_READ(h_chan, H_RSTA);
110 if((rsta & 0xf0) != 0xa0)
112 if((rsta & HSCX_RSTA_VFR) == 0)
115 cmd |= (HSCX_CMDR_RHR);
116 NDBGL1(L1_H_XFRERR, "received invalid Frame");
120 if(rsta & HSCX_RSTA_RDO)
123 NDBGL1(L1_H_XFRERR, "receive data overflow");
127 if((rsta & HSCX_RSTA_CRC) == 0)
130 cmd |= (HSCX_CMDR_RHR);
131 NDBGL1(L1_H_XFRERR, "CRC check failed");
135 if(rsta & HSCX_RSTA_RAB)
138 NDBGL1(L1_H_XFRERR, "Receive message aborted");
143 fifo_data_len = ((HSCX_READ(h_chan, H_RBCL)) &
144 ((sc->sc_bfifolen)-1));
146 if(fifo_data_len == 0)
147 fifo_data_len = sc->sc_bfifolen;
149 /* all error conditions checked, now decide and take action */
153 if(chan->in_mbuf == NULL)
155 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
156 panic("L1 isic_hscx_irq: RME, cannot allocate mbuf!\n");
157 chan->in_cbptr = chan->in_mbuf->m_data;
161 fifo_data_len -= 1; /* last byte in fifo is RSTA ! */
163 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
165 /* read data from HSCX fifo */
167 HSCX_RDFIFO(h_chan, chan->in_cbptr, fifo_data_len);
169 cmd |= (HSCX_CMDR_RMC);
170 isic_hscx_cmd(sc, h_chan, cmd);
173 chan->in_len += fifo_data_len;
174 chan->rxcount += fifo_data_len;
176 /* setup mbuf data length */
178 chan->in_mbuf->m_len = chan->in_len;
179 chan->in_mbuf->m_pkthdr.len = chan->in_len;
181 if(sc->sc_trace & TRACE_B_RX)
184 hdr.unit = L0ISICUNIT(sc->sc_unit);
185 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
187 hdr.count = ++sc->sc_trace_bcount;
189 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
192 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
196 /* mark buffer ptr as unused */
198 chan->in_mbuf = NULL;
199 chan->in_cbptr = NULL;
204 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RME, in_len=%d, fifolen=%d", chan->in_len, fifo_data_len);
205 chan->in_cbptr = chan->in_mbuf->m_data;
207 cmd |= (HSCX_CMDR_RHR | HSCX_CMDR_RMC);
212 if (chan->in_mbuf != NULL)
214 i4b_Bfreembuf(chan->in_mbuf);
215 chan->in_mbuf = NULL;
216 chan->in_cbptr = NULL;
219 cmd |= (HSCX_CMDR_RMC);
225 if(ista & HSCX_ISTA_RPF)
227 if(chan->in_mbuf == NULL)
229 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
230 panic("L1 isic_hscx_irq: RPF, cannot allocate mbuf!\n");
231 chan->in_cbptr = chan->in_mbuf->m_data;
235 chan->rxcount += sc->sc_bfifolen;
237 if((chan->in_len + sc->sc_bfifolen) <= BCH_MAX_DATALEN)
239 /* read data from HSCX fifo */
241 HSCX_RDFIFO(h_chan, chan->in_cbptr, sc->sc_bfifolen);
243 chan->in_cbptr += sc->sc_bfifolen;
244 chan->in_len += sc->sc_bfifolen;
248 if(chan->bprot == BPROT_NONE)
250 /* setup mbuf data length */
252 chan->in_mbuf->m_len = chan->in_len;
253 chan->in_mbuf->m_pkthdr.len = chan->in_len;
255 if(sc->sc_trace & TRACE_B_RX)
258 hdr.unit = L0ISICUNIT(sc->sc_unit);
259 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
261 hdr.count = ++sc->sc_trace_bcount;
263 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
266 /* silence detection */
268 if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
271 if(!(IF_QFULL(&chan->rx_queue)))
273 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
277 i4b_Bfreembuf(chan->in_mbuf);
279 /* signal upper driver that data is available */
281 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
283 /* alloc new buffer */
285 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
286 panic("L1 isic_hscx_irq: RPF, cannot allocate new mbuf!\n");
288 /* setup new data ptr */
290 chan->in_cbptr = chan->in_mbuf->m_data;
292 /* read data from HSCX fifo */
294 HSCX_RDFIFO(h_chan, chan->in_cbptr, sc->sc_bfifolen);
296 chan->in_cbptr += sc->sc_bfifolen;
297 chan->in_len = sc->sc_bfifolen;
299 chan->rxcount += sc->sc_bfifolen;
303 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
304 chan->in_cbptr = chan->in_mbuf->m_data;
306 cmd |= (HSCX_CMDR_RHR);
310 /* command to release fifo space */
312 cmd |= HSCX_CMDR_RMC;
315 /* transmit fifo empty, new data can be written to fifo */
317 if(ista & HSCX_ISTA_XPR)
320 * for a description what is going on here, please have
321 * a look at isic_bchannel_start() in i4b_bchan.c !
328 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
330 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
332 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
334 if(chan->out_mbuf_head == NULL)
336 chan->state &= ~HSCX_TX_ACTIVE;
337 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
341 chan->state |= HSCX_TX_ACTIVE;
342 chan->out_mbuf_cur = chan->out_mbuf_head;
343 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
344 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
346 if(sc->sc_trace & TRACE_B_TX)
349 hdr.unit = L0ISICUNIT(sc->sc_unit);
350 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
352 hdr.count = ++sc->sc_trace_bcount;
354 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
357 if(chan->bprot == BPROT_NONE)
359 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
371 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
373 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
376 kprintf("i:mh=%x, mc=%x, mcp=%x, mcl=%d l=%d nl=%d # ",
379 chan->out_mbuf_cur_ptr,
380 chan->out_mbuf_cur_len,
385 isic_hscx_waitxfw(sc, h_chan); /* necessary !!! */
387 HSCX_WRFIFO(h_chan, chan->out_mbuf_cur_ptr, nextlen);
388 cmd |= HSCX_CMDR_XTF;
391 chan->txcount += nextlen;
393 chan->out_mbuf_cur_ptr += nextlen;
394 chan->out_mbuf_cur_len -= nextlen;
396 if(chan->out_mbuf_cur_len == 0)
398 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
400 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
401 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
403 if(sc->sc_trace & TRACE_B_TX)
406 hdr.unit = L0ISICUNIT(sc->sc_unit);
407 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
409 hdr.count = ++sc->sc_trace_bcount;
411 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
416 if (chan->bprot != BPROT_NONE)
417 cmd |= HSCX_CMDR_XME;
418 i4b_Bfreembuf(chan->out_mbuf_head);
419 chan->out_mbuf_head = NULL;
426 if(cmd) /* is there a command for the HSCX ? */
428 isic_hscx_cmd(sc, h_chan, cmd); /* yes, to HSCX */
431 /* call timeout handling routine */
433 if(activity == ACT_RX || activity == ACT_TX)
434 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
437 /*---------------------------------------------------------------------------*
438 * HSCX initialization
440 * for telephony: extended transparent mode 1
441 * for raw hdlc: transparent mode 0
442 *---------------------------------------------------------------------------*/
444 isic_hscx_init(struct l1_softc *sc, int h_chan, int activate)
446 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
448 HSCX_WRITE(h_chan, H_MASK, 0xff); /* mask irq's */
452 /* CCR1: Power Up, Clock Mode 5 */
453 HSCX_WRITE(h_chan, H_CCR1, HSCX_CCR1_PU | /* power up */
454 HSCX_CCR1_CM1); /* IPAC clock mode 5 */
458 /* CCR1: Power Up, Clock Mode 5 */
459 HSCX_WRITE(h_chan, H_CCR1, HSCX_CCR1_PU | /* power up */
460 HSCX_CCR1_CM2 | /* HSCX clock mode 5 */
464 /* XAD1: Transmit Address Byte 1 */
465 HSCX_WRITE(h_chan, H_XAD1, 0xff);
467 /* XAD2: Transmit Address Byte 2 */
468 HSCX_WRITE(h_chan, H_XAD2, 0xff);
470 /* RAH2: Receive Address Byte High Reg. 2 */
471 HSCX_WRITE(h_chan, H_RAH2, 0xff);
473 /* XBCH: reset Transmit Byte Count High */
474 HSCX_WRITE(h_chan, H_XBCH, 0x00);
476 /* RLCR: reset Receive Length Check Register */
477 HSCX_WRITE(h_chan, H_RLCR, 0x00);
479 /* CCR2: set tx/rx clock shift bit 0 */
480 /* disable CTS irq, disable RIE irq*/
481 HSCX_WRITE(h_chan, H_CCR2, HSCX_CCR2_XCS0|HSCX_CCR2_RCS0);
483 /* XCCR: tx bit count per time slot */
484 HSCX_WRITE(h_chan, H_XCCR, 0x07);
486 /* RCCR: rx bit count per time slot */
487 HSCX_WRITE(h_chan, H_RCCR, 0x07);
489 if(sc->sc_bustyp == BUS_TYPE_IOM2)
493 case HSCX_CH_A: /* Prepare HSCX channel A */
494 /* TSAX: tx clock shift bits 1 & 2 */
495 /* tx time slot number */
496 HSCX_WRITE(h_chan, H_TSAX, 0x2f);
498 /* TSAR: rx clock shift bits 1 & 2 */
499 /* rx time slot number */
500 HSCX_WRITE(h_chan, H_TSAR, 0x2f);
503 case HSCX_CH_B: /* Prepare HSCX channel B */
504 /* TSAX: tx clock shift bits 1 & 2 */
505 /* tx time slot number */
506 HSCX_WRITE(h_chan, H_TSAX, 0x03);
508 /* TSAR: rx clock shift bits 1 & 2 */
509 /* rx time slot number */
510 HSCX_WRITE(h_chan, H_TSAR, 0x03);
514 else /* IOM 1 setup */
516 /* TSAX: tx clock shift bits 1 & 2 */
517 /* tx time slot number */
518 HSCX_WRITE(h_chan, H_TSAX, 0x07);
520 /* TSAR: rx clock shift bits 1 & 2 */
521 /* rx time slot number */
522 HSCX_WRITE(h_chan, H_TSAR, 0x07);
527 if(chan->bprot == BPROT_RHDLC)
529 /* HDLC Frames, transparent mode 0 */
530 HSCX_WRITE(h_chan, H_MODE,
531 HSCX_MODE_MDS1|HSCX_MODE_RAC|HSCX_MODE_RTS);
535 /* Raw Telephony, extended transparent mode 1 */
536 HSCX_WRITE(h_chan, H_MODE,
537 HSCX_MODE_MDS1|HSCX_MODE_MDS0|HSCX_MODE_ADM|HSCX_MODE_RTS);
540 isic_hscx_cmd(sc, h_chan, HSCX_CMDR_RHR|HSCX_CMDR_XRES);
542 isic_hscx_cmd(sc, h_chan, HSCX_CMDR_RHR);
547 /* TSAX: tx time slot */
548 HSCX_WRITE(h_chan, H_TSAX, 0xff);
550 /* TSAR: rx time slot */
551 HSCX_WRITE(h_chan, H_TSAR, 0xff);
553 /* Raw Telephony, extended transparent mode 1 */
554 HSCX_WRITE(h_chan, H_MODE,
555 HSCX_MODE_MDS1|HSCX_MODE_MDS0|HSCX_MODE_ADM|HSCX_MODE_RTS);
558 /* don't touch ICA, EXA and EXB bits, this could be HSCX_CH_B */
559 /* always disable RSC and TIN */
561 chan->hscx_mask |= HSCX_MASK_RSC | HSCX_MASK_TIN;
566 chan->hscx_mask &= ~(HSCX_MASK_RME | HSCX_MASK_RPF | HSCX_MASK_XPR);
571 chan->hscx_mask |= HSCX_MASK_RME | HSCX_MASK_RPF | HSCX_MASK_XPR;
574 /* handle ICA, EXA, and EXB via interrupt mask of channel b */
576 if (h_chan == HSCX_CH_A)
579 HSCX_B_IMASK &= ~(HSCX_MASK_EXA | HSCX_MASK_ICA);
581 HSCX_B_IMASK |= HSCX_MASK_EXA | HSCX_MASK_ICA;
582 HSCX_WRITE(HSCX_CH_A, H_MASK, HSCX_A_IMASK);
583 HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
588 HSCX_B_IMASK &= ~HSCX_MASK_EXB;
590 HSCX_B_IMASK |= HSCX_MASK_EXB;
591 HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
594 /* clear spurious interrupts left over */
596 if(h_chan == HSCX_CH_A)
598 HSCX_READ(h_chan, H_EXIR);
599 HSCX_READ(h_chan, H_ISTA);
601 else /* mask ICA, because it must not be cleared by reading ISTA */
603 HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK | HSCX_MASK_ICA);
604 HSCX_READ(h_chan, H_EXIR);
605 HSCX_READ(h_chan, H_ISTA);
606 HSCX_WRITE(HSCX_CH_B, H_MASK, HSCX_B_IMASK);
610 /*---------------------------------------------------------------------------*
611 * write command to HSCX command register
612 *---------------------------------------------------------------------------*/
614 isic_hscx_cmd(struct l1_softc *sc, int h_chan, unsigned char cmd)
618 while(((HSCX_READ(h_chan, H_STAR)) & HSCX_STAR_CEC) && timeout)
626 NDBGL1(L1_H_ERR, "HSCX wait for CEC timeout!");
629 HSCX_WRITE(h_chan, H_CMDR, cmd);
632 /*---------------------------------------------------------------------------*
633 * wait for HSCX transmit FIFO write enable
634 *---------------------------------------------------------------------------*/
636 isic_hscx_waitxfw(struct l1_softc *sc, int h_chan)
641 int timeout = WAITTO;
643 while((!(((HSCX_READ(h_chan, H_STAR)) &
644 (HSCX_STAR_CEC | HSCX_STAR_XFW)) == HSCX_STAR_XFW)) && timeout)
652 NDBGL1(L1_H_ERR, "HSCX wait for XFW timeout!");
654 else if (timeout != WAITTO)
656 NDBGL1(L1_H_XFRERR, "HSCX wait for XFW time: %d uS", (WAITTO-timeout)*50);
660 #endif /* NISIC > 0 */