1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 * Gareth Hughes <gareth@valinux.com>
34 * $FreeBSD: src/sys/dev/drm/mga_state.c,v 1.6.2.1 2003/04/26 07:05:29 anholt Exp $
35 * $DragonFly: src/sys/dev/drm/mga/Attic/mga_state.c,v 1.4 2005/02/17 13:59:36 joerg Exp $
39 #include "dev/drm/drmP.h"
40 #include "dev/drm/drm.h"
45 /* ================================================================
46 * DMA hardware state programming functions
49 static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
50 drm_clip_rect_t *box )
52 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
53 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
54 unsigned int pitch = dev_priv->front_pitch;
59 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
61 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
62 DMA_BLOCK( MGA_DWGCTL, ctx->dwgctl,
63 MGA_LEN + MGA_EXEC, 0x80000000,
64 MGA_DWGCTL, ctx->dwgctl,
65 MGA_LEN + MGA_EXEC, 0x80000000 );
67 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
68 MGA_CXBNDRY, (box->x2 << 16) | box->x1,
69 MGA_YTOP, box->y1 * pitch,
70 MGA_YBOT, box->y2 * pitch );
75 static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv )
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
78 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
83 DMA_BLOCK( MGA_DSTORG, ctx->dstorg,
84 MGA_MACCESS, ctx->maccess,
85 MGA_PLNWT, ctx->plnwt,
86 MGA_DWGCTL, ctx->dwgctl );
88 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl,
89 MGA_FOGCOL, ctx->fogcolor,
90 MGA_WFLAG, ctx->wflag,
91 MGA_ZORG, dev_priv->depth_offset );
93 DMA_BLOCK( MGA_FCOL, ctx->fcol,
94 MGA_DMAPAD, 0x00000000,
95 MGA_DMAPAD, 0x00000000,
96 MGA_DMAPAD, 0x00000000 );
101 static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv )
103 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
104 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
109 DMA_BLOCK( MGA_DSTORG, ctx->dstorg,
110 MGA_MACCESS, ctx->maccess,
111 MGA_PLNWT, ctx->plnwt,
112 MGA_DWGCTL, ctx->dwgctl );
114 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl,
115 MGA_FOGCOL, ctx->fogcolor,
116 MGA_WFLAG, ctx->wflag,
117 MGA_ZORG, dev_priv->depth_offset );
119 DMA_BLOCK( MGA_WFLAG1, ctx->wflag,
120 MGA_TDUALSTAGE0, ctx->tdualstage0,
121 MGA_TDUALSTAGE1, ctx->tdualstage1,
122 MGA_FCOL, ctx->fcol );
124 DMA_BLOCK( MGA_STENCIL, ctx->stencil,
125 MGA_STENCILCTL, ctx->stencilctl,
126 MGA_DMAPAD, 0x00000000,
127 MGA_DMAPAD, 0x00000000 );
132 static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
134 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
135 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
140 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2,
141 MGA_TEXCTL, tex->texctl,
142 MGA_TEXFILTER, tex->texfilter,
143 MGA_TEXBORDERCOL, tex->texbordercol );
145 DMA_BLOCK( MGA_TEXORG, tex->texorg,
146 MGA_TEXORG1, tex->texorg1,
147 MGA_TEXORG2, tex->texorg2,
148 MGA_TEXORG3, tex->texorg3 );
150 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
151 MGA_TEXWIDTH, tex->texwidth,
152 MGA_TEXHEIGHT, tex->texheight,
153 MGA_WR24, tex->texwidth );
155 DMA_BLOCK( MGA_WR34, tex->texheight,
156 MGA_TEXTRANS, 0x0000ffff,
157 MGA_TEXTRANSHIGH, 0x0000ffff,
158 MGA_DMAPAD, 0x00000000 );
163 static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
165 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
166 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
169 /* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
170 /* tex->texctl, tex->texctl2); */
174 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
175 MGA_TEXCTL, tex->texctl,
176 MGA_TEXFILTER, tex->texfilter,
177 MGA_TEXBORDERCOL, tex->texbordercol );
179 DMA_BLOCK( MGA_TEXORG, tex->texorg,
180 MGA_TEXORG1, tex->texorg1,
181 MGA_TEXORG2, tex->texorg2,
182 MGA_TEXORG3, tex->texorg3 );
184 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
185 MGA_TEXWIDTH, tex->texwidth,
186 MGA_TEXHEIGHT, tex->texheight,
187 MGA_WR49, 0x00000000 );
189 DMA_BLOCK( MGA_WR57, 0x00000000,
190 MGA_WR53, 0x00000000,
191 MGA_WR61, 0x00000000,
192 MGA_WR52, MGA_G400_WR_MAGIC );
194 DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC,
195 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
196 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
197 MGA_DMAPAD, 0x00000000 );
199 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
200 MGA_DMAPAD, 0x00000000,
201 MGA_TEXTRANS, 0x0000ffff,
202 MGA_TEXTRANSHIGH, 0x0000ffff );
207 static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
209 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
210 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
213 /* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
214 /* tex->texctl, tex->texctl2); */
218 DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 |
221 MGA_TEXCTL, tex->texctl,
222 MGA_TEXFILTER, tex->texfilter,
223 MGA_TEXBORDERCOL, tex->texbordercol );
225 DMA_BLOCK( MGA_TEXORG, tex->texorg,
226 MGA_TEXORG1, tex->texorg1,
227 MGA_TEXORG2, tex->texorg2,
228 MGA_TEXORG3, tex->texorg3 );
230 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
231 MGA_TEXWIDTH, tex->texwidth,
232 MGA_TEXHEIGHT, tex->texheight,
233 MGA_WR49, 0x00000000 );
235 DMA_BLOCK( MGA_WR57, 0x00000000,
236 MGA_WR53, 0x00000000,
237 MGA_WR61, 0x00000000,
238 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC );
240 DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
241 MGA_TEXTRANS, 0x0000ffff,
242 MGA_TEXTRANSHIGH, 0x0000ffff,
243 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC );
248 static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
250 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
251 unsigned int pipe = sarea_priv->warp_pipe;
256 DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND,
257 MGA_WVRTXSZ, 0x00000007,
258 MGA_WFLAG, 0x00000000,
259 MGA_WR24, 0x00000000 );
261 DMA_BLOCK( MGA_WR25, 0x00000100,
262 MGA_WR34, 0x00000000,
263 MGA_WR42, 0x0000ffff,
264 MGA_WR60, 0x0000ffff );
266 /* Padding required to to hardware bug.
268 DMA_BLOCK( MGA_DMAPAD, 0xffffffff,
269 MGA_DMAPAD, 0xffffffff,
270 MGA_DMAPAD, 0xffffffff,
271 MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
278 static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
280 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
281 unsigned int pipe = sarea_priv->warp_pipe;
284 /* printk("mga_g400_emit_pipe %x\n", pipe); */
288 DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND,
289 MGA_DMAPAD, 0x00000000,
290 MGA_DMAPAD, 0x00000000,
291 MGA_DMAPAD, 0x00000000 );
293 if ( pipe & MGA_T2 ) {
294 DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09,
295 MGA_DMAPAD, 0x00000000,
296 MGA_DMAPAD, 0x00000000,
297 MGA_DMAPAD, 0x00000000 );
299 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000,
300 MGA_WACCEPTSEQ, 0x00000000,
301 MGA_WACCEPTSEQ, 0x00000000,
302 MGA_WACCEPTSEQ, 0x1e000000 );
304 if ( dev_priv->warp_pipe & MGA_T2 ) {
305 /* Flush the WARP pipe */
306 DMA_BLOCK( MGA_YDST, 0x00000000,
307 MGA_FXLEFT, 0x00000000,
308 MGA_FXRIGHT, 0x00000001,
309 MGA_DWGCTL, MGA_DWGCTL_FLUSH );
311 DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001,
312 MGA_DWGSYNC, 0x00007000,
313 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
314 MGA_LEN + MGA_EXEC, 0x00000000 );
316 DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX |
318 MGA_LEN + MGA_EXEC, 0x00000000,
319 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
320 MGA_DMAPAD, 0x00000000 );
323 DMA_BLOCK( MGA_WVRTXSZ, 0x00001807,
324 MGA_DMAPAD, 0x00000000,
325 MGA_DMAPAD, 0x00000000,
326 MGA_DMAPAD, 0x00000000 );
328 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000,
329 MGA_WACCEPTSEQ, 0x00000000,
330 MGA_WACCEPTSEQ, 0x00000000,
331 MGA_WACCEPTSEQ, 0x18000000 );
334 DMA_BLOCK( MGA_WFLAG, 0x00000000,
335 MGA_WFLAG1, 0x00000000,
336 MGA_WR56, MGA_G400_WR56_MAGIC,
337 MGA_DMAPAD, 0x00000000 );
339 DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */
340 MGA_WR57, 0x00000000, /* tex0 */
341 MGA_WR53, 0x00000000, /* tex1 */
342 MGA_WR61, 0x00000000 ); /* tex1 */
344 DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
345 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
346 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
347 MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */
349 /* Padding required to to hardware bug */
350 DMA_BLOCK( MGA_DMAPAD, 0xffffffff,
351 MGA_DMAPAD, 0xffffffff,
352 MGA_DMAPAD, 0xffffffff,
353 MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
360 static void mga_g200_emit_state( drm_mga_private_t *dev_priv )
362 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
363 unsigned int dirty = sarea_priv->dirty;
365 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
366 mga_g200_emit_pipe( dev_priv );
367 dev_priv->warp_pipe = sarea_priv->warp_pipe;
370 if ( dirty & MGA_UPLOAD_CONTEXT ) {
371 mga_g200_emit_context( dev_priv );
372 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
375 if ( dirty & MGA_UPLOAD_TEX0 ) {
376 mga_g200_emit_tex0( dev_priv );
377 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
381 static void mga_g400_emit_state( drm_mga_private_t *dev_priv )
383 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
384 unsigned int dirty = sarea_priv->dirty;
385 int multitex = sarea_priv->warp_pipe & MGA_T2;
387 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
388 mga_g400_emit_pipe( dev_priv );
389 dev_priv->warp_pipe = sarea_priv->warp_pipe;
392 if ( dirty & MGA_UPLOAD_CONTEXT ) {
393 mga_g400_emit_context( dev_priv );
394 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
397 if ( dirty & MGA_UPLOAD_TEX0 ) {
398 mga_g400_emit_tex0( dev_priv );
399 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
402 if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) {
403 mga_g400_emit_tex1( dev_priv );
404 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
409 /* ================================================================
410 * SAREA state verification
413 /* Disallow all write destinations except the front and backbuffer.
415 static int mga_verify_context( drm_mga_private_t *dev_priv )
417 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
418 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
420 if ( ctx->dstorg != dev_priv->front_offset &&
421 ctx->dstorg != dev_priv->back_offset ) {
422 DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n",
423 ctx->dstorg, dev_priv->front_offset,
424 dev_priv->back_offset );
426 return DRM_ERR(EINVAL);
432 /* Disallow texture reads from PCI space.
434 static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
436 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
437 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
440 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
442 if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) {
443 DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n",
446 return DRM_ERR(EINVAL);
452 static int mga_verify_state( drm_mga_private_t *dev_priv )
454 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
455 unsigned int dirty = sarea_priv->dirty;
458 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
459 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
461 if ( dirty & MGA_UPLOAD_CONTEXT )
462 ret |= mga_verify_context( dev_priv );
464 if ( dirty & MGA_UPLOAD_TEX0 )
465 ret |= mga_verify_tex( dev_priv, 0 );
467 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
468 if ( dirty & MGA_UPLOAD_TEX1 )
469 ret |= mga_verify_tex( dev_priv, 1 );
471 if ( dirty & MGA_UPLOAD_PIPE )
472 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES );
474 if ( dirty & MGA_UPLOAD_PIPE )
475 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES );
481 static int mga_verify_iload( drm_mga_private_t *dev_priv,
482 unsigned int dstorg, unsigned int length )
484 if ( dstorg < dev_priv->texture_offset ||
485 dstorg + length > (dev_priv->texture_offset +
486 dev_priv->texture_size) ) {
487 DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg );
488 return DRM_ERR(EINVAL);
491 if ( length & MGA_ILOAD_MASK ) {
492 DRM_ERROR( "*** bad iload length: 0x%x\n",
493 length & MGA_ILOAD_MASK );
494 return DRM_ERR(EINVAL);
500 static int mga_verify_blit( drm_mga_private_t *dev_priv,
501 unsigned int srcorg, unsigned int dstorg )
503 if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
504 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) {
505 DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n",
507 return DRM_ERR(EINVAL);
513 /* ================================================================
517 static void mga_dma_dispatch_clear( drm_device_t *dev,
518 drm_mga_clear_t *clear )
520 drm_mga_private_t *dev_priv = dev->dev_private;
521 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
522 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
523 drm_clip_rect_t *pbox = sarea_priv->boxes;
524 int nbox = sarea_priv->nbox;
531 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
532 MGA_DMAPAD, 0x00000000,
533 MGA_DWGSYNC, 0x00007100,
534 MGA_DWGSYNC, 0x00007000 );
538 for ( i = 0 ; i < nbox ; i++ ) {
539 drm_clip_rect_t *box = &pbox[i];
540 u32 height = box->y2 - box->y1;
542 DRM_DEBUG( " from=%d,%d to=%d,%d\n",
543 box->x1, box->y1, box->x2, box->y2 );
545 if ( clear->flags & MGA_FRONT ) {
548 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
549 MGA_PLNWT, clear->color_mask,
550 MGA_YDSTLEN, (box->y1 << 16) | height,
551 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
553 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
554 MGA_FCOL, clear->clear_color,
555 MGA_DSTORG, dev_priv->front_offset,
556 MGA_DWGCTL + MGA_EXEC,
557 dev_priv->clear_cmd );
563 if ( clear->flags & MGA_BACK ) {
566 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
567 MGA_PLNWT, clear->color_mask,
568 MGA_YDSTLEN, (box->y1 << 16) | height,
569 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
571 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
572 MGA_FCOL, clear->clear_color,
573 MGA_DSTORG, dev_priv->back_offset,
574 MGA_DWGCTL + MGA_EXEC,
575 dev_priv->clear_cmd );
580 if ( clear->flags & MGA_DEPTH ) {
583 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
584 MGA_PLNWT, clear->depth_mask,
585 MGA_YDSTLEN, (box->y1 << 16) | height,
586 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
588 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
589 MGA_FCOL, clear->clear_depth,
590 MGA_DSTORG, dev_priv->depth_offset,
591 MGA_DWGCTL + MGA_EXEC,
592 dev_priv->clear_cmd );
601 /* Force reset of DWGCTL */
602 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
603 MGA_DMAPAD, 0x00000000,
604 MGA_PLNWT, ctx->plnwt,
605 MGA_DWGCTL, ctx->dwgctl );
612 static void mga_dma_dispatch_swap( drm_device_t *dev )
614 drm_mga_private_t *dev_priv = dev->dev_private;
615 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
616 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
617 drm_clip_rect_t *pbox = sarea_priv->boxes;
618 int nbox = sarea_priv->nbox;
623 sarea_priv->last_frame.head = dev_priv->prim.tail;
624 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
626 BEGIN_DMA( 4 + nbox );
628 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
629 MGA_DMAPAD, 0x00000000,
630 MGA_DWGSYNC, 0x00007100,
631 MGA_DWGSYNC, 0x00007000 );
633 DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset,
634 MGA_MACCESS, dev_priv->maccess,
635 MGA_SRCORG, dev_priv->back_offset,
636 MGA_AR5, dev_priv->front_pitch );
638 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
639 MGA_DMAPAD, 0x00000000,
640 MGA_PLNWT, 0xffffffff,
641 MGA_DWGCTL, MGA_DWGCTL_COPY );
643 for ( i = 0 ; i < nbox ; i++ ) {
644 drm_clip_rect_t *box = &pbox[i];
645 u32 height = box->y2 - box->y1;
646 u32 start = box->y1 * dev_priv->front_pitch;
648 DRM_DEBUG( " from=%d,%d to=%d,%d\n",
649 box->x1, box->y1, box->x2, box->y2 );
651 DMA_BLOCK( MGA_AR0, start + box->x2 - 1,
652 MGA_AR3, start + box->x1,
653 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
654 MGA_YDSTLEN + MGA_EXEC,
655 (box->y1 << 16) | height );
658 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
659 MGA_PLNWT, ctx->plnwt,
660 MGA_SRCORG, dev_priv->front_offset,
661 MGA_DWGCTL, ctx->dwgctl );
667 DRM_DEBUG( "%s... done.\n", __func__ );
670 static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
672 drm_mga_private_t *dev_priv = dev->dev_private;
673 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
674 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
675 u32 address = (u32) buf->bus_address;
676 u32 length = (u32) buf->used;
679 DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used );
682 buf_priv->dispatched = 1;
684 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
687 if ( i < sarea_priv->nbox ) {
688 mga_emit_clip_rect( dev_priv,
689 &sarea_priv->boxes[i] );
694 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
695 MGA_DMAPAD, 0x00000000,
696 MGA_SECADDRESS, (address |
698 MGA_SECEND, ((address + length) |
702 } while ( ++i < sarea_priv->nbox );
705 if ( buf_priv->discard ) {
706 AGE_BUFFER( buf_priv );
709 buf_priv->dispatched = 0;
711 mga_freelist_put( dev, buf );
717 static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
718 unsigned int start, unsigned int end )
720 drm_mga_private_t *dev_priv = dev->dev_private;
721 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
722 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
723 u32 address = (u32) buf->bus_address;
726 DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end );
728 if ( start != end ) {
729 buf_priv->dispatched = 1;
731 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
734 if ( i < sarea_priv->nbox ) {
735 mga_emit_clip_rect( dev_priv,
736 &sarea_priv->boxes[i] );
741 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
742 MGA_DMAPAD, 0x00000000,
743 MGA_SETUPADDRESS, address + start,
744 MGA_SETUPEND, ((address + end) |
748 } while ( ++i < sarea_priv->nbox );
751 if ( buf_priv->discard ) {
752 AGE_BUFFER( buf_priv );
755 buf_priv->dispatched = 0;
757 mga_freelist_put( dev, buf );
763 /* This copies a 64 byte aligned agp region to the frambuffer with a
764 * standard blit, the ioctl needs to do checking.
766 static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
767 unsigned int dstorg, unsigned int length )
769 drm_mga_private_t *dev_priv = dev->dev_private;
770 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
771 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
772 u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
775 DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used );
781 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
782 MGA_DMAPAD, 0x00000000,
783 MGA_DWGSYNC, 0x00007100,
784 MGA_DWGSYNC, 0x00007000 );
786 DMA_BLOCK( MGA_DSTORG, dstorg,
787 MGA_MACCESS, 0x00000000,
791 DMA_BLOCK( MGA_PITCH, 64,
792 MGA_PLNWT, 0xffffffff,
793 MGA_DMAPAD, 0x00000000,
794 MGA_DWGCTL, MGA_DWGCTL_COPY );
796 DMA_BLOCK( MGA_AR0, 63,
798 MGA_FXBNDRY, (63 << 16) | 0,
799 MGA_YDSTLEN + MGA_EXEC, y2 );
801 DMA_BLOCK( MGA_PLNWT, ctx->plnwt,
802 MGA_SRCORG, dev_priv->front_offset,
803 MGA_PITCH, dev_priv->front_pitch,
804 MGA_DWGSYNC, 0x00007000 );
808 AGE_BUFFER( buf_priv );
812 buf_priv->dispatched = 0;
814 mga_freelist_put( dev, buf );
819 static void mga_dma_dispatch_blit( drm_device_t *dev,
820 drm_mga_blit_t *blit )
822 drm_mga_private_t *dev_priv = dev->dev_private;
823 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
824 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
825 drm_clip_rect_t *pbox = sarea_priv->boxes;
826 int nbox = sarea_priv->nbox;
831 BEGIN_DMA( 4 + nbox );
833 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
834 MGA_DMAPAD, 0x00000000,
835 MGA_DWGSYNC, 0x00007100,
836 MGA_DWGSYNC, 0x00007000 );
838 DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY,
839 MGA_PLNWT, blit->planemask,
840 MGA_SRCORG, blit->srcorg,
841 MGA_DSTORG, blit->dstorg );
843 DMA_BLOCK( MGA_SGN, scandir,
844 MGA_MACCESS, dev_priv->maccess,
845 MGA_AR5, blit->ydir * blit->src_pitch,
846 MGA_PITCH, blit->dst_pitch );
848 for ( i = 0 ; i < nbox ; i++ ) {
849 int srcx = pbox[i].x1 + blit->delta_sx;
850 int srcy = pbox[i].y1 + blit->delta_sy;
851 int dstx = pbox[i].x1 + blit->delta_dx;
852 int dsty = pbox[i].y1 + blit->delta_dy;
853 int h = pbox[i].y2 - pbox[i].y1;
854 int w = pbox[i].x2 - pbox[i].x1 - 1;
857 if ( blit->ydir == -1 ) {
858 srcy = blit->height - srcy - 1;
861 start = srcy * blit->src_pitch + srcx;
863 DMA_BLOCK( MGA_AR0, start + w,
865 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
866 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h );
869 /* Do something to flush AGP?
872 /* Force reset of DWGCTL */
873 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
874 MGA_PLNWT, ctx->plnwt,
875 MGA_PITCH, dev_priv->front_pitch,
876 MGA_DWGCTL, ctx->dwgctl );
882 /* ================================================================
886 int mga_dma_clear( DRM_IOCTL_ARGS )
889 drm_mga_private_t *dev_priv = dev->dev_private;
890 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
891 drm_mga_clear_t clear;
893 LOCK_TEST_WITH_RETURN( dev, filp );
895 DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t *)data, sizeof(clear) );
897 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
898 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
900 WRAP_TEST_WITH_RETURN( dev_priv );
902 mga_dma_dispatch_clear( dev, &clear );
904 /* Make sure we restore the 3D state next time.
906 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
911 int mga_dma_swap( DRM_IOCTL_ARGS )
914 drm_mga_private_t *dev_priv = dev->dev_private;
915 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
917 LOCK_TEST_WITH_RETURN( dev, filp );
919 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
920 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
922 WRAP_TEST_WITH_RETURN( dev_priv );
924 mga_dma_dispatch_swap( dev );
926 /* Make sure we restore the 3D state next time.
928 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
933 int mga_dma_vertex( DRM_IOCTL_ARGS )
936 drm_mga_private_t *dev_priv = dev->dev_private;
937 drm_device_dma_t *dma = dev->dma;
939 drm_mga_buf_priv_t *buf_priv;
940 drm_mga_vertex_t vertex;
942 LOCK_TEST_WITH_RETURN( dev, filp );
944 DRM_COPY_FROM_USER_IOCTL( vertex,
945 (drm_mga_vertex_t *)data,
948 if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL);
949 buf = dma->buflist[vertex.idx];
950 buf_priv = buf->dev_private;
952 buf->used = vertex.used;
953 buf_priv->discard = vertex.discard;
955 if ( !mga_verify_state( dev_priv ) ) {
956 if ( vertex.discard ) {
957 if ( buf_priv->dispatched == 1 )
958 AGE_BUFFER( buf_priv );
959 buf_priv->dispatched = 0;
960 mga_freelist_put( dev, buf );
962 return DRM_ERR(EINVAL);
965 WRAP_TEST_WITH_RETURN( dev_priv );
967 mga_dma_dispatch_vertex( dev, buf );
972 int mga_dma_indices( DRM_IOCTL_ARGS )
975 drm_mga_private_t *dev_priv = dev->dev_private;
976 drm_device_dma_t *dma = dev->dma;
978 drm_mga_buf_priv_t *buf_priv;
979 drm_mga_indices_t indices;
981 LOCK_TEST_WITH_RETURN( dev, filp );
983 DRM_COPY_FROM_USER_IOCTL( indices,
984 (drm_mga_indices_t *)data,
987 if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL);
989 buf = dma->buflist[indices.idx];
990 buf_priv = buf->dev_private;
992 buf_priv->discard = indices.discard;
994 if ( !mga_verify_state( dev_priv ) ) {
995 if ( indices.discard ) {
996 if ( buf_priv->dispatched == 1 )
997 AGE_BUFFER( buf_priv );
998 buf_priv->dispatched = 0;
999 mga_freelist_put( dev, buf );
1001 return DRM_ERR(EINVAL);
1004 WRAP_TEST_WITH_RETURN( dev_priv );
1006 mga_dma_dispatch_indices( dev, buf, indices.start, indices.end );
1011 int mga_dma_iload( DRM_IOCTL_ARGS )
1014 drm_device_dma_t *dma = dev->dma;
1015 drm_mga_private_t *dev_priv = dev->dev_private;
1017 drm_mga_buf_priv_t *buf_priv;
1018 drm_mga_iload_t iload;
1021 LOCK_TEST_WITH_RETURN( dev, filp );
1023 DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t *)data, sizeof(iload) );
1026 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {
1027 if ( MGA_DMA_DEBUG )
1028 DRM_INFO( "%s: -EBUSY\n", __func__ );
1029 return DRM_ERR(EBUSY);
1032 if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL);
1034 buf = dma->buflist[iload.idx];
1035 buf_priv = buf->dev_private;
1037 if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) {
1038 mga_freelist_put( dev, buf );
1039 return DRM_ERR(EINVAL);
1042 WRAP_TEST_WITH_RETURN( dev_priv );
1044 mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length );
1046 /* Make sure we restore the 3D state next time.
1048 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1053 int mga_dma_blit( DRM_IOCTL_ARGS )
1056 drm_mga_private_t *dev_priv = dev->dev_private;
1057 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1058 drm_mga_blit_t blit;
1061 LOCK_TEST_WITH_RETURN( dev, filp );
1063 DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t *)data, sizeof(blit) );
1065 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
1066 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1068 if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) )
1069 return DRM_ERR(EINVAL);
1071 WRAP_TEST_WITH_RETURN( dev_priv );
1073 mga_dma_dispatch_blit( dev, &blit );
1075 /* Make sure we restore the 3D state next time.
1077 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1082 int mga_getparam( DRM_IOCTL_ARGS )
1085 drm_mga_private_t *dev_priv = dev->dev_private;
1086 drm_mga_getparam_t param;
1090 DRM_ERROR( "%s called with no initialization\n", __func__ );
1091 return DRM_ERR(EINVAL);
1094 DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t *)data,
1097 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
1099 switch( param.param ) {
1100 case MGA_PARAM_IRQ_NR:
1104 return DRM_ERR(EINVAL);
1107 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
1108 DRM_ERROR( "copy_to_user\n" );
1109 return DRM_ERR(EFAULT);