1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
30 * $FreeBSD: src/sys/dev/drm/r128_cce.c,v 1.6.2.1 2003/04/26 07:05:29 anholt Exp $
31 * $DragonFly: src/sys/dev/drm/r128/Attic/r128_cce.c,v 1.4 2005/02/17 13:59:36 joerg Exp $
35 #include "dev/drm/drmP.h"
36 #include "dev/drm/drm.h"
40 #define R128_FIFO_DEBUG 0
42 /* CCE microcode (from ATI) */
43 static u32 r128_cce_microcode[] = {
44 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
45 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
46 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
47 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
48 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
49 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
50 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
51 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
52 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
53 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
54 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
55 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
56 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
57 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
58 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
59 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
60 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
61 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
62 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
63 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
64 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
65 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
66 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
67 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
68 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
69 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
70 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
71 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
72 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
73 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
74 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
75 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
76 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
77 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
78 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
84 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
87 int r128_do_wait_for_idle( drm_r128_private_t *dev_priv );
89 int R128_READ_PLL(drm_device_t *dev, int addr)
91 drm_r128_private_t *dev_priv = dev->dev_private;
93 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
94 return R128_READ(R128_CLOCK_CNTL_DATA);
98 static void r128_status( drm_r128_private_t *dev_priv )
100 printk( "GUI_STAT = 0x%08x\n",
101 (unsigned int)R128_READ( R128_GUI_STAT ) );
102 printk( "PM4_STAT = 0x%08x\n",
103 (unsigned int)R128_READ( R128_PM4_STAT ) );
104 printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n",
105 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) );
106 printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n",
107 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) );
108 printk( "PM4_MICRO_CNTL = 0x%08x\n",
109 (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) );
110 printk( "PM4_BUFFER_CNTL = 0x%08x\n",
111 (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) );
116 /* ================================================================
117 * Engine, FIFO control
120 static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
125 tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL;
126 R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp );
128 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
129 if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
136 DRM_ERROR( "failed!\n" );
138 return DRM_ERR(EBUSY);
141 static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
145 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
146 int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
147 if ( slots >= entries ) return 0;
152 DRM_ERROR( "failed!\n" );
154 return DRM_ERR(EBUSY);
157 int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
161 ret = r128_do_wait_for_fifo( dev_priv, 64 );
162 if ( ret ) return ret;
164 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
165 if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
166 r128_do_pixcache_flush( dev_priv );
173 DRM_ERROR( "failed!\n" );
175 return DRM_ERR(EBUSY);
179 /* ================================================================
180 * CCE control, initialization
183 /* Load the microcode for the CCE */
184 static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
190 r128_do_wait_for_idle( dev_priv );
192 R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 );
193 for ( i = 0 ; i < 256 ; i++ ) {
194 R128_WRITE( R128_PM4_MICROCODE_DATAH,
195 r128_cce_microcode[i * 2] );
196 R128_WRITE( R128_PM4_MICROCODE_DATAL,
197 r128_cce_microcode[i * 2 + 1] );
201 /* Flush any pending commands to the CCE. This should only be used just
202 * prior to a wait for idle, as it informs the engine that the command
205 static void r128_do_cce_flush( drm_r128_private_t *dev_priv )
209 tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE;
210 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp );
213 /* Wait for the CCE to go idle.
215 int r128_do_cce_idle( drm_r128_private_t *dev_priv )
219 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
220 if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) {
221 int pm4stat = R128_READ( R128_PM4_STAT );
222 if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
223 dev_priv->cce_fifo_size ) &&
224 !(pm4stat & (R128_PM4_BUSY |
225 R128_PM4_GUI_ACTIVE)) ) {
226 return r128_do_pixcache_flush( dev_priv );
233 DRM_ERROR( "failed!\n" );
234 r128_status( dev_priv );
236 return DRM_ERR(EBUSY);
239 /* Start the Concurrent Command Engine.
241 static void r128_do_cce_start( drm_r128_private_t *dev_priv )
243 r128_do_wait_for_idle( dev_priv );
245 R128_WRITE( R128_PM4_BUFFER_CNTL,
246 dev_priv->cce_mode | dev_priv->ring.size_l2qw );
247 R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */
248 R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN );
250 dev_priv->cce_running = 1;
253 /* Reset the Concurrent Command Engine. This will not flush any pending
254 * commands, so you must wait for the CCE command stream to complete
255 * before calling this routine.
257 static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
259 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
260 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
261 SET_RING_HEAD( &dev_priv->ring, 0 );
262 dev_priv->ring.tail = 0;
265 /* Stop the Concurrent Command Engine. This will not flush any pending
266 * commands, so you must flush the command stream and wait for the CCE
267 * to go idle before calling this routine.
269 static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
271 R128_WRITE( R128_PM4_MICRO_CNTL, 0 );
272 R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 );
274 dev_priv->cce_running = 0;
277 /* Reset the engine. This will stop the CCE if it is running.
279 static int r128_do_engine_reset( drm_device_t *dev )
281 drm_r128_private_t *dev_priv = dev->dev_private;
282 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
284 r128_do_pixcache_flush( dev_priv );
286 clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX );
287 mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL );
289 R128_WRITE_PLL( R128_MCLK_CNTL,
290 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP );
292 gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL );
294 /* Taken from the sample code - do not change */
295 R128_WRITE( R128_GEN_RESET_CNTL,
296 gen_reset_cntl | R128_SOFT_RESET_GUI );
297 R128_READ( R128_GEN_RESET_CNTL );
298 R128_WRITE( R128_GEN_RESET_CNTL,
299 gen_reset_cntl & ~R128_SOFT_RESET_GUI );
300 R128_READ( R128_GEN_RESET_CNTL );
302 R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl );
303 R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index );
304 R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl );
306 /* Reset the CCE ring */
307 r128_do_cce_reset( dev_priv );
309 /* The CCE is no longer running after an engine reset */
310 dev_priv->cce_running = 0;
312 /* Reset any pending vertex, indirect buffers */
313 r128_freelist_reset( dev );
318 static void r128_cce_init_ring_buffer( drm_device_t *dev,
319 drm_r128_private_t *dev_priv )
326 /* The manual (p. 2) says this address is in "VM space". This
327 * means it's an offset from the start of AGP space.
329 #if __REALLY_HAVE_AGP
330 if ( !dev_priv->is_pci )
331 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
334 ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
336 R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );
338 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
339 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
341 /* DL_RPTR_ADDR is a physical address in AGP space. */
342 SET_RING_HEAD( &dev_priv->ring, 0 );
344 if ( !dev_priv->is_pci ) {
345 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
346 dev_priv->ring_rptr->offset );
348 drm_sg_mem_t *entry = dev->sg;
349 unsigned long tmp_ofs, page_ofs;
351 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
352 page_ofs = tmp_ofs >> PAGE_SHIFT;
354 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
355 entry->busaddr[page_ofs]);
356 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
357 entry->busaddr[page_ofs],
358 entry->handle + tmp_ofs );
361 /* Set watermark control */
362 R128_WRITE( R128_PM4_BUFFER_WM_CNTL,
363 ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)
364 | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)
365 | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)
366 | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );
368 /* Force read. Why? Because it's in the examples... */
369 R128_READ( R128_PM4_BUFFER_ADDR );
371 /* Turn on bus mastering */
372 tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;
373 R128_WRITE( R128_BUS_CNTL, tmp );
376 static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
378 drm_r128_private_t *dev_priv;
382 dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
383 if ( dev_priv == NULL )
384 return DRM_ERR(ENOMEM);
386 memset( dev_priv, 0, sizeof(drm_r128_private_t) );
388 dev_priv->is_pci = init->is_pci;
390 if ( dev_priv->is_pci && !dev->sg ) {
391 DRM_ERROR( "PCI GART memory not allocated!\n" );
392 dev->dev_private = (void *)dev_priv;
393 r128_do_cleanup_cce( dev );
394 return DRM_ERR(EINVAL);
397 dev_priv->usec_timeout = init->usec_timeout;
398 if ( dev_priv->usec_timeout < 1 ||
399 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) {
400 DRM_DEBUG( "TIMEOUT problem!\n" );
401 dev->dev_private = (void *)dev_priv;
402 r128_do_cleanup_cce( dev );
403 return DRM_ERR(EINVAL);
406 dev_priv->cce_mode = init->cce_mode;
408 /* GH: Simple idle check.
410 atomic_set( &dev_priv->idle_count, 0 );
412 /* We don't support anything other than bus-mastering ring mode,
413 * but the ring can be in either AGP or PCI space for the ring
416 if ( ( init->cce_mode != R128_PM4_192BM ) &&
417 ( init->cce_mode != R128_PM4_128BM_64INDBM ) &&
418 ( init->cce_mode != R128_PM4_64BM_128INDBM ) &&
419 ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) {
420 DRM_DEBUG( "Bad cce_mode!\n" );
421 dev->dev_private = (void *)dev_priv;
422 r128_do_cleanup_cce( dev );
423 return DRM_ERR(EINVAL);
426 switch ( init->cce_mode ) {
427 case R128_PM4_NONPM4:
428 dev_priv->cce_fifo_size = 0;
430 case R128_PM4_192PIO:
432 dev_priv->cce_fifo_size = 192;
434 case R128_PM4_128PIO_64INDBM:
435 case R128_PM4_128BM_64INDBM:
436 dev_priv->cce_fifo_size = 128;
438 case R128_PM4_64PIO_128INDBM:
439 case R128_PM4_64BM_128INDBM:
440 case R128_PM4_64PIO_64VCBM_64INDBM:
441 case R128_PM4_64BM_64VCBM_64INDBM:
442 case R128_PM4_64PIO_64VCPIO_64INDPIO:
443 dev_priv->cce_fifo_size = 64;
447 switch ( init->fb_bpp ) {
449 dev_priv->color_fmt = R128_DATATYPE_RGB565;
453 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
456 dev_priv->front_offset = init->front_offset;
457 dev_priv->front_pitch = init->front_pitch;
458 dev_priv->back_offset = init->back_offset;
459 dev_priv->back_pitch = init->back_pitch;
461 switch ( init->depth_bpp ) {
463 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
468 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
471 dev_priv->depth_offset = init->depth_offset;
472 dev_priv->depth_pitch = init->depth_pitch;
473 dev_priv->span_offset = init->span_offset;
475 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) |
476 (dev_priv->front_offset >> 5));
477 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) |
478 (dev_priv->back_offset >> 5));
479 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
480 (dev_priv->depth_offset >> 5) |
482 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
483 (dev_priv->span_offset >> 5));
487 if(!dev_priv->sarea) {
488 DRM_ERROR("could not find sarea!\n");
489 dev->dev_private = (void *)dev_priv;
490 r128_do_cleanup_cce( dev );
491 return DRM_ERR(EINVAL);
494 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
496 DRM_ERROR("could not find framebuffer!\n");
497 dev->dev_private = (void *)dev_priv;
498 r128_do_cleanup_cce( dev );
499 return DRM_ERR(EINVAL);
501 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
502 if(!dev_priv->mmio) {
503 DRM_ERROR("could not find mmio region!\n");
504 dev->dev_private = (void *)dev_priv;
505 r128_do_cleanup_cce( dev );
506 return DRM_ERR(EINVAL);
508 DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset );
509 if(!dev_priv->cce_ring) {
510 DRM_ERROR("could not find cce ring region!\n");
511 dev->dev_private = (void *)dev_priv;
512 r128_do_cleanup_cce( dev );
513 return DRM_ERR(EINVAL);
515 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
516 if(!dev_priv->ring_rptr) {
517 DRM_ERROR("could not find ring read pointer!\n");
518 dev->dev_private = (void *)dev_priv;
519 r128_do_cleanup_cce( dev );
520 return DRM_ERR(EINVAL);
522 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
523 if(!dev_priv->buffers) {
524 DRM_ERROR("could not find dma buffer region!\n");
525 dev->dev_private = (void *)dev_priv;
526 r128_do_cleanup_cce( dev );
527 return DRM_ERR(EINVAL);
530 if ( !dev_priv->is_pci ) {
531 DRM_FIND_MAP( dev_priv->agp_textures,
532 init->agp_textures_offset );
533 if(!dev_priv->agp_textures) {
534 DRM_ERROR("could not find agp texture region!\n");
535 dev->dev_private = (void *)dev_priv;
536 r128_do_cleanup_cce( dev );
537 return DRM_ERR(EINVAL);
541 dev_priv->sarea_priv =
542 (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
543 init->sarea_priv_offset);
545 if ( !dev_priv->is_pci ) {
546 DRM_IOREMAP( dev_priv->cce_ring );
547 DRM_IOREMAP( dev_priv->ring_rptr );
548 DRM_IOREMAP( dev_priv->buffers );
549 if(!dev_priv->cce_ring->handle ||
550 !dev_priv->ring_rptr->handle ||
551 !dev_priv->buffers->handle) {
552 DRM_ERROR("Could not ioremap agp regions!\n");
553 dev->dev_private = (void *)dev_priv;
554 r128_do_cleanup_cce( dev );
555 return DRM_ERR(ENOMEM);
558 dev_priv->cce_ring->handle =
559 (void *)dev_priv->cce_ring->offset;
560 dev_priv->ring_rptr->handle =
561 (void *)dev_priv->ring_rptr->offset;
562 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
565 #if __REALLY_HAVE_AGP
566 if ( !dev_priv->is_pci )
567 dev_priv->cce_buffers_offset = dev->agp->base;
570 dev_priv->cce_buffers_offset = dev->sg->handle;
572 dev_priv->ring.head = ((__volatile__ u32 *)
573 dev_priv->ring_rptr->handle);
575 dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle;
576 dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle
577 + init->ring_size / sizeof(u32));
578 dev_priv->ring.size = init->ring_size;
579 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
581 dev_priv->ring.tail_mask =
582 (dev_priv->ring.size / sizeof(u32)) - 1;
584 dev_priv->ring.high_mark = 128;
585 dev_priv->ring.ring_rptr = dev_priv->ring_rptr;
587 dev_priv->sarea_priv->last_frame = 0;
588 R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
590 dev_priv->sarea_priv->last_dispatch = 0;
591 R128_WRITE( R128_LAST_DISPATCH_REG,
592 dev_priv->sarea_priv->last_dispatch );
595 if ( dev_priv->is_pci ) {
596 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
597 &dev_priv->bus_pci_gart) ) {
598 DRM_ERROR( "failed to init PCI GART!\n" );
599 dev->dev_private = (void *)dev_priv;
600 r128_do_cleanup_cce( dev );
601 return DRM_ERR(ENOMEM);
603 R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart );
607 r128_cce_init_ring_buffer( dev, dev_priv );
608 r128_cce_load_microcode( dev_priv );
610 dev->dev_private = (void *)dev_priv;
612 r128_do_engine_reset( dev );
617 int r128_do_cleanup_cce( drm_device_t *dev )
619 if ( dev->dev_private ) {
620 drm_r128_private_t *dev_priv = dev->dev_private;
623 if ( !dev_priv->is_pci ) {
625 if ( dev_priv->cce_ring != NULL )
626 DRM_IOREMAPFREE( dev_priv->cce_ring );
627 if ( dev_priv->ring_rptr != NULL )
628 DRM_IOREMAPFREE( dev_priv->ring_rptr );
629 if ( dev_priv->buffers != NULL )
630 DRM_IOREMAPFREE( dev_priv->buffers );
633 if (!DRM(ati_pcigart_cleanup)( dev,
634 dev_priv->phys_pci_gart,
635 dev_priv->bus_pci_gart ))
636 DRM_ERROR( "failed to cleanup PCI GART!\n" );
640 DRM(free)( dev->dev_private, sizeof(drm_r128_private_t),
642 dev->dev_private = NULL;
648 int r128_cce_init( DRM_IOCTL_ARGS )
651 drm_r128_init_t init;
655 DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t *)data, sizeof(init) );
657 switch ( init.func ) {
659 return r128_do_init_cce( dev, &init );
660 case R128_CLEANUP_CCE:
661 return r128_do_cleanup_cce( dev );
664 return DRM_ERR(EINVAL);
667 int r128_cce_start( DRM_IOCTL_ARGS )
670 drm_r128_private_t *dev_priv = dev->dev_private;
673 LOCK_TEST_WITH_RETURN( dev, filp );
675 if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
676 DRM_DEBUG( "%s while CCE running\n", __func__ );
680 r128_do_cce_start( dev_priv );
685 /* Stop the CCE. The engine must have been idled before calling this
688 int r128_cce_stop( DRM_IOCTL_ARGS )
691 drm_r128_private_t *dev_priv = dev->dev_private;
692 drm_r128_cce_stop_t stop;
696 LOCK_TEST_WITH_RETURN( dev, filp );
698 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t *)data, sizeof(stop) );
700 /* Flush any pending CCE commands. This ensures any outstanding
701 * commands are exectuted by the engine before we turn it off.
704 r128_do_cce_flush( dev_priv );
707 /* If we fail to make the engine go idle, we return an error
708 * code so that the DRM ioctl wrapper can try again.
711 ret = r128_do_cce_idle( dev_priv );
712 if ( ret ) return ret;
715 /* Finally, we can turn off the CCE. If the engine isn't idle,
716 * we will get some dropped triangles as they won't be fully
717 * rendered before the CCE is shut down.
719 r128_do_cce_stop( dev_priv );
721 /* Reset the engine */
722 r128_do_engine_reset( dev );
727 /* Just reset the CCE ring. Called as part of an X Server engine reset.
729 int r128_cce_reset( DRM_IOCTL_ARGS )
732 drm_r128_private_t *dev_priv = dev->dev_private;
735 LOCK_TEST_WITH_RETURN( dev, filp );
738 DRM_DEBUG( "%s called before init done\n", __func__ );
739 return DRM_ERR(EINVAL);
742 r128_do_cce_reset( dev_priv );
744 /* The CCE is no longer running after an engine reset */
745 dev_priv->cce_running = 0;
750 int r128_cce_idle( DRM_IOCTL_ARGS )
753 drm_r128_private_t *dev_priv = dev->dev_private;
756 LOCK_TEST_WITH_RETURN( dev, filp );
758 if ( dev_priv->cce_running ) {
759 r128_do_cce_flush( dev_priv );
762 return r128_do_cce_idle( dev_priv );
765 int r128_engine_reset( DRM_IOCTL_ARGS )
770 LOCK_TEST_WITH_RETURN( dev, filp );
772 return r128_do_engine_reset( dev );
776 /* ================================================================
780 static int r128_do_init_pageflip( drm_device_t *dev )
782 drm_r128_private_t *dev_priv = dev->dev_private;
785 dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET );
786 dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL );
788 R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset );
789 R128_WRITE( R128_CRTC_OFFSET_CNTL,
790 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL );
792 dev_priv->page_flipping = 1;
793 dev_priv->current_page = 0;
798 int r128_do_cleanup_pageflip( drm_device_t *dev )
800 drm_r128_private_t *dev_priv = dev->dev_private;
803 R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset );
804 R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
806 dev_priv->page_flipping = 0;
807 dev_priv->current_page = 0;
812 int r128_fullscreen( DRM_IOCTL_ARGS )
815 drm_r128_fullscreen_t fs;
817 LOCK_TEST_WITH_RETURN( dev, filp );
819 DRM_COPY_FROM_USER_IOCTL( fs, (drm_r128_fullscreen_t *)data, sizeof(fs) );
822 case R128_INIT_FULLSCREEN:
823 return r128_do_init_pageflip( dev );
824 case R128_CLEANUP_FULLSCREEN:
825 return r128_do_cleanup_pageflip( dev );
828 return DRM_ERR(EINVAL);
832 /* ================================================================
833 * Freelist management
835 #define R128_BUFFER_USED 0xffffffff
836 #define R128_BUFFER_FREE 0
839 static int r128_freelist_init( drm_device_t *dev )
841 drm_device_dma_t *dma = dev->dma;
842 drm_r128_private_t *dev_priv = dev->dev_private;
844 drm_r128_buf_priv_t *buf_priv;
845 drm_r128_freelist_t *entry;
848 dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t),
850 if ( dev_priv->head == NULL )
851 return DRM_ERR(ENOMEM);
853 memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
854 dev_priv->head->age = R128_BUFFER_USED;
856 for ( i = 0 ; i < dma->buf_count ; i++ ) {
857 buf = dma->buflist[i];
858 buf_priv = buf->dev_private;
860 entry = DRM(alloc)( sizeof(drm_r128_freelist_t),
862 if ( !entry ) return DRM_ERR(ENOMEM);
864 entry->age = R128_BUFFER_FREE;
866 entry->prev = dev_priv->head;
867 entry->next = dev_priv->head->next;
869 dev_priv->tail = entry;
871 buf_priv->discard = 0;
872 buf_priv->dispatched = 0;
873 buf_priv->list_entry = entry;
875 dev_priv->head->next = entry;
877 if ( dev_priv->head->next )
878 dev_priv->head->next->prev = entry;
886 drm_buf_t *r128_freelist_get( drm_device_t *dev )
888 drm_device_dma_t *dma = dev->dma;
889 drm_r128_private_t *dev_priv = dev->dev_private;
890 drm_r128_buf_priv_t *buf_priv;
894 /* FIXME: Optimize -- use freelist code */
896 for ( i = 0 ; i < dma->buf_count ; i++ ) {
897 buf = dma->buflist[i];
898 buf_priv = buf->dev_private;
899 if ( buf->filp == 0 )
903 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
904 u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
906 for ( i = 0 ; i < dma->buf_count ; i++ ) {
907 buf = dma->buflist[i];
908 buf_priv = buf->dev_private;
909 if ( buf->pending && buf_priv->age <= done_age ) {
910 /* The buffer has been processed, so it
920 DRM_ERROR( "returning NULL!\n" );
924 void r128_freelist_reset( drm_device_t *dev )
926 drm_device_dma_t *dma = dev->dma;
929 for ( i = 0 ; i < dma->buf_count ; i++ ) {
930 drm_buf_t *buf = dma->buflist[i];
931 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
937 /* ================================================================
938 * CCE command submission
941 int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
943 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
946 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
947 r128_update_ring_snapshot( ring );
948 if ( ring->space >= n )
953 /* FIXME: This is being ignored... */
954 DRM_ERROR( "failed!\n" );
955 return DRM_ERR(EBUSY);
958 static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
963 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
964 buf = r128_freelist_get( dev );
965 if ( !buf ) return DRM_ERR(EAGAIN);
969 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
971 return DRM_ERR(EFAULT);
972 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
973 sizeof(buf->total) ) )
974 return DRM_ERR(EFAULT);
981 int r128_cce_buffers( DRM_IOCTL_ARGS )
984 drm_device_dma_t *dma = dev->dma;
988 LOCK_TEST_WITH_RETURN( dev, filp );
990 DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *) data, sizeof(d) );
992 /* Please don't send us buffers.
994 if ( d.send_count != 0 ) {
995 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
996 DRM_CURRENTPID, d.send_count );
997 return DRM_ERR(EINVAL);
1000 /* We'll send you buffers.
1002 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1003 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1004 DRM_CURRENTPID, d.request_count, dma->buf_count );
1005 return DRM_ERR(EINVAL);
1008 d.granted_count = 0;
1010 if ( d.request_count ) {
1011 ret = r128_cce_get_buffers( filp, dev, &d );
1014 DRM_COPY_TO_USER_IOCTL((drm_dma_t *) data, d, sizeof(d) );