1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel Dänzer <michel@daenzer.net>
32 * $FreeBSD: src/sys/dev/drm/radeon_irq.c,v 1.2.2.1 2003/04/26 07:05:29 anholt Exp $
33 * $DragonFly: src/sys/dev/drm/radeon/Attic/radeon_irq.c,v 1.4 2005/02/17 13:59:36 joerg Exp $
37 #include "dev/drm/drmP.h"
38 #include "dev/drm/drm.h"
39 #include "radeon_drm.h"
40 #include "radeon_drv.h"
42 /* Interrupts - Used for device synchronization and flushing in the
43 * following circumstances:
45 * - Exclusive FB access with hw idle:
46 * - Wait for GUI Idle (?) interrupt, then do normal flush.
48 * - Frame throttling, NV_fence:
49 * - Drop marker irq's into command stream ahead of time.
50 * - Wait on irq's with lock *not held*
51 * - Check each for termination condition
53 * - Internally in cp_getbuffer, etc:
54 * - as above, but wait with lock held???
56 * NOTE: These functions are misleadingly named -- the irq's aren't
57 * tied to dma at all, this is just a hangover from dri prehistory.
60 void DRM(dma_service)( DRM_IRQ_ARGS )
62 drm_device_t *dev = (drm_device_t *) arg;
63 drm_radeon_private_t *dev_priv =
64 (drm_radeon_private_t *)dev->dev_private;
67 /* Only consider the bits we're interested in - others could be used
70 stat = RADEON_READ(RADEON_GEN_INT_STATUS)
71 & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
76 if (stat & RADEON_SW_INT_TEST) {
77 DRM_WAKEUP( &dev_priv->swi_queue );
80 /* VBLANK interrupt */
81 if (stat & RADEON_CRTC_VBLANK_STAT) {
82 atomic_inc(&dev->vbl_received);
83 DRM_WAKEUP(&dev->vbl_queue);
84 DRM(vbl_send_signals)( dev );
87 /* Acknowledge interrupts we handle */
88 RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
91 static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
93 u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
94 & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
96 RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
99 int radeon_emit_irq(drm_device_t *dev)
101 drm_radeon_private_t *dev_priv = dev->dev_private;
105 atomic_inc(&dev_priv->swi_emitted);
106 ret = atomic_read(&dev_priv->swi_emitted);
109 OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
110 OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
118 int radeon_wait_irq(drm_device_t *dev, int swi_nr)
120 drm_radeon_private_t *dev_priv =
121 (drm_radeon_private_t *)dev->dev_private;
124 if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)
127 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
129 /* This is a hack to work around mysterious freezes on certain
132 radeon_acknowledge_irqs( dev_priv );
134 DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ,
135 RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );
140 int radeon_emit_and_wait_irq(drm_device_t *dev)
142 return radeon_wait_irq( dev, radeon_emit_irq(dev) );
146 int DRM(vblank_wait)(drm_device_t *dev, unsigned int *sequence)
148 drm_radeon_private_t *dev_priv =
149 (drm_radeon_private_t *)dev->dev_private;
150 unsigned int cur_vblank;
154 DRM_ERROR( "%s called with no initialization\n", __func__ );
155 return DRM_ERR(EINVAL);
158 radeon_acknowledge_irqs( dev_priv );
160 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
162 /* Assume that the user has missed the current sequence number
163 * by about a day rather than she wants to wait for years
164 * using vertical blanks...
166 DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
167 ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
168 - *sequence ) <= (1<<23) ) );
170 *sequence = cur_vblank;
176 /* Needs the lock as it touches the ring.
178 int radeon_irq_emit( DRM_IOCTL_ARGS )
181 drm_radeon_private_t *dev_priv = dev->dev_private;
182 drm_radeon_irq_emit_t emit;
185 LOCK_TEST_WITH_RETURN( dev, filp );
188 DRM_ERROR( "%s called with no initialization\n", __func__ );
189 return DRM_ERR(EINVAL);
192 DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t *)data,
195 result = radeon_emit_irq( dev );
197 if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
198 DRM_ERROR( "copy_to_user\n" );
199 return DRM_ERR(EFAULT);
206 /* Doesn't need the hardware lock.
208 int radeon_irq_wait( DRM_IOCTL_ARGS )
211 drm_radeon_private_t *dev_priv = dev->dev_private;
212 drm_radeon_irq_wait_t irqwait;
215 DRM_ERROR( "%s called with no initialization\n", __func__ );
216 return DRM_ERR(EINVAL);
219 DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t *)data,
222 return radeon_wait_irq( dev, irqwait.irq_seq );
228 void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
229 drm_radeon_private_t *dev_priv =
230 (drm_radeon_private_t *)dev->dev_private;
232 /* Disable *all* interrupts */
233 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
235 /* Clear bits if they're already high */
236 radeon_acknowledge_irqs( dev_priv );
239 void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
240 drm_radeon_private_t *dev_priv =
241 (drm_radeon_private_t *)dev->dev_private;
243 atomic_set(&dev_priv->swi_emitted, 0);
244 DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );
246 /* Turn on SW and VBL ints */
247 RADEON_WRITE( RADEON_GEN_INT_CNTL,
248 RADEON_CRTC_VBLANK_MASK |
249 RADEON_SW_INT_ENABLE );
252 void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
253 drm_radeon_private_t *dev_priv =
254 (drm_radeon_private_t *)dev->dev_private;
256 /* Disable *all* interrupts */
257 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );