2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/pci/pcireg.h,v 1.64.2.4.2.1 2009/04/15 03:14:26 kensmith Exp $
34 #include <sys/types.h>
37 typedef u_int16_t pci_vendor_id_t;
38 typedef u_int16_t pci_product_id_t;
39 typedef u_int8_t pci_class_t;
40 typedef u_int8_t pci_subclass_t;
41 typedef u_int8_t pci_interface_t;
42 typedef u_int8_t pci_revision_t;
43 typedef u_int8_t pci_intr_pin_t;
44 typedef u_int8_t pci_intr_line_t;
45 typedef u_int32_t pcireg_t; /* ~typical configuration space */
48 * PCIM_xxx: mask to locate subfield in register
49 * PCIR_xxx: config register offset
50 * PCIC_xxx: device class
51 * PCIS_xxx: device subclass
52 * PCIP_xxx: device programming interface
53 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
55 * PCIY_xxx: capability identification number
58 /* some PCI bus constants */
60 #define PCI_BUSMAX 255
61 #define PCI_SLOTMAX 31
63 #define PCI_REGMAX 255
64 #define PCIE_REGMAX 4095
65 #define PCI_MAXHDRTYPE 2
67 /* PCI config header registers for all devices */
69 #define PCIR_DEVVENDOR 0x00
70 #define PCIR_VENDOR 0x00
71 #define PCIR_DEVICE 0x02
72 #define PCIR_COMMAND 0x04
73 #define PCIR_CARDBUSCIS 0x28
74 #define PCIM_CMD_PORTEN 0x0001
75 #define PCIM_CMD_MEMEN 0x0002
76 #define PCIM_CMD_BUSMASTEREN 0x0004
77 #define PCIM_CMD_SPECIALEN 0x0008
78 #define PCIM_CMD_MWRICEN 0x0010
79 #define PCIM_CMD_PERRESPEN 0x0040
80 #define PCIM_CMD_SERRESPEN 0x0100
81 #define PCIM_CMD_BACKTOBACK 0x0200
82 #define PCIM_CMD_INTxDIS 0x0400
83 #define PCIR_STATUS 0x06
84 #define PCIM_STATUS_CAPPRESENT 0x0010
85 #define PCIM_STATUS_66CAPABLE 0x0020
86 #define PCIM_STATUS_BACKTOBACK 0x0080
87 #define PCIM_STATUS_PERRREPORT 0x0100
88 #define PCIM_STATUS_SEL_FAST 0x0000
89 #define PCIM_STATUS_SEL_MEDIMUM 0x0200
90 #define PCIM_STATUS_SEL_SLOW 0x0400
91 #define PCIM_STATUS_SEL_MASK 0x0600
92 #define PCIM_STATUS_STABORT 0x0800
93 #define PCIM_STATUS_RTABORT 0x1000
94 #define PCIM_STATUS_RMABORT 0x2000
95 #define PCIM_STATUS_SERR 0x4000
96 #define PCIM_STATUS_PERR 0x8000
97 #define PCIR_REVID 0x08
98 #define PCIR_PROGIF 0x09
99 #define PCIR_SUBCLASS 0x0a
100 #define PCIR_CLASS 0x0b
101 #define PCIR_CACHELNSZ 0x0c
102 #define PCIR_LATTIMER 0x0d
103 #define PCIR_HDRTYPE 0x0e
104 #define PCIM_HDRTYPE 0x7f
105 #define PCIM_HDRTYPE_NORMAL 0x00
106 #define PCIM_HDRTYPE_BRIDGE 0x01
107 #define PCIM_HDRTYPE_CARDBUS 0x02
108 #define PCIM_MFDEV 0x80
109 #define PCIR_BIST 0x0f
111 /* Capability Register Offsets */
113 #define PCICAP_ID 0x0
114 #define PCICAP_NEXTPTR 0x1
116 /* Capability Identification Numbers */
118 #define PCIY_PMG 0x01 /* PCI Power Management */
119 #define PCIY_AGP 0x02 /* AGP */
120 #define PCIY_VPD 0x03 /* Vital Product Data */
121 #define PCIY_SLOTID 0x04 /* Slot Identification */
122 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */
123 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
124 #define PCIY_PCIX 0x07 /* PCI-X */
125 #define PCIY_HT 0x08 /* HyperTransport */
126 #define PCIY_VENDOR 0x09 /* Vendor Unique */
127 #define PCIY_DEBUG 0x0a /* Debug port */
128 #define PCIY_CRES 0x0b /* CompactPCI central resource control */
129 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
130 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */
131 #define PCIY_AGP8X 0x0e /* AGP 8x */
132 #define PCIY_SECDEV 0x0f /* Secure Device */
133 #define PCIY_EXPRESS 0x10 /* PCI Express */
134 #define PCIY_MSIX 0x11 /* MSI-X */
136 /* config registers for header type 0 devices */
138 #define PCIR_BARS 0x10
139 #define PCIR_MAPS PCIR_BARS
140 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
141 #define PCIR_MAX_BAR_0 5
142 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4)
143 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
144 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
145 #define PCIM_BAR_SPACE 0x00000001
146 #define PCIM_BAR_MEM_SPACE 0
147 #define PCIM_BAR_IO_SPACE 1
148 #define PCIM_BAR_MEM_TYPE 0x00000006
149 #define PCIM_BAR_MEM_32 0
150 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
151 #define PCIM_BAR_MEM_64 4
152 #define PCIM_BAR_MEM_PREFETCH 0x00000008
153 #define PCIM_BAR_MEM_BASE 0xfffffff0
154 #define PCIM_BAR_IO_RESERVED 0x00000002
155 #define PCIM_BAR_IO_BASE 0xfffffffc
156 #define PCIR_CIS 0x28
157 #define PCIM_CIS_ASI_MASK 0x7
158 #define PCIM_CIS_ASI_CONFIG 0
159 #define PCIM_CIS_ASI_BAR0 1
160 #define PCIM_CIS_ASI_BAR1 2
161 #define PCIM_CIS_ASI_BAR2 3
162 #define PCIM_CIS_ASI_BAR3 4
163 #define PCIM_CIS_ASI_BAR4 5
164 #define PCIM_CIS_ASI_BAR5 6
165 #define PCIM_CIS_ASI_ROM 7
166 #define PCIM_CIS_ADDR_MASK 0x0ffffff8
167 #define PCIM_CIS_ROM_MASK 0xf0000000
168 #define PCIM_CIS_CONFIG_MASK 0xff
169 #define PCIR_SUBVEND_0 0x2c
170 #define PCIR_SUBDEV_0 0x2e
171 #define PCIR_BIOS 0x30
172 #define PCIM_BIOS_ENABLE 0x01
173 #define PCIM_BIOS_ADDR_MASK 0xfffff800
174 #define PCIR_CAP_PTR 0x34
175 #define PCIR_INTLINE 0x3c
176 #define PCIR_INTPIN 0x3d
177 #define PCIR_MINGNT 0x3e
178 #define PCIR_MAXLAT 0x3f
180 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
182 #define PCIR_MAX_BAR_1 1
183 #define PCIR_SECSTAT_1 0x1e
185 #define PCIR_PRIBUS_1 0x18
186 #define PCIR_SECBUS_1 0x19
187 #define PCIR_SUBBUS_1 0x1a
188 #define PCIR_SECLAT_1 0x1b
190 #define PCIR_IOBASEL_1 0x1c
191 #define PCIR_IOLIMITL_1 0x1d
192 #define PCIR_IOBASEH_1 0x30
193 #define PCIR_IOLIMITH_1 0x32
194 #define PCIM_BRIO_16 0x0
195 #define PCIM_BRIO_32 0x1
196 #define PCIM_BRIO_MASK 0xf
198 #define PCIR_MEMBASE_1 0x20
199 #define PCIR_MEMLIMIT_1 0x22
201 #define PCIR_PMBASEL_1 0x24
202 #define PCIR_PMLIMITL_1 0x26
203 #define PCIR_PMBASEH_1 0x28
204 #define PCIR_PMLIMITH_1 0x2c
205 #define PCIM_BRPM_32 0x0
206 #define PCIM_BRPM_64 0x1
207 #define PCIM_BRPM_MASK 0xf
209 #define PCIR_BRIDGECTL_1 0x3e
211 /* config registers for header type 2 (CardBus) devices */
213 #define PCIR_MAX_BAR_2 0
214 #define PCIR_CAP_PTR_2 0x14
215 #define PCIR_SECSTAT_2 0x16
217 #define PCIR_PRIBUS_2 0x18
218 #define PCIR_SECBUS_2 0x19
219 #define PCIR_SUBBUS_2 0x1a
220 #define PCIR_SECLAT_2 0x1b
222 #define PCIR_MEMBASE0_2 0x1c
223 #define PCIR_MEMLIMIT0_2 0x20
224 #define PCIR_MEMBASE1_2 0x24
225 #define PCIR_MEMLIMIT1_2 0x28
226 #define PCIR_IOBASE0_2 0x2c
227 #define PCIR_IOLIMIT0_2 0x30
228 #define PCIR_IOBASE1_2 0x34
229 #define PCIR_IOLIMIT1_2 0x38
231 #define PCIR_BRIDGECTL_2 0x3e
233 #define PCIR_SUBVEND_2 0x40
234 #define PCIR_SUBDEV_2 0x42
236 #define PCIR_PCCARDIF_2 0x44
238 /* PCI device class, subclass and programming interface definitions */
240 #define PCIC_OLD 0x00
241 #define PCIS_OLD_NONVGA 0x00
242 #define PCIS_OLD_VGA 0x01
244 #define PCIC_STORAGE 0x01
245 #define PCIS_STORAGE_SCSI 0x00
246 #define PCIS_STORAGE_IDE 0x01
247 #define PCIP_STORAGE_IDE_MODEPRIM 0x01
248 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
249 #define PCIP_STORAGE_IDE_MODESEC 0x04
250 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08
251 #define PCIP_STORAGE_IDE_MASTERDEV 0x80
252 #define PCIS_STORAGE_FLOPPY 0x02
253 #define PCIS_STORAGE_IPI 0x03
254 #define PCIS_STORAGE_RAID 0x04
255 #define PCIS_STORAGE_ATA_ADMA 0x05
256 #define PCIS_STORAGE_SATA 0x06
257 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01
258 #define PCIS_STORAGE_SAS 0x07
259 #define PCIS_STORAGE_OTHER 0x80
261 #define PCIC_NETWORK 0x02
262 #define PCIS_NETWORK_ETHERNET 0x00
263 #define PCIS_NETWORK_TOKENRING 0x01
264 #define PCIS_NETWORK_FDDI 0x02
265 #define PCIS_NETWORK_ATM 0x03
266 #define PCIS_NETWORK_ISDN 0x04
267 #define PCIS_NETWORK_WORLDFIP 0x05
268 #define PCIS_NETWORK_PICMG 0x06
269 #define PCIS_NETWORK_OTHER 0x80
271 #define PCIC_DISPLAY 0x03
272 #define PCIS_DISPLAY_VGA 0x00
273 #define PCIS_DISPLAY_XGA 0x01
274 #define PCIS_DISPLAY_3D 0x02
275 #define PCIS_DISPLAY_OTHER 0x80
277 #define PCIC_MULTIMEDIA 0x04
278 #define PCIS_MULTIMEDIA_VIDEO 0x00
279 #define PCIS_MULTIMEDIA_AUDIO 0x01
280 #define PCIS_MULTIMEDIA_TELE 0x02
281 #define PCIS_MULTIMEDIA_HDA 0x03
282 #define PCIS_MULTIMEDIA_OTHER 0x80
284 #define PCIC_MEMORY 0x05
285 #define PCIS_MEMORY_RAM 0x00
286 #define PCIS_MEMORY_FLASH 0x01
287 #define PCIS_MEMORY_OTHER 0x80
289 #define PCIC_BRIDGE 0x06
290 #define PCIS_BRIDGE_HOST 0x00
291 #define PCIS_BRIDGE_ISA 0x01
292 #define PCIS_BRIDGE_EISA 0x02
293 #define PCIS_BRIDGE_MCA 0x03
294 #define PCIS_BRIDGE_PCI 0x04
295 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01
296 #define PCIS_BRIDGE_PCMCIA 0x05
297 #define PCIS_BRIDGE_NUBUS 0x06
298 #define PCIS_BRIDGE_CARDBUS 0x07
299 #define PCIS_BRIDGE_RACEWAY 0x08
300 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
301 #define PCIS_BRIDGE_INFINIBAND 0x0a
302 #define PCIS_BRIDGE_OTHER 0x80
304 #define PCIC_SIMPLECOMM 0x07
305 #define PCIS_SIMPLECOMM_UART 0x00
306 #define PCIP_SIMPLECOMM_UART_8250 0x00
307 #define PCIP_SIMPLECOMM_UART_16450A 0x01
308 #define PCIP_SIMPLECOMM_UART_16550A 0x02
309 #define PCIP_SIMPLECOMM_UART_16650A 0x03
310 #define PCIP_SIMPLECOMM_UART_16750A 0x04
311 #define PCIP_SIMPLECOMM_UART_16850A 0x05
312 #define PCIP_SIMPLECOMM_UART_16950A 0x06
313 #define PCIS_SIMPLECOMM_PAR 0x01
314 #define PCIS_SIMPLECOMM_MULSER 0x02
315 #define PCIS_SIMPLECOMM_MODEM 0x03
316 #define PCIS_SIMPLECOMM_GPIB 0x04
317 #define PCIS_SIMPLECOMM_SMART_CARD 0x05
318 #define PCIS_SIMPLECOMM_OTHER 0x80
320 #define PCIC_BASEPERIPH 0x08
321 #define PCIS_BASEPERIPH_PIC 0x00
322 #define PCIP_BASEPERIPH_PIC_8259A 0x00
323 #define PCIP_BASEPERIPH_PIC_ISA 0x01
324 #define PCIP_BASEPERIPH_PIC_EISA 0x02
325 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10
326 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20
327 #define PCIS_BASEPERIPH_DMA 0x01
328 #define PCIS_BASEPERIPH_TIMER 0x02
329 #define PCIS_BASEPERIPH_RTC 0x03
330 #define PCIS_BASEPERIPH_PCIHOT 0x04
331 #define PCIS_BASEPERIPH_SDHC 0x05
332 #define PCIS_BASEPERIPH_OTHER 0x80
334 #define PCIC_INPUTDEV 0x09
335 #define PCIS_INPUTDEV_KEYBOARD 0x00
336 #define PCIS_INPUTDEV_DIGITIZER 0x01
337 #define PCIS_INPUTDEV_MOUSE 0x02
338 #define PCIS_INPUTDEV_SCANNER 0x03
339 #define PCIS_INPUTDEV_GAMEPORT 0x04
340 #define PCIS_INPUTDEV_OTHER 0x80
342 #define PCIC_DOCKING 0x0a
343 #define PCIS_DOCKING_GENERIC 0x00
344 #define PCIS_DOCKING_OTHER 0x80
346 #define PCIC_PROCESSOR 0x0b
347 #define PCIS_PROCESSOR_386 0x00
348 #define PCIS_PROCESSOR_486 0x01
349 #define PCIS_PROCESSOR_PENTIUM 0x02
350 #define PCIS_PROCESSOR_ALPHA 0x10
351 #define PCIS_PROCESSOR_POWERPC 0x20
352 #define PCIS_PROCESSOR_MIPS 0x30
353 #define PCIS_PROCESSOR_COPROC 0x40
355 #define PCIC_SERIALBUS 0x0c
356 #define PCIS_SERIALBUS_FW 0x00
357 #define PCIS_SERIALBUS_ACCESS 0x01
358 #define PCIS_SERIALBUS_SSA 0x02
359 #define PCIS_SERIALBUS_USB 0x03
360 #define PCIP_SERIALBUS_USB_UHCI 0x00
361 #define PCIP_SERIALBUS_USB_OHCI 0x10
362 #define PCIP_SERIALBUS_USB_EHCI 0x20
363 #define PCIP_SERIALBUS_USB_DEVICE 0xfe
364 #define PCIS_SERIALBUS_FC 0x04
365 #define PCIS_SERIALBUS_SMBUS 0x05
366 #define PCIS_SERIALBUS_INFINIBAND 0x06
367 #define PCIS_SERIALBUS_IPMI 0x07
368 #define PCIP_SERIALBUS_IPMI_SMIC 0x00
369 #define PCIP_SERIALBUS_IPMI_KCS 0x01
370 #define PCIP_SERIALBUS_IPMI_BT 0x02
371 #define PCIS_SERIALBUS_SERCOS 0x08
372 #define PCIS_SERIALBUS_CANBUS 0x09
374 #define PCIC_WIRELESS 0x0d
375 #define PCIS_WIRELESS_IRDA 0x00
376 #define PCIS_WIRELESS_IR 0x01
377 #define PCIS_WIRELESS_RF 0x10
378 #define PCIS_WIRELESS_BLUETOOTH 0x11
379 #define PCIS_WIRELESS_BROADBAND 0x12
380 #define PCIS_WIRELESS_80211A 0x20
381 #define PCIS_WIRELESS_80211B 0x21
382 #define PCIS_WIRELESS_OTHER 0x80
384 #define PCIC_INTELLIIO 0x0e
385 #define PCIS_INTELLIIO_I2O 0x00
387 #define PCIC_SATCOM 0x0f
388 #define PCIS_SATCOM_TV 0x01
389 #define PCIS_SATCOM_AUDIO 0x02
390 #define PCIS_SATCOM_VOICE 0x03
391 #define PCIS_SATCOM_DATA 0x04
393 #define PCIC_CRYPTO 0x10
394 #define PCIS_CRYPTO_NETCOMP 0x00
395 #define PCIS_CRYPTO_ENTERTAIN 0x10
396 #define PCIS_CRYPTO_OTHER 0x80
398 #define PCIC_DASP 0x11
399 #define PCIS_DASP_DPIO 0x00
400 #define PCIS_DASP_PERFCNTRS 0x01
401 #define PCIS_DASP_COMM_SYNC 0x10
402 #define PCIS_DASP_MGMT_CARD 0x20
403 #define PCIS_DASP_OTHER 0x80
405 #define PCIC_OTHER 0xff
407 /* Bridge Control Values. */
408 #define PCIB_BCR_PERR_ENABLE 0x0001
409 #define PCIB_BCR_SERR_ENABLE 0x0002
410 #define PCIB_BCR_ISA_ENABLE 0x0004
411 #define PCIB_BCR_VGA_ENABLE 0x0008
412 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020
413 #define PCIB_BCR_SECBUS_RESET 0x0040
414 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080
415 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100
416 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200
417 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400
418 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800
420 /* PCI power manangement */
421 #define PCIR_POWER_CAP 0x2
422 #define PCIM_PCAP_SPEC 0x0007
423 #define PCIM_PCAP_PMEREQCLK 0x0008
424 #define PCIM_PCAP_PMEREQPWR 0x0010
425 #define PCIM_PCAP_DEVSPECINIT 0x0020
426 #define PCIM_PCAP_DYNCLOCK 0x0040
427 #define PCIM_PCAP_SECCLOCK 0x00c0
428 #define PCIM_PCAP_CLOCKMASK 0x00c0
429 #define PCIM_PCAP_REQFULLCLOCK 0x0100
430 #define PCIM_PCAP_D1SUPP 0x0200
431 #define PCIM_PCAP_D2SUPP 0x0400
432 #define PCIM_PCAP_D0PME 0x0800
433 #define PCIM_PCAP_D1PME 0x1000
434 #define PCIM_PCAP_D2PME 0x2000
435 #define PCIM_PCAP_D3PME_HOT 0x4000
436 #define PCIM_PCAP_D3PME_COLD 0x8000
438 #define PCIR_POWER_STATUS 0x4
439 #define PCIM_PSTAT_D0 0x0000
440 #define PCIM_PSTAT_D1 0x0001
441 #define PCIM_PSTAT_D2 0x0002
442 #define PCIM_PSTAT_D3 0x0003
443 #define PCIM_PSTAT_DMASK 0x0003
444 #define PCIM_PSTAT_REPENABLE 0x0010
445 #define PCIM_PSTAT_PMEENABLE 0x0100
446 #define PCIM_PSTAT_D0POWER 0x0000
447 #define PCIM_PSTAT_D1POWER 0x0200
448 #define PCIM_PSTAT_D2POWER 0x0400
449 #define PCIM_PSTAT_D3POWER 0x0600
450 #define PCIM_PSTAT_D0HEAT 0x0800
451 #define PCIM_PSTAT_D1HEAT 0x1000
452 #define PCIM_PSTAT_D2HEAT 0x1200
453 #define PCIM_PSTAT_D3HEAT 0x1400
454 #define PCIM_PSTAT_DATAUNKN 0x0000
455 #define PCIM_PSTAT_DATADIV10 0x2000
456 #define PCIM_PSTAT_DATADIV100 0x4000
457 #define PCIM_PSTAT_DATADIV1000 0x6000
458 #define PCIM_PSTAT_DATADIVMASK 0x6000
459 #define PCIM_PSTAT_PME 0x8000
461 #define PCIR_POWER_PMCSR 0x6
462 #define PCIM_PMCSR_DCLOCK 0x10
463 #define PCIM_PMCSR_B2SUPP 0x20
464 #define PCIM_BMCSR_B3SUPP 0x40
465 #define PCIM_BMCSR_BPCE 0x80
467 #define PCIR_POWER_DATA 0x7
469 /* VPD capability registers */
470 #define PCIR_VPD_ADDR 0x2
471 #define PCIR_VPD_DATA 0x4
473 /* PCI Message Signalled Interrupts (MSI) */
474 #define PCIR_MSI_CTRL 0x2
475 #define PCIM_MSICTRL_VECTOR 0x0100
476 #define PCIM_MSICTRL_64BIT 0x0080
477 #define PCIM_MSICTRL_MME_MASK 0x0070
478 #define PCIM_MSICTRL_MME_1 0x0000
479 #define PCIM_MSICTRL_MME_2 0x0010
480 #define PCIM_MSICTRL_MME_4 0x0020
481 #define PCIM_MSICTRL_MME_8 0x0030
482 #define PCIM_MSICTRL_MME_16 0x0040
483 #define PCIM_MSICTRL_MME_32 0x0050
484 #define PCIM_MSICTRL_MMC_MASK 0x000E
485 #define PCIM_MSICTRL_MMC_1 0x0000
486 #define PCIM_MSICTRL_MMC_2 0x0002
487 #define PCIM_MSICTRL_MMC_4 0x0004
488 #define PCIM_MSICTRL_MMC_8 0x0006
489 #define PCIM_MSICTRL_MMC_16 0x0008
490 #define PCIM_MSICTRL_MMC_32 0x000A
491 #define PCIM_MSICTRL_MSI_ENABLE 0x0001
492 #define PCIR_MSI_ADDR 0x4
493 #define PCIR_MSI_ADDR_HIGH 0x8
494 #define PCIR_MSI_DATA 0x8
495 #define PCIR_MSI_DATA_64BIT 0xc
496 #define PCIR_MSI_MASK 0x10
497 #define PCIR_MSI_PENDING 0x14
499 /* PCI-X definitions */
501 /* For header type 0 devices */
502 #define PCIXR_COMMAND 0x2
503 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
504 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
505 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
506 #define PCIXM_COMMAND_MAX_READ_512 0x0000
507 #define PCIXM_COMMAND_MAX_READ_1024 0x0004
508 #define PCIXM_COMMAND_MAX_READ_2048 0x0008
509 #define PCIXM_COMMAND_MAX_READ_4096 0x000c
510 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
511 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
512 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
513 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
514 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
515 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
516 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
517 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
518 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
519 #define PCIXM_COMMAND_VERSION 0x3000
520 #define PCIXR_STATUS 0x4
521 #define PCIXM_STATUS_DEVFN 0x000000FF
522 #define PCIXM_STATUS_BUS 0x0000FF00
523 #define PCIXM_STATUS_64BIT 0x00010000
524 #define PCIXM_STATUS_133CAP 0x00020000
525 #define PCIXM_STATUS_SC_DISCARDED 0x00040000
526 #define PCIXM_STATUS_UNEXP_SC 0x00080000
527 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000
528 #define PCIXM_STATUS_MAX_READ 0x00600000
529 #define PCIXM_STATUS_MAX_READ_512 0x00000000
530 #define PCIXM_STATUS_MAX_READ_1024 0x00200000
531 #define PCIXM_STATUS_MAX_READ_2048 0x00400000
532 #define PCIXM_STATUS_MAX_READ_4096 0x00600000
533 #define PCIXM_STATUS_MAX_SPLITS 0x03800000
534 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
535 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
536 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
537 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
538 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
539 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
540 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
541 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
542 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
543 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
544 #define PCIXM_STATUS_266CAP 0x40000000
545 #define PCIXM_STATUS_533CAP 0x80000000
547 /* For header type 1 devices (PCI-X bridges) */
548 #define PCIXR_SEC_STATUS 0x2
549 #define PCIXM_SEC_STATUS_64BIT 0x0001
550 #define PCIXM_SEC_STATUS_133CAP 0x0002
551 #define PCIXM_SEC_STATUS_SC_DISC 0x0004
552 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
553 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
554 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
555 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
556 #define PCIXM_SEC_STATUS_VERSION 0x3000
557 #define PCIXM_SEC_STATUS_266CAP 0x4000
558 #define PCIXM_SEC_STATUS_533CAP 0x8000
559 #define PCIXR_BRIDGE_STATUS 0x4
560 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
561 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
562 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
563 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
564 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
565 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
566 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
567 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
568 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
569 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
570 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
572 /* HT (HyperTransport) Capability definitions */
573 #define PCIR_HT_COMMAND 0x2
574 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */
575 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */
576 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */
577 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */
578 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */
579 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */
580 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */
581 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */
582 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */
583 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */
584 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */
585 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */
586 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */
587 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */
589 /* HT MSI Mapping Capability definitions. */
590 #define PCIM_HTCMD_MSI_ENABLE 0x0001
591 #define PCIM_HTCMD_MSI_FIXED 0x0002
592 #define PCIR_HTMSI_ADDRESS_LO 0x4
593 #define PCIR_HTMSI_ADDRESS_HI 0x8
595 /* PCI Vendor capability definitions */
596 #define PCIR_VENDOR_LENGTH 0x2
597 #define PCIR_VENDOR_DATA 0x3
599 /* PCI EHCI Debug Port definitions */
600 #define PCIR_DEBUG_PORT 0x2
601 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF
602 #define PCIM_DEBUG_PORT_BAR 0xe000
604 /* PCI-PCI Bridge Subvendor definitions */
605 #define PCIR_SUBVENDCAP_ID 0x4
607 /* MSI-X definitions */
608 #define PCIR_MSIX_CTRL 0x2
609 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000
610 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000
611 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF
612 #define PCIR_MSIX_TABLE 0x4
613 #define PCIR_MSIX_PBA 0x8
614 #define PCIM_MSIX_BIR_MASK 0x7
615 #define PCIM_MSIX_BIR_BAR_10 0
616 #define PCIM_MSIX_BIR_BAR_14 1
617 #define PCIM_MSIX_BIR_BAR_18 2
618 #define PCIM_MSIX_BIR_BAR_1C 3
619 #define PCIM_MSIX_BIR_BAR_20 4
620 #define PCIM_MSIX_BIR_BAR_24 5
621 #define PCIM_MSIX_VCTRL_MASK 0x1
624 * PCI Express definitions
626 * PCI Express base specification, REV. 1.0a
629 /* PCI Express capabilities, 16bits */
630 #define PCIER_CAPABILITY 0x2
631 #define PCIEM_CAP_VER_MASK 0x000f /* Version */
632 #define PCIEM_CAP_VER_1 0x0001
633 #define PCIEM_CAP_VER_2 0x0002
634 #define PCIEM_CAP_PORT_TYPE 0x00f0 /* Port type mask */
635 #define PCIEM_CAP_SLOT_IMPL 0x0100 /* Slot implemented,
636 * valid only for root port and
637 * switch downstream port
639 /* PCI Express port types */
640 #define PCIE_END_POINT 0x0000 /* Endpoint device */
641 #define PCIE_LEG_END_POINT 0x0010 /* Legacy endpoint device */
642 #define PCIE_ROOT_PORT 0x0040 /* Root port */
643 #define PCIE_UP_STREAM_PORT 0x0050 /* Switch upstream port */
644 #define PCIE_DOWN_STREAM_PORT 0x0060 /* Switch downstream port */
645 #define PCIE_PCIE2PCI_BRIDGE 0x0070 /* PCI Express to PCI/PCI-X bridge */
646 #define PCIE_PCI2PCIE_BRIDGE 0x0080 /* PCI/PCI-X to PCI Express bridge */
647 #define PCIE_ROOT_END_POINT 0x0090 /* Root Complex Integrated Endpoint */
648 #define PCIE_ROOT_EVT_COLL 0x00a0 /* Root Complex Event Collector */
650 /* PCI Express device control, 16bits */
651 #define PCIER_DEVCTRL 0x08
652 #define PCIEM_DEVCTL_MAX_READRQ_MASK 0x7000 /* Max read request size */
653 #define PCIEM_DEVCTL_MAX_READRQ_128 0x0000
654 #define PCIEM_DEVCTL_MAX_READRQ_256 0x1000
655 #define PCIEM_DEVCTL_MAX_READRQ_512 0x2000
656 #define PCIEM_DEVCTL_MAX_READRQ_1024 0x3000
657 #define PCIEM_DEVCTL_MAX_READRQ_2048 0x4000
658 #define PCIEM_DEVCTL_MAX_READRQ_4096 0x5000
660 /* PCI Express link capabilities, 32bits */
661 #define PCIER_LINKCAP 0x0c
662 #define PCIEM_LNKCAP_SPEED_MASK 0x000f /* Supported link speeds */
663 #define PCIEM_LNKCAP_SPEED_2_5 0x1 /* 2.5GT/s */
664 #define PCIEM_LNKCAP_SPEED_5 0x2 /* 5.0GT/s and 2.5GT/s */
665 #define PCIEM_LNKCAP_MAXW_MASK 0x03f0 /* Maximum link width */
666 #define PCIEM_LNKCAP_MAXW_X1 0x0010
667 #define PCIEM_LNKCAP_MAXW_X2 0x0020
668 #define PCIEM_LNKCAP_MAXW_X4 0x0040
669 #define PCIEM_LNKCAP_MAXW_X8 0x0080
670 #define PCIEM_LNKCAP_MAXW_X12 0x00c0
671 #define PCIEM_LNKCAP_MAXW_X16 0x0100
672 #define PCIEM_LNKCAP_MAXW_X32 0x0200
673 #define PCIEM_LNKCAP_ASPM_MASK 0x0c00 /* ASPM */
674 #define PCIEM_LNKCAP_ASPM_L0S 0x0400
675 #define PCIEM_LNKCAP_ASPM_L1 0x0c00
677 /* PCI Express link control, 32bits */
678 #define PCIER_LINKCTRL 0x10
679 #define PCIEM_LNKCTL_ASPM_MASK 0x3 /* ASPM */
680 #define PCIEM_LNKCTL_ASPM_DISABLE 0x0
681 #define PCIEM_LNKCTL_ASPM_L0S 0x1
682 #define PCIEM_LNKCTL_ASPM_L1 0x2
684 /* PCI Express slot capabilities, 32bits */
685 #define PCIER_SLOTCAP 0x14
686 #define PCIEM_SLTCAP_ATTEN_BTN 0x00000001 /* Attention button present */
687 #define PCIEM_SLTCAP_PWR_CTRL 0x00000002 /* Power controller present */
688 #define PCIEM_SLTCAP_MRL_SNS 0x00000004 /* MRL sensor present */
689 #define PCIEM_SLTCAP_ATTEN_IND 0x00000008 /* Attention indicator present */
690 #define PCIEM_SLTCAP_PWR_IND 0x00000010 /* Power indicator present */
691 #define PCIEM_SLTCAP_HP_SURP 0x00000020 /* Hot-Plug surprise */
692 #define PCIEM_SLTCAP_HP_CAP 0x00000040 /* Hot-Plug capable */
693 #define PCIEM_SLTCAP_HP_MASK 0x0000007f /* Hot-Plug related bits */
695 /* PCI Express slot control, 16bits */
696 #define PCIER_SLOTCTRL 0x18
697 #define PCIEM_SLTCTL_HPINTR_MASK 0x001f /* Hot-plug interrupts mask */
698 #define PCIEM_SLTCTL_HPINTR_EN 0x0020 /* Enable hot-plug interrupts */
699 /* PCI Expres hot-plug interrupts */
700 #define PCIE_HPINTR_ATTEN_BTN 0x0001 /* Attention button intr */
701 #define PCIE_HPINTR_PWR_FAULT 0x0002 /* Power fault intr */
702 #define PCIE_HPINTR_MRL_SNS 0x0004 /* MRL sensor changed intr */
703 #define PCIE_HPINTR_PRSN_DETECT 0x0008 /* Presence detect intr */
704 #define PCIE_HPINTR_CMD_COMPL 0x0010 /* Command completed intr */
706 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
708 #if defined(_KERNEL) && !defined(KLD_MODULE)
709 #include "opt_compat_oldpci.h"
714 #define PCI_ID_REG 0x00
715 #define PCI_COMMAND_STATUS_REG 0x04
716 #define PCI_COMMAND_IO_ENABLE 0x00000001
717 #define PCI_COMMAND_MEM_ENABLE 0x00000002
718 #define PCI_CLASS_REG 0x08
719 #define PCI_CLASS_MASK 0xff000000
720 #define PCI_SUBCLASS_MASK 0x00ff0000
721 #define PCI_REVISION_MASK 0x000000ff
722 #define PCI_CLASS_PREHISTORIC 0x00000000
723 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000
724 #define PCI_CLASS_MASS_STORAGE 0x01000000
725 #define PCI_CLASS_DISPLAY 0x03000000
726 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000
727 #define PCI_CLASS_BRIDGE 0x06000000
728 #define PCI_MAP_REG_START 0x10
729 #define PCI_MAP_REG_END 0x28
730 #define PCI_MAP_IO 0x00000001
731 #define PCI_INTERRUPT_REG 0x3c
733 #endif /* COMPAT_OLDPCI */
735 #endif /* _PCIREG_H_ */
nant's projects / dragonfly.git / blob