2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 * $FreeBSD: head/sys/dev/drm2/radeon/atombios_encoders.c 254885 2013-08-25 19:37:15Z dumbbell $
30 #include <drm/drm_crtc_helper.h>
31 #include <uapi_drm/radeon_drm.h>
33 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */
37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
42 if (rdev->family >= CHIP_R600)
43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
50 return backlight_level;
54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
59 if (rdev->family >= CHIP_R600)
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK);
68 if (rdev->family >= CHIP_R600)
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
77 struct drm_device *dev = radeon_encoder->base.dev;
78 struct radeon_device *rdev = dev->dev_private;
80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
83 return radeon_atom_get_backlight_level_from_reg(rdev);
87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
89 struct drm_encoder *encoder = &radeon_encoder->base;
90 struct drm_device *dev = radeon_encoder->base.dev;
91 struct radeon_device *rdev = dev->dev_private;
92 struct radeon_encoder_atom_dig *dig;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100 radeon_encoder->enc_priv) {
101 dig = radeon_encoder->enc_priv;
102 dig->backlight_level = level;
103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
105 switch (radeon_encoder->encoder_id) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109 if (dig->backlight_level == 0) {
110 args.ucAction = ATOM_LCD_BLOFF;
111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 args.ucAction = ATOM_LCD_BLON;
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
142 /* Convert brightness to hardware level */
143 if (bd->props.brightness < 0)
145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 level = RADEON_MAX_BL_LEVEL;
148 level = bd->props.brightness;
153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
155 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 struct radeon_encoder *radeon_encoder = pdata->encoder;
158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
165 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 struct radeon_encoder *radeon_encoder = pdata->encoder;
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
170 return radeon_atom_get_backlight_level_from_reg(rdev);
173 static const struct backlight_ops radeon_atom_backlight_ops = {
174 .get_brightness = radeon_atom_backlight_get_brightness,
175 .update_status = radeon_atom_backlight_update_status,
178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 struct drm_connector *drm_connector)
181 struct drm_device *dev = radeon_encoder->base.dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct backlight_device *bd;
184 struct backlight_properties props;
185 struct radeon_backlight_privdata *pdata;
186 struct radeon_encoder_atom_dig *dig;
190 if (!radeon_encoder->enc_priv)
193 if (!rdev->is_atom_bios)
196 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
199 pdata = kmalloc(sizeof(struct radeon_backlight_privdata),
200 DRM_MEM_DRIVER, M_WAITOK);
202 DRM_ERROR("Memory allocation failed\n");
206 memset(&props, 0, sizeof(props));
207 props.max_brightness = RADEON_MAX_BL_LEVEL;
208 props.type = BACKLIGHT_RAW;
209 snprintf(bl_name, sizeof(bl_name),
210 "radeon_bl%d", dev->primary->index);
211 bd = backlight_device_register(bl_name, &drm_connector->kdev,
212 pdata, &radeon_atom_backlight_ops, &props);
214 DRM_ERROR("Backlight registration failed\n");
218 pdata->encoder = radeon_encoder;
220 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
222 dig = radeon_encoder->enc_priv;
225 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
226 bd->props.power = FB_BLANK_UNBLANK;
227 backlight_update_status(bd);
229 DRM_INFO("radeon atom DIG backlight initialized\n");
234 drm_free(pdata, DRM_MEM_DRIVER);
238 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
240 struct drm_device *dev = radeon_encoder->base.dev;
241 struct radeon_device *rdev = dev->dev_private;
242 struct backlight_device *bd = NULL;
243 struct radeon_encoder_atom_dig *dig;
245 if (!radeon_encoder->enc_priv)
248 if (!rdev->is_atom_bios)
251 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
254 dig = radeon_encoder->enc_priv;
259 struct radeon_legacy_backlight_privdata *pdata;
261 pdata = bl_get_data(bd);
262 backlight_device_unregister(bd);
263 drm_free(pdata, DRM_MEM_DRIVER);
265 DRM_INFO("radeon atom LVDS backlight unloaded\n");
269 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
271 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
272 struct drm_connector *drm_connector)
276 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
283 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
285 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
286 switch (radeon_encoder->encoder_id) {
287 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
288 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
289 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
290 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
291 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
292 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
293 case ENCODER_OBJECT_ID_INTERNAL_DDI:
294 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
295 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
296 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
304 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
305 const struct drm_display_mode *mode,
306 struct drm_display_mode *adjusted_mode)
308 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
309 struct drm_device *dev = encoder->dev;
310 struct radeon_device *rdev = dev->dev_private;
312 /* set the active encoder to connector routing */
313 radeon_encoder_set_active_device(encoder);
314 drm_mode_set_crtcinfo(adjusted_mode, 0);
317 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
318 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
319 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
321 /* get the native mode for LVDS */
322 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
323 radeon_panel_mode_fixup(encoder, adjusted_mode);
325 /* get the native mode for TV */
326 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
327 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
329 if (tv_dac->tv_std == TV_STD_NTSC ||
330 tv_dac->tv_std == TV_STD_NTSC_J ||
331 tv_dac->tv_std == TV_STD_PAL_M)
332 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
334 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
338 if (ASIC_IS_DCE3(rdev) &&
339 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
340 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
341 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
342 radeon_dp_set_link_config(connector, adjusted_mode);
349 atombios_dac_setup(struct drm_encoder *encoder, int action)
351 struct drm_device *dev = encoder->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
354 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
356 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
358 memset(&args, 0, sizeof(args));
360 switch (radeon_encoder->encoder_id) {
361 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
362 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
363 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
365 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
366 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
367 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
371 args.ucAction = action;
373 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
374 args.ucDacStandard = ATOM_DAC1_PS2;
375 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
376 args.ucDacStandard = ATOM_DAC1_CV;
378 switch (dac_info->tv_std) {
381 case TV_STD_SCART_PAL:
384 args.ucDacStandard = ATOM_DAC1_PAL;
390 args.ucDacStandard = ATOM_DAC1_NTSC;
394 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
396 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
401 atombios_tv_setup(struct drm_encoder *encoder, int action)
403 struct drm_device *dev = encoder->dev;
404 struct radeon_device *rdev = dev->dev_private;
405 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
406 TV_ENCODER_CONTROL_PS_ALLOCATION args;
408 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
410 memset(&args, 0, sizeof(args));
412 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
414 args.sTVEncoder.ucAction = action;
416 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
417 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
419 switch (dac_info->tv_std) {
421 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
424 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
427 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
430 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
433 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
435 case TV_STD_SCART_PAL:
436 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
439 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
442 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
445 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
450 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
452 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
456 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
458 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
462 bpc = radeon_get_monitor_bpc(connector);
466 return PANEL_BPC_UNDEFINE;
468 return PANEL_6BIT_PER_COLOR;
471 return PANEL_8BIT_PER_COLOR;
473 return PANEL_10BIT_PER_COLOR;
475 return PANEL_12BIT_PER_COLOR;
477 return PANEL_16BIT_PER_COLOR;
482 union dvo_encoder_control {
483 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
484 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
485 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
489 atombios_dvo_setup(struct drm_encoder *encoder, int action)
491 struct drm_device *dev = encoder->dev;
492 struct radeon_device *rdev = dev->dev_private;
493 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
494 union dvo_encoder_control args;
495 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
498 memset(&args, 0, sizeof(args));
500 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
503 /* some R4xx chips have the wrong frev */
504 if (rdev->family <= CHIP_RV410)
512 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
514 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
515 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
517 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
521 args.dvo.sDVOEncoder.ucAction = action;
522 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
523 /* DFP1, CRT1, TV1 depending on the type of port */
524 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
526 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
527 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
531 args.dvo_v3.ucAction = action;
532 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
533 args.dvo_v3.ucDVOConfig = 0; /* XXX */
536 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
541 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
545 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
548 union lvds_encoder_control {
549 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
550 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
554 atombios_digital_setup(struct drm_encoder *encoder, int action)
556 struct drm_device *dev = encoder->dev;
557 struct radeon_device *rdev = dev->dev_private;
558 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
559 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
560 union lvds_encoder_control args;
562 int hdmi_detected = 0;
568 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
571 memset(&args, 0, sizeof(args));
573 switch (radeon_encoder->encoder_id) {
574 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
575 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
577 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
579 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
581 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
582 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
583 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
585 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
589 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
598 args.v1.ucAction = action;
600 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
601 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
602 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
603 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
604 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
605 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
606 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
609 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
610 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
611 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
612 /*if (pScrn->rgbBits == 8) */
613 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
619 args.v2.ucAction = action;
621 if (dig->coherent_mode)
622 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
625 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
626 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
627 args.v2.ucTruncate = 0;
628 args.v2.ucSpatial = 0;
629 args.v2.ucTemporal = 0;
631 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
632 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
633 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
634 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
635 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
636 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
637 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
639 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
640 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
641 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
642 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
643 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
644 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
648 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
649 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
650 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
654 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
659 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
663 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
667 atombios_get_encoder_mode(struct drm_encoder *encoder)
669 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
670 struct drm_connector *connector;
671 struct radeon_connector *radeon_connector;
672 struct radeon_connector_atom_dig *dig_connector;
674 /* dp bridges are always DP */
675 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
676 return ATOM_ENCODER_MODE_DP;
678 /* DVO is always DVO */
679 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
680 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
681 return ATOM_ENCODER_MODE_DVO;
683 connector = radeon_get_connector_for_encoder(encoder);
684 /* if we don't have an active device yet, just use one of
685 * the connectors tied to the encoder.
688 connector = radeon_get_connector_for_encoder_init(encoder);
689 radeon_connector = to_radeon_connector(connector);
691 switch (connector->connector_type) {
692 case DRM_MODE_CONNECTOR_DVII:
693 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
694 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
696 return ATOM_ENCODER_MODE_HDMI;
697 else if (radeon_connector->use_digital)
698 return ATOM_ENCODER_MODE_DVI;
700 return ATOM_ENCODER_MODE_CRT;
702 case DRM_MODE_CONNECTOR_DVID:
703 case DRM_MODE_CONNECTOR_HDMIA:
705 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
707 return ATOM_ENCODER_MODE_HDMI;
709 return ATOM_ENCODER_MODE_DVI;
711 case DRM_MODE_CONNECTOR_LVDS:
712 return ATOM_ENCODER_MODE_LVDS;
714 case DRM_MODE_CONNECTOR_DisplayPort:
715 dig_connector = radeon_connector->con_priv;
716 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
717 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
718 return ATOM_ENCODER_MODE_DP;
719 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
721 return ATOM_ENCODER_MODE_HDMI;
723 return ATOM_ENCODER_MODE_DVI;
725 case DRM_MODE_CONNECTOR_eDP:
726 return ATOM_ENCODER_MODE_DP;
727 case DRM_MODE_CONNECTOR_DVIA:
728 case DRM_MODE_CONNECTOR_VGA:
729 return ATOM_ENCODER_MODE_CRT;
731 case DRM_MODE_CONNECTOR_Composite:
732 case DRM_MODE_CONNECTOR_SVIDEO:
733 case DRM_MODE_CONNECTOR_9PinDIN:
735 return ATOM_ENCODER_MODE_TV;
736 /*return ATOM_ENCODER_MODE_CV;*/
742 * DIG Encoder/Transmitter Setup
745 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
746 * Supports up to 3 digital outputs
747 * - 2 DIG encoder blocks.
748 * DIG1 can drive UNIPHY link A or link B
749 * DIG2 can drive UNIPHY link B or LVTMA
752 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
753 * Supports up to 5 digital outputs
754 * - 2 DIG encoder blocks.
755 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
758 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
759 * Supports up to 6 digital outputs
760 * - 6 DIG encoder blocks.
761 * - DIG to PHY mapping is hardcoded
762 * DIG1 drives UNIPHY0 link A, A+B
763 * DIG2 drives UNIPHY0 link B
764 * DIG3 drives UNIPHY1 link A, A+B
765 * DIG4 drives UNIPHY1 link B
766 * DIG5 drives UNIPHY2 link A, A+B
767 * DIG6 drives UNIPHY2 link B
770 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
771 * Supports up to 6 digital outputs
772 * - 2 DIG encoder blocks.
774 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
776 * DIG1 drives UNIPHY0/1/2 link A
777 * DIG2 drives UNIPHY0/1/2 link B
780 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
782 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
783 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
784 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
785 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
788 union dig_encoder_control {
789 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
790 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
791 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
792 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
796 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
798 struct drm_device *dev = encoder->dev;
799 struct radeon_device *rdev = dev->dev_private;
800 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
801 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
802 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
803 union dig_encoder_control args;
807 int dp_lane_count = 0;
808 int hpd_id = RADEON_HPD_NONE;
811 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
812 struct radeon_connector_atom_dig *dig_connector =
813 radeon_connector->con_priv;
815 dp_clock = dig_connector->dp_clock;
816 dp_lane_count = dig_connector->dp_lane_count;
817 hpd_id = radeon_connector->hpd.hpd;
820 /* no dig encoder assigned */
821 if (dig->dig_encoder == -1)
824 memset(&args, 0, sizeof(args));
826 if (ASIC_IS_DCE4(rdev))
827 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
829 if (dig->dig_encoder)
830 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
832 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
835 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
842 args.v1.ucAction = action;
843 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
844 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
845 args.v3.ucPanelMode = panel_mode;
847 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
849 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
850 args.v1.ucLaneNum = dp_lane_count;
851 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
852 args.v1.ucLaneNum = 8;
854 args.v1.ucLaneNum = 4;
856 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
857 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
858 switch (radeon_encoder->encoder_id) {
859 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
860 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
862 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
863 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
864 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
866 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
867 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
871 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
873 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
877 args.v3.ucAction = action;
878 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
879 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
880 args.v3.ucPanelMode = panel_mode;
882 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
884 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
885 args.v3.ucLaneNum = dp_lane_count;
886 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
887 args.v3.ucLaneNum = 8;
889 args.v3.ucLaneNum = 4;
891 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
892 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
893 args.v3.acConfig.ucDigSel = dig->dig_encoder;
894 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
897 args.v4.ucAction = action;
898 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
899 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
900 args.v4.ucPanelMode = panel_mode;
902 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
904 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
905 args.v4.ucLaneNum = dp_lane_count;
906 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
907 args.v4.ucLaneNum = 8;
909 args.v4.ucLaneNum = 4;
911 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
912 if (dp_clock == 270000)
913 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
914 else if (dp_clock == 540000)
915 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
917 args.v4.acConfig.ucDigSel = dig->dig_encoder;
918 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
919 if (hpd_id == RADEON_HPD_NONE)
920 args.v4.ucHPD_ID = 0;
922 args.v4.ucHPD_ID = hpd_id + 1;
925 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
930 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
934 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
938 union dig_transmitter_control {
939 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
940 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
941 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
942 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
943 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
947 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
949 struct drm_device *dev = encoder->dev;
950 struct radeon_device *rdev = dev->dev_private;
951 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
952 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
953 struct drm_connector *connector;
954 union dig_transmitter_control args;
960 int dp_lane_count = 0;
961 int connector_object_id = 0;
962 int igp_lane_info = 0;
963 int dig_encoder = dig->dig_encoder;
964 int hpd_id = RADEON_HPD_NONE;
966 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
967 connector = radeon_get_connector_for_encoder_init(encoder);
968 /* just needed to avoid bailing in the encoder check. the encoder
969 * isn't used for init
973 connector = radeon_get_connector_for_encoder(encoder);
976 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
977 struct radeon_connector_atom_dig *dig_connector =
978 radeon_connector->con_priv;
980 hpd_id = radeon_connector->hpd.hpd;
981 dp_clock = dig_connector->dp_clock;
982 dp_lane_count = dig_connector->dp_lane_count;
983 connector_object_id =
984 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
985 igp_lane_info = dig_connector->igp_lane_info;
989 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
990 pll_id = radeon_crtc->pll_id;
993 /* no dig encoder assigned */
994 if (dig_encoder == -1)
997 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1000 memset(&args, 0, sizeof(args));
1002 switch (radeon_encoder->encoder_id) {
1003 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1004 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1006 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1007 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1008 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1009 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1011 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1012 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1016 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1023 args.v1.ucAction = action;
1024 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1025 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1026 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1027 args.v1.asMode.ucLaneSel = lane_num;
1028 args.v1.asMode.ucLaneSet = lane_set;
1031 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1032 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1033 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1035 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1038 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1041 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1043 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1045 if ((rdev->flags & RADEON_IS_IGP) &&
1046 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1048 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1049 if (igp_lane_info & 0x1)
1050 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1051 else if (igp_lane_info & 0x2)
1052 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1053 else if (igp_lane_info & 0x4)
1054 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1055 else if (igp_lane_info & 0x8)
1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1058 if (igp_lane_info & 0x3)
1059 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1060 else if (igp_lane_info & 0xc)
1061 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1066 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1068 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1071 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1072 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1073 if (dig->coherent_mode)
1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1075 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1076 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1080 args.v2.ucAction = action;
1081 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1082 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1083 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1084 args.v2.asMode.ucLaneSel = lane_num;
1085 args.v2.asMode.ucLaneSet = lane_set;
1088 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1089 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1090 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1092 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1095 args.v2.acConfig.ucEncoderSel = dig_encoder;
1097 args.v2.acConfig.ucLinkSel = 1;
1099 switch (radeon_encoder->encoder_id) {
1100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1101 args.v2.acConfig.ucTransmitterSel = 0;
1103 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1104 args.v2.acConfig.ucTransmitterSel = 1;
1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1107 args.v2.acConfig.ucTransmitterSel = 2;
1112 args.v2.acConfig.fCoherentMode = 1;
1113 args.v2.acConfig.fDPConnector = 1;
1114 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1115 if (dig->coherent_mode)
1116 args.v2.acConfig.fCoherentMode = 1;
1117 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1118 args.v2.acConfig.fDualLinkConnector = 1;
1122 args.v3.ucAction = action;
1123 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1124 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1125 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1126 args.v3.asMode.ucLaneSel = lane_num;
1127 args.v3.asMode.ucLaneSet = lane_set;
1130 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1131 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1132 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1134 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1138 args.v3.ucLaneNum = dp_lane_count;
1139 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1140 args.v3.ucLaneNum = 8;
1142 args.v3.ucLaneNum = 4;
1145 args.v3.acConfig.ucLinkSel = 1;
1146 if (dig_encoder & 1)
1147 args.v3.acConfig.ucEncoderSel = 1;
1149 /* Select the PLL for the PHY
1150 * DP PHY should be clocked from external src if there is
1153 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1154 if (is_dp && rdev->clock.dp_extclk)
1155 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1157 args.v3.acConfig.ucRefClkSource = pll_id;
1159 switch (radeon_encoder->encoder_id) {
1160 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1161 args.v3.acConfig.ucTransmitterSel = 0;
1163 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1164 args.v3.acConfig.ucTransmitterSel = 1;
1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1167 args.v3.acConfig.ucTransmitterSel = 2;
1172 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1173 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1174 if (dig->coherent_mode)
1175 args.v3.acConfig.fCoherentMode = 1;
1176 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1177 args.v3.acConfig.fDualLinkConnector = 1;
1181 args.v4.ucAction = action;
1182 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1183 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1184 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1185 args.v4.asMode.ucLaneSel = lane_num;
1186 args.v4.asMode.ucLaneSet = lane_set;
1189 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1190 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1191 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1193 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1197 args.v4.ucLaneNum = dp_lane_count;
1198 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1199 args.v4.ucLaneNum = 8;
1201 args.v4.ucLaneNum = 4;
1204 args.v4.acConfig.ucLinkSel = 1;
1205 if (dig_encoder & 1)
1206 args.v4.acConfig.ucEncoderSel = 1;
1208 /* Select the PLL for the PHY
1209 * DP PHY should be clocked from external src if there is
1212 /* On DCE5 DCPLL usually generates the DP ref clock */
1214 if (rdev->clock.dp_extclk)
1215 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1217 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1219 args.v4.acConfig.ucRefClkSource = pll_id;
1221 switch (radeon_encoder->encoder_id) {
1222 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1223 args.v4.acConfig.ucTransmitterSel = 0;
1225 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1226 args.v4.acConfig.ucTransmitterSel = 1;
1228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1229 args.v4.acConfig.ucTransmitterSel = 2;
1234 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1235 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1236 if (dig->coherent_mode)
1237 args.v4.acConfig.fCoherentMode = 1;
1238 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1239 args.v4.acConfig.fDualLinkConnector = 1;
1243 args.v5.ucAction = action;
1245 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1247 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1249 switch (radeon_encoder->encoder_id) {
1250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1252 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1254 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1258 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1260 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1264 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1266 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1270 args.v5.ucLaneNum = dp_lane_count;
1271 else if (radeon_encoder->pixel_clock > 165000)
1272 args.v5.ucLaneNum = 8;
1274 args.v5.ucLaneNum = 4;
1275 args.v5.ucConnObjId = connector_object_id;
1276 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1278 if (is_dp && rdev->clock.dp_extclk)
1279 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1281 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1284 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1285 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1286 if (dig->coherent_mode)
1287 args.v5.asConfig.ucCoherentMode = 1;
1289 if (hpd_id == RADEON_HPD_NONE)
1290 args.v5.asConfig.ucHPDSel = 0;
1292 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1293 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1294 args.v5.ucDPLaneSet = lane_set;
1297 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1302 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1306 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1310 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1312 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1313 struct drm_device *dev = radeon_connector->base.dev;
1314 struct radeon_device *rdev = dev->dev_private;
1315 union dig_transmitter_control args;
1316 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1319 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1322 if (!ASIC_IS_DCE4(rdev))
1325 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1326 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1329 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1332 memset(&args, 0, sizeof(args));
1334 args.v1.ucAction = action;
1336 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1338 /* wait for the panel to power up */
1339 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1342 for (i = 0; i < 300; i++) {
1343 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1353 union external_encoder_control {
1354 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1355 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1359 atombios_external_encoder_setup(struct drm_encoder *encoder,
1360 struct drm_encoder *ext_encoder,
1363 struct drm_device *dev = encoder->dev;
1364 struct radeon_device *rdev = dev->dev_private;
1365 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1366 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1367 union external_encoder_control args;
1368 struct drm_connector *connector;
1369 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1372 int dp_lane_count = 0;
1373 int connector_object_id = 0;
1374 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1376 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1377 connector = radeon_get_connector_for_encoder_init(encoder);
1379 connector = radeon_get_connector_for_encoder(encoder);
1382 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1383 struct radeon_connector_atom_dig *dig_connector =
1384 radeon_connector->con_priv;
1386 dp_clock = dig_connector->dp_clock;
1387 dp_lane_count = dig_connector->dp_lane_count;
1388 connector_object_id =
1389 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1392 memset(&args, 0, sizeof(args));
1394 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1399 /* no params on frev 1 */
1405 args.v1.sDigEncoder.ucAction = action;
1406 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1407 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1409 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1410 if (dp_clock == 270000)
1411 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1412 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1413 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1414 args.v1.sDigEncoder.ucLaneNum = 8;
1416 args.v1.sDigEncoder.ucLaneNum = 4;
1419 args.v3.sExtEncoder.ucAction = action;
1420 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1421 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1423 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1424 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1426 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1427 if (dp_clock == 270000)
1428 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1429 else if (dp_clock == 540000)
1430 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1431 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1432 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1433 args.v3.sExtEncoder.ucLaneNum = 8;
1435 args.v3.sExtEncoder.ucLaneNum = 4;
1437 case GRAPH_OBJECT_ENUM_ID1:
1438 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1440 case GRAPH_OBJECT_ENUM_ID2:
1441 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1443 case GRAPH_OBJECT_ENUM_ID3:
1444 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1447 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1450 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1455 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1458 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1462 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1464 struct drm_device *dev = encoder->dev;
1465 struct radeon_device *rdev = dev->dev_private;
1466 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1467 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1468 ENABLE_YUV_PS_ALLOCATION args;
1469 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1472 memset(&args, 0, sizeof(args));
1474 if (rdev->family >= CHIP_R600)
1475 reg = R600_BIOS_3_SCRATCH;
1477 reg = RADEON_BIOS_3_SCRATCH;
1479 /* XXX: fix up scratch reg handling */
1481 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1482 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1483 (radeon_crtc->crtc_id << 18)));
1484 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1485 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1490 args.ucEnable = ATOM_ENABLE;
1491 args.ucCRTC = radeon_crtc->crtc_id;
1493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1499 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1501 struct drm_device *dev = encoder->dev;
1502 struct radeon_device *rdev = dev->dev_private;
1503 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1504 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1507 memset(&args, 0, sizeof(args));
1509 switch (radeon_encoder->encoder_id) {
1510 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1511 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1512 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1514 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1515 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1516 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1517 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1519 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1520 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1522 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1523 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1524 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1526 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1528 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1529 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1530 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1531 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1532 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1533 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1535 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1537 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1538 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1539 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1540 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1541 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1542 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1544 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1551 case DRM_MODE_DPMS_ON:
1552 args.ucAction = ATOM_ENABLE;
1553 /* workaround for DVOOutputControl on some RS690 systems */
1554 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1555 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1556 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1557 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1558 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1560 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1561 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1562 args.ucAction = ATOM_LCD_BLON;
1563 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1566 case DRM_MODE_DPMS_STANDBY:
1567 case DRM_MODE_DPMS_SUSPEND:
1568 case DRM_MODE_DPMS_OFF:
1569 args.ucAction = ATOM_DISABLE;
1570 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1571 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1572 args.ucAction = ATOM_LCD_BLOFF;
1573 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1580 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1582 struct drm_device *dev = encoder->dev;
1583 struct radeon_device *rdev = dev->dev_private;
1584 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1585 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1586 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1587 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1588 struct radeon_connector *radeon_connector = NULL;
1589 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1592 radeon_connector = to_radeon_connector(connector);
1593 radeon_dig_connector = radeon_connector->con_priv;
1597 case DRM_MODE_DPMS_ON:
1598 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1600 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1602 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1604 /* setup and enable the encoder */
1605 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1606 atombios_dig_encoder_setup(encoder,
1607 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1610 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1611 atombios_external_encoder_setup(encoder, ext_encoder,
1612 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1614 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1615 } else if (ASIC_IS_DCE4(rdev)) {
1616 /* setup and enable the encoder */
1617 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1618 /* enable the transmitter */
1619 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1620 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1622 /* setup and enable the encoder and transmitter */
1623 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1624 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1625 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1626 /* some early dce3.2 boards have a bug in their transmitter control table */
1627 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
1628 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1630 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1631 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1632 atombios_set_edp_panel_power(connector,
1633 ATOM_TRANSMITTER_ACTION_POWER_ON);
1634 radeon_dig_connector->edp_on = true;
1636 radeon_dp_link_train(encoder, connector);
1637 if (ASIC_IS_DCE4(rdev))
1638 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1640 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1641 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1643 case DRM_MODE_DPMS_STANDBY:
1644 case DRM_MODE_DPMS_SUSPEND:
1645 case DRM_MODE_DPMS_OFF:
1646 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1647 /* disable the transmitter */
1648 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1649 } else if (ASIC_IS_DCE4(rdev)) {
1650 /* disable the transmitter */
1651 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1652 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1654 /* disable the encoder and transmitter */
1655 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1656 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1657 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1659 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1660 if (ASIC_IS_DCE4(rdev))
1661 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1662 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1663 atombios_set_edp_panel_power(connector,
1664 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1665 radeon_dig_connector->edp_on = false;
1668 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1669 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1675 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1676 struct drm_encoder *ext_encoder,
1679 struct drm_device *dev = encoder->dev;
1680 struct radeon_device *rdev = dev->dev_private;
1683 case DRM_MODE_DPMS_ON:
1685 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1686 atombios_external_encoder_setup(encoder, ext_encoder,
1687 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1688 atombios_external_encoder_setup(encoder, ext_encoder,
1689 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1691 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1693 case DRM_MODE_DPMS_STANDBY:
1694 case DRM_MODE_DPMS_SUSPEND:
1695 case DRM_MODE_DPMS_OFF:
1696 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1697 atombios_external_encoder_setup(encoder, ext_encoder,
1698 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1699 atombios_external_encoder_setup(encoder, ext_encoder,
1700 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1702 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1708 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1710 struct drm_device *dev = encoder->dev;
1711 struct radeon_device *rdev = dev->dev_private;
1712 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1713 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1715 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1716 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1717 radeon_encoder->active_device);
1718 switch (radeon_encoder->encoder_id) {
1719 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1720 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1721 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1722 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1723 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1724 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1725 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1726 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1727 radeon_atom_encoder_dpms_avivo(encoder, mode);
1729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1730 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1731 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1733 radeon_atom_encoder_dpms_dig(encoder, mode);
1735 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1736 if (ASIC_IS_DCE5(rdev)) {
1738 case DRM_MODE_DPMS_ON:
1739 atombios_dvo_setup(encoder, ATOM_ENABLE);
1741 case DRM_MODE_DPMS_STANDBY:
1742 case DRM_MODE_DPMS_SUSPEND:
1743 case DRM_MODE_DPMS_OFF:
1744 atombios_dvo_setup(encoder, ATOM_DISABLE);
1747 } else if (ASIC_IS_DCE3(rdev))
1748 radeon_atom_encoder_dpms_dig(encoder, mode);
1750 radeon_atom_encoder_dpms_avivo(encoder, mode);
1752 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1753 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1754 if (ASIC_IS_DCE5(rdev)) {
1756 case DRM_MODE_DPMS_ON:
1757 atombios_dac_setup(encoder, ATOM_ENABLE);
1759 case DRM_MODE_DPMS_STANDBY:
1760 case DRM_MODE_DPMS_SUSPEND:
1761 case DRM_MODE_DPMS_OFF:
1762 atombios_dac_setup(encoder, ATOM_DISABLE);
1766 radeon_atom_encoder_dpms_avivo(encoder, mode);
1773 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1775 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1779 union crtc_source_param {
1780 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1781 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1785 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1787 struct drm_device *dev = encoder->dev;
1788 struct radeon_device *rdev = dev->dev_private;
1789 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1790 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1791 union crtc_source_param args;
1792 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1794 struct radeon_encoder_atom_dig *dig;
1796 memset(&args, 0, sizeof(args));
1798 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1806 if (ASIC_IS_AVIVO(rdev))
1807 args.v1.ucCRTC = radeon_crtc->crtc_id;
1809 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1810 args.v1.ucCRTC = radeon_crtc->crtc_id;
1812 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1815 switch (radeon_encoder->encoder_id) {
1816 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1817 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1818 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1820 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1821 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1822 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1823 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1825 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1827 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1828 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1829 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1830 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1832 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1833 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1834 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1835 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1836 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1837 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1839 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1841 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1843 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1844 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1845 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1846 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1848 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1853 args.v2.ucCRTC = radeon_crtc->crtc_id;
1854 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1855 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1857 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1858 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1859 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1860 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1862 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1864 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1865 switch (radeon_encoder->encoder_id) {
1866 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1867 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1869 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1870 dig = radeon_encoder->enc_priv;
1871 switch (dig->dig_encoder) {
1873 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1876 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1879 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1882 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1885 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1888 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1893 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1895 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1896 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1897 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1898 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1899 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1901 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1903 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1904 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1905 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1906 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1907 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1909 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1916 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1920 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1922 /* update scratch regs with new routing */
1923 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1927 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1928 struct drm_display_mode *mode)
1930 struct drm_device *dev = encoder->dev;
1931 struct radeon_device *rdev = dev->dev_private;
1932 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1933 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1935 /* Funky macbooks */
1936 if ((dev->pci_device == 0x71C5) &&
1937 (dev->pci_subvendor == 0x106b) &&
1938 (dev->pci_subdevice == 0x0080)) {
1939 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1940 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1942 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1943 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1945 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1949 /* set scaler clears this on some chips */
1950 if (ASIC_IS_AVIVO(rdev) &&
1951 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1952 if (ASIC_IS_DCE4(rdev)) {
1953 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1954 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1955 EVERGREEN_INTERLEAVE_EN);
1957 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1959 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1960 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1961 AVIVO_D1MODE_INTERLEAVE_EN);
1963 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1968 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1970 struct drm_device *dev = encoder->dev;
1971 struct radeon_device *rdev = dev->dev_private;
1972 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1973 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1974 struct drm_encoder *test_encoder;
1975 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1976 uint32_t dig_enc_in_use = 0;
1978 if (ASIC_IS_DCE6(rdev)) {
1980 switch (radeon_encoder->encoder_id) {
1981 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1987 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2000 } else if (ASIC_IS_DCE4(rdev)) {
2002 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2003 /* ontario follows DCE4 */
2004 if (rdev->family == CHIP_PALM) {
2010 /* llano follows DCE3.2 */
2011 return radeon_crtc->crtc_id;
2013 switch (radeon_encoder->encoder_id) {
2014 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2036 /* on DCE32 and encoder can driver any block so just crtc id */
2037 if (ASIC_IS_DCE32(rdev)) {
2038 return radeon_crtc->crtc_id;
2041 /* on DCE3 - LVTMA can only be driven by DIGB */
2042 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2043 struct radeon_encoder *radeon_test_encoder;
2045 if (encoder == test_encoder)
2048 if (!radeon_encoder_is_digital(test_encoder))
2051 radeon_test_encoder = to_radeon_encoder(test_encoder);
2052 dig = radeon_test_encoder->enc_priv;
2054 if (dig->dig_encoder >= 0)
2055 dig_enc_in_use |= (1 << dig->dig_encoder);
2058 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2059 if (dig_enc_in_use & 0x2)
2060 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2063 if (!(dig_enc_in_use & 1))
2068 /* This only needs to be called once at startup */
2070 radeon_atom_encoder_init(struct radeon_device *rdev)
2072 struct drm_device *dev = rdev->ddev;
2073 struct drm_encoder *encoder;
2075 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2076 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2077 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2079 switch (radeon_encoder->encoder_id) {
2080 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2081 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2082 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2083 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2084 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2090 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2091 atombios_external_encoder_setup(encoder, ext_encoder,
2092 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2097 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2098 struct drm_display_mode *mode,
2099 struct drm_display_mode *adjusted_mode)
2101 struct drm_device *dev = encoder->dev;
2102 struct radeon_device *rdev = dev->dev_private;
2103 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2105 radeon_encoder->pixel_clock = adjusted_mode->clock;
2107 /* need to call this here rather than in prepare() since we need some crtc info */
2108 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2110 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2111 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2112 atombios_yuv_setup(encoder, true);
2114 atombios_yuv_setup(encoder, false);
2117 switch (radeon_encoder->encoder_id) {
2118 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2120 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2121 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2122 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2128 /* handled in dpms */
2130 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2131 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2132 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2133 atombios_dvo_setup(encoder, ATOM_ENABLE);
2135 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2136 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2137 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2139 atombios_dac_setup(encoder, ATOM_ENABLE);
2140 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2141 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2142 atombios_tv_setup(encoder, ATOM_ENABLE);
2144 atombios_tv_setup(encoder, ATOM_DISABLE);
2149 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2151 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2152 r600_hdmi_enable(encoder);
2153 if (ASIC_IS_DCE6(rdev))
2154 ; /* TODO (use pointers instead of if-s?) */
2155 else if (ASIC_IS_DCE4(rdev))
2156 evergreen_hdmi_setmode(encoder, adjusted_mode);
2158 r600_hdmi_setmode(encoder, adjusted_mode);
2163 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2165 struct drm_device *dev = encoder->dev;
2166 struct radeon_device *rdev = dev->dev_private;
2167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2168 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2170 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2171 ATOM_DEVICE_CV_SUPPORT |
2172 ATOM_DEVICE_CRT_SUPPORT)) {
2173 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2174 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2177 memset(&args, 0, sizeof(args));
2179 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2182 args.sDacload.ucMisc = 0;
2184 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2185 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2186 args.sDacload.ucDacType = ATOM_DAC_A;
2188 args.sDacload.ucDacType = ATOM_DAC_B;
2190 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2191 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2192 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2193 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2194 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2195 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2197 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2198 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2199 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2201 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2204 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2211 static enum drm_connector_status
2212 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2214 struct drm_device *dev = encoder->dev;
2215 struct radeon_device *rdev = dev->dev_private;
2216 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2217 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2218 uint32_t bios_0_scratch;
2220 if (!atombios_dac_load_detect(encoder, connector)) {
2221 DRM_DEBUG_KMS("detect returned false \n");
2222 return connector_status_unknown;
2225 if (rdev->family >= CHIP_R600)
2226 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2228 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2230 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2231 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2232 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2233 return connector_status_connected;
2235 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2236 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2237 return connector_status_connected;
2239 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2240 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2241 return connector_status_connected;
2243 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2244 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2245 return connector_status_connected; /* CTV */
2246 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2247 return connector_status_connected; /* STV */
2249 return connector_status_disconnected;
2252 static enum drm_connector_status
2253 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2255 struct drm_device *dev = encoder->dev;
2256 struct radeon_device *rdev = dev->dev_private;
2257 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2258 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2259 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2262 if (!ASIC_IS_DCE4(rdev))
2263 return connector_status_unknown;
2266 return connector_status_unknown;
2268 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2269 return connector_status_unknown;
2271 /* load detect on the dp bridge */
2272 atombios_external_encoder_setup(encoder, ext_encoder,
2273 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2275 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2277 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2278 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2279 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2280 return connector_status_connected;
2282 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2283 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2284 return connector_status_connected;
2286 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2287 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2288 return connector_status_connected;
2290 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2291 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2292 return connector_status_connected; /* CTV */
2293 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2294 return connector_status_connected; /* STV */
2296 return connector_status_disconnected;
2300 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2302 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2305 /* ddc_setup on the dp bridge */
2306 atombios_external_encoder_setup(encoder, ext_encoder,
2307 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2311 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2313 struct radeon_device *rdev = encoder->dev->dev_private;
2314 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2315 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2317 if ((radeon_encoder->active_device &
2318 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2319 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2320 ENCODER_OBJECT_ID_NONE)) {
2321 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2323 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2324 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2325 if (rdev->family >= CHIP_R600)
2326 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2328 /* RS600/690/740 have only 1 afmt block */
2329 dig->afmt = rdev->mode_info.afmt[0];
2334 radeon_atom_output_lock(encoder, true);
2337 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2339 /* select the clock/data port if it uses a router */
2340 if (radeon_connector->router.cd_valid)
2341 radeon_router_select_cd_port(radeon_connector);
2343 /* turn eDP panel on for mode set */
2344 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2345 atombios_set_edp_panel_power(connector,
2346 ATOM_TRANSMITTER_ACTION_POWER_ON);
2349 /* this is needed for the pll/ss setup to work correctly in some cases */
2350 atombios_set_encoder_crtc_source(encoder);
2353 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2355 /* need to call this here as we need the crtc set up */
2356 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2357 radeon_atom_output_lock(encoder, false);
2360 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2362 struct drm_device *dev = encoder->dev;
2363 struct radeon_device *rdev = dev->dev_private;
2364 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2365 struct radeon_encoder_atom_dig *dig;
2367 /* check for pre-DCE3 cards with shared encoders;
2368 * can't really use the links individually, so don't disable
2369 * the encoder if it's in use by another connector
2371 if (!ASIC_IS_DCE3(rdev)) {
2372 struct drm_encoder *other_encoder;
2373 struct radeon_encoder *other_radeon_encoder;
2375 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2376 other_radeon_encoder = to_radeon_encoder(other_encoder);
2377 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2378 drm_helper_encoder_in_use(other_encoder))
2383 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2385 switch (radeon_encoder->encoder_id) {
2386 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2387 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2388 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2389 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2390 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2392 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2393 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2394 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2395 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2396 /* handled in dpms */
2398 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2399 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2400 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2401 atombios_dvo_setup(encoder, ATOM_DISABLE);
2403 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2404 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2405 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2406 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2407 atombios_dac_setup(encoder, ATOM_DISABLE);
2408 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2409 atombios_tv_setup(encoder, ATOM_DISABLE);
2414 if (radeon_encoder_is_digital(encoder)) {
2415 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2416 r600_hdmi_disable(encoder);
2417 dig = radeon_encoder->enc_priv;
2418 dig->dig_encoder = -1;
2420 radeon_encoder->active_device = 0;
2423 /* these are handled by the primary encoders */
2424 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2429 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2435 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2436 struct drm_display_mode *mode,
2437 struct drm_display_mode *adjusted_mode)
2442 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2448 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2453 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2454 const struct drm_display_mode *mode,
2455 struct drm_display_mode *adjusted_mode)
2460 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2461 .dpms = radeon_atom_ext_dpms,
2462 .mode_fixup = radeon_atom_ext_mode_fixup,
2463 .prepare = radeon_atom_ext_prepare,
2464 .mode_set = radeon_atom_ext_mode_set,
2465 .commit = radeon_atom_ext_commit,
2466 .disable = radeon_atom_ext_disable,
2467 /* no detect for TMDS/LVDS yet */
2470 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2471 .dpms = radeon_atom_encoder_dpms,
2472 .mode_fixup = radeon_atom_mode_fixup,
2473 .prepare = radeon_atom_encoder_prepare,
2474 .mode_set = radeon_atom_encoder_mode_set,
2475 .commit = radeon_atom_encoder_commit,
2476 .disable = radeon_atom_encoder_disable,
2477 .detect = radeon_atom_dig_detect,
2480 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2481 .dpms = radeon_atom_encoder_dpms,
2482 .mode_fixup = radeon_atom_mode_fixup,
2483 .prepare = radeon_atom_encoder_prepare,
2484 .mode_set = radeon_atom_encoder_mode_set,
2485 .commit = radeon_atom_encoder_commit,
2486 .detect = radeon_atom_dac_detect,
2489 void radeon_enc_destroy(struct drm_encoder *encoder)
2491 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2492 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2493 radeon_atom_backlight_exit(radeon_encoder);
2494 drm_free(radeon_encoder->enc_priv, DRM_MEM_DRIVER);
2495 drm_encoder_cleanup(encoder);
2496 drm_free(radeon_encoder, DRM_MEM_DRIVER);
2499 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2500 .destroy = radeon_enc_destroy,
2503 static struct radeon_encoder_atom_dac *
2504 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2506 struct drm_device *dev = radeon_encoder->base.dev;
2507 struct radeon_device *rdev = dev->dev_private;
2508 struct radeon_encoder_atom_dac *dac = kmalloc(sizeof(struct radeon_encoder_atom_dac),
2515 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2519 static struct radeon_encoder_atom_dig *
2520 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2522 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2523 struct radeon_encoder_atom_dig *dig = kmalloc(sizeof(struct radeon_encoder_atom_dig),
2530 /* coherent mode by default */
2531 dig->coherent_mode = true;
2532 dig->dig_encoder = -1;
2534 if (encoder_enum == 2)
2543 radeon_add_atom_encoder(struct drm_device *dev,
2544 uint32_t encoder_enum,
2545 uint32_t supported_device,
2548 struct radeon_device *rdev = dev->dev_private;
2549 struct drm_encoder *encoder;
2550 struct radeon_encoder *radeon_encoder;
2552 /* see if we already added it */
2553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2554 radeon_encoder = to_radeon_encoder(encoder);
2555 if (radeon_encoder->encoder_enum == encoder_enum) {
2556 radeon_encoder->devices |= supported_device;
2563 radeon_encoder = kmalloc(sizeof(struct radeon_encoder),
2564 DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
2565 if (!radeon_encoder)
2568 encoder = &radeon_encoder->base;
2569 switch (rdev->num_crtc) {
2571 encoder->possible_crtcs = 0x1;
2575 encoder->possible_crtcs = 0x3;
2578 encoder->possible_crtcs = 0xf;
2581 encoder->possible_crtcs = 0x3f;
2585 radeon_encoder->enc_priv = NULL;
2587 radeon_encoder->encoder_enum = encoder_enum;
2588 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2589 radeon_encoder->devices = supported_device;
2590 radeon_encoder->rmx_type = RMX_OFF;
2591 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2592 radeon_encoder->is_ext_encoder = false;
2593 radeon_encoder->caps = caps;
2595 switch (radeon_encoder->encoder_id) {
2596 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2597 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2598 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2599 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2600 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2601 radeon_encoder->rmx_type = RMX_FULL;
2602 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2603 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2605 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2606 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2608 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2610 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2611 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2612 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2613 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2615 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2616 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2617 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2618 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2619 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2620 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2622 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2623 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2624 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2625 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2626 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2629 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2630 radeon_encoder->rmx_type = RMX_FULL;
2631 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2632 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2633 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2634 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2635 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2637 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2638 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2640 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2642 case ENCODER_OBJECT_ID_SI170B:
2643 case ENCODER_OBJECT_ID_CH7303:
2644 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2645 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2646 case ENCODER_OBJECT_ID_TITFP513:
2647 case ENCODER_OBJECT_ID_VT1623:
2648 case ENCODER_OBJECT_ID_HDMI_SI1930:
2649 case ENCODER_OBJECT_ID_TRAVIS:
2650 case ENCODER_OBJECT_ID_NUTMEG:
2651 /* these are handled by the primary encoders */
2652 radeon_encoder->is_ext_encoder = true;
2653 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2654 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2655 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2656 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2658 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2659 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);