2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
5 * ISA-specific part separated from:
6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted prodived that the follwoing conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notive, this list of conditions and the following disclainer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials prodided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Comtrol Corporation.
19 * 4. The name of Comtrol Corporation may not be used to endorse or
20 * promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/dev/rp/rp_isa.c,v 1.3.2.1 2002/06/18 03:11:46 obrien Exp $
36 * $DragonFly: src/sys/dev/serial/rp/rp_isa.c,v 1.7 2006/10/25 20:56:02 dillon Exp $
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/fcntl.h>
42 #include <sys/malloc.h>
45 #include <sys/kernel.h>
53 #include <bus/isa/isavar.h>
55 /* ISA-specific part of CONTROLLER_t */
56 struct ISACONTROLLER_T {
57 int MBaseIO; /* rid of the Mudbac controller for this controller */
58 int MReg0IO; /* offset0 of the Mudbac controller for this controller */
59 int MReg1IO; /* offset1 of the Mudbac controller for this controller */
60 int MReg2IO; /* offset2 of the Mudbac controller for this controller */
61 int MReg3IO; /* offset3 of the Mudbac controller for this controller */
65 typedef struct ISACONTROLLER_T ISACONTROLLER_t;
67 #define ISACTL(ctlp) ((ISACONTROLLER_t *)((ctlp)->bus_ctlp))
69 /***************************************************************************
70 Function: sControllerEOI
71 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
72 Call: sControllerEOI(MudbacCtlP,CtlP)
73 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
74 CONTROLLER_T *CtlP; Ptr to controller structure
76 #define sControllerEOI(MudbacCtlP,CtlP) \
77 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg2IO,ISACTL(CtlP)->MReg2 | INT_STROB)
79 /***************************************************************************
81 Purpose: Disable I/O access to an AIOP
82 Call: sDisAiop(MudbacCtlP,CtlP)
83 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
84 CONTROLLER_T *CtlP; Ptr to controller structure
85 int AiopNum; Number of AIOP on controller
87 #define sDisAiop(MudbacCtlP,CtlP,AIOPNUM) \
89 ISACTL(CtlP)->MReg3 &= rp_sBitMapClrTbl[AIOPNUM]; \
90 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3); \
93 /***************************************************************************
95 Purpose: Enable I/O access to an AIOP
96 Call: sEnAiop(MudbacCtlP,CtlP)
97 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
98 CONTROLLER_T *CtlP; Ptr to controller structure
99 int AiopNum; Number of AIOP on controller
101 #define sEnAiop(MudbacCtlP,CtlP,AIOPNUM) \
103 ISACTL(CtlP)->MReg3 |= rp_sBitMapSetTbl[AIOPNUM]; \
104 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3); \
107 /***************************************************************************
108 Function: sGetControllerIntStatus
109 Purpose: Get the controller interrupt status
110 Call: sGetControllerIntStatus(MudbacCtlP,CtlP)
111 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
112 CONTROLLER_T *CtlP; Ptr to controller structure
113 Return: Byte_t: The controller interrupt status in the lower 4
114 bits. Bits 0 through 3 represent AIOP's 0
115 through 3 respectively. If a bit is set that
116 AIOP is interrupting. Bits 4 through 7 will
119 #define sGetControllerIntStatus(MudbacCtlP,CtlP) \
120 (rp_readio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg1IO) & 0x0f)
122 static devclass_t rp_devclass;
123 static CONTROLLER_t *rp_controller;
124 static int rp_nisadevs;
126 static int rp_probe(device_t dev);
127 static int rp_attach(device_t dev);
128 static void rp_isareleaseresource(CONTROLLER_t *ctlp);
129 static int sInitController(CONTROLLER_T *CtlP,
130 CONTROLLER_T *MudbacCtlP,
135 static rp_aiop2rid_t rp_isa_aiop2rid;
136 static rp_aiop2off_t rp_isa_aiop2off;
137 static rp_ctlmask_t rp_isa_ctlmask;
140 rp_probe(device_t dev)
143 CONTROLLER_t *controller;
149 * We have no PnP RocketPort cards.
150 * (At least according to LINT)
152 if (isa_get_logicalid(dev) != 0)
155 /* We need IO port resource to configure an ISA device. */
156 if (bus_get_resource_count(dev, SYS_RES_IOPORT, 0) == 0)
159 unit = device_get_unit(dev);
161 device_printf(dev, "rpprobe: unit number %d invalid.\n", unit);
164 device_printf(dev, "probing for RocketPort(ISA) unit %d.\n", unit);
166 ctlp = device_get_softc(dev);
167 bzero(ctlp, sizeof(*ctlp));
169 ctlp->aiop2rid = rp_isa_aiop2rid;
170 ctlp->aiop2off = rp_isa_aiop2off;
171 ctlp->ctlmask = rp_isa_ctlmask;
173 /* The IO ports of AIOPs for an ISA controller are discrete. */
175 ctlp->io_rid = kmalloc(sizeof(*(ctlp->io_rid)) * MAX_AIOPS_PER_BOARD,
176 M_DEVBUF, M_WAITOK | M_ZERO);
177 ctlp->io = kmalloc(sizeof(*(ctlp->io)) * MAX_AIOPS_PER_BOARD,
178 M_DEVBUF, M_WAITOK | M_ZERO);
180 ctlp->bus_ctlp = kmalloc(sizeof(ISACONTROLLER_t) * 1,
181 M_DEVBUF, M_WAITOK | M_ZERO);
184 if (rp_controller != NULL) {
185 controller = rp_controller;
186 ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 0x40, RF_ACTIVE);
188 controller = rp_controller = ctlp;
189 ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 0x44, RF_ACTIVE);
191 if (ctlp->io[0] == NULL) {
192 device_printf(dev, "rp_attach: Resource not available.\n");
197 num_aiops = sInitController(ctlp,
199 MAX_AIOPS_PER_BOARD, 0,
201 if (num_aiops <= 0) {
202 device_printf(dev, "board%d init failed.\n", unit);
207 if (rp_controller == NULL)
208 rp_controller = controller;
211 device_set_desc(dev, "RocketPort ISA");
216 rp_isareleaseresource(ctlp);
222 rp_attach(device_t dev)
225 int num_ports, num_aiops;
230 unit = device_get_unit(dev);
232 ctlp = device_get_softc(dev);
235 num_aiops = sInitController(ctlp,
237 MAX_AIOPS_PER_BOARD, 0,
240 num_aiops = ctlp->NumAiop;
244 for(aiop=0; aiop < num_aiops; aiop++) {
245 sResetAiopByNum(ctlp, aiop);
246 sEnAiop(rp_controller, ctlp, aiop);
247 num_ports += sGetAiopNumChan(ctlp, aiop);
250 retval = rp_attachcommon(ctlp, num_aiops, num_ports);
257 rp_isareleaseresource(ctlp);
263 rp_isareleaseresource(CONTROLLER_t *ctlp)
267 rp_releaseresource(ctlp);
269 if (ctlp == rp_controller)
270 rp_controller = NULL;
271 if (ctlp->io != NULL) {
272 for (i = 0 ; i < MAX_AIOPS_PER_BOARD ; i++)
273 if (ctlp->io[i] != NULL)
274 bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[i], ctlp->io[i]);
275 kfree(ctlp->io, M_DEVBUF);
277 if (ctlp->io_rid != NULL)
278 kfree(ctlp->io_rid, M_DEVBUF);
279 if (rp_controller != NULL && rp_controller->io[ISACTL(ctlp)->MBaseIO] != NULL) {
280 bus_release_resource(rp_controller->dev, SYS_RES_IOPORT, rp_controller->io_rid[ISACTL(ctlp)->MBaseIO], rp_controller->io[ISACTL(ctlp)->MBaseIO]);
281 rp_controller->io[ISACTL(ctlp)->MBaseIO] = NULL;
282 rp_controller->io_rid[ISACTL(ctlp)->MBaseIO] = 0;
284 if (ctlp->bus_ctlp != NULL)
285 kfree(ctlp->bus_ctlp, M_DEVBUF);
288 /***************************************************************************
289 Function: sInitController
290 Purpose: Initialization of controller global registers and controller
292 Call: sInitController(CtlP,MudbacCtlP,AiopNum,
293 IRQNum,Frequency,PeriodicOnly)
294 CONTROLLER_T *CtlP; Ptr to controller structure
295 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
296 int AiopNum; Number of Aiops
297 int IRQNum; Interrupt Request number. Can be any of the following:
298 0: Disable global interrupts
307 Byte_t Frequency: A flag identifying the frequency
308 of the periodic interrupt, can be any one of the following:
309 FREQ_DIS - periodic interrupt disabled
310 FREQ_137HZ - 137 Hertz
316 If IRQNum is set to 0 the Frequency parameter is
317 overidden, it is forced to a value of FREQ_DIS.
318 int PeriodicOnly: TRUE if all interrupts except the periodic
319 interrupt are to be blocked.
320 FALSE is both the periodic interrupt and
321 other channel interrupts are allowed.
322 If IRQNum is set to 0 the PeriodicOnly parameter is
323 overidden, it is forced to a value of FALSE.
324 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
325 initialization failed.
328 If periodic interrupts are to be disabled but AIOP interrupts
329 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE.
331 If interrupts are to be completely disabled set IRQNum to 0.
333 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an
336 This function performs initialization of global interrupt modes,
337 but it does not actually enable global interrupts. To enable
338 and disable global interrupts use functions sEnGlobalInt() and
339 sDisGlobalInt(). Enabling of global interrupts is normally not
340 done until all other initializations are complete.
342 Even if interrupts are globally enabled, they must also be
343 individually enabled for each channel that is to generate
346 Warnings: No range checking on any of the parameters is done.
348 No context switches are allowed while executing this function.
350 After this function all AIOPs on the controller are disabled,
351 they can be enabled with sEnAiop().
354 sInitController( CONTROLLER_T *CtlP,
355 CONTROLLER_T *MudbacCtlP,
362 int ctl_base, aiop_base, aiop_size;
364 CtlP->CtlID = CTLID_0001; /* controller release 1 */
366 ISACTL(CtlP)->MBaseIO = rp_nisadevs;
367 if (MudbacCtlP->io[ISACTL(CtlP)->MBaseIO] != NULL) {
368 ISACTL(CtlP)->MReg0IO = 0x40 + 0;
369 ISACTL(CtlP)->MReg1IO = 0x40 + 1;
370 ISACTL(CtlP)->MReg2IO = 0x40 + 2;
371 ISACTL(CtlP)->MReg3IO = 0x40 + 3;
373 MudbacCtlP->io_rid[ISACTL(CtlP)->MBaseIO] = ISACTL(CtlP)->MBaseIO;
374 ctl_base = rman_get_start(MudbacCtlP->io[0]) + 0x40 + 0x400 * rp_nisadevs;
375 MudbacCtlP->io[ISACTL(CtlP)->MBaseIO] = bus_alloc_resource(MudbacCtlP->dev, SYS_RES_IOPORT, &CtlP->io_rid[ISACTL(CtlP)->MBaseIO], ctl_base, ctl_base + 3, 4, RF_ACTIVE);
376 ISACTL(CtlP)->MReg0IO = 0;
377 ISACTL(CtlP)->MReg1IO = 1;
378 ISACTL(CtlP)->MReg2IO = 2;
379 ISACTL(CtlP)->MReg3IO = 3;
382 ISACTL(CtlP)->MReg2 = 0; /* interrupt disable */
383 ISACTL(CtlP)->MReg3 = 0; /* no periodic interrupts */
385 if(sIRQMap[IRQNum] == 0) /* interrupts globally disabled */
387 ISACTL(CtlP)->MReg2 = 0; /* interrupt disable */
388 ISACTL(CtlP)->MReg3 = 0; /* no periodic interrupts */
392 ISACTL(CtlP)->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
393 ISACTL(CtlP)->MReg3 = Frequency; /* set frequency */
394 if(PeriodicOnly) /* periodic interrupt only */
396 ISACTL(CtlP)->MReg3 |= PERIODIC_ONLY;
400 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg2IO,ISACTL(CtlP)->MReg2);
401 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3);
402 sControllerEOI(MudbacCtlP,CtlP); /* clear EOI if warm init */
406 for(i=0; i < AiopNum; i++)
408 if (CtlP->io[i] == NULL) {
410 aiop_base = rman_get_start(CtlP->io[0]) + 0x400 * i;
411 if (rp_nisadevs == 0)
415 CtlP->io[i] = bus_alloc_resource(CtlP->dev, SYS_RES_IOPORT, &CtlP->io_rid[i], aiop_base, aiop_base + aiop_size - 1, aiop_size, RF_ACTIVE);
417 aiop_base = rman_get_start(CtlP->io[i]);
418 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,
419 ISACTL(CtlP)->MReg2IO,
420 ISACTL(CtlP)->MReg2 | (i & 0x03)); /* AIOP index */
421 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,
422 ISACTL(CtlP)->MReg0IO,
423 (Byte_t)(aiop_base >> 6)); /* set up AIOP I/O in MUDBAC */
424 sEnAiop(MudbacCtlP,CtlP,i); /* enable the AIOP */
426 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
427 if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
429 sDisAiop(MudbacCtlP,CtlP,i); /* disable AIOP */
430 bus_release_resource(CtlP->dev, SYS_RES_IOPORT, CtlP->io_rid[i], CtlP->io[i]);
432 break; /* done looking for AIOPs */
435 CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i); /* num channels in AIOP */
436 rp_writeaiop2(CtlP,i,_INDX_ADDR,_CLK_PRE); /* clock prescaler */
437 rp_writeaiop1(CtlP,i,_INDX_DATA,CLOCK_PRESC);
438 CtlP->NumAiop++; /* bump count of AIOPs */
439 sDisAiop(MudbacCtlP,CtlP,i); /* disable AIOP */
442 if(CtlP->NumAiop == 0)
445 return(CtlP->NumAiop);
450 * Maps (aiop, offset) to rid.
453 rp_isa_aiop2rid(int aiop, int offset)
455 /* rid equals to aiop for an ISA controller. */
461 * Maps (aiop, offset) to the offset of resource.
464 rp_isa_aiop2off(int aiop, int offset)
466 /* Each aiop has its own resource. */
470 /* Read the int status for an ISA controller. */
472 rp_isa_ctlmask(CONTROLLER_t *ctlp)
474 return sGetControllerIntStatus(rp_controller,ctlp);
477 static device_method_t rp_methods[] = {
478 /* Device interface */
479 DEVMETHOD(device_probe, rp_probe),
480 DEVMETHOD(device_attach, rp_attach),
485 static driver_t rp_driver = {
488 sizeof(CONTROLLER_t),
492 * rp can be attached to an isa bus.
494 DRIVER_MODULE(rp, isa, rp_driver, rp_devclass, 0, 0);