sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  * $DragonFly: src/sys/dev/netif/bce/if_bce.c,v 1.21 2008/11/19 13:57:49 sephe Exp $
  32  */
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5708C B1, B2
  38  *
  39  * The following controllers are not supported by this driver:
  40  *   BCM5706C A0, A1
  41  *   BCM5706S A0, A1, A2, A3
  42  *   BCM5708C A0, B0
  43  *   BCM5708S A0, B0, B1, B2
  44  */
  45
  46 #include "opt_bce.h"
  47 #include "opt_polling.h"
  48
  49 #include <sys/param.h>
  50 #include <sys/bus.h>
  51 #include <sys/endian.h>
  52 #include <sys/kernel.h>
  53 #include <sys/interrupt.h>
  54 #include <sys/mbuf.h>
  55 #include <sys/malloc.h>
  56 #include <sys/queue.h>
  57 #ifdef BCE_DEBUG
  58 #include <sys/random.h>
  59 #endif
  60 #include <sys/rman.h>
  61 #include <sys/serialize.h>
  62 #include <sys/socket.h>
  63 #include <sys/sockio.h>
  64 #include <sys/sysctl.h>
  65
  66 #include <net/bpf.h>
  67 #include <net/ethernet.h>
  68 #include <net/if.h>
  69 #include <net/if_arp.h>
  70 #include <net/if_dl.h>
  71 #include <net/if_media.h>
  72 #include <net/if_types.h>
  73 #include <net/ifq_var.h>
  74 #include <net/vlan/if_vlan_var.h>
  75 #include <net/vlan/if_vlan_ether.h>
  76
  77 #include <dev/netif/mii_layer/mii.h>
  78 #include <dev/netif/mii_layer/miivar.h>
  79
  80 #include <bus/pci/pcireg.h>
  81 #include <bus/pci/pcivar.h>
  82
  83 #include "miibus_if.h"
  84
  85 #include <dev/netif/bce/if_bcereg.h>
  86 #include <dev/netif/bce/if_bcefw.h>
  87
  88 /****************************************************************************/
  89 /* BCE Debug Options                                                        */
  90 /****************************************************************************/
  91 #ifdef BCE_DEBUG
  92
  93 static uint32_t bce_debug = BCE_WARN;
  94
  95 /*
  96  *          0 = Never
  97  *          1 = 1 in 2,147,483,648
  98  *        256 = 1 in     8,388,608
  99  *       2048 = 1 in     1,048,576
 100  *      65536 = 1 in        32,768
 101  *    1048576 = 1 in         2,048
 102  *  268435456 = 1 in             8
 103  *  536870912 = 1 in             4
 104  * 1073741824 = 1 in             2
 105  *
 106  * bce_debug_l2fhdr_status_check:
 107  *     How often the l2_fhdr frame error check will fail.
 108  *
 109  * bce_debug_unexpected_attention:
 110  *     How often the unexpected attention check will fail.
 111  *
 112  * bce_debug_mbuf_allocation_failure:
 113  *     How often to simulate an mbuf allocation failure.
 114  *
 115  * bce_debug_dma_map_addr_failure:
 116  *     How often to simulate a DMA mapping failure.
 117  *
 118  * bce_debug_bootcode_running_failure:
 119  *     How often to simulate a bootcode failure.
 120  */
 121 static int      bce_debug_l2fhdr_status_check = 0;
 122 static int      bce_debug_unexpected_attention = 0;
 123 static int      bce_debug_mbuf_allocation_failure = 0;
 124 static int      bce_debug_dma_map_addr_failure = 0;
 125 static int      bce_debug_bootcode_running_failure = 0;
 126
 127 #endif  /* BCE_DEBUG */
 128
 129
 130 /****************************************************************************/
 131 /* PCI Device ID Table                                                      */
 132 /*                                                                          */
 133 /* Used by bce_probe() to identify the devices supported by this driver.    */
 134 /****************************************************************************/
 135 #define BCE_DEVDESC_MAX         64
 136
 137 static struct bce_type bce_devs[] = {
 138         /* BCM5706C Controllers and OEM boards. */
 139         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 140                 "HP NC370T Multifunction Gigabit Server Adapter" },
 141         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 142                 "HP NC370i Multifunction Gigabit Server Adapter" },
 143         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 144                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 145
 146         /* BCM5706S controllers and OEM boards. */
 147         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 148                 "HP NC370F Multifunction Gigabit Server Adapter" },
 149         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 150                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 151
 152         /* BCM5708C controllers and OEM boards. */
 153         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 154                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 155
 156         /* BCM5708S controllers and OEM boards. */
 157         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 158                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 159         { 0, 0, 0, 0, NULL }
 160 };
 161
 162
 163 /****************************************************************************/
 164 /* Supported Flash NVRAM device data.                                       */
 165 /****************************************************************************/
 166 static const struct flash_spec flash_table[] =
 167 {
 168         /* Slow EEPROM */
 169         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 170          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 171          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 172          "EEPROM - slow"},
 173         /* Expansion entry 0001 */
 174         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 175          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 176          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 177          "Entry 0001"},
 178         /* Saifun SA25F010 (non-buffered flash) */
 179         /* strap, cfg1, & write1 need updates */
 180         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 181          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 182          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 183          "Non-buffered flash (128kB)"},
 184         /* Saifun SA25F020 (non-buffered flash) */
 185         /* strap, cfg1, & write1 need updates */
 186         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 187          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 188          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 189          "Non-buffered flash (256kB)"},
 190         /* Expansion entry 0100 */
 191         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 192          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 193          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 194          "Entry 0100"},
 195         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 196         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 197          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 198          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 199          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 200         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 201         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 202          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 203          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 204          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 205         /* Saifun SA25F005 (non-buffered flash) */
 206         /* strap, cfg1, & write1 need updates */
 207         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 208          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 209          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 210          "Non-buffered flash (64kB)"},
 211         /* Fast EEPROM */
 212         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 213          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 214          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 215          "EEPROM - fast"},
 216         /* Expansion entry 1001 */
 217         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 218          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 219          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 220          "Entry 1001"},
 221         /* Expansion entry 1010 */
 222         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 223          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 224          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 225          "Entry 1010"},
 226         /* ATMEL AT45DB011B (buffered flash) */
 227         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 228          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 229          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 230          "Buffered flash (128kB)"},
 231         /* Expansion entry 1100 */
 232         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 233          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 234          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 235          "Entry 1100"},
 236         /* Expansion entry 1101 */
 237         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 238          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 239          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 240          "Entry 1101"},
 241         /* Ateml Expansion entry 1110 */
 242         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 243          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 244          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 245          "Entry 1110 (Atmel)"},
 246         /* ATMEL AT45DB021B (buffered flash) */
 247         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 248          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 249          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 250          "Buffered flash (256kB)"},
 251 };
 252
 253
 254 /****************************************************************************/
 255 /* DragonFly device entry points.                                           */
 256 /****************************************************************************/
 257 static int      bce_probe(device_t);
 258 static int      bce_attach(device_t);
 259 static int      bce_detach(device_t);
 260 static void     bce_shutdown(device_t);
 261
 262 /****************************************************************************/
 263 /* BCE Debug Data Structure Dump Routines                                   */
 264 /****************************************************************************/
 265 #ifdef BCE_DEBUG
 266 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 267 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 268 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 269 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 270 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 271 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 272                                 struct l2_fhdr *) __unused;
 273 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 274 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 275 static void     bce_dump_status_block(struct bce_softc *);
 276 static void     bce_dump_driver_state(struct bce_softc *);
 277 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 278 static void     bce_dump_hw_state(struct bce_softc *);
 279 static void     bce_dump_txp_state(struct bce_softc *);
 280 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 281 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 282 static void     bce_freeze_controller(struct bce_softc *) __unused;
 283 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 284 static void     bce_breakpoint(struct bce_softc *);
 285 #endif  /* BCE_DEBUG */
 286
 287
 288 /****************************************************************************/
 289 /* BCE Register/Memory Access Routines                                      */
 290 /****************************************************************************/
 291 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 292 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 293 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 294 static int      bce_miibus_read_reg(device_t, int, int);
 295 static int      bce_miibus_write_reg(device_t, int, int, int);
 296 static void     bce_miibus_statchg(device_t);
 297
 298
 299 /****************************************************************************/
 300 /* BCE NVRAM Access Routines                                                */
 301 /****************************************************************************/
 302 static int      bce_acquire_nvram_lock(struct bce_softc *);
 303 static int      bce_release_nvram_lock(struct bce_softc *);
 304 static void     bce_enable_nvram_access(struct bce_softc *);
 305 static void     bce_disable_nvram_access(struct bce_softc *);
 306 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 307                                      uint32_t);
 308 static int      bce_init_nvram(struct bce_softc *);
 309 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 310 static int      bce_nvram_test(struct bce_softc *);
 311 #ifdef BCE_NVRAM_WRITE_SUPPORT
 312 static int      bce_enable_nvram_write(struct bce_softc *);
 313 static void     bce_disable_nvram_write(struct bce_softc *);
 314 static int      bce_nvram_erase_page(struct bce_softc *, uint32_t);
 315 static int      bce_nvram_write_dword(struct bce_softc *, uint32_t, uint8_t *,
 316                                       uint32_t);
 317 static int      bce_nvram_write(struct bce_softc *, uint32_t, uint8_t *,
 318                                 int) __unused;
 319 #endif
 320
 321 /****************************************************************************/
 322 /* BCE DMA Allocate/Free Routines                                           */
 323 /****************************************************************************/
 324 static int      bce_dma_alloc(struct bce_softc *);
 325 static void     bce_dma_free(struct bce_softc *);
 326 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 327 static void     bce_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 328                                  bus_size_t, int);
 329
 330 /****************************************************************************/
 331 /* BCE Firmware Synchronization and Load                                    */
 332 /****************************************************************************/
 333 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 334 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 335                                  uint32_t, uint32_t);
 336 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 337                                 struct fw_info *);
 338 static void     bce_init_cpus(struct bce_softc *);
 339
 340 static void     bce_stop(struct bce_softc *);
 341 static int      bce_reset(struct bce_softc *, uint32_t);
 342 static int      bce_chipinit(struct bce_softc *);
 343 static int      bce_blockinit(struct bce_softc *);
 344 static int      bce_newbuf_std(struct bce_softc *, struct mbuf *,
 345                                uint16_t *, uint16_t *, uint32_t *);
 346
 347 static int      bce_init_tx_chain(struct bce_softc *);
 348 static int      bce_init_rx_chain(struct bce_softc *);
 349 static void     bce_free_rx_chain(struct bce_softc *);
 350 static void     bce_free_tx_chain(struct bce_softc *);
 351
 352 static int      bce_encap(struct bce_softc *, struct mbuf **);
 353 static void     bce_start(struct ifnet *);
 354 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 355 static void     bce_watchdog(struct ifnet *);
 356 static int      bce_ifmedia_upd(struct ifnet *);
 357 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 358 static void     bce_init(void *);
 359 static void     bce_mgmt_init(struct bce_softc *);
 360
 361 static void     bce_init_ctx(struct bce_softc *);
 362 static void     bce_get_mac_addr(struct bce_softc *);
 363 static void     bce_set_mac_addr(struct bce_softc *);
 364 static void     bce_phy_intr(struct bce_softc *);
 365 static void     bce_rx_intr(struct bce_softc *, int);
 366 static void     bce_tx_intr(struct bce_softc *);
 367 static void     bce_disable_intr(struct bce_softc *);
 368 static void     bce_enable_intr(struct bce_softc *);
 369
 370 #ifdef DEVICE_POLLING
 371 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 372 #endif
 373 static void     bce_intr(void *);
 374 static void     bce_set_rx_mode(struct bce_softc *);
 375 static void     bce_stats_update(struct bce_softc *);
 376 static void     bce_tick(void *);
 377 static void     bce_tick_serialized(struct bce_softc *);
 378 static void     bce_add_sysctls(struct bce_softc *);
 379
 380 static void     bce_coal_change(struct bce_softc *);
 381 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 382 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 383 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 384 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 385 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 386 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 387 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 388 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 389 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 390                                        uint32_t *, uint32_t);
 391
 392 /*
 393  * NOTE:
 394  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 395  * takes 1023 as the TX ticks limit.  However, using 1023 will
 396  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 397  * there is _no_ network activity on the NIC.
 398  */
 399 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 400 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 401 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 402 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 403 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 404 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 405 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 406 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 407
 408 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 409 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 410 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 411 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 412 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 413 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 414 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 415 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 416
 417 /****************************************************************************/
 418 /* DragonFly device dispatch table.                                         */
 419 /****************************************************************************/
 420 static device_method_t bce_methods[] = {
 421         /* Device interface */
 422         DEVMETHOD(device_probe,         bce_probe),
 423         DEVMETHOD(device_attach,        bce_attach),
 424         DEVMETHOD(device_detach,        bce_detach),
 425         DEVMETHOD(device_shutdown,      bce_shutdown),
 426
 427         /* bus interface */
 428         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 429         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 430
 431         /* MII interface */
 432         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 433         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 434         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 435
 436         { 0, 0 }
 437 };
 438
 439 static driver_t bce_driver = {
 440         "bce",
 441         bce_methods,
 442         sizeof(struct bce_softc)
 443 };
 444
 445 static devclass_t bce_devclass;
 446
 447
 448 DECLARE_DUMMY_MODULE(if_xl);
 449 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 450 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, 0, 0);
 451 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
 452
 453
 454 /****************************************************************************/
 455 /* Device probe function.                                                   */
 456 /*                                                                          */
 457 /* Compares the device to the driver's list of supported devices and        */
 458 /* reports back to the OS whether this is the right driver for the device.  */
 459 /*                                                                          */
 460 /* Returns:                                                                 */
 461 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 462 /****************************************************************************/
 463 static int
 464 bce_probe(device_t dev)
 465 {
 466         struct bce_type *t;
 467         uint16_t vid, did, svid, sdid;
 468
 469         /* Get the data for the device to be probed. */
 470         vid  = pci_get_vendor(dev);
 471         did  = pci_get_device(dev);
 472         svid = pci_get_subvendor(dev);
 473         sdid = pci_get_subdevice(dev);
 474
 475         /* Look through the list of known devices for a match. */
 476         for (t = bce_devs; t->bce_name != NULL; ++t) {
 477                 if (vid == t->bce_vid && did == t->bce_did &&
 478                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 479                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 480                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 481                         char *descbuf;
 482
 483                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 484
 485                         /* Print out the device identity. */
 486                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 487                                   t->bce_name,
 488                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 489
 490                         device_set_desc_copy(dev, descbuf);
 491                         kfree(descbuf, M_TEMP);
 492                         return 0;
 493                 }
 494         }
 495         return ENXIO;
 496 }
 497
 498
 499 /****************************************************************************/
 500 /* Device attach function.                                                  */
 501 /*                                                                          */
 502 /* Allocates device resources, performs secondary chip identification,      */
 503 /* resets and initializes the hardware, and initializes driver instance     */
 504 /* variables.                                                               */
 505 /*                                                                          */
 506 /* Returns:                                                                 */
 507 /*   0 on success, positive value on failure.                               */
 508 /****************************************************************************/
 509 static int
 510 bce_attach(device_t dev)
 511 {
 512         struct bce_softc *sc = device_get_softc(dev);
 513         struct ifnet *ifp = &sc->arpcom.ac_if;
 514         uint32_t val;
 515         int rid, rc = 0;
 516 #ifdef notyet
 517         int count;
 518 #endif
 519
 520         sc->bce_dev = dev;
 521         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 522
 523         pci_enable_busmaster(dev);
 524
 525         /* Allocate PCI memory resources. */
 526         rid = PCIR_BAR(0);
 527         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 528                                                  RF_ACTIVE | PCI_RF_DENSE);
 529         if (sc->bce_res_mem == NULL) {
 530                 device_printf(dev, "PCI memory allocation failed\n");
 531                 return ENXIO;
 532         }
 533         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 534         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 535
 536         /* Allocate PCI IRQ resources. */
 537 #ifdef notyet
 538         count = pci_msi_count(dev);
 539         if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
 540                 rid = 1;
 541                 sc->bce_flags |= BCE_USING_MSI_FLAG;
 542         } else
 543 #endif
 544         rid = 0;
 545         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 546                                                  RF_SHAREABLE | RF_ACTIVE);
 547         if (sc->bce_res_irq == NULL) {
 548                 device_printf(dev, "PCI map interrupt failed\n");
 549                 rc = ENXIO;
 550                 goto fail;
 551         }
 552
 553         /*
 554          * Configure byte swap and enable indirect register access.
 555          * Rely on CPU to do target byte swapping on big endian systems.
 556          * Access to registers outside of PCI configurtion space are not
 557          * valid until this is done.
 558          */
 559         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 560                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 561                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 562
 563         /* Save ASIC revsion info. */
 564         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 565
 566         /* Weed out any non-production controller revisions. */
 567         switch(BCE_CHIP_ID(sc)) {
 568         case BCE_CHIP_ID_5706_A0:
 569         case BCE_CHIP_ID_5706_A1:
 570         case BCE_CHIP_ID_5708_A0:
 571         case BCE_CHIP_ID_5708_B0:
 572                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 573                               BCE_CHIP_ID(sc));
 574                 rc = ENODEV;
 575                 goto fail;
 576         }
 577
 578         /*
 579          * The embedded PCIe to PCI-X bridge (EPB)
 580          * in the 5708 cannot address memory above
 581          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
 582          */
 583         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
 584                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
 585         else
 586                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
 587
 588         /*
 589          * Find the base address for shared memory access.
 590          * Newer versions of bootcode use a signature and offset
 591          * while older versions use a fixed address.
 592          */
 593         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 594         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
 595                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0);
 596         else
 597                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 598
 599         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 600
 601         /* Get PCI bus information (speed and type). */
 602         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 603         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 604                 uint32_t clkreg;
 605
 606                 sc->bce_flags |= BCE_PCIX_FLAG;
 607
 608                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 609                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 610                 switch (clkreg) {
 611                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 612                         sc->bus_speed_mhz = 133;
 613                         break;
 614
 615                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 616                         sc->bus_speed_mhz = 100;
 617                         break;
 618
 619                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 620                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 621                         sc->bus_speed_mhz = 66;
 622                         break;
 623
 624                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 625                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 626                         sc->bus_speed_mhz = 50;
 627                         break;
 628
 629                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 630                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 631                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 632                         sc->bus_speed_mhz = 33;
 633                         break;
 634                 }
 635         } else {
 636                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 637                         sc->bus_speed_mhz = 66;
 638                 else
 639                         sc->bus_speed_mhz = 33;
 640         }
 641
 642         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 643                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 644
 645         device_printf(dev, "ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n",
 646                       sc->bce_chipid,
 647                       ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 648                       (BCE_CHIP_ID(sc) & 0x0ff0) >> 4,
 649                       (sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : "",
 650                       (sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 651                       "32-bit" : "64-bit", sc->bus_speed_mhz);
 652
 653         /* Reset the controller. */
 654         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 655         if (rc != 0)
 656                 goto fail;
 657
 658         /* Initialize the controller. */
 659         rc = bce_chipinit(sc);
 660         if (rc != 0) {
 661                 device_printf(dev, "Controller initialization failed!\n");
 662                 goto fail;
 663         }
 664
 665         /* Perform NVRAM test. */
 666         rc = bce_nvram_test(sc);
 667         if (rc != 0) {
 668                 device_printf(dev, "NVRAM test failed!\n");
 669                 goto fail;
 670         }
 671
 672         /* Fetch the permanent Ethernet MAC address. */
 673         bce_get_mac_addr(sc);
 674
 675         /*
 676          * Trip points control how many BDs
 677          * should be ready before generating an
 678          * interrupt while ticks control how long
 679          * a BD can sit in the chain before
 680          * generating an interrupt.  Set the default
 681          * values for the RX and TX rings.
 682          */
 683
 684 #ifdef BCE_DRBUG
 685         /* Force more frequent interrupts. */
 686         sc->bce_tx_quick_cons_trip_int = 1;
 687         sc->bce_tx_quick_cons_trip     = 1;
 688         sc->bce_tx_ticks_int           = 0;
 689         sc->bce_tx_ticks               = 0;
 690
 691         sc->bce_rx_quick_cons_trip_int = 1;
 692         sc->bce_rx_quick_cons_trip     = 1;
 693         sc->bce_rx_ticks_int           = 0;
 694         sc->bce_rx_ticks               = 0;
 695 #else
 696         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 697         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 698         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 699         sc->bce_tx_ticks               = bce_tx_ticks;
 700
 701         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 702         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 703         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 704         sc->bce_rx_ticks               = bce_rx_ticks;
 705 #endif
 706
 707         /* Update statistics once every second. */
 708         sc->bce_stats_ticks = 1000000 & 0xffff00;
 709
 710         /*
 711          * The copper based NetXtreme II controllers
 712          * use an integrated PHY at address 1 while
 713          * the SerDes controllers use a PHY at
 714          * address 2.
 715          */
 716         sc->bce_phy_addr = 1;
 717
 718         if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
 719                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
 720                 sc->bce_flags |= BCE_NO_WOL_FLAG;
 721                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) {
 722                         sc->bce_phy_addr = 2;
 723                         val = REG_RD_IND(sc, sc->bce_shmem_base +
 724                                          BCE_SHARED_HW_CFG_CONFIG);
 725                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
 726                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
 727                 }
 728         }
 729
 730         /* Allocate DMA memory resources. */
 731         rc = bce_dma_alloc(sc);
 732         if (rc != 0) {
 733                 device_printf(dev, "DMA resource allocation failed!\n");
 734                 goto fail;
 735         }
 736
 737         /* Initialize the ifnet interface. */
 738         ifp->if_softc = sc;
 739         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 740         ifp->if_ioctl = bce_ioctl;
 741         ifp->if_start = bce_start;
 742         ifp->if_init = bce_init;
 743         ifp->if_watchdog = bce_watchdog;
 744 #ifdef DEVICE_POLLING
 745         ifp->if_poll = bce_poll;
 746 #endif
 747         ifp->if_mtu = ETHERMTU;
 748         ifp->if_hwassist = BCE_IF_HWASSIST;
 749         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 750         ifp->if_capenable = ifp->if_capabilities;
 751         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 752         ifq_set_ready(&ifp->if_snd);
 753
 754         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 755                 ifp->if_baudrate = IF_Gbps(2.5);
 756         else
 757                 ifp->if_baudrate = IF_Gbps(1);
 758
 759         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 760         sc->mbuf_alloc_size  = MCLBYTES;
 761
 762         /* Look for our PHY. */
 763         rc = mii_phy_probe(dev, &sc->bce_miibus,
 764                            bce_ifmedia_upd, bce_ifmedia_sts);
 765         if (rc != 0) {
 766                 device_printf(dev, "PHY probe failed!\n");
 767                 goto fail;
 768         }
 769
 770         /* Attach to the Ethernet interface list. */
 771         ether_ifattach(ifp, sc->eaddr, NULL);
 772
 773         callout_init(&sc->bce_stat_ch);
 774
 775         /* Hookup IRQ last. */
 776         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
 777                             &sc->bce_intrhand, ifp->if_serializer);
 778         if (rc != 0) {
 779                 device_printf(dev, "Failed to setup IRQ!\n");
 780                 ether_ifdetach(ifp);
 781                 goto fail;
 782         }
 783
 784         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 785         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 786
 787         /* Print some important debugging info. */
 788         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 789
 790         /* Add the supported sysctls to the kernel. */
 791         bce_add_sysctls(sc);
 792
 793         /* Get the firmware running so IPMI still works */
 794         bce_mgmt_init(sc);
 795
 796         return 0;
 797 fail:
 798         bce_detach(dev);
 799         return(rc);
 800 }
 801
 802
 803 /****************************************************************************/
 804 /* Device detach function.                                                  */
 805 /*                                                                          */
 806 /* Stops the controller, resets the controller, and releases resources.     */
 807 /*                                                                          */
 808 /* Returns:                                                                 */
 809 /*   0 on success, positive value on failure.                               */
 810 /****************************************************************************/
 811 static int
 812 bce_detach(device_t dev)
 813 {
 814         struct bce_softc *sc = device_get_softc(dev);
 815
 816         if (device_is_attached(dev)) {
 817                 struct ifnet *ifp = &sc->arpcom.ac_if;
 818
 819                 /* Stop and reset the controller. */
 820                 lwkt_serialize_enter(ifp->if_serializer);
 821                 bce_stop(sc);
 822                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 823                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
 824                 lwkt_serialize_exit(ifp->if_serializer);
 825
 826                 ether_ifdetach(ifp);
 827         }
 828
 829         /* If we have a child device on the MII bus remove it too. */
 830         if (sc->bce_miibus)
 831                 device_delete_child(dev, sc->bce_miibus);
 832         bus_generic_detach(dev);
 833
 834         if (sc->bce_res_irq != NULL) {
 835                 bus_release_resource(dev, SYS_RES_IRQ,
 836                         sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
 837                         sc->bce_res_irq);
 838         }
 839
 840 #ifdef notyet
 841         if (sc->bce_flags & BCE_USING_MSI_FLAG)
 842                 pci_release_msi(dev);
 843 #endif
 844
 845         if (sc->bce_res_mem != NULL) {
 846                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
 847                                      sc->bce_res_mem);
 848         }
 849
 850         bce_dma_free(sc);
 851
 852         if (sc->bce_sysctl_tree != NULL)
 853                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
 854
 855         return 0;
 856 }
 857
 858
 859 /****************************************************************************/
 860 /* Device shutdown function.                                                */
 861 /*                                                                          */
 862 /* Stops and resets the controller.                                         */
 863 /*                                                                          */
 864 /* Returns:                                                                 */
 865 /*   Nothing                                                                */
 866 /****************************************************************************/
 867 static void
 868 bce_shutdown(device_t dev)
 869 {
 870         struct bce_softc *sc = device_get_softc(dev);
 871         struct ifnet *ifp = &sc->arpcom.ac_if;
 872
 873         lwkt_serialize_enter(ifp->if_serializer);
 874         bce_stop(sc);
 875         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 876         lwkt_serialize_exit(ifp->if_serializer);
 877 }
 878
 879
 880 /****************************************************************************/
 881 /* Indirect register read.                                                  */
 882 /*                                                                          */
 883 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
 884 /* configuration space.  Using this mechanism avoids issues with posted     */
 885 /* reads but is much slower than memory-mapped I/O.                         */
 886 /*                                                                          */
 887 /* Returns:                                                                 */
 888 /*   The value of the register.                                             */
 889 /****************************************************************************/
 890 static uint32_t
 891 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
 892 {
 893         device_t dev = sc->bce_dev;
 894
 895         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
 896 #ifdef BCE_DEBUG
 897         {
 898                 uint32_t val;
 899                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
 900                 DBPRINT(sc, BCE_EXCESSIVE,
 901                         "%s(); offset = 0x%08X, val = 0x%08X\n",
 902                         __func__, offset, val);
 903                 return val;
 904         }
 905 #else
 906         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
 907 #endif
 908 }
 909
 910
 911 /****************************************************************************/
 912 /* Indirect register write.                                                 */
 913 /*                                                                          */
 914 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
 915 /* configuration space.  Using this mechanism avoids issues with posted     */
 916 /* writes but is muchh slower than memory-mapped I/O.                       */
 917 /*                                                                          */
 918 /* Returns:                                                                 */
 919 /*   Nothing.                                                               */
 920 /****************************************************************************/
 921 static void
 922 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
 923 {
 924         device_t dev = sc->bce_dev;
 925
 926         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
 927                 __func__, offset, val);
 928
 929         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
 930         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
 931 }
 932
 933
 934 /****************************************************************************/
 935 /* Context memory write.                                                    */
 936 /*                                                                          */
 937 /* The NetXtreme II controller uses context memory to track connection      */
 938 /* information for L2 and higher network protocols.                         */
 939 /*                                                                          */
 940 /* Returns:                                                                 */
 941 /*   Nothing.                                                               */
 942 /****************************************************************************/
 943 static void
 944 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t offset,
 945            uint32_t val)
 946 {
 947         DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
 948                 "val = 0x%08X\n", __func__, cid_addr, offset, val);
 949
 950         offset += cid_addr;
 951         REG_WR(sc, BCE_CTX_DATA_ADR, offset);
 952         REG_WR(sc, BCE_CTX_DATA, val);
 953 }
 954
 955
 956 /****************************************************************************/
 957 /* PHY register read.                                                       */
 958 /*                                                                          */
 959 /* Implements register reads on the MII bus.                                */
 960 /*                                                                          */
 961 /* Returns:                                                                 */
 962 /*   The value of the register.                                             */
 963 /****************************************************************************/
 964 static int
 965 bce_miibus_read_reg(device_t dev, int phy, int reg)
 966 {
 967         struct bce_softc *sc = device_get_softc(dev);
 968         uint32_t val;
 969         int i;
 970
 971         /* Make sure we are accessing the correct PHY address. */
 972         if (phy != sc->bce_phy_addr) {
 973                 DBPRINT(sc, BCE_VERBOSE,
 974                         "Invalid PHY address %d for PHY read!\n", phy);
 975                 return 0;
 976         }
 977
 978         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
 979                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
 980                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
 981
 982                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
 983                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
 984
 985                 DELAY(40);
 986         }
 987
 988         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
 989               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
 990               BCE_EMAC_MDIO_COMM_START_BUSY;
 991         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
 992
 993         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
 994                 DELAY(10);
 995
 996                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
 997                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
 998                         DELAY(5);
 999
1000                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1001                         val &= BCE_EMAC_MDIO_COMM_DATA;
1002                         break;
1003                 }
1004         }
1005
1006         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1007                 if_printf(&sc->arpcom.ac_if,
1008                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1009                           phy, reg);
1010                 val = 0x0;
1011         } else {
1012                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1013         }
1014
1015         DBPRINT(sc, BCE_EXCESSIVE,
1016                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1017                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1018
1019         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1020                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1021                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1022
1023                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1024                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1025
1026                 DELAY(40);
1027         }
1028         return (val & 0xffff);
1029 }
1030
1031
1032 /****************************************************************************/
1033 /* PHY register write.                                                      */
1034 /*                                                                          */
1035 /* Implements register writes on the MII bus.                               */
1036 /*                                                                          */
1037 /* Returns:                                                                 */
1038 /*   The value of the register.                                             */
1039 /****************************************************************************/
1040 static int
1041 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1042 {
1043         struct bce_softc *sc = device_get_softc(dev);
1044         uint32_t val1;
1045         int i;
1046
1047         /* Make sure we are accessing the correct PHY address. */
1048         if (phy != sc->bce_phy_addr) {
1049                 DBPRINT(sc, BCE_WARN,
1050                         "Invalid PHY address %d for PHY write!\n", phy);
1051                 return(0);
1052         }
1053
1054         DBPRINT(sc, BCE_EXCESSIVE,
1055                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1056                 __func__, phy, (uint16_t)(reg & 0xffff),
1057                 (uint16_t)(val & 0xffff));
1058
1059         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1060                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1061                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1062
1063                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1064                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1065
1066                 DELAY(40);
1067         }
1068
1069         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1070                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1071                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1072         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1073
1074         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1075                 DELAY(10);
1076
1077                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1078                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1079                         DELAY(5);
1080                         break;
1081                 }
1082         }
1083
1084         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1085                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1086
1087         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1088                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1089                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1090
1091                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1092                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1093
1094                 DELAY(40);
1095         }
1096         return 0;
1097 }
1098
1099
1100 /****************************************************************************/
1101 /* MII bus status change.                                                   */
1102 /*                                                                          */
1103 /* Called by the MII bus driver when the PHY establishes link to set the    */
1104 /* MAC interface registers.                                                 */
1105 /*                                                                          */
1106 /* Returns:                                                                 */
1107 /*   Nothing.                                                               */
1108 /****************************************************************************/
1109 static void
1110 bce_miibus_statchg(device_t dev)
1111 {
1112         struct bce_softc *sc = device_get_softc(dev);
1113         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1114
1115         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1116                 mii->mii_media_active);
1117
1118 #ifdef BCE_DEBUG
1119         /* Decode the interface media flags. */
1120         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1121         switch(IFM_TYPE(mii->mii_media_active)) {
1122         case IFM_ETHER:
1123                 kprintf("Ethernet )");
1124                 break;
1125         default:
1126                 kprintf("Unknown )");
1127                 break;
1128         }
1129
1130         kprintf(" Media Options: ( ");
1131         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1132         case IFM_AUTO:
1133                 kprintf("Autoselect )");
1134                 break;
1135         case IFM_MANUAL:
1136                 kprintf("Manual )");
1137                 break;
1138         case IFM_NONE:
1139                 kprintf("None )");
1140                 break;
1141         case IFM_10_T:
1142                 kprintf("10Base-T )");
1143                 break;
1144         case IFM_100_TX:
1145                 kprintf("100Base-TX )");
1146                 break;
1147         case IFM_1000_SX:
1148                 kprintf("1000Base-SX )");
1149                 break;
1150         case IFM_1000_T:
1151                 kprintf("1000Base-T )");
1152                 break;
1153         default:
1154                 kprintf("Other )");
1155                 break;
1156         }
1157
1158         kprintf(" Global Options: (");
1159         if (mii->mii_media_active & IFM_FDX)
1160                 kprintf(" FullDuplex");
1161         if (mii->mii_media_active & IFM_HDX)
1162                 kprintf(" HalfDuplex");
1163         if (mii->mii_media_active & IFM_LOOP)
1164                 kprintf(" Loopback");
1165         if (mii->mii_media_active & IFM_FLAG0)
1166                 kprintf(" Flag0");
1167         if (mii->mii_media_active & IFM_FLAG1)
1168                 kprintf(" Flag1");
1169         if (mii->mii_media_active & IFM_FLAG2)
1170                 kprintf(" Flag2");
1171         kprintf(" )\n");
1172 #endif
1173
1174         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1175
1176         /*
1177          * Set MII or GMII interface based on the speed negotiated
1178          * by the PHY.
1179          */
1180         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1181             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1182                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1183                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1184         } else {
1185                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1186                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1187         }
1188
1189         /*
1190          * Set half or full duplex based on the duplicity negotiated
1191          * by the PHY.
1192          */
1193         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1194                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1195                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1196         } else {
1197                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1198                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1199         }
1200 }
1201
1202
1203 /****************************************************************************/
1204 /* Acquire NVRAM lock.                                                      */
1205 /*                                                                          */
1206 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1207 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1208 /* for use by the driver.                                                   */
1209 /*                                                                          */
1210 /* Returns:                                                                 */
1211 /*   0 on success, positive value on failure.                               */
1212 /****************************************************************************/
1213 static int
1214 bce_acquire_nvram_lock(struct bce_softc *sc)
1215 {
1216         uint32_t val;
1217         int j;
1218
1219         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1220
1221         /* Request access to the flash interface. */
1222         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1223         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1224                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1225                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1226                         break;
1227
1228                 DELAY(5);
1229         }
1230
1231         if (j >= NVRAM_TIMEOUT_COUNT) {
1232                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1233                 return EBUSY;
1234         }
1235         return 0;
1236 }
1237
1238
1239 /****************************************************************************/
1240 /* Release NVRAM lock.                                                      */
1241 /*                                                                          */
1242 /* When the caller is finished accessing NVRAM the lock must be released.   */
1243 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1244 /* for use by the driver.                                                   */
1245 /*                                                                          */
1246 /* Returns:                                                                 */
1247 /*   0 on success, positive value on failure.                               */
1248 /****************************************************************************/
1249 static int
1250 bce_release_nvram_lock(struct bce_softc *sc)
1251 {
1252         int j;
1253         uint32_t val;
1254
1255         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1256
1257         /*
1258          * Relinquish nvram interface.
1259          */
1260         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1261
1262         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1263                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1264                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1265                         break;
1266
1267                 DELAY(5);
1268         }
1269
1270         if (j >= NVRAM_TIMEOUT_COUNT) {
1271                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1272                 return EBUSY;
1273         }
1274         return 0;
1275 }
1276
1277
1278 #ifdef BCE_NVRAM_WRITE_SUPPORT
1279 /****************************************************************************/
1280 /* Enable NVRAM write access.                                               */
1281 /*                                                                          */
1282 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
1283 /*                                                                          */
1284 /* Returns:                                                                 */
1285 /*   0 on success, positive value on failure.                               */
1286 /****************************************************************************/
1287 static int
1288 bce_enable_nvram_write(struct bce_softc *sc)
1289 {
1290         uint32_t val;
1291
1292         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n");
1293
1294         val = REG_RD(sc, BCE_MISC_CFG);
1295         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1296
1297         if (!sc->bce_flash_info->buffered) {
1298                 int j;
1299
1300                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1301                 REG_WR(sc, BCE_NVM_COMMAND,
1302                        BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1303
1304                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1305                         DELAY(5);
1306
1307                         val = REG_RD(sc, BCE_NVM_COMMAND);
1308                         if (val & BCE_NVM_COMMAND_DONE)
1309                                 break;
1310                 }
1311
1312                 if (j >= NVRAM_TIMEOUT_COUNT) {
1313                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1314                         return EBUSY;
1315                 }
1316         }
1317         return 0;
1318 }
1319
1320
1321 /****************************************************************************/
1322 /* Disable NVRAM write access.                                              */
1323 /*                                                                          */
1324 /* When the caller is finished writing to NVRAM write access must be        */
1325 /* disabled.                                                                */
1326 /*                                                                          */
1327 /* Returns:                                                                 */
1328 /*   Nothing.                                                               */
1329 /****************************************************************************/
1330 static void
1331 bce_disable_nvram_write(struct bce_softc *sc)
1332 {
1333         uint32_t val;
1334
1335         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n");
1336
1337         val = REG_RD(sc, BCE_MISC_CFG);
1338         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1339 }
1340 #endif  /* BCE_NVRAM_WRITE_SUPPORT */
1341
1342
1343 /****************************************************************************/
1344 /* Enable NVRAM access.                                                     */
1345 /*                                                                          */
1346 /* Before accessing NVRAM for read or write operations the caller must      */
1347 /* enabled NVRAM access.                                                    */
1348 /*                                                                          */
1349 /* Returns:                                                                 */
1350 /*   Nothing.                                                               */
1351 /****************************************************************************/
1352 static void
1353 bce_enable_nvram_access(struct bce_softc *sc)
1354 {
1355         uint32_t val;
1356
1357         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1358
1359         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1360         /* Enable both bits, even on read. */
1361         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1362                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1363 }
1364
1365
1366 /****************************************************************************/
1367 /* Disable NVRAM access.                                                    */
1368 /*                                                                          */
1369 /* When the caller is finished accessing NVRAM access must be disabled.     */
1370 /*                                                                          */
1371 /* Returns:                                                                 */
1372 /*   Nothing.                                                               */
1373 /****************************************************************************/
1374 static void
1375 bce_disable_nvram_access(struct bce_softc *sc)
1376 {
1377         uint32_t val;
1378
1379         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1380
1381         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1382
1383         /* Disable both bits, even after read. */
1384         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1385                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1386 }
1387
1388
1389 #ifdef BCE_NVRAM_WRITE_SUPPORT
1390 /****************************************************************************/
1391 /* Erase NVRAM page before writing.                                         */
1392 /*                                                                          */
1393 /* Non-buffered flash parts require that a page be erased before it is      */
1394 /* written.                                                                 */
1395 /*                                                                          */
1396 /* Returns:                                                                 */
1397 /*   0 on success, positive value on failure.                               */
1398 /****************************************************************************/
1399 static int
1400 bce_nvram_erase_page(struct bce_softc *sc, uint32_t offset)
1401 {
1402         uint32_t cmd;
1403         int j;
1404
1405         /* Buffered flash doesn't require an erase. */
1406         if (sc->bce_flash_info->buffered)
1407                 return 0;
1408
1409         DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n");
1410
1411         /* Build an erase command. */
1412         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
1413               BCE_NVM_COMMAND_DOIT;
1414
1415         /*
1416          * Clear the DONE bit separately, set the NVRAM adress to erase,
1417          * and issue the erase command.
1418          */
1419         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1420         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1421         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1422
1423         /* Wait for completion. */
1424         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1425                 uint32_t val;
1426
1427                 DELAY(5);
1428
1429                 val = REG_RD(sc, BCE_NVM_COMMAND);
1430                 if (val & BCE_NVM_COMMAND_DONE)
1431                         break;
1432         }
1433
1434         if (j >= NVRAM_TIMEOUT_COUNT) {
1435                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
1436                 return EBUSY;
1437         }
1438         return 0;
1439 }
1440 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1441
1442
1443 /****************************************************************************/
1444 /* Read a dword (32 bits) from NVRAM.                                       */
1445 /*                                                                          */
1446 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1447 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1448 /*                                                                          */
1449 /* Returns:                                                                 */
1450 /*   0 on success and the 32 bit value read, positive value on failure.     */
1451 /****************************************************************************/
1452 static int
1453 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1454                      uint32_t cmd_flags)
1455 {
1456         uint32_t cmd;
1457         int i, rc = 0;
1458
1459         /* Build the command word. */
1460         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1461
1462         /* Calculate the offset for buffered flash. */
1463         if (sc->bce_flash_info->buffered) {
1464                 offset = ((offset / sc->bce_flash_info->page_size) <<
1465                           sc->bce_flash_info->page_bits) +
1466                          (offset % sc->bce_flash_info->page_size);
1467         }
1468
1469         /*
1470          * Clear the DONE bit separately, set the address to read,
1471          * and issue the read.
1472          */
1473         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1474         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1475         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1476
1477         /* Wait for completion. */
1478         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1479                 uint32_t val;
1480
1481                 DELAY(5);
1482
1483                 val = REG_RD(sc, BCE_NVM_COMMAND);
1484                 if (val & BCE_NVM_COMMAND_DONE) {
1485                         val = REG_RD(sc, BCE_NVM_READ);
1486
1487                         val = be32toh(val);
1488                         memcpy(ret_val, &val, 4);
1489                         break;
1490                 }
1491         }
1492
1493         /* Check for errors. */
1494         if (i >= NVRAM_TIMEOUT_COUNT) {
1495                 if_printf(&sc->arpcom.ac_if,
1496                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1497                           offset);
1498                 rc = EBUSY;
1499         }
1500         return rc;
1501 }
1502
1503
1504 #ifdef BCE_NVRAM_WRITE_SUPPORT
1505 /****************************************************************************/
1506 /* Write a dword (32 bits) to NVRAM.                                        */
1507 /*                                                                          */
1508 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
1509 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
1510 /* enabled NVRAM write access.                                              */
1511 /*                                                                          */
1512 /* Returns:                                                                 */
1513 /*   0 on success, positive value on failure.                               */
1514 /****************************************************************************/
1515 static int
1516 bce_nvram_write_dword(struct bce_softc *sc, uint32_t offset, uint8_t *val,
1517                       uint32_t cmd_flags)
1518 {
1519         uint32_t cmd, val32;
1520         int j;
1521
1522         /* Build the command word. */
1523         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
1524
1525         /* Calculate the offset for buffered flash. */
1526         if (sc->bce_flash_info->buffered) {
1527                 offset = ((offset / sc->bce_flash_info->page_size) <<
1528                           sc->bce_flash_info->page_bits) +
1529                          (offset % sc->bce_flash_info->page_size);
1530         }
1531
1532         /*
1533          * Clear the DONE bit separately, convert NVRAM data to big-endian,
1534          * set the NVRAM address to write, and issue the write command
1535          */
1536         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1537         memcpy(&val32, val, 4);
1538         val32 = htobe32(val32);
1539         REG_WR(sc, BCE_NVM_WRITE, val32);
1540         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1541         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1542
1543         /* Wait for completion. */
1544         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1545                 DELAY(5);
1546
1547                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
1548                         break;
1549         }
1550         if (j >= NVRAM_TIMEOUT_COUNT) {
1551                 if_printf(&sc->arpcom.ac_if,
1552                           "Timeout error writing NVRAM at offset 0x%08X\n",
1553                           offset);
1554                 return EBUSY;
1555         }
1556         return 0;
1557 }
1558 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1559
1560
1561 /****************************************************************************/
1562 /* Initialize NVRAM access.                                                 */
1563 /*                                                                          */
1564 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1565 /* access that device.                                                      */
1566 /*                                                                          */
1567 /* Returns:                                                                 */
1568 /*   0 on success, positive value on failure.                               */
1569 /****************************************************************************/
1570 static int
1571 bce_init_nvram(struct bce_softc *sc)
1572 {
1573         uint32_t val;
1574         int j, entry_count, rc = 0;
1575         const struct flash_spec *flash;
1576
1577         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1578
1579         /* Determine the selected interface. */
1580         val = REG_RD(sc, BCE_NVM_CFG1);
1581
1582         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1583
1584         /*
1585          * Flash reconfiguration is required to support additional
1586          * NVRAM devices not directly supported in hardware.
1587          * Check if the flash interface was reconfigured
1588          * by the bootcode.
1589          */
1590
1591         if (val & 0x40000000) {
1592                 /* Flash interface reconfigured by bootcode. */
1593
1594                 DBPRINT(sc, BCE_INFO_LOAD,
1595                         "%s(): Flash WAS reconfigured.\n", __func__);
1596
1597                 for (j = 0, flash = flash_table; j < entry_count;
1598                      j++, flash++) {
1599                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1600                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1601                                 sc->bce_flash_info = flash;
1602                                 break;
1603                         }
1604                 }
1605         } else {
1606                 /* Flash interface not yet reconfigured. */
1607                 uint32_t mask;
1608
1609                 DBPRINT(sc, BCE_INFO_LOAD,
1610                         "%s(): Flash was NOT reconfigured.\n", __func__);
1611
1612                 if (val & (1 << 23))
1613                         mask = FLASH_BACKUP_STRAP_MASK;
1614                 else
1615                         mask = FLASH_STRAP_MASK;
1616
1617                 /* Look for the matching NVRAM device configuration data. */
1618                 for (j = 0, flash = flash_table; j < entry_count;
1619                      j++, flash++) {
1620                         /* Check if the device matches any of the known devices. */
1621                         if ((val & mask) == (flash->strapping & mask)) {
1622                                 /* Found a device match. */
1623                                 sc->bce_flash_info = flash;
1624
1625                                 /* Request access to the flash interface. */
1626                                 rc = bce_acquire_nvram_lock(sc);
1627                                 if (rc != 0)
1628                                         return rc;
1629
1630                                 /* Reconfigure the flash interface. */
1631                                 bce_enable_nvram_access(sc);
1632                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1633                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1634                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1635                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1636                                 bce_disable_nvram_access(sc);
1637                                 bce_release_nvram_lock(sc);
1638                                 break;
1639                         }
1640                 }
1641         }
1642
1643         /* Check if a matching device was found. */
1644         if (j == entry_count) {
1645                 sc->bce_flash_info = NULL;
1646                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1647                 rc = ENODEV;
1648         }
1649
1650         /* Write the flash config data to the shared memory interface. */
1651         val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1652               BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1653         if (val)
1654                 sc->bce_flash_size = val;
1655         else
1656                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1657
1658         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1659                 __func__, sc->bce_flash_info->total_size);
1660
1661         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1662
1663         return rc;
1664 }
1665
1666
1667 /****************************************************************************/
1668 /* Read an arbitrary range of data from NVRAM.                              */
1669 /*                                                                          */
1670 /* Prepares the NVRAM interface for access and reads the requested data     */
1671 /* into the supplied buffer.                                                */
1672 /*                                                                          */
1673 /* Returns:                                                                 */
1674 /*   0 on success and the data read, positive value on failure.             */
1675 /****************************************************************************/
1676 static int
1677 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1678                int buf_size)
1679 {
1680         uint32_t cmd_flags, offset32, len32, extra;
1681         int rc = 0;
1682
1683         if (buf_size == 0)
1684                 return 0;
1685
1686         /* Request access to the flash interface. */
1687         rc = bce_acquire_nvram_lock(sc);
1688         if (rc != 0)
1689                 return rc;
1690
1691         /* Enable access to flash interface */
1692         bce_enable_nvram_access(sc);
1693
1694         len32 = buf_size;
1695         offset32 = offset;
1696         extra = 0;
1697
1698         cmd_flags = 0;
1699
1700         /* XXX should we release nvram lock if read_dword() fails? */
1701         if (offset32 & 3) {
1702                 uint8_t buf[4];
1703                 uint32_t pre_len;
1704
1705                 offset32 &= ~3;
1706                 pre_len = 4 - (offset & 3);
1707
1708                 if (pre_len >= len32) {
1709                         pre_len = len32;
1710                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1711                 } else {
1712                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1713                 }
1714
1715                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1716                 if (rc)
1717                         return rc;
1718
1719                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1720
1721                 offset32 += 4;
1722                 ret_buf += pre_len;
1723                 len32 -= pre_len;
1724         }
1725
1726         if (len32 & 3) {
1727                 extra = 4 - (len32 & 3);
1728                 len32 = (len32 + 4) & ~3;
1729         }
1730
1731         if (len32 == 4) {
1732                 uint8_t buf[4];
1733
1734                 if (cmd_flags)
1735                         cmd_flags = BCE_NVM_COMMAND_LAST;
1736                 else
1737                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1738                                     BCE_NVM_COMMAND_LAST;
1739
1740                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1741
1742                 memcpy(ret_buf, buf, 4 - extra);
1743         } else if (len32 > 0) {
1744                 uint8_t buf[4];
1745
1746                 /* Read the first word. */
1747                 if (cmd_flags)
1748                         cmd_flags = 0;
1749                 else
1750                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1751
1752                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1753
1754                 /* Advance to the next dword. */
1755                 offset32 += 4;
1756                 ret_buf += 4;
1757                 len32 -= 4;
1758
1759                 while (len32 > 4 && rc == 0) {
1760                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1761
1762                         /* Advance to the next dword. */
1763                         offset32 += 4;
1764                         ret_buf += 4;
1765                         len32 -= 4;
1766                 }
1767
1768                 if (rc)
1769                         return rc;
1770
1771                 cmd_flags = BCE_NVM_COMMAND_LAST;
1772                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1773
1774                 memcpy(ret_buf, buf, 4 - extra);
1775         }
1776
1777         /* Disable access to flash interface and release the lock. */
1778         bce_disable_nvram_access(sc);
1779         bce_release_nvram_lock(sc);
1780
1781         return rc;
1782 }
1783
1784
1785 #ifdef BCE_NVRAM_WRITE_SUPPORT
1786 /****************************************************************************/
1787 /* Write an arbitrary range of data from NVRAM.                             */
1788 /*                                                                          */
1789 /* Prepares the NVRAM interface for write access and writes the requested   */
1790 /* data from the supplied buffer.  The caller is responsible for            */
1791 /* calculating any appropriate CRCs.                                        */
1792 /*                                                                          */
1793 /* Returns:                                                                 */
1794 /*   0 on success, positive value on failure.                               */
1795 /****************************************************************************/
1796 static int
1797 bce_nvram_write(struct bce_softc *sc, uint32_t offset, uint8_t *data_buf,
1798                 int buf_size)
1799 {
1800         uint32_t written, offset32, len32;
1801         uint8_t *buf, start[4], end[4];
1802         int rc = 0;
1803         int align_start, align_end;
1804
1805         buf = data_buf;
1806         offset32 = offset;
1807         len32 = buf_size;
1808         align_end = 0;
1809         align_start = (offset32 & 3);
1810
1811         if (align_start) {
1812                 offset32 &= ~3;
1813                 len32 += align_start;
1814                 rc = bce_nvram_read(sc, offset32, start, 4);
1815                 if (rc)
1816                         return rc;
1817         }
1818
1819         if (len32 & 3) {
1820                 if (len32 > 4 || !align_start) {
1821                         align_end = 4 - (len32 & 3);
1822                         len32 += align_end;
1823                         rc = bce_nvram_read(sc, offset32 + len32 - 4, end, 4);
1824                         if (rc)
1825                                 return rc;
1826                 }
1827         }
1828
1829         if (align_start || align_end) {
1830                 buf = kmalloc(len32, M_DEVBUF, M_NOWAIT);
1831                 if (buf == NULL)
1832                         return ENOMEM;
1833                 if (align_start)
1834                         memcpy(buf, start, 4);
1835                 if (align_end)
1836                         memcpy(buf + len32 - 4, end, 4);
1837                 memcpy(buf + align_start, data_buf, buf_size);
1838         }
1839
1840         written = 0;
1841         while (written < len32 && rc == 0) {
1842                 uint32_t page_start, page_end, data_start, data_end;
1843                 uint32_t addr, cmd_flags;
1844                 int i;
1845                 uint8_t flash_buffer[264];
1846
1847                 /* Find the page_start addr */
1848                 page_start = offset32 + written;
1849                 page_start -= (page_start % sc->bce_flash_info->page_size);
1850                 /* Find the page_end addr */
1851                 page_end = page_start + sc->bce_flash_info->page_size;
1852                 /* Find the data_start addr */
1853                 data_start = (written == 0) ? offset32 : page_start;
1854                 /* Find the data_end addr */
1855                 data_end = (page_end > offset32 + len32) ? (offset32 + len32)
1856                                                          : page_end;
1857
1858                 /* Request access to the flash interface. */
1859                 rc = bce_acquire_nvram_lock(sc);
1860                 if (rc != 0)
1861                         goto nvram_write_end;
1862
1863                 /* Enable access to flash interface */
1864                 bce_enable_nvram_access(sc);
1865
1866                 cmd_flags = BCE_NVM_COMMAND_FIRST;
1867                 if (sc->bce_flash_info->buffered == 0) {
1868                         int j;
1869
1870                         /*
1871                          * Read the whole page into the buffer
1872                          * (non-buffer flash only)
1873                          */
1874                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
1875                                 if (j == (sc->bce_flash_info->page_size - 4))
1876                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
1877
1878                                 rc = bce_nvram_read_dword(sc, page_start + j,
1879                                                           &flash_buffer[j],
1880                                                           cmd_flags);
1881                                 if (rc)
1882                                         goto nvram_write_end;
1883
1884                                 cmd_flags = 0;
1885                         }
1886                 }
1887
1888                 /* Enable writes to flash interface (unlock write-protect) */
1889                 rc = bce_enable_nvram_write(sc);
1890                 if (rc != 0)
1891                         goto nvram_write_end;
1892
1893                 /* Erase the page */
1894                 rc = bce_nvram_erase_page(sc, page_start);
1895                 if (rc != 0)
1896                         goto nvram_write_end;
1897
1898                 /* Re-enable the write again for the actual write */
1899                 bce_enable_nvram_write(sc);
1900
1901                 /* Loop to write back the buffer data from page_start to
1902                  * data_start */
1903                 i = 0;
1904                 if (sc->bce_flash_info->buffered == 0) {
1905                         for (addr = page_start; addr < data_start;
1906                              addr += 4, i += 4) {
1907                                 rc = bce_nvram_write_dword(sc, addr,
1908                                                            &flash_buffer[i],
1909                                                            cmd_flags);
1910                                 if (rc != 0)
1911                                         goto nvram_write_end;
1912
1913                                 cmd_flags = 0;
1914                         }
1915                 }
1916
1917                 /* Loop to write the new data from data_start to data_end */
1918                 for (addr = data_start; addr < data_end; addr += 4, i++) {
1919                         if (addr == page_end - 4 ||
1920                             (sc->bce_flash_info->buffered &&
1921                              addr == data_end - 4))
1922                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
1923
1924                         rc = bce_nvram_write_dword(sc, addr, buf, cmd_flags);
1925                         if (rc != 0)
1926                                 goto nvram_write_end;
1927
1928                         cmd_flags = 0;
1929                         buf += 4;
1930                 }
1931
1932                 /* Loop to write back the buffer data from data_end
1933                  * to page_end */
1934                 if (sc->bce_flash_info->buffered == 0) {
1935                         for (addr = data_end; addr < page_end;
1936                              addr += 4, i += 4) {
1937                                 if (addr == page_end-4)
1938                                         cmd_flags = BCE_NVM_COMMAND_LAST;
1939
1940                                 rc = bce_nvram_write_dword(sc, addr,
1941                                         &flash_buffer[i], cmd_flags);
1942                                 if (rc != 0)
1943                                         goto nvram_write_end;
1944
1945                                 cmd_flags = 0;
1946                         }
1947                 }
1948
1949                 /* Disable writes to flash interface (lock write-protect) */
1950                 bce_disable_nvram_write(sc);
1951
1952                 /* Disable access to flash interface */
1953                 bce_disable_nvram_access(sc);
1954                 bce_release_nvram_lock(sc);
1955
1956                 /* Increment written */
1957                 written += data_end - data_start;
1958         }
1959
1960 nvram_write_end:
1961         if (align_start || align_end)
1962                 kfree(buf, M_DEVBUF);
1963         return rc;
1964 }
1965 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1966
1967
1968 /****************************************************************************/
1969 /* Verifies that NVRAM is accessible and contains valid data.               */
1970 /*                                                                          */
1971 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1972 /* correct.                                                                 */
1973 /*                                                                          */
1974 /* Returns:                                                                 */
1975 /*   0 on success, positive value on failure.                               */
1976 /****************************************************************************/
1977 static int
1978 bce_nvram_test(struct bce_softc *sc)
1979 {
1980         uint32_t buf[BCE_NVRAM_SIZE / 4];
1981         uint32_t magic, csum;
1982         uint8_t *data = (uint8_t *)buf;
1983         int rc = 0;
1984
1985         /*
1986          * Check that the device NVRAM is valid by reading
1987          * the magic value at offset 0.
1988          */
1989         rc = bce_nvram_read(sc, 0, data, 4);
1990         if (rc != 0)
1991                 return rc;
1992
1993         magic = be32toh(buf[0]);
1994         if (magic != BCE_NVRAM_MAGIC) {
1995                 if_printf(&sc->arpcom.ac_if,
1996                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1997                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1998                 return ENODEV;
1999         }
2000
2001         /*
2002          * Verify that the device NVRAM includes valid
2003          * configuration data.
2004          */
2005         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
2006         if (rc != 0)
2007                 return rc;
2008
2009         csum = ether_crc32_le(data, 0x100);
2010         if (csum != BCE_CRC32_RESIDUAL) {
2011                 if_printf(&sc->arpcom.ac_if,
2012                           "Invalid Manufacturing Information NVRAM CRC! "
2013                           "Expected: 0x%08X, Found: 0x%08X\n",
2014                           BCE_CRC32_RESIDUAL, csum);
2015                 return ENODEV;
2016         }
2017
2018         csum = ether_crc32_le(data + 0x100, 0x100);
2019         if (csum != BCE_CRC32_RESIDUAL) {
2020                 if_printf(&sc->arpcom.ac_if,
2021                           "Invalid Feature Configuration Information "
2022                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
2023                           BCE_CRC32_RESIDUAL, csum);
2024                 rc = ENODEV;
2025         }
2026         return rc;
2027 }
2028
2029
2030 /****************************************************************************/
2031 /* Free any DMA memory owned by the driver.                                 */
2032 /*                                                                          */
2033 /* Scans through each data structre that requires DMA memory and frees      */
2034 /* the memory if allocated.                                                 */
2035 /*                                                                          */
2036 /* Returns:                                                                 */
2037 /*   Nothing.                                                               */
2038 /****************************************************************************/
2039 static void
2040 bce_dma_free(struct bce_softc *sc)
2041 {
2042         int i;
2043
2044         /* Destroy the status block. */
2045         if (sc->status_tag != NULL) {
2046                 if (sc->status_block != NULL) {
2047                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2048                         bus_dmamem_free(sc->status_tag, sc->status_block,
2049                                         sc->status_map);
2050                 }
2051                 bus_dma_tag_destroy(sc->status_tag);
2052         }
2053
2054
2055         /* Destroy the statistics block. */
2056         if (sc->stats_tag != NULL) {
2057                 if (sc->stats_block != NULL) {
2058                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2059                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2060                                         sc->stats_map);
2061                 }
2062                 bus_dma_tag_destroy(sc->stats_tag);
2063         }
2064
2065         /* Destroy the TX buffer descriptor DMA stuffs. */
2066         if (sc->tx_bd_chain_tag != NULL) {
2067                 for (i = 0; i < TX_PAGES; i++) {
2068                         if (sc->tx_bd_chain[i] != NULL) {
2069                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2070                                                   sc->tx_bd_chain_map[i]);
2071                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2072                                                 sc->tx_bd_chain[i],
2073                                                 sc->tx_bd_chain_map[i]);
2074                         }
2075                 }
2076                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2077         }
2078
2079         /* Destroy the RX buffer descriptor DMA stuffs. */
2080         if (sc->rx_bd_chain_tag != NULL) {
2081                 for (i = 0; i < RX_PAGES; i++) {
2082                         if (sc->rx_bd_chain[i] != NULL) {
2083                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2084                                                   sc->rx_bd_chain_map[i]);
2085                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2086                                                 sc->rx_bd_chain[i],
2087                                                 sc->rx_bd_chain_map[i]);
2088                         }
2089                 }
2090                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2091         }
2092
2093         /* Destroy the TX mbuf DMA stuffs. */
2094         if (sc->tx_mbuf_tag != NULL) {
2095                 for (i = 0; i < TOTAL_TX_BD; i++) {
2096                         /* Must have been unloaded in bce_stop() */
2097                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2098                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2099                                            sc->tx_mbuf_map[i]);
2100                 }
2101                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2102         }
2103
2104         /* Destroy the RX mbuf DMA stuffs. */
2105         if (sc->rx_mbuf_tag != NULL) {
2106                 for (i = 0; i < TOTAL_RX_BD; i++) {
2107                         /* Must have been unloaded in bce_stop() */
2108                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2109                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2110                                            sc->rx_mbuf_map[i]);
2111                 }
2112                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2113         }
2114
2115         /* Destroy the parent tag */
2116         if (sc->parent_tag != NULL)
2117                 bus_dma_tag_destroy(sc->parent_tag);
2118 }
2119
2120
2121 /****************************************************************************/
2122 /* Get DMA memory from the OS.                                              */
2123 /*                                                                          */
2124 /* Validates that the OS has provided DMA buffers in response to a          */
2125 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2126 /* When the callback is used the OS will return 0 for the mapping function  */
2127 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2128 /* failures back to the caller.                                             */
2129 /*                                                                          */
2130 /* Returns:                                                                 */
2131 /*   Nothing.                                                               */
2132 /****************************************************************************/
2133 static void
2134 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2135 {
2136         bus_addr_t *busaddr = arg;
2137
2138         /*
2139          * Simulate a mapping failure.
2140          * XXX not correct.
2141          */
2142         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2143                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2144                         __FILE__, __LINE__);
2145                 error = ENOMEM);
2146
2147         /* Check for an error and signal the caller that an error occurred. */
2148         if (error)
2149                 return;
2150
2151         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2152         *busaddr = segs->ds_addr;
2153 }
2154
2155
2156 static void
2157 bce_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
2158                  bus_size_t mapsz __unused, int error)
2159 {
2160         struct bce_dmamap_arg *ctx = arg;
2161         int i;
2162
2163         if (error)
2164                 return;
2165
2166         if (nsegs > ctx->bce_maxsegs) {
2167                 ctx->bce_maxsegs = 0;
2168                 return;
2169         }
2170
2171         ctx->bce_maxsegs = nsegs;
2172         for (i = 0; i < nsegs; ++i)
2173                 ctx->bce_segs[i] = segs[i];
2174 }
2175
2176
2177 /****************************************************************************/
2178 /* Allocate any DMA memory needed by the driver.                            */
2179 /*                                                                          */
2180 /* Allocates DMA memory needed for the various global structures needed by  */
2181 /* hardware.                                                                */
2182 /*                                                                          */
2183 /* Returns:                                                                 */
2184 /*   0 for success, positive value for failure.                             */
2185 /****************************************************************************/
2186 static int
2187 bce_dma_alloc(struct bce_softc *sc)
2188 {
2189         struct ifnet *ifp = &sc->arpcom.ac_if;
2190         int i, j, rc = 0;
2191         bus_addr_t busaddr;
2192
2193         /*
2194          * Allocate the parent bus DMA tag appropriate for PCI.
2195          */
2196         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2197                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2198                                 NULL, NULL,
2199                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2200                                 BUS_SPACE_MAXSIZE_32BIT,
2201                                 0, &sc->parent_tag);
2202         if (rc != 0) {
2203                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2204                 return rc;
2205         }
2206
2207         /*
2208          * Allocate status block.
2209          */
2210         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2211                                 BCE_DMA_ALIGN, BCE_STATUS_BLK_SZ,
2212                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2213                                 &sc->status_tag, &sc->status_map,
2214                                 &sc->status_block_paddr);
2215         if (sc->status_block == NULL) {
2216                 if_printf(ifp, "Could not allocate status block!\n");
2217                 return ENOMEM;
2218         }
2219
2220         /*
2221          * Allocate statistics block.
2222          */
2223         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2224                                 BCE_DMA_ALIGN, BCE_STATS_BLK_SZ,
2225                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2226                                 &sc->stats_tag, &sc->stats_map,
2227                                 &sc->stats_block_paddr);
2228         if (sc->stats_block == NULL) {
2229                 if_printf(ifp, "Could not allocate statistics block!\n");
2230                 return ENOMEM;
2231         }
2232
2233         /*
2234          * Create a DMA tag for the TX buffer descriptor chain,
2235          * allocate and clear the  memory, and fetch the
2236          * physical address of the block.
2237          */
2238         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2239                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2240                                 NULL, NULL,
2241                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2242                                 0, &sc->tx_bd_chain_tag);
2243         if (rc != 0) {
2244                 if_printf(ifp, "Could not allocate "
2245                           "TX descriptor chain DMA tag!\n");
2246                 return rc;
2247         }
2248
2249         for (i = 0; i < TX_PAGES; i++) {
2250                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2251                                       (void **)&sc->tx_bd_chain[i],
2252                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2253                                       BUS_DMA_COHERENT,
2254                                       &sc->tx_bd_chain_map[i]);
2255                 if (rc != 0) {
2256                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2257                                   "chain DMA memory!\n", i);
2258                         return rc;
2259                 }
2260
2261                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2262                                      sc->tx_bd_chain_map[i],
2263                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2264                                      bce_dma_map_addr, &busaddr,
2265                                      BUS_DMA_WAITOK);
2266                 if (rc != 0) {
2267                         if (rc == EINPROGRESS) {
2268                                 panic("%s coherent memory loading "
2269                                       "is still in progress!", ifp->if_xname);
2270                         }
2271                         if_printf(ifp, "Could not map %dth TX descriptor "
2272                                   "chain DMA memory!\n", i);
2273                         bus_dmamem_free(sc->tx_bd_chain_tag,
2274                                         sc->tx_bd_chain[i],
2275                                         sc->tx_bd_chain_map[i]);
2276                         sc->tx_bd_chain[i] = NULL;
2277                         return rc;
2278                 }
2279
2280                 sc->tx_bd_chain_paddr[i] = busaddr;
2281                 /* DRC - Fix for 64 bit systems. */
2282                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2283                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2284         }
2285
2286         /* Create a DMA tag for TX mbufs. */
2287         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2288                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2289                                 NULL, NULL,
2290                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2291                                 BCE_MAX_SEGMENTS, MCLBYTES,
2292                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2293                                 BUS_DMA_ONEBPAGE,
2294                                 &sc->tx_mbuf_tag);
2295         if (rc != 0) {
2296                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2297                 return rc;
2298         }
2299
2300         /* Create DMA maps for the TX mbufs clusters. */
2301         for (i = 0; i < TOTAL_TX_BD; i++) {
2302                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2303                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2304                                        &sc->tx_mbuf_map[i]);
2305                 if (rc != 0) {
2306                         for (j = 0; j < i; ++j) {
2307                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2308                                                    sc->tx_mbuf_map[i]);
2309                         }
2310                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2311                         sc->tx_mbuf_tag = NULL;
2312
2313                         if_printf(ifp, "Unable to create "
2314                                   "%dth TX mbuf DMA map!\n", i);
2315                         return rc;
2316                 }
2317         }
2318
2319         /*
2320          * Create a DMA tag for the RX buffer descriptor chain,
2321          * allocate and clear the  memory, and fetch the physical
2322          * address of the blocks.
2323          */
2324         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2325                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2326                                 NULL, NULL,
2327                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2328                                 0, &sc->rx_bd_chain_tag);
2329         if (rc != 0) {
2330                 if_printf(ifp, "Could not allocate "
2331                           "RX descriptor chain DMA tag!\n");
2332                 return rc;
2333         }
2334
2335         for (i = 0; i < RX_PAGES; i++) {
2336                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2337                                       (void **)&sc->rx_bd_chain[i],
2338                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2339                                       BUS_DMA_COHERENT,
2340                                       &sc->rx_bd_chain_map[i]);
2341                 if (rc != 0) {
2342                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2343                                   "chain DMA memory!\n", i);
2344                         return rc;
2345                 }
2346
2347                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2348                                      sc->rx_bd_chain_map[i],
2349                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2350                                      bce_dma_map_addr, &busaddr,
2351                                      BUS_DMA_WAITOK);
2352                 if (rc != 0) {
2353                         if (rc == EINPROGRESS) {
2354                                 panic("%s coherent memory loading "
2355                                       "is still in progress!", ifp->if_xname);
2356                         }
2357                         if_printf(ifp, "Could not map %dth RX descriptor "
2358                                   "chain DMA memory!\n", i);
2359                         bus_dmamem_free(sc->rx_bd_chain_tag,
2360                                         sc->rx_bd_chain[i],
2361                                         sc->rx_bd_chain_map[i]);
2362                         sc->rx_bd_chain[i] = NULL;
2363                         return rc;
2364                 }
2365
2366                 sc->rx_bd_chain_paddr[i] = busaddr;
2367                 /* DRC - Fix for 64 bit systems. */
2368                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2369                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2370         }
2371
2372         /* Create a DMA tag for RX mbufs. */
2373         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2374                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2375                                 NULL, NULL,
2376                                 MCLBYTES, 1, MCLBYTES,
2377                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
2378                                 &sc->rx_mbuf_tag);
2379         if (rc != 0) {
2380                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2381                 return rc;
2382         }
2383
2384         /* Create DMA maps for the RX mbuf clusters. */
2385         for (i = 0; i < TOTAL_RX_BD; i++) {
2386                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2387                                        &sc->rx_mbuf_map[i]);
2388                 if (rc != 0) {
2389                         for (j = 0; j < i; ++j) {
2390                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2391                                                    sc->rx_mbuf_map[j]);
2392                         }
2393                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2394                         sc->rx_mbuf_tag = NULL;
2395
2396                         if_printf(ifp, "Unable to create "
2397                                   "%dth RX mbuf DMA map!\n", i);
2398                         return rc;
2399                 }
2400         }
2401         return 0;
2402 }
2403
2404
2405 /****************************************************************************/
2406 /* Firmware synchronization.                                                */
2407 /*                                                                          */
2408 /* Before performing certain events such as a chip reset, synchronize with  */
2409 /* the firmware first.                                                      */
2410 /*                                                                          */
2411 /* Returns:                                                                 */
2412 /*   0 for success, positive value for failure.                             */
2413 /****************************************************************************/
2414 static int
2415 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2416 {
2417         int i, rc = 0;
2418         uint32_t val;
2419
2420         /* Don't waste any time if we've timed out before. */
2421         if (sc->bce_fw_timed_out)
2422                 return EBUSY;
2423
2424         /* Increment the message sequence number. */
2425         sc->bce_fw_wr_seq++;
2426         msg_data |= sc->bce_fw_wr_seq;
2427
2428         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2429
2430         /* Send the message to the bootcode driver mailbox. */
2431         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2432
2433         /* Wait for the bootcode to acknowledge the message. */
2434         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2435                 /* Check for a response in the bootcode firmware mailbox. */
2436                 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2437                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2438                         break;
2439                 DELAY(1000);
2440         }
2441
2442         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2443         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2444             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2445                 if_printf(&sc->arpcom.ac_if,
2446                           "Firmware synchronization timeout! "
2447                           "msg_data = 0x%08X\n", msg_data);
2448
2449                 msg_data &= ~BCE_DRV_MSG_CODE;
2450                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2451
2452                 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2453
2454                 sc->bce_fw_timed_out = 1;
2455                 rc = EBUSY;
2456         }
2457         return rc;
2458 }
2459
2460
2461 /****************************************************************************/
2462 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2463 /*                                                                          */
2464 /* Returns:                                                                 */
2465 /*   Nothing.                                                               */
2466 /****************************************************************************/
2467 static void
2468 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2469                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2470 {
2471         int i;
2472         uint32_t val;
2473
2474         for (i = 0; i < rv2p_code_len; i += 8) {
2475                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2476                 rv2p_code++;
2477                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2478                 rv2p_code++;
2479
2480                 if (rv2p_proc == RV2P_PROC1) {
2481                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2482                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2483                 } else {
2484                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2485                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2486                 }
2487         }
2488
2489         /* Reset the processor, un-stall is done later. */
2490         if (rv2p_proc == RV2P_PROC1)
2491                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2492         else
2493                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2494 }
2495
2496
2497 /****************************************************************************/
2498 /* Load RISC processor firmware.                                            */
2499 /*                                                                          */
2500 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2501 /* associated with a particular processor.                                  */
2502 /*                                                                          */
2503 /* Returns:                                                                 */
2504 /*   Nothing.                                                               */
2505 /****************************************************************************/
2506 static void
2507 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2508                 struct fw_info *fw)
2509 {
2510         uint32_t offset, val;
2511         int j;
2512
2513         /* Halt the CPU. */
2514         val = REG_RD_IND(sc, cpu_reg->mode);
2515         val |= cpu_reg->mode_value_halt;
2516         REG_WR_IND(sc, cpu_reg->mode, val);
2517         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2518
2519         /* Load the Text area. */
2520         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2521         if (fw->text) {
2522                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2523                         REG_WR_IND(sc, offset, fw->text[j]);
2524         }
2525
2526         /* Load the Data area. */
2527         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2528         if (fw->data) {
2529                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2530                         REG_WR_IND(sc, offset, fw->data[j]);
2531         }
2532
2533         /* Load the SBSS area. */
2534         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2535         if (fw->sbss) {
2536                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2537                         REG_WR_IND(sc, offset, fw->sbss[j]);
2538         }
2539
2540         /* Load the BSS area. */
2541         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2542         if (fw->bss) {
2543                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2544                         REG_WR_IND(sc, offset, fw->bss[j]);
2545         }
2546
2547         /* Load the Read-Only area. */
2548         offset = cpu_reg->spad_base +
2549                 (fw->rodata_addr - cpu_reg->mips_view_base);
2550         if (fw->rodata) {
2551                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2552                         REG_WR_IND(sc, offset, fw->rodata[j]);
2553         }
2554
2555         /* Clear the pre-fetch instruction. */
2556         REG_WR_IND(sc, cpu_reg->inst, 0);
2557         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2558
2559         /* Start the CPU. */
2560         val = REG_RD_IND(sc, cpu_reg->mode);
2561         val &= ~cpu_reg->mode_value_halt;
2562         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2563         REG_WR_IND(sc, cpu_reg->mode, val);
2564 }
2565
2566
2567 /****************************************************************************/
2568 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs.                         */
2569 /*                                                                          */
2570 /* Loads the firmware for each CPU and starts the CPU.                      */
2571 /*                                                                          */
2572 /* Returns:                                                                 */
2573 /*   Nothing.                                                               */
2574 /****************************************************************************/
2575 static void
2576 bce_init_cpus(struct bce_softc *sc)
2577 {
2578         struct cpu_reg cpu_reg;
2579         struct fw_info fw;
2580
2581         /* Initialize the RV2P processor. */
2582         bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1);
2583         bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2);
2584
2585         /* Initialize the RX Processor. */
2586         cpu_reg.mode = BCE_RXP_CPU_MODE;
2587         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2588         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2589         cpu_reg.state = BCE_RXP_CPU_STATE;
2590         cpu_reg.state_value_clear = 0xffffff;
2591         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2592         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2593         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2594         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2595         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2596         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2597         cpu_reg.mips_view_base = 0x8000000;
2598
2599         fw.ver_major = bce_RXP_b06FwReleaseMajor;
2600         fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2601         fw.ver_fix = bce_RXP_b06FwReleaseFix;
2602         fw.start_addr = bce_RXP_b06FwStartAddr;
2603
2604         fw.text_addr = bce_RXP_b06FwTextAddr;
2605         fw.text_len = bce_RXP_b06FwTextLen;
2606         fw.text_index = 0;
2607         fw.text = bce_RXP_b06FwText;
2608
2609         fw.data_addr = bce_RXP_b06FwDataAddr;
2610         fw.data_len = bce_RXP_b06FwDataLen;
2611         fw.data_index = 0;
2612         fw.data = bce_RXP_b06FwData;
2613
2614         fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2615         fw.sbss_len = bce_RXP_b06FwSbssLen;
2616         fw.sbss_index = 0;
2617         fw.sbss = bce_RXP_b06FwSbss;
2618
2619         fw.bss_addr = bce_RXP_b06FwBssAddr;
2620         fw.bss_len = bce_RXP_b06FwBssLen;
2621         fw.bss_index = 0;
2622         fw.bss = bce_RXP_b06FwBss;
2623
2624         fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2625         fw.rodata_len = bce_RXP_b06FwRodataLen;
2626         fw.rodata_index = 0;
2627         fw.rodata = bce_RXP_b06FwRodata;
2628
2629         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2630         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2631
2632         /* Initialize the TX Processor. */
2633         cpu_reg.mode = BCE_TXP_CPU_MODE;
2634         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2635         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2636         cpu_reg.state = BCE_TXP_CPU_STATE;
2637         cpu_reg.state_value_clear = 0xffffff;
2638         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2639         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2640         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2641         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2642         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2643         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2644         cpu_reg.mips_view_base = 0x8000000;
2645
2646         fw.ver_major = bce_TXP_b06FwReleaseMajor;
2647         fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2648         fw.ver_fix = bce_TXP_b06FwReleaseFix;
2649         fw.start_addr = bce_TXP_b06FwStartAddr;
2650
2651         fw.text_addr = bce_TXP_b06FwTextAddr;
2652         fw.text_len = bce_TXP_b06FwTextLen;
2653         fw.text_index = 0;
2654         fw.text = bce_TXP_b06FwText;
2655
2656         fw.data_addr = bce_TXP_b06FwDataAddr;
2657         fw.data_len = bce_TXP_b06FwDataLen;
2658         fw.data_index = 0;
2659         fw.data = bce_TXP_b06FwData;
2660
2661         fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2662         fw.sbss_len = bce_TXP_b06FwSbssLen;
2663         fw.sbss_index = 0;
2664         fw.sbss = bce_TXP_b06FwSbss;
2665
2666         fw.bss_addr = bce_TXP_b06FwBssAddr;
2667         fw.bss_len = bce_TXP_b06FwBssLen;
2668         fw.bss_index = 0;
2669         fw.bss = bce_TXP_b06FwBss;
2670
2671         fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2672         fw.rodata_len = bce_TXP_b06FwRodataLen;
2673         fw.rodata_index = 0;
2674         fw.rodata = bce_TXP_b06FwRodata;
2675
2676         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2677         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2678
2679         /* Initialize the TX Patch-up Processor. */
2680         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2681         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2682         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2683         cpu_reg.state = BCE_TPAT_CPU_STATE;
2684         cpu_reg.state_value_clear = 0xffffff;
2685         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2686         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2687         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2688         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2689         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2690         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2691         cpu_reg.mips_view_base = 0x8000000;
2692
2693         fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2694         fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2695         fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2696         fw.start_addr = bce_TPAT_b06FwStartAddr;
2697
2698         fw.text_addr = bce_TPAT_b06FwTextAddr;
2699         fw.text_len = bce_TPAT_b06FwTextLen;
2700         fw.text_index = 0;
2701         fw.text = bce_TPAT_b06FwText;
2702
2703         fw.data_addr = bce_TPAT_b06FwDataAddr;
2704         fw.data_len = bce_TPAT_b06FwDataLen;
2705         fw.data_index = 0;
2706         fw.data = bce_TPAT_b06FwData;
2707
2708         fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2709         fw.sbss_len = bce_TPAT_b06FwSbssLen;
2710         fw.sbss_index = 0;
2711         fw.sbss = bce_TPAT_b06FwSbss;
2712
2713         fw.bss_addr = bce_TPAT_b06FwBssAddr;
2714         fw.bss_len = bce_TPAT_b06FwBssLen;
2715         fw.bss_index = 0;
2716         fw.bss = bce_TPAT_b06FwBss;
2717
2718         fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2719         fw.rodata_len = bce_TPAT_b06FwRodataLen;
2720         fw.rodata_index = 0;
2721         fw.rodata = bce_TPAT_b06FwRodata;
2722
2723         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2724         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2725
2726         /* Initialize the Completion Processor. */
2727         cpu_reg.mode = BCE_COM_CPU_MODE;
2728         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2729         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2730         cpu_reg.state = BCE_COM_CPU_STATE;
2731         cpu_reg.state_value_clear = 0xffffff;
2732         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2733         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2734         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2735         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2736         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2737         cpu_reg.spad_base = BCE_COM_SCRATCH;
2738         cpu_reg.mips_view_base = 0x8000000;
2739
2740         fw.ver_major = bce_COM_b06FwReleaseMajor;
2741         fw.ver_minor = bce_COM_b06FwReleaseMinor;
2742         fw.ver_fix = bce_COM_b06FwReleaseFix;
2743         fw.start_addr = bce_COM_b06FwStartAddr;
2744
2745         fw.text_addr = bce_COM_b06FwTextAddr;
2746         fw.text_len = bce_COM_b06FwTextLen;
2747         fw.text_index = 0;
2748         fw.text = bce_COM_b06FwText;
2749
2750         fw.data_addr = bce_COM_b06FwDataAddr;
2751         fw.data_len = bce_COM_b06FwDataLen;
2752         fw.data_index = 0;
2753         fw.data = bce_COM_b06FwData;
2754
2755         fw.sbss_addr = bce_COM_b06FwSbssAddr;
2756         fw.sbss_len = bce_COM_b06FwSbssLen;
2757         fw.sbss_index = 0;
2758         fw.sbss = bce_COM_b06FwSbss;
2759
2760         fw.bss_addr = bce_COM_b06FwBssAddr;
2761         fw.bss_len = bce_COM_b06FwBssLen;
2762         fw.bss_index = 0;
2763         fw.bss = bce_COM_b06FwBss;
2764
2765         fw.rodata_addr = bce_COM_b06FwRodataAddr;
2766         fw.rodata_len = bce_COM_b06FwRodataLen;
2767         fw.rodata_index = 0;
2768         fw.rodata = bce_COM_b06FwRodata;
2769
2770         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
2771         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2772 }
2773
2774
2775 /****************************************************************************/
2776 /* Initialize context memory.                                               */
2777 /*                                                                          */
2778 /* Clears the memory associated with each Context ID (CID).                 */
2779 /*                                                                          */
2780 /* Returns:                                                                 */
2781 /*   Nothing.                                                               */
2782 /****************************************************************************/
2783 static void
2784 bce_init_ctx(struct bce_softc *sc)
2785 {
2786         uint32_t vcid = 96;
2787
2788         while (vcid) {
2789                 uint32_t vcid_addr, pcid_addr, offset;
2790                 int i;
2791
2792                 vcid--;
2793
2794                 vcid_addr = GET_CID_ADDR(vcid);
2795                 pcid_addr = vcid_addr;
2796
2797                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2798                         vcid_addr += (i << PHY_CTX_SHIFT);
2799                         pcid_addr += (i << PHY_CTX_SHIFT);
2800
2801                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
2802                         REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr);
2803
2804                         /* Zero out the context. */
2805                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2806                                 CTX_WR(sc, vcid_addr, offset, 0);
2807                 }
2808         }
2809 }
2810
2811
2812 /****************************************************************************/
2813 /* Fetch the permanent MAC address of the controller.                       */
2814 /*                                                                          */
2815 /* Returns:                                                                 */
2816 /*   Nothing.                                                               */
2817 /****************************************************************************/
2818 static void
2819 bce_get_mac_addr(struct bce_softc *sc)
2820 {
2821         uint32_t mac_lo = 0, mac_hi = 0;
2822
2823         /*
2824          * The NetXtreme II bootcode populates various NIC
2825          * power-on and runtime configuration items in a
2826          * shared memory area.  The factory configured MAC
2827          * address is available from both NVRAM and the
2828          * shared memory area so we'll read the value from
2829          * shared memory for speed.
2830          */
2831
2832         mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
2833         mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
2834
2835         if (mac_lo == 0 && mac_hi == 0) {
2836                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
2837         } else {
2838                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
2839                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
2840                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
2841                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
2842                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
2843                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
2844         }
2845
2846         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
2847 }
2848
2849
2850 /****************************************************************************/
2851 /* Program the MAC address.                                                 */
2852 /*                                                                          */
2853 /* Returns:                                                                 */
2854 /*   Nothing.                                                               */
2855 /****************************************************************************/
2856 static void
2857 bce_set_mac_addr(struct bce_softc *sc)
2858 {
2859         const uint8_t *mac_addr = sc->eaddr;
2860         uint32_t val;
2861
2862         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
2863                 sc->eaddr, ":");
2864
2865         val = (mac_addr[0] << 8) | mac_addr[1];
2866         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
2867
2868         val = (mac_addr[2] << 24) |
2869               (mac_addr[3] << 16) |
2870               (mac_addr[4] << 8) |
2871               mac_addr[5];
2872         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
2873 }
2874
2875
2876 /****************************************************************************/
2877 /* Stop the controller.                                                     */
2878 /*                                                                          */
2879 /* Returns:                                                                 */
2880 /*   Nothing.                                                               */
2881 /****************************************************************************/
2882 static void
2883 bce_stop(struct bce_softc *sc)
2884 {
2885         struct ifnet *ifp = &sc->arpcom.ac_if;
2886         struct mii_data *mii = device_get_softc(sc->bce_miibus);
2887         struct ifmedia_entry *ifm;
2888         int mtmp, itmp;
2889
2890         ASSERT_SERIALIZED(ifp->if_serializer);
2891
2892         callout_stop(&sc->bce_stat_ch);
2893
2894         /* Disable the transmit/receive blocks. */
2895         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff);
2896         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2897         DELAY(20);
2898
2899         bce_disable_intr(sc);
2900
2901         /* Tell firmware that the driver is going away. */
2902         bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL);
2903
2904         /* Free the RX lists. */
2905         bce_free_rx_chain(sc);
2906
2907         /* Free TX buffers. */
2908         bce_free_tx_chain(sc);
2909
2910         /*
2911          * Isolate/power down the PHY, but leave the media selection
2912          * unchanged so that things will be put back to normal when
2913          * we bring the interface back up.
2914          *
2915          * 'mii' may be NULL if bce_stop() is called by bce_detach().
2916          */
2917         if (mii != NULL) {
2918                 itmp = ifp->if_flags;
2919                 ifp->if_flags |= IFF_UP;
2920                 ifm = mii->mii_media.ifm_cur;
2921                 mtmp = ifm->ifm_media;
2922                 ifm->ifm_media = IFM_ETHER | IFM_NONE;
2923                 mii_mediachg(mii);
2924                 ifm->ifm_media = mtmp;
2925                 ifp->if_flags = itmp;
2926         }
2927
2928         sc->bce_link = 0;
2929         sc->bce_coalchg_mask = 0;
2930
2931         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2932         ifp->if_timer = 0;
2933
2934         bce_mgmt_init(sc);
2935 }
2936
2937
2938 static int
2939 bce_reset(struct bce_softc *sc, uint32_t reset_code)
2940 {
2941         uint32_t val;
2942         int i, rc = 0;
2943
2944         /* Wait for pending PCI transactions to complete. */
2945         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
2946                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2947                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2948                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2949                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2950         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2951         DELAY(5);
2952
2953         /* Assume bootcode is running. */
2954         sc->bce_fw_timed_out = 0;
2955
2956         /* Give the firmware a chance to prepare for the reset. */
2957         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
2958         if (rc) {
2959                 if_printf(&sc->arpcom.ac_if,
2960                           "Firmware is not ready for reset\n");
2961                 return rc;
2962         }
2963
2964         /* Set a firmware reminder that this is a soft reset. */
2965         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
2966                    BCE_DRV_RESET_SIGNATURE_MAGIC);
2967
2968         /* Dummy read to force the chip to complete all current transactions. */
2969         val = REG_RD(sc, BCE_MISC_ID);
2970
2971         /* Chip reset. */
2972         val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2973               BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2974               BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2975         REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
2976
2977         /* Allow up to 30us for reset to complete. */
2978         for (i = 0; i < 10; i++) {
2979                 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
2980                 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2981                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2982                         break;
2983                 }
2984                 DELAY(10);
2985         }
2986
2987         /* Check that reset completed successfully. */
2988         if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2989                    BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2990                 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
2991                 return EBUSY;
2992         }
2993
2994         /* Make sure byte swapping is properly configured. */
2995         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
2996         if (val != 0x01020304) {
2997                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
2998                 return ENODEV;
2999         }
3000
3001         /* Just completed a reset, assume that firmware is running again. */
3002         sc->bce_fw_timed_out = 0;
3003
3004         /* Wait for the firmware to finish its initialization. */
3005         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3006         if (rc) {
3007                 if_printf(&sc->arpcom.ac_if,
3008                           "Firmware did not complete initialization!\n");
3009         }
3010         return rc;
3011 }
3012
3013
3014 static int
3015 bce_chipinit(struct bce_softc *sc)
3016 {
3017         uint32_t val;
3018         int rc = 0;
3019
3020         /* Make sure the interrupt is not active. */
3021         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3022
3023         /*
3024          * Initialize DMA byte/word swapping, configure the number of DMA
3025          * channels and PCI clock compensation delay.
3026          */
3027         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3028               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3029 #if BYTE_ORDER == BIG_ENDIAN
3030               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3031 #endif
3032               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3033               DMA_READ_CHANS << 12 |
3034               DMA_WRITE_CHANS << 16;
3035
3036         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3037
3038         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3039                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3040
3041         /*
3042          * This setting resolves a problem observed on certain Intel PCI
3043          * chipsets that cannot handle multiple outstanding DMA operations.
3044          * See errata E9_5706A1_65.
3045          */
3046         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3047             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3048             !(sc->bce_flags & BCE_PCIX_FLAG))
3049                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3050
3051         REG_WR(sc, BCE_DMA_CONFIG, val);
3052
3053         /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */
3054         if (sc->bce_flags & BCE_PCIX_FLAG) {
3055                 uint16_t cmd;
3056
3057                 cmd = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2);
3058                 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, cmd & ~0x2, 2);
3059         }
3060
3061         /* Enable the RX_V2P and Context state machines before access. */
3062         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3063                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3064                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3065                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3066
3067         /* Initialize context mapping and zero out the quick contexts. */
3068         bce_init_ctx(sc);
3069
3070         /* Initialize the on-boards CPUs */
3071         bce_init_cpus(sc);
3072
3073         /* Prepare NVRAM for access. */
3074         rc = bce_init_nvram(sc);
3075         if (rc != 0)
3076                 return rc;
3077
3078         /* Set the kernel bypass block size */
3079         val = REG_RD(sc, BCE_MQ_CONFIG);
3080         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3081         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3082         REG_WR(sc, BCE_MQ_CONFIG, val);
3083
3084         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3085         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3086         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3087
3088         /* Set the page size and clear the RV2P processor stall bits. */
3089         val = (BCM_PAGE_BITS - 8) << 24;
3090         REG_WR(sc, BCE_RV2P_CONFIG, val);
3091
3092         /* Configure page size. */
3093         val = REG_RD(sc, BCE_TBDR_CONFIG);
3094         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3095         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3096         REG_WR(sc, BCE_TBDR_CONFIG, val);
3097
3098         return 0;
3099 }
3100
3101
3102 /****************************************************************************/
3103 /* Initialize the controller in preparation to send/receive traffic.        */
3104 /*                                                                          */
3105 /* Returns:                                                                 */
3106 /*   0 for success, positive value for failure.                             */
3107 /****************************************************************************/
3108 static int
3109 bce_blockinit(struct bce_softc *sc)
3110 {
3111         uint32_t reg, val;
3112         int rc = 0;
3113
3114         /* Load the hardware default MAC address. */
3115         bce_set_mac_addr(sc);
3116
3117         /* Set the Ethernet backoff seed value */
3118         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3119               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3120         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3121
3122         sc->last_status_idx = 0;
3123         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3124
3125         /* Set up link change interrupt generation. */
3126         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3127
3128         /* Program the physical address of the status block. */
3129         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3130         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3131
3132         /* Program the physical address of the statistics block. */
3133         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3134                BCE_ADDR_LO(sc->stats_block_paddr));
3135         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3136                BCE_ADDR_HI(sc->stats_block_paddr));
3137
3138         /* Program various host coalescing parameters. */
3139         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3140                (sc->bce_tx_quick_cons_trip_int << 16) |
3141                sc->bce_tx_quick_cons_trip);
3142         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3143                (sc->bce_rx_quick_cons_trip_int << 16) |
3144                sc->bce_rx_quick_cons_trip);
3145         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3146                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3147         REG_WR(sc, BCE_HC_TX_TICKS,
3148                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3149         REG_WR(sc, BCE_HC_RX_TICKS,
3150                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3151         REG_WR(sc, BCE_HC_COM_TICKS,
3152                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3153         REG_WR(sc, BCE_HC_CMD_TICKS,
3154                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3155         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3156         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3157         REG_WR(sc, BCE_HC_CONFIG,
3158                BCE_HC_CONFIG_TX_TMR_MODE |
3159                BCE_HC_CONFIG_COLLECT_STATS);
3160
3161         /* Clear the internal statistics counters. */
3162         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3163
3164         /* Verify that bootcode is running. */
3165         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3166
3167         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3168                 if_printf(&sc->arpcom.ac_if,
3169                           "%s(%d): Simulating bootcode failure.\n",
3170                           __FILE__, __LINE__);
3171                 reg = 0);
3172
3173         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3174             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3175                 if_printf(&sc->arpcom.ac_if,
3176                           "Bootcode not running! Found: 0x%08X, "
3177                           "Expected: 08%08X\n",
3178                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3179                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3180                 return ENODEV;
3181         }
3182
3183         /* Check if any management firmware is running. */
3184         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
3185         if (reg & (BCE_PORT_FEATURE_ASF_ENABLED |
3186                    BCE_PORT_FEATURE_IMD_ENABLED)) {
3187                 DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n");
3188                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
3189         }
3190
3191         sc->bce_fw_ver =
3192                 REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV);
3193         DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver);
3194
3195         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3196         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3197
3198         /* Enable link state change interrupt generation. */
3199         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3200
3201         /* Enable all remaining blocks in the MAC. */
3202         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff);
3203         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3204         DELAY(20);
3205
3206         return 0;
3207 }
3208
3209
3210 /****************************************************************************/
3211 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3212 /*                                                                          */
3213 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3214 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3215 /* necessary.                                                               */
3216 /*                                                                          */
3217 /* Returns:                                                                 */
3218 /*   0 for success, positive value for failure.                             */
3219 /****************************************************************************/
3220 static int
3221 bce_newbuf_std(struct bce_softc *sc, struct mbuf *m,
3222                uint16_t *prod, uint16_t *chain_prod, uint32_t *prod_bseq)
3223 {
3224         bus_dmamap_t map;
3225         struct bce_dmamap_arg ctx;
3226         bus_dma_segment_t seg;
3227         struct mbuf *m_new;
3228         struct rx_bd *rxbd;
3229         int error;
3230 #ifdef BCE_DEBUG
3231         uint16_t debug_chain_prod = *chain_prod;
3232 #endif
3233
3234         /* Make sure the inputs are valid. */
3235         DBRUNIF((*chain_prod > MAX_RX_BD),
3236                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3237                           "RX producer out of range: 0x%04X > 0x%04X\n",
3238                           __FILE__, __LINE__,
3239                           *chain_prod, (uint16_t)MAX_RX_BD));
3240
3241         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3242                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3243
3244         if (m == NULL) {
3245                 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3246                         if_printf(&sc->arpcom.ac_if, "%s(%d): "
3247                                   "Simulating mbuf allocation failure.\n",
3248                                   __FILE__, __LINE__);
3249                         sc->mbuf_alloc_failed++;
3250                         return ENOBUFS);
3251
3252                 /* This is a new mbuf allocation. */
3253                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
3254                 if (m_new == NULL)
3255                         return ENOBUFS;
3256                 DBRUNIF(1, sc->rx_mbuf_alloc++);
3257         } else {
3258                 m_new = m;
3259                 m_new->m_data = m_new->m_ext.ext_buf;
3260         }
3261         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3262
3263         /* Map the mbuf cluster into device memory. */
3264         map = sc->rx_mbuf_map[*chain_prod];
3265
3266         ctx.bce_maxsegs = 1;
3267         ctx.bce_segs = &seg;
3268         error = bus_dmamap_load_mbuf(sc->rx_mbuf_tag, map, m_new,
3269                                      bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
3270         if (error || ctx.bce_maxsegs == 0) {
3271                 if_printf(&sc->arpcom.ac_if,
3272                           "Error mapping mbuf into RX chain!\n");
3273
3274                 if (m == NULL)
3275                         m_freem(m_new);
3276
3277                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3278                 return ENOBUFS;
3279         }
3280
3281         /* Watch for overflow. */
3282         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3283                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3284                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3285                           __FILE__, __LINE__, sc->free_rx_bd,
3286                           (uint16_t)USABLE_RX_BD));
3287
3288         /* Update some debug statistic counters */
3289         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3290                 sc->rx_low_watermark = sc->free_rx_bd);
3291         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3292
3293         /* Setup the rx_bd for the first segment. */
3294         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
3295
3296         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(seg.ds_addr));
3297         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(seg.ds_addr));
3298         rxbd->rx_bd_len = htole32(seg.ds_len);
3299         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3300         *prod_bseq += seg.ds_len;
3301
3302         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3303
3304         /* Save the mbuf and update our counter. */
3305         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3306         sc->free_rx_bd--;
3307
3308         DBRUN(BCE_VERBOSE_RECV,
3309               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3310
3311         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3312                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3313
3314         return 0;
3315 }
3316
3317
3318 /****************************************************************************/
3319 /* Allocate memory and initialize the TX data structures.                   */
3320 /*                                                                          */
3321 /* Returns:                                                                 */
3322 /*   0 for success, positive value for failure.                             */
3323 /****************************************************************************/
3324 static int
3325 bce_init_tx_chain(struct bce_softc *sc)
3326 {
3327         struct tx_bd *txbd;
3328         uint32_t val;
3329         int i, rc = 0;
3330
3331         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3332
3333         /* Set the initial TX producer/consumer indices. */
3334         sc->tx_prod = 0;
3335         sc->tx_cons = 0;
3336         sc->tx_prod_bseq   = 0;
3337         sc->used_tx_bd = 0;
3338         sc->max_tx_bd = USABLE_TX_BD;
3339         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3340         DBRUNIF(1, sc->tx_full_count = 0);
3341
3342         /*
3343          * The NetXtreme II supports a linked-list structre called
3344          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3345          * consists of a series of 1 or more chain pages, each of which
3346          * consists of a fixed number of BD entries.
3347          * The last BD entry on each page is a pointer to the next page
3348          * in the chain, and the last pointer in the BD chain
3349          * points back to the beginning of the chain.
3350          */
3351
3352         /* Set the TX next pointer chain entries. */
3353         for (i = 0; i < TX_PAGES; i++) {
3354                 int j;
3355
3356                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3357
3358                 /* Check if we've reached the last page. */
3359                 if (i == (TX_PAGES - 1))
3360                         j = 0;
3361                 else
3362                         j = i + 1;
3363
3364                 txbd->tx_bd_haddr_hi =
3365                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3366                 txbd->tx_bd_haddr_lo =
3367                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3368         }
3369
3370         /* Initialize the context ID for an L2 TX chain. */
3371         val = BCE_L2CTX_TYPE_TYPE_L2;
3372         val |= BCE_L2CTX_TYPE_SIZE_L2;
3373         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val);
3374
3375         val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3376         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val);
3377
3378         /* Point the hardware to the first page in the chain. */
3379         val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3380         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val);
3381         val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3382         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val);
3383
3384         DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
3385
3386         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3387
3388         return(rc);
3389 }
3390
3391
3392 /****************************************************************************/
3393 /* Free memory and clear the TX data structures.                            */
3394 /*                                                                          */
3395 /* Returns:                                                                 */
3396 /*   Nothing.                                                               */
3397 /****************************************************************************/
3398 static void
3399 bce_free_tx_chain(struct bce_softc *sc)
3400 {
3401         int i;
3402
3403         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3404
3405         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3406         for (i = 0; i < TOTAL_TX_BD; i++) {
3407                 if (sc->tx_mbuf_ptr[i] != NULL) {
3408                         bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i],
3409                                         BUS_DMASYNC_POSTWRITE);
3410                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3411                         m_freem(sc->tx_mbuf_ptr[i]);
3412                         sc->tx_mbuf_ptr[i] = NULL;
3413                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3414                 }
3415         }
3416
3417         /* Clear each TX chain page. */
3418         for (i = 0; i < TX_PAGES; i++)
3419                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3420         sc->used_tx_bd = 0;
3421
3422         /* Check if we lost any mbufs in the process. */
3423         DBRUNIF((sc->tx_mbuf_alloc),
3424                 if_printf(&sc->arpcom.ac_if,
3425                           "%s(%d): Memory leak! "
3426                           "Lost %d mbufs from tx chain!\n",
3427                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3428
3429         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3430 }
3431
3432
3433 /****************************************************************************/
3434 /* Allocate memory and initialize the RX data structures.                   */
3435 /*                                                                          */
3436 /* Returns:                                                                 */
3437 /*   0 for success, positive value for failure.                             */
3438 /****************************************************************************/
3439 static int
3440 bce_init_rx_chain(struct bce_softc *sc)
3441 {
3442         struct rx_bd *rxbd;
3443         int i, rc = 0;
3444         uint16_t prod, chain_prod;
3445         uint32_t prod_bseq, val;
3446
3447         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3448
3449         /* Initialize the RX producer and consumer indices. */
3450         sc->rx_prod = 0;
3451         sc->rx_cons = 0;
3452         sc->rx_prod_bseq = 0;
3453         sc->free_rx_bd = USABLE_RX_BD;
3454         sc->max_rx_bd = USABLE_RX_BD;
3455         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3456         DBRUNIF(1, sc->rx_empty_count = 0);
3457
3458         /* Initialize the RX next pointer chain entries. */
3459         for (i = 0; i < RX_PAGES; i++) {
3460                 int j;
3461
3462                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3463
3464                 /* Check if we've reached the last page. */
3465                 if (i == (RX_PAGES - 1))
3466                         j = 0;
3467                 else
3468                         j = i + 1;
3469
3470                 /* Setup the chain page pointers. */
3471                 rxbd->rx_bd_haddr_hi =
3472                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3473                 rxbd->rx_bd_haddr_lo =
3474                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3475         }
3476
3477         /* Initialize the context ID for an L2 RX chain. */
3478         val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3479         val |= BCE_L2CTX_CTX_TYPE_SIZE_L2;
3480         val |= 0x02 << 8;
3481         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val);
3482
3483         /* Point the hardware to the first page in the chain. */
3484         /* XXX shouldn't this after RX descriptor initialization? */
3485         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3486         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val);
3487         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3488         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val);
3489
3490         /* Allocate mbuf clusters for the rx_bd chain. */
3491         prod = prod_bseq = 0;
3492         while (prod < TOTAL_RX_BD) {
3493                 chain_prod = RX_CHAIN_IDX(prod);
3494                 if (bce_newbuf_std(sc, NULL, &prod, &chain_prod, &prod_bseq)) {
3495                         if_printf(&sc->arpcom.ac_if,
3496                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
3497                                   chain_prod);
3498                         rc = ENOBUFS;
3499                         break;
3500                 }
3501                 prod = NEXT_RX_BD(prod);
3502         }
3503
3504         /* Save the RX chain producer index. */
3505         sc->rx_prod = prod;
3506         sc->rx_prod_bseq = prod_bseq;
3507
3508         /* Tell the chip about the waiting rx_bd's. */
3509         REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
3510         REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3511
3512         DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD));
3513
3514         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3515
3516         return(rc);
3517 }
3518
3519
3520 /****************************************************************************/
3521 /* Free memory and clear the RX data structures.                            */
3522 /*                                                                          */
3523 /* Returns:                                                                 */
3524 /*   Nothing.                                                               */
3525 /****************************************************************************/
3526 static void
3527 bce_free_rx_chain(struct bce_softc *sc)
3528 {
3529         int i;
3530
3531         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3532
3533         /* Free any mbufs still in the RX mbuf chain. */
3534         for (i = 0; i < TOTAL_RX_BD; i++) {
3535                 if (sc->rx_mbuf_ptr[i] != NULL) {
3536                         bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i],
3537                                         BUS_DMASYNC_POSTREAD);
3538                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3539                         m_freem(sc->rx_mbuf_ptr[i]);
3540                         sc->rx_mbuf_ptr[i] = NULL;
3541                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3542                 }
3543         }
3544
3545         /* Clear each RX chain page. */
3546         for (i = 0; i < RX_PAGES; i++)
3547                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3548
3549         /* Check if we lost any mbufs in the process. */
3550         DBRUNIF((sc->rx_mbuf_alloc),
3551                 if_printf(&sc->arpcom.ac_if,
3552                           "%s(%d): Memory leak! "
3553                           "Lost %d mbufs from rx chain!\n",
3554                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
3555
3556         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3557 }
3558
3559
3560 /****************************************************************************/
3561 /* Set media options.                                                       */
3562 /*                                                                          */
3563 /* Returns:                                                                 */
3564 /*   0 for success, positive value for failure.                             */
3565 /****************************************************************************/
3566 static int
3567 bce_ifmedia_upd(struct ifnet *ifp)
3568 {
3569         struct bce_softc *sc = ifp->if_softc;
3570         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3571
3572         /*
3573          * 'mii' will be NULL, when this function is called on following
3574          * code path: bce_attach() -> bce_mgmt_init()
3575          */
3576         if (mii != NULL) {
3577                 /* Make sure the MII bus has been enumerated. */
3578                 sc->bce_link = 0;
3579                 if (mii->mii_instance) {
3580                         struct mii_softc *miisc;
3581
3582                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3583                                 mii_phy_reset(miisc);
3584                 }
3585                 mii_mediachg(mii);
3586         }
3587         return 0;
3588 }
3589
3590
3591 /****************************************************************************/
3592 /* Reports current media status.                                            */
3593 /*                                                                          */
3594 /* Returns:                                                                 */
3595 /*   Nothing.                                                               */
3596 /****************************************************************************/
3597 static void
3598 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3599 {
3600         struct bce_softc *sc = ifp->if_softc;
3601         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3602
3603         mii_pollstat(mii);
3604         ifmr->ifm_active = mii->mii_media_active;
3605         ifmr->ifm_status = mii->mii_media_status;
3606 }
3607
3608
3609 /****************************************************************************/
3610 /* Handles PHY generated interrupt events.                                  */
3611 /*                                                                          */
3612 /* Returns:                                                                 */
3613 /*   Nothing.                                                               */
3614 /****************************************************************************/
3615 static void
3616 bce_phy_intr(struct bce_softc *sc)
3617 {
3618         uint32_t new_link_state, old_link_state;
3619         struct ifnet *ifp = &sc->arpcom.ac_if;
3620
3621         ASSERT_SERIALIZED(ifp->if_serializer);
3622
3623         new_link_state = sc->status_block->status_attn_bits &
3624                          STATUS_ATTN_BITS_LINK_STATE;
3625         old_link_state = sc->status_block->status_attn_bits_ack &
3626                          STATUS_ATTN_BITS_LINK_STATE;
3627
3628         /* Handle any changes if the link state has changed. */
3629         if (new_link_state != old_link_state) { /* XXX redundant? */
3630                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
3631
3632                 sc->bce_link = 0;
3633                 callout_stop(&sc->bce_stat_ch);
3634                 bce_tick_serialized(sc);
3635
3636                 /* Update the status_attn_bits_ack field in the status block. */
3637                 if (new_link_state) {
3638                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
3639                                STATUS_ATTN_BITS_LINK_STATE);
3640                         if (bootverbose)
3641                                 if_printf(ifp, "Link is now UP.\n");
3642                 } else {
3643                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
3644                                STATUS_ATTN_BITS_LINK_STATE);
3645                         if (bootverbose)
3646                                 if_printf(ifp, "Link is now DOWN.\n");
3647                 }
3648         }
3649
3650         /* Acknowledge the link change interrupt. */
3651         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
3652 }
3653
3654
3655 /****************************************************************************/
3656 /* Reads the receive consumer value from the status block (skipping over    */
3657 /* chain page pointer if necessary).                                        */
3658 /*                                                                          */
3659 /* Returns:                                                                 */
3660 /*   hw_cons                                                                */
3661 /****************************************************************************/
3662 static __inline uint16_t
3663 bce_get_hw_rx_cons(struct bce_softc *sc)
3664 {
3665         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
3666
3667         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
3668                 hw_cons++;
3669         return hw_cons;
3670 }
3671
3672
3673 /****************************************************************************/
3674 /* Handles received frame interrupt events.                                 */
3675 /*                                                                          */
3676 /* Returns:                                                                 */
3677 /*   Nothing.                                                               */
3678 /****************************************************************************/
3679 static void
3680 bce_rx_intr(struct bce_softc *sc, int count)
3681 {
3682         struct ifnet *ifp = &sc->arpcom.ac_if;
3683         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
3684         uint32_t sw_prod_bseq;
3685         struct mbuf_chain chain[MAXCPU];
3686
3687         ASSERT_SERIALIZED(ifp->if_serializer);
3688
3689         ether_input_chain_init(chain);
3690
3691         DBRUNIF(1, sc->rx_interrupts++);
3692
3693         /* Get the hardware's view of the RX consumer index. */
3694         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
3695
3696         /* Get working copies of the driver's view of the RX indices. */
3697         sw_cons = sc->rx_cons;
3698         sw_prod = sc->rx_prod;
3699         sw_prod_bseq = sc->rx_prod_bseq;
3700
3701         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
3702                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
3703                 __func__, sw_prod, sw_cons, sw_prod_bseq);
3704
3705         /* Prevent speculative reads from getting ahead of the status block. */
3706         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
3707                           BUS_SPACE_BARRIER_READ);
3708
3709         /* Update some debug statistics counters */
3710         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3711                 sc->rx_low_watermark = sc->free_rx_bd);
3712         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3713
3714         /* Scan through the receive chain as long as there is work to do. */
3715         while (sw_cons != hw_cons) {
3716                 struct mbuf *m = NULL;
3717                 struct l2_fhdr *l2fhdr = NULL;
3718                 struct rx_bd *rxbd;
3719                 unsigned int len;
3720                 uint32_t status = 0;
3721
3722 #ifdef DEVICE_POLLING
3723                 if (count >= 0 && count-- == 0) {
3724                         sc->hw_rx_cons = sw_cons;
3725                         break;
3726                 }
3727 #endif
3728
3729                 /*
3730                  * Convert the producer/consumer indices
3731                  * to an actual rx_bd index.
3732                  */
3733                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
3734                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
3735
3736                 /* Get the used rx_bd. */
3737                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
3738                                        [RX_IDX(sw_chain_cons)];
3739                 sc->free_rx_bd++;
3740
3741                 DBRUN(BCE_VERBOSE_RECV,
3742                       if_printf(ifp, "%s(): ", __func__);
3743                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
3744
3745                 /* The mbuf is stored with the last rx_bd entry of a packet. */
3746                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
3747                         /* Validate that this is the last rx_bd. */
3748                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
3749                                 if_printf(ifp, "%s(%d): "
3750                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
3751                                 __FILE__, __LINE__, sw_chain_cons);
3752                                 bce_breakpoint(sc));
3753
3754                         /*
3755                          * ToDo: If the received packet is small enough
3756                          * to fit into a single, non-M_EXT mbuf,
3757                          * allocate a new mbuf here, copy the data to
3758                          * that mbuf, and recycle the mapped jumbo frame.
3759                          */
3760
3761                         /* Unmap the mbuf from DMA space. */
3762                         bus_dmamap_sync(sc->rx_mbuf_tag,
3763                                         sc->rx_mbuf_map[sw_chain_cons],
3764                                         BUS_DMASYNC_POSTREAD);
3765                         bus_dmamap_unload(sc->rx_mbuf_tag,
3766                                           sc->rx_mbuf_map[sw_chain_cons]);
3767
3768                         /* Remove the mbuf from the driver's chain. */
3769                         m = sc->rx_mbuf_ptr[sw_chain_cons];
3770                         sc->rx_mbuf_ptr[sw_chain_cons] = NULL;
3771
3772                         /*
3773                          * Frames received on the NetXteme II are prepended
3774                          * with an l2_fhdr structure which provides status
3775                          * information about the received frame (including
3776                          * VLAN tags and checksum info).  The frames are also
3777                          * automatically adjusted to align the IP header
3778                          * (i.e. two null bytes are inserted before the
3779                          * Ethernet header).
3780                          */
3781                         l2fhdr = mtod(m, struct l2_fhdr *);
3782
3783                         len = l2fhdr->l2_fhdr_pkt_len;
3784                         status = l2fhdr->l2_fhdr_status;
3785
3786                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
3787                                 if_printf(ifp,
3788                                 "Simulating l2_fhdr status error.\n");
3789                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
3790
3791                         /* Watch for unusual sized frames. */
3792                         DBRUNIF((len < BCE_MIN_MTU ||
3793                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
3794                                 if_printf(ifp,
3795                                 "%s(%d): Unusual frame size found. "
3796                                 "Min(%d), Actual(%d), Max(%d)\n",
3797                                 __FILE__, __LINE__,
3798                                 (int)BCE_MIN_MTU, len,
3799                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
3800                                 bce_dump_mbuf(sc, m);
3801                                 bce_breakpoint(sc));
3802
3803                         len -= ETHER_CRC_LEN;
3804
3805                         /* Check the received frame for errors. */
3806                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
3807                                       L2_FHDR_ERRORS_PHY_DECODE |
3808                                       L2_FHDR_ERRORS_ALIGNMENT |
3809                                       L2_FHDR_ERRORS_TOO_SHORT |
3810                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
3811                                 ifp->if_ierrors++;
3812                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
3813
3814                                 /* Reuse the mbuf for a new frame. */
3815                                 if (bce_newbuf_std(sc, m, &sw_prod,
3816                                                    &sw_chain_prod,
3817                                                    &sw_prod_bseq)) {
3818                                         DBRUNIF(1, bce_breakpoint(sc));
3819                                         /* XXX */
3820                                         panic("%s: Can't reuse RX mbuf!\n",
3821                                               ifp->if_xname);
3822                                 }
3823                                 m = NULL;
3824                                 goto bce_rx_int_next_rx;
3825                         }
3826
3827                         /*
3828                          * Get a new mbuf for the rx_bd.   If no new
3829                          * mbufs are available then reuse the current mbuf,
3830                          * log an ierror on the interface, and generate
3831                          * an error in the system log.
3832                          */
3833                         if (bce_newbuf_std(sc, NULL, &sw_prod, &sw_chain_prod,
3834                                            &sw_prod_bseq)) {
3835                                 DBRUN(BCE_WARN,
3836                                       if_printf(ifp,
3837                                       "%s(%d): Failed to allocate new mbuf, "
3838                                       "incoming frame dropped!\n",
3839                                       __FILE__, __LINE__));
3840
3841                                 ifp->if_ierrors++;
3842
3843                                 /* Try and reuse the exisitng mbuf. */
3844                                 if (bce_newbuf_std(sc, m, &sw_prod,
3845                                                    &sw_chain_prod,
3846                                                    &sw_prod_bseq)) {
3847                                         DBRUNIF(1, bce_breakpoint(sc));
3848                                         /* XXX */
3849                                         panic("%s: Double mbuf allocation "
3850                                               "failure!", ifp->if_xname);
3851                                 }
3852                                 m = NULL;
3853                                 goto bce_rx_int_next_rx;
3854                         }
3855
3856                         /*
3857                          * Skip over the l2_fhdr when passing
3858                          * the data up the stack.
3859                          */
3860                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
3861
3862                         m->m_pkthdr.len = m->m_len = len;
3863                         m->m_pkthdr.rcvif = ifp;
3864
3865                         DBRUN(BCE_VERBOSE_RECV,
3866                               struct ether_header *eh;
3867                               eh = mtod(m, struct ether_header *);
3868                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
3869                                         "type: 0x%04X\n", __func__,
3870                                         eh->ether_dhost, ":",
3871                                         eh->ether_shost, ":",
3872                                         htons(eh->ether_type)));
3873
3874                         /* Validate the checksum if offload enabled. */
3875                         if (ifp->if_capenable & IFCAP_RXCSUM) {
3876                                 /* Check for an IP datagram. */
3877                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
3878                                         m->m_pkthdr.csum_flags |=
3879                                                 CSUM_IP_CHECKED;
3880
3881                                         /* Check if the IP checksum is valid. */
3882                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
3883                                              0xffff) == 0) {
3884                                                 m->m_pkthdr.csum_flags |=
3885                                                         CSUM_IP_VALID;
3886                                         } else {
3887                                                 DBPRINT(sc, BCE_WARN_RECV,
3888                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
3889                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
3890                                         }
3891                                 }
3892
3893                                 /* Check for a valid TCP/UDP frame. */
3894                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3895                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
3896
3897                                         /* Check for a good TCP/UDP checksum. */
3898                                         if ((status &
3899                                              (L2_FHDR_ERRORS_TCP_XSUM |
3900                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
3901                                                 m->m_pkthdr.csum_data =
3902                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
3903                                                 m->m_pkthdr.csum_flags |=
3904                                                         CSUM_DATA_VALID |
3905                                                         CSUM_PSEUDO_HDR;
3906                                         } else {
3907                                                 DBPRINT(sc, BCE_WARN_RECV,
3908                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
3909                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
3910                                         }
3911                                 }
3912                         }
3913
3914                         ifp->if_ipackets++;
3915 bce_rx_int_next_rx:
3916                         sw_prod = NEXT_RX_BD(sw_prod);
3917                 }
3918
3919                 sw_cons = NEXT_RX_BD(sw_cons);
3920
3921                 /* If we have a packet, pass it up the stack */
3922                 if (m) {
3923                         DBPRINT(sc, BCE_VERBOSE_RECV,
3924                                 "%s(): Passing received frame up.\n", __func__);
3925
3926                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
3927                                 m->m_flags |= M_VLANTAG;
3928                                 m->m_pkthdr.ether_vlantag =
3929                                         l2fhdr->l2_fhdr_vlan_tag;
3930                         }
3931                         ether_input_chain(ifp, m, chain);
3932
3933                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3934                 }
3935
3936                 /*
3937                  * If polling(4) is not enabled, refresh hw_cons to see
3938                  * whether there's new work.
3939                  *
3940                  * If polling(4) is enabled, i.e count >= 0, refreshing
3941                  * should not be performed, so that we would not spend
3942                  * too much time in RX processing.
3943                  */
3944                 if (count < 0 && sw_cons == hw_cons)
3945                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
3946
3947                 /*
3948                  * Prevent speculative reads from getting ahead
3949                  * of the status block.
3950                  */
3951                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
3952                                   BUS_SPACE_BARRIER_READ);
3953         }
3954
3955         ether_input_dispatch(chain);
3956
3957         sc->rx_cons = sw_cons;
3958         sc->rx_prod = sw_prod;
3959         sc->rx_prod_bseq = sw_prod_bseq;
3960
3961         REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
3962         REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3963
3964         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
3965                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
3966                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
3967 }
3968
3969
3970 /****************************************************************************/
3971 /* Reads the transmit consumer value from the status block (skipping over   */
3972 /* chain page pointer if necessary).                                        */
3973 /*                                                                          */
3974 /* Returns:                                                                 */
3975 /*   hw_cons                                                                */
3976 /****************************************************************************/
3977 static __inline uint16_t
3978 bce_get_hw_tx_cons(struct bce_softc *sc)
3979 {
3980         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
3981
3982         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
3983                 hw_cons++;
3984         return hw_cons;
3985 }
3986
3987
3988 /****************************************************************************/
3989 /* Handles transmit completion interrupt events.                            */
3990 /*                                                                          */
3991 /* Returns:                                                                 */
3992 /*   Nothing.                                                               */
3993 /****************************************************************************/
3994 static void
3995 bce_tx_intr(struct bce_softc *sc)
3996 {
3997         struct ifnet *ifp = &sc->arpcom.ac_if;
3998         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
3999
4000         ASSERT_SERIALIZED(ifp->if_serializer);
4001
4002         DBRUNIF(1, sc->tx_interrupts++);
4003
4004         /* Get the hardware's view of the TX consumer index. */
4005         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4006         sw_tx_cons = sc->tx_cons;
4007
4008         /* Prevent speculative reads from getting ahead of the status block. */
4009         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4010                           BUS_SPACE_BARRIER_READ);
4011
4012         /* Cycle through any completed TX chain page entries. */
4013         while (sw_tx_cons != hw_tx_cons) {
4014 #ifdef BCE_DEBUG
4015                 struct tx_bd *txbd = NULL;
4016 #endif
4017                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4018
4019                 DBPRINT(sc, BCE_INFO_SEND,
4020                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4021                         "sw_tx_chain_cons = 0x%04X\n",
4022                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4023
4024                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4025                         if_printf(ifp, "%s(%d): "
4026                                   "TX chain consumer out of range! "
4027                                   " 0x%04X > 0x%04X\n",
4028                                   __FILE__, __LINE__, sw_tx_chain_cons,
4029                                   (int)MAX_TX_BD);
4030                         bce_breakpoint(sc));
4031
4032                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4033                                 [TX_IDX(sw_tx_chain_cons)]);
4034
4035                 DBRUNIF((txbd == NULL),
4036                         if_printf(ifp, "%s(%d): "
4037                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4038                                   __FILE__, __LINE__, sw_tx_chain_cons);
4039                         bce_breakpoint(sc));
4040
4041                 DBRUN(BCE_INFO_SEND,
4042                       if_printf(ifp, "%s(): ", __func__);
4043                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4044
4045                 /*
4046                  * Free the associated mbuf. Remember
4047                  * that only the last tx_bd of a packet
4048                  * has an mbuf pointer and DMA map.
4049                  */
4050                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4051                         /* Validate that this is the last tx_bd. */
4052                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4053                                 if_printf(ifp, "%s(%d): "
4054                                 "tx_bd END flag not set but "
4055                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4056                                 bce_breakpoint(sc));
4057
4058                         DBRUN(BCE_INFO_SEND,
4059                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4060                                         "from tx_bd[0x%04X]\n", __func__,
4061                                         sw_tx_chain_cons));
4062
4063                         /* Unmap the mbuf. */
4064                         bus_dmamap_unload(sc->tx_mbuf_tag,
4065                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4066
4067                         /* Free the mbuf. */
4068                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4069                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4070                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4071
4072                         ifp->if_opackets++;
4073                 }
4074
4075                 sc->used_tx_bd--;
4076                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4077
4078                 if (sw_tx_cons == hw_tx_cons) {
4079                         /* Refresh hw_cons to see if there's new work. */
4080                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4081                 }
4082
4083                 /*
4084                  * Prevent speculative reads from getting
4085                  * ahead of the status block.
4086                  */
4087                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4088                                   BUS_SPACE_BARRIER_READ);
4089         }
4090
4091         if (sc->used_tx_bd == 0) {
4092                 /* Clear the TX timeout timer. */
4093                 ifp->if_timer = 0;
4094         }
4095
4096         /* Clear the tx hardware queue full flag. */
4097         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4098                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4099                         DBPRINT(sc, BCE_WARN_SEND,
4100                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4101                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4102                 ifp->if_flags &= ~IFF_OACTIVE;
4103         }
4104         sc->tx_cons = sw_tx_cons;
4105 }
4106
4107
4108 /****************************************************************************/
4109 /* Disables interrupt generation.                                           */
4110 /*                                                                          */
4111 /* Returns:                                                                 */
4112 /*   Nothing.                                                               */
4113 /****************************************************************************/
4114 static void
4115 bce_disable_intr(struct bce_softc *sc)
4116 {
4117         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4118         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4119         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4120 }
4121
4122
4123 /****************************************************************************/
4124 /* Enables interrupt generation.                                            */
4125 /*                                                                          */
4126 /* Returns:                                                                 */
4127 /*   Nothing.                                                               */
4128 /****************************************************************************/
4129 static void
4130 bce_enable_intr(struct bce_softc *sc)
4131 {
4132         uint32_t val;
4133
4134         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4135
4136         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4137                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4138                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4139
4140         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4141                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4142
4143         val = REG_RD(sc, BCE_HC_COMMAND);
4144         REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW);
4145 }
4146
4147
4148 /****************************************************************************/
4149 /* Handles controller initialization.                                       */
4150 /*                                                                          */
4151 /* Returns:                                                                 */
4152 /*   Nothing.                                                               */
4153 /****************************************************************************/
4154 static void
4155 bce_init(void *xsc)
4156 {
4157         struct bce_softc *sc = xsc;
4158         struct ifnet *ifp = &sc->arpcom.ac_if;
4159         uint32_t ether_mtu;
4160         int error;
4161
4162         ASSERT_SERIALIZED(ifp->if_serializer);
4163
4164         /* Check if the driver is still running and bail out if it is. */
4165         if (ifp->if_flags & IFF_RUNNING)
4166                 return;
4167
4168         bce_stop(sc);
4169
4170         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4171         if (error) {
4172                 if_printf(ifp, "Controller reset failed!\n");
4173                 goto back;
4174         }
4175
4176         error = bce_chipinit(sc);
4177         if (error) {
4178                 if_printf(ifp, "Controller initialization failed!\n");
4179                 goto back;
4180         }
4181
4182         error = bce_blockinit(sc);
4183         if (error) {
4184                 if_printf(ifp, "Block initialization failed!\n");
4185                 goto back;
4186         }
4187
4188         /* Load our MAC address. */
4189         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4190         bce_set_mac_addr(sc);
4191
4192         /* Calculate and program the Ethernet MTU size. */
4193         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4194
4195         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4196
4197         /*
4198          * Program the mtu, enabling jumbo frame
4199          * support if necessary.  Also set the mbuf
4200          * allocation count for RX frames.
4201          */
4202         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4203 #ifdef notyet
4204                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4205                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4206                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4207                 sc->mbuf_alloc_size = MJUM9BYTES;
4208 #else
4209                 panic("jumbo buffer is not supported yet\n");
4210 #endif
4211         } else {
4212                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4213                 sc->mbuf_alloc_size = MCLBYTES;
4214         }
4215
4216         /* Calculate the RX Ethernet frame size for rx_bd's. */
4217         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4218
4219         DBPRINT(sc, BCE_INFO,
4220                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4221                 "max_frame_size = %d\n",
4222                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4223                 sc->max_frame_size);
4224
4225         /* Program appropriate promiscuous/multicast filtering. */
4226         bce_set_rx_mode(sc);
4227
4228         /* Init RX buffer descriptor chain. */
4229         bce_init_rx_chain(sc);  /* XXX return value */
4230
4231         /* Init TX buffer descriptor chain. */
4232         bce_init_tx_chain(sc);  /* XXX return value */
4233
4234 #ifdef DEVICE_POLLING
4235         /* Disable interrupts if we are polling. */
4236         if (ifp->if_flags & IFF_POLLING) {
4237                 bce_disable_intr(sc);
4238
4239                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4240                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4241                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4242                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4243         } else
4244 #endif
4245         /* Enable host interrupts. */
4246         bce_enable_intr(sc);
4247
4248         bce_ifmedia_upd(ifp);
4249
4250         ifp->if_flags |= IFF_RUNNING;
4251         ifp->if_flags &= ~IFF_OACTIVE;
4252
4253         callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
4254 back:
4255         if (error)
4256                 bce_stop(sc);
4257 }
4258
4259
4260 /****************************************************************************/
4261 /* Initialize the controller just enough so that any management firmware    */
4262 /* running on the device will continue to operate corectly.                 */
4263 /*                                                                          */
4264 /* Returns:                                                                 */
4265 /*   Nothing.                                                               */
4266 /****************************************************************************/
4267 static void
4268 bce_mgmt_init(struct bce_softc *sc)
4269 {
4270         struct ifnet *ifp = &sc->arpcom.ac_if;
4271         uint32_t val;
4272
4273         /* Check if the driver is still running and bail out if it is. */
4274         if (ifp->if_flags & IFF_RUNNING)
4275                 return;
4276
4277         /* Initialize the on-boards CPUs */
4278         bce_init_cpus(sc);
4279
4280         /* Set the page size and clear the RV2P processor stall bits. */
4281         val = (BCM_PAGE_BITS - 8) << 24;
4282         REG_WR(sc, BCE_RV2P_CONFIG, val);
4283
4284         /* Enable all critical blocks in the MAC. */
4285         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4286                BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE |
4287                BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE |
4288                BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE);
4289         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4290         DELAY(20);
4291
4292         bce_ifmedia_upd(ifp);
4293 }
4294
4295
4296 /****************************************************************************/
4297 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4298 /* memory visible to the controller.                                        */
4299 /*                                                                          */
4300 /* Returns:                                                                 */
4301 /*   0 for success, positive value for failure.                             */
4302 /****************************************************************************/
4303 static int
4304 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4305 {
4306         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4307         bus_dmamap_t map, tmp_map;
4308         struct mbuf *m0 = *m_head;
4309         struct tx_bd *txbd = NULL;
4310         uint16_t vlan_tag = 0, flags = 0;
4311         uint16_t chain_prod, chain_prod_start, prod;
4312         uint32_t prod_bseq;
4313         int i, error, maxsegs, nsegs;
4314 #ifdef BCE_DEBUG
4315         uint16_t debug_prod;
4316 #endif
4317
4318         /* Transfer any checksum offload flags to the bd. */
4319         if (m0->m_pkthdr.csum_flags) {
4320                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4321                         flags |= TX_BD_FLAGS_IP_CKSUM;
4322                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4323                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4324         }
4325
4326         /* Transfer any VLAN tags to the bd. */
4327         if (m0->m_flags & M_VLANTAG) {
4328                 flags |= TX_BD_FLAGS_VLAN_TAG;
4329                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4330         }
4331
4332         prod = sc->tx_prod;
4333         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4334
4335         /* Map the mbuf into DMAable memory. */
4336         map = sc->tx_mbuf_map[chain_prod_start];
4337
4338         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4339         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4340                 ("not enough segements %d\n", maxsegs));
4341         if (maxsegs > BCE_MAX_SEGMENTS)
4342                 maxsegs = BCE_MAX_SEGMENTS;
4343
4344         /* Map the mbuf into our DMA address space. */
4345         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4346                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4347         if (error)
4348                 goto back;
4349         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4350
4351         /* Reset m0 */
4352         m0 = *m_head;
4353
4354         /* prod points to an empty tx_bd at this point. */
4355         prod_bseq  = sc->tx_prod_bseq;
4356
4357 #ifdef BCE_DEBUG
4358         debug_prod = chain_prod;
4359 #endif
4360
4361         DBPRINT(sc, BCE_INFO_SEND,
4362                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4363                 "prod_bseq = 0x%08X\n",
4364                 __func__, prod, chain_prod, prod_bseq);
4365
4366         /*
4367          * Cycle through each mbuf segment that makes up
4368          * the outgoing frame, gathering the mapping info
4369          * for that segment and creating a tx_bd to for
4370          * the mbuf.
4371          */
4372         for (i = 0; i < nsegs; i++) {
4373                 chain_prod = TX_CHAIN_IDX(prod);
4374                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4375
4376                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4377                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4378                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4379                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4380                 txbd->tx_bd_flags = htole16(flags);
4381                 prod_bseq += segs[i].ds_len;
4382                 if (i == 0)
4383                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4384                 prod = NEXT_TX_BD(prod);
4385         }
4386
4387         /* Set the END flag on the last TX buffer descriptor. */
4388         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4389
4390         DBRUN(BCE_EXCESSIVE_SEND,
4391               bce_dump_tx_chain(sc, debug_prod, ctx.bce_maxsegs));
4392
4393         DBPRINT(sc, BCE_INFO_SEND,
4394                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4395                 "prod_bseq = 0x%08X\n",
4396                 __func__, prod, chain_prod, prod_bseq);
4397
4398         /*
4399          * Ensure that the mbuf pointer for this transmission
4400          * is placed at the array index of the last
4401          * descriptor in this chain.  This is done
4402          * because a single map is used for all
4403          * segments of the mbuf and we don't want to
4404          * unload the map before all of the segments
4405          * have been freed.
4406          */
4407         sc->tx_mbuf_ptr[chain_prod] = m0;
4408
4409         tmp_map = sc->tx_mbuf_map[chain_prod];
4410         sc->tx_mbuf_map[chain_prod] = map;
4411         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4412
4413         sc->used_tx_bd += nsegs;
4414
4415         /* Update some debug statistic counters */
4416         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4417                 sc->tx_hi_watermark = sc->used_tx_bd);
4418         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4419         DBRUNIF(1, sc->tx_mbuf_alloc++);
4420
4421         DBRUN(BCE_VERBOSE_SEND,
4422               bce_dump_tx_mbuf_chain(sc, chain_prod, ctx.bce_maxsegs));
4423
4424         /* prod points to the next free tx_bd at this point. */
4425         sc->tx_prod = prod;
4426         sc->tx_prod_bseq = prod_bseq;
4427 back:
4428         if (error) {
4429                 m_freem(*m_head);
4430                 *m_head = NULL;
4431         }
4432         return error;
4433 }
4434
4435
4436 /****************************************************************************/
4437 /* Main transmit routine when called from another routine with a lock.      */
4438 /*                                                                          */
4439 /* Returns:                                                                 */
4440 /*   Nothing.                                                               */
4441 /****************************************************************************/
4442 static void
4443 bce_start(struct ifnet *ifp)
4444 {
4445         struct bce_softc *sc = ifp->if_softc;
4446         int count = 0;
4447
4448         ASSERT_SERIALIZED(ifp->if_serializer);
4449
4450         /* If there's no link or the transmit queue is empty then just exit. */
4451         if (!sc->bce_link) {
4452                 ifq_purge(&ifp->if_snd);
4453                 return;
4454         }
4455
4456         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4457                 return;
4458
4459         DBPRINT(sc, BCE_INFO_SEND,
4460                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, "
4461                 "tx_prod_bseq = 0x%08X\n",
4462                 __func__,
4463                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4464
4465         for (;;) {
4466                 struct mbuf *m_head;
4467
4468                 /*
4469                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4470                  * unlikely to fail.
4471                  */
4472                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4473                         ifp->if_flags |= IFF_OACTIVE;
4474                         break;
4475                 }
4476
4477                 /* Check for any frames to send. */
4478                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4479                 if (m_head == NULL)
4480                         break;
4481
4482                 /*
4483                  * Pack the data into the transmit ring. If we
4484                  * don't have room, place the mbuf back at the
4485                  * head of the queue and set the OACTIVE flag
4486                  * to wait for the NIC to drain the chain.
4487                  */
4488                 if (bce_encap(sc, &m_head)) {
4489                         ifp->if_oerrors++;
4490                         if (sc->used_tx_bd == 0) {
4491                                 continue;
4492                         } else {
4493                                 ifp->if_flags |= IFF_OACTIVE;
4494                                 break;
4495                         }
4496                 }
4497
4498                 count++;
4499
4500                 /* Send a copy of the frame to any BPF listeners. */
4501                 ETHER_BPF_MTAP(ifp, m_head);
4502         }
4503
4504         if (count == 0) {
4505                 /* no packets were dequeued */
4506                 DBPRINT(sc, BCE_VERBOSE_SEND,
4507                         "%s(): No packets were dequeued\n", __func__);
4508                 return;
4509         }
4510
4511         DBPRINT(sc, BCE_INFO_SEND,
4512                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
4513                 "tx_prod_bseq = 0x%08X\n",
4514                 __func__,
4515                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4516
4517         /* Start the transmit. */
4518         REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4519         REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4520
4521         /* Set the tx timeout. */
4522         ifp->if_timer = BCE_TX_TIMEOUT;
4523 }
4524
4525
4526 /****************************************************************************/
4527 /* Handles any IOCTL calls from the operating system.                       */
4528 /*                                                                          */
4529 /* Returns:                                                                 */
4530 /*   0 for success, positive value for failure.                             */
4531 /****************************************************************************/
4532 static int
4533 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4534 {
4535         struct bce_softc *sc = ifp->if_softc;
4536         struct ifreq *ifr = (struct ifreq *)data;
4537         struct mii_data *mii;
4538         int mask, error = 0;
4539
4540         ASSERT_SERIALIZED(ifp->if_serializer);
4541
4542         switch(command) {
4543         case SIOCSIFMTU:
4544                 /* Check that the MTU setting is supported. */
4545                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4546 #ifdef notyet
4547                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4548 #else
4549                     ifr->ifr_mtu > ETHERMTU
4550 #endif
4551                    ) {
4552                         error = EINVAL;
4553                         break;
4554                 }
4555
4556                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
4557
4558                 ifp->if_mtu = ifr->ifr_mtu;
4559                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4560                 bce_init(sc);
4561                 break;
4562
4563         case SIOCSIFFLAGS:
4564                 if (ifp->if_flags & IFF_UP) {
4565                         if (ifp->if_flags & IFF_RUNNING) {
4566                                 mask = ifp->if_flags ^ sc->bce_if_flags;
4567
4568                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
4569                                         bce_set_rx_mode(sc);
4570                         } else {
4571                                 bce_init(sc);
4572                         }
4573                 } else if (ifp->if_flags & IFF_RUNNING) {
4574                         bce_stop(sc);
4575                 }
4576                 sc->bce_if_flags = ifp->if_flags;
4577                 break;
4578
4579         case SIOCADDMULTI:
4580         case SIOCDELMULTI:
4581                 if (ifp->if_flags & IFF_RUNNING)
4582                         bce_set_rx_mode(sc);
4583                 break;
4584
4585         case SIOCSIFMEDIA:
4586         case SIOCGIFMEDIA:
4587                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
4588                         sc->bce_phy_flags);
4589                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
4590
4591                 mii = device_get_softc(sc->bce_miibus);
4592                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
4593                 break;
4594
4595         case SIOCSIFCAP:
4596                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4597                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
4598                         (uint32_t) mask);
4599
4600                 if (mask & IFCAP_HWCSUM) {
4601                         ifp->if_capenable ^= IFCAP_HWCSUM;
4602                         if (IFCAP_HWCSUM & ifp->if_capenable)
4603                                 ifp->if_hwassist = BCE_IF_HWASSIST;
4604                         else
4605                                 ifp->if_hwassist = 0;
4606                 }
4607                 break;
4608
4609         default:
4610                 error = ether_ioctl(ifp, command, data);
4611                 break;
4612         }
4613         return error;
4614 }
4615
4616
4617 /****************************************************************************/
4618 /* Transmit timeout handler.                                                */
4619 /*                                                                          */
4620 /* Returns:                                                                 */
4621 /*   Nothing.                                                               */
4622 /****************************************************************************/
4623 static void
4624 bce_watchdog(struct ifnet *ifp)
4625 {
4626         struct bce_softc *sc = ifp->if_softc;
4627
4628         ASSERT_SERIALIZED(ifp->if_serializer);
4629
4630         DBRUN(BCE_VERBOSE_SEND,
4631               bce_dump_driver_state(sc);
4632               bce_dump_status_block(sc));
4633
4634         /*
4635          * If we are in this routine because of pause frames, then
4636          * don't reset the hardware.
4637          */
4638         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
4639                 return;
4640
4641         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
4642
4643         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
4644
4645         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4646         bce_init(sc);
4647
4648         ifp->if_oerrors++;
4649
4650         if (!ifq_is_empty(&ifp->if_snd))
4651                 if_devstart(ifp);
4652 }
4653
4654
4655 #ifdef DEVICE_POLLING
4656
4657 static void
4658 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4659 {
4660         struct bce_softc *sc = ifp->if_softc;
4661         struct status_block *sblk = sc->status_block;
4662         uint16_t hw_tx_cons, hw_rx_cons;
4663
4664         ASSERT_SERIALIZED(ifp->if_serializer);
4665
4666         switch (cmd) {
4667         case POLL_REGISTER:
4668                 bce_disable_intr(sc);
4669
4670                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4671                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4672                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4673                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4674                 return;
4675         case POLL_DEREGISTER:
4676                 bce_enable_intr(sc);
4677
4678                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4679                        (sc->bce_tx_quick_cons_trip_int << 16) |
4680                        sc->bce_tx_quick_cons_trip);
4681                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4682                        (sc->bce_rx_quick_cons_trip_int << 16) |
4683                        sc->bce_rx_quick_cons_trip);
4684                 return;
4685         default:
4686                 break;
4687         }
4688
4689         if (cmd == POLL_AND_CHECK_STATUS) {
4690                 uint32_t status_attn_bits;
4691
4692                 status_attn_bits = sblk->status_attn_bits;
4693
4694                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4695                         if_printf(ifp,
4696                         "Simulating unexpected status attention bit set.");
4697                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4698
4699                 /* Was it a link change interrupt? */
4700                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4701                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4702                         bce_phy_intr(sc);
4703
4704                 /*
4705                  * If any other attention is asserted then
4706                  * the chip is toast.
4707                  */
4708                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4709                      (sblk->status_attn_bits_ack &
4710                       ~STATUS_ATTN_BITS_LINK_STATE)) {
4711                         DBRUN(1, sc->unexpected_attentions++);
4712
4713                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4714                                   sblk->status_attn_bits);
4715
4716                         DBRUN(BCE_FATAL,
4717                         if (bce_debug_unexpected_attention == 0)
4718                                 bce_breakpoint(sc));
4719
4720                         bce_init(sc);
4721                         return;
4722                 }
4723         }
4724
4725         hw_rx_cons = bce_get_hw_rx_cons(sc);
4726         hw_tx_cons = bce_get_hw_tx_cons(sc);
4727
4728         /* Check for any completed RX frames. */
4729         if (hw_rx_cons != sc->hw_rx_cons)
4730                 bce_rx_intr(sc, count);
4731
4732         /* Check for any completed TX frames. */
4733         if (hw_tx_cons != sc->hw_tx_cons)
4734                 bce_tx_intr(sc);
4735
4736         /* Check for new frames to transmit. */
4737         if (!ifq_is_empty(&ifp->if_snd))
4738                 if_devstart(ifp);
4739 }
4740
4741 #endif  /* DEVICE_POLLING */
4742
4743
4744 /*
4745  * Interrupt handler.
4746  */
4747 /****************************************************************************/
4748 /* Main interrupt entry point.  Verifies that the controller generated the  */
4749 /* interrupt and then calls a separate routine for handle the various       */
4750 /* interrupt causes (PHY, TX, RX).                                          */
4751 /*                                                                          */
4752 /* Returns:                                                                 */
4753 /*   0 for success, positive value for failure.                             */
4754 /****************************************************************************/
4755 static void
4756 bce_intr(void *xsc)
4757 {
4758         struct bce_softc *sc = xsc;
4759         struct ifnet *ifp = &sc->arpcom.ac_if;
4760         struct status_block *sblk;
4761         uint16_t hw_rx_cons, hw_tx_cons;
4762
4763         ASSERT_SERIALIZED(ifp->if_serializer);
4764
4765         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
4766         DBRUNIF(1, sc->interrupts_generated++);
4767
4768         sblk = sc->status_block;
4769
4770         /*
4771          * If the hardware status block index matches the last value
4772          * read by the driver and we haven't asserted our interrupt
4773          * then there's nothing to do.
4774          */
4775         if (sblk->status_idx == sc->last_status_idx &&
4776             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
4777              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
4778                 return;
4779
4780         /* Ack the interrupt and stop others from occuring. */
4781         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4782                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
4783                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4784
4785         /* Check if the hardware has finished any work. */
4786         hw_rx_cons = bce_get_hw_rx_cons(sc);
4787         hw_tx_cons = bce_get_hw_tx_cons(sc);
4788
4789         /* Keep processing data as long as there is work to do. */
4790         for (;;) {
4791                 uint32_t status_attn_bits;
4792
4793                 status_attn_bits = sblk->status_attn_bits;
4794
4795                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4796                         if_printf(ifp,
4797                         "Simulating unexpected status attention bit set.");
4798                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4799
4800                 /* Was it a link change interrupt? */
4801                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4802                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4803                         bce_phy_intr(sc);
4804
4805                 /*
4806                  * If any other attention is asserted then
4807                  * the chip is toast.
4808                  */
4809                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4810                      (sblk->status_attn_bits_ack &
4811                       ~STATUS_ATTN_BITS_LINK_STATE)) {
4812                         DBRUN(1, sc->unexpected_attentions++);
4813
4814                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4815                                   sblk->status_attn_bits);
4816
4817                         DBRUN(BCE_FATAL,
4818                         if (bce_debug_unexpected_attention == 0)
4819                                 bce_breakpoint(sc));
4820
4821                         bce_init(sc);
4822                         return;
4823                 }
4824
4825                 /* Check for any completed RX frames. */
4826                 if (hw_rx_cons != sc->hw_rx_cons)
4827                         bce_rx_intr(sc, -1);
4828
4829                 /* Check for any completed TX frames. */
4830                 if (hw_tx_cons != sc->hw_tx_cons)
4831                         bce_tx_intr(sc);
4832
4833                 /*
4834                  * Save the status block index value
4835                  * for use during the next interrupt.
4836                  */
4837                 sc->last_status_idx = sblk->status_idx;
4838
4839                 /*
4840                  * Prevent speculative reads from getting
4841                  * ahead of the status block.
4842                  */
4843                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4844                                   BUS_SPACE_BARRIER_READ);
4845
4846                 /*
4847                  * If there's no work left then exit the
4848                  * interrupt service routine.
4849                  */
4850                 hw_rx_cons = bce_get_hw_rx_cons(sc);
4851                 hw_tx_cons = bce_get_hw_tx_cons(sc);
4852                 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
4853                         break;
4854         }
4855
4856         /* Re-enable interrupts. */
4857         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4858                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx |
4859                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4860         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4861                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4862
4863         if (sc->bce_coalchg_mask)
4864                 bce_coal_change(sc);
4865
4866         /* Handle any frames that arrived while handling the interrupt. */
4867         if (!ifq_is_empty(&ifp->if_snd))
4868                 if_devstart(ifp);
4869 }
4870
4871
4872 /****************************************************************************/
4873 /* Programs the various packet receive modes (broadcast and multicast).     */
4874 /*                                                                          */
4875 /* Returns:                                                                 */
4876 /*   Nothing.                                                               */
4877 /****************************************************************************/
4878 static void
4879 bce_set_rx_mode(struct bce_softc *sc)
4880 {
4881         struct ifnet *ifp = &sc->arpcom.ac_if;
4882         struct ifmultiaddr *ifma;
4883         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
4884         uint32_t rx_mode, sort_mode;
4885         int h, i;
4886
4887         ASSERT_SERIALIZED(ifp->if_serializer);
4888
4889         /* Initialize receive mode default settings. */
4890         rx_mode = sc->rx_mode &
4891                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
4892                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
4893         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
4894
4895         /*
4896          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
4897          * be enbled.
4898          */
4899         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
4900             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4901                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
4902
4903         /*
4904          * Check for promiscuous, all multicast, or selected
4905          * multicast address filtering.
4906          */
4907         if (ifp->if_flags & IFF_PROMISC) {
4908                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
4909
4910                 /* Enable promiscuous mode. */
4911                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
4912                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
4913         } else if (ifp->if_flags & IFF_ALLMULTI) {
4914                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
4915
4916                 /* Enable all multicast addresses. */
4917                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
4918                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
4919                                0xffffffff);
4920                 }
4921                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
4922         } else {
4923                 /* Accept one or more multicast(s). */
4924                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
4925
4926                 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4927                         if (ifma->ifma_addr->sa_family != AF_LINK)
4928                                 continue;
4929                         h = ether_crc32_le(
4930                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
4931                             ETHER_ADDR_LEN) & 0xFF;
4932                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
4933                 }
4934
4935                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
4936                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
4937                                hashes[i]);
4938                 }
4939                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
4940         }
4941
4942         /* Only make changes if the recive mode has actually changed. */
4943         if (rx_mode != sc->rx_mode) {
4944                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
4945                         rx_mode);
4946
4947                 sc->rx_mode = rx_mode;
4948                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
4949         }
4950
4951         /* Disable and clear the exisitng sort before enabling a new sort. */
4952         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
4953         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
4954         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
4955 }
4956
4957
4958 /****************************************************************************/
4959 /* Called periodically to updates statistics from the controllers           */
4960 /* statistics block.                                                        */
4961 /*                                                                          */
4962 /* Returns:                                                                 */
4963 /*   Nothing.                                                               */
4964 /****************************************************************************/
4965 static void
4966 bce_stats_update(struct bce_softc *sc)
4967 {
4968         struct ifnet *ifp = &sc->arpcom.ac_if;
4969         struct statistics_block *stats = sc->stats_block;
4970
4971         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
4972
4973         ASSERT_SERIALIZED(ifp->if_serializer);
4974
4975         /*
4976          * Update the interface statistics from the hardware statistics.
4977          */
4978         ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions;
4979
4980         ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts +
4981                           (u_long)stats->stat_EtherStatsOverrsizePkts +
4982                           (u_long)stats->stat_IfInMBUFDiscards +
4983                           (u_long)stats->stat_Dot3StatsAlignmentErrors +
4984                           (u_long)stats->stat_Dot3StatsFCSErrors;
4985
4986         ifp->if_oerrors =
4987         (u_long)stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
4988         (u_long)stats->stat_Dot3StatsExcessiveCollisions +
4989         (u_long)stats->stat_Dot3StatsLateCollisions;
4990
4991         /*
4992          * Certain controllers don't report carrier sense errors correctly.
4993          * See errata E11_5708CA0_1165.
4994          */
4995         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
4996             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
4997                 ifp->if_oerrors +=
4998                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
4999         }
5000
5001         /*
5002          * Update the sysctl statistics from the hardware statistics.
5003          */
5004         sc->stat_IfHCInOctets =
5005                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5006                  (uint64_t)stats->stat_IfHCInOctets_lo;
5007
5008         sc->stat_IfHCInBadOctets =
5009                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5010                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5011
5012         sc->stat_IfHCOutOctets =
5013                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5014                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5015
5016         sc->stat_IfHCOutBadOctets =
5017                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5018                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5019
5020         sc->stat_IfHCInUcastPkts =
5021                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5022                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5023
5024         sc->stat_IfHCInMulticastPkts =
5025                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5026                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5027
5028         sc->stat_IfHCInBroadcastPkts =
5029                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5030                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5031
5032         sc->stat_IfHCOutUcastPkts =
5033                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5034                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5035
5036         sc->stat_IfHCOutMulticastPkts =
5037                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5038                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5039
5040         sc->stat_IfHCOutBroadcastPkts =
5041                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5042                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5043
5044         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5045                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5046
5047         sc->stat_Dot3StatsCarrierSenseErrors =
5048                 stats->stat_Dot3StatsCarrierSenseErrors;
5049
5050         sc->stat_Dot3StatsFCSErrors =
5051                 stats->stat_Dot3StatsFCSErrors;
5052
5053         sc->stat_Dot3StatsAlignmentErrors =
5054                 stats->stat_Dot3StatsAlignmentErrors;
5055
5056         sc->stat_Dot3StatsSingleCollisionFrames =
5057                 stats->stat_Dot3StatsSingleCollisionFrames;
5058
5059         sc->stat_Dot3StatsMultipleCollisionFrames =
5060                 stats->stat_Dot3StatsMultipleCollisionFrames;
5061
5062         sc->stat_Dot3StatsDeferredTransmissions =
5063                 stats->stat_Dot3StatsDeferredTransmissions;
5064
5065         sc->stat_Dot3StatsExcessiveCollisions =
5066                 stats->stat_Dot3StatsExcessiveCollisions;
5067
5068         sc->stat_Dot3StatsLateCollisions =
5069                 stats->stat_Dot3StatsLateCollisions;
5070
5071         sc->stat_EtherStatsCollisions =
5072                 stats->stat_EtherStatsCollisions;
5073
5074         sc->stat_EtherStatsFragments =
5075                 stats->stat_EtherStatsFragments;
5076
5077         sc->stat_EtherStatsJabbers =
5078                 stats->stat_EtherStatsJabbers;
5079
5080         sc->stat_EtherStatsUndersizePkts =
5081                 stats->stat_EtherStatsUndersizePkts;
5082
5083         sc->stat_EtherStatsOverrsizePkts =
5084                 stats->stat_EtherStatsOverrsizePkts;
5085
5086         sc->stat_EtherStatsPktsRx64Octets =
5087                 stats->stat_EtherStatsPktsRx64Octets;
5088
5089         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5090                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5091
5092         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5093                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5094
5095         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5096                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5097
5098         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5099                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5100
5101         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5102                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5103
5104         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5105                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5106
5107         sc->stat_EtherStatsPktsTx64Octets =
5108                 stats->stat_EtherStatsPktsTx64Octets;
5109
5110         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5111                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5112
5113         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5114                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5115
5116         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5117                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5118
5119         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5120                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5121
5122         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5123                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5124
5125         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5126                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5127
5128         sc->stat_XonPauseFramesReceived =
5129                 stats->stat_XonPauseFramesReceived;
5130
5131         sc->stat_XoffPauseFramesReceived =
5132                 stats->stat_XoffPauseFramesReceived;
5133
5134         sc->stat_OutXonSent =
5135                 stats->stat_OutXonSent;
5136
5137         sc->stat_OutXoffSent =
5138                 stats->stat_OutXoffSent;
5139
5140         sc->stat_FlowControlDone =
5141                 stats->stat_FlowControlDone;
5142
5143         sc->stat_MacControlFramesReceived =
5144                 stats->stat_MacControlFramesReceived;
5145
5146         sc->stat_XoffStateEntered =
5147                 stats->stat_XoffStateEntered;
5148
5149         sc->stat_IfInFramesL2FilterDiscards =
5150                 stats->stat_IfInFramesL2FilterDiscards;
5151
5152         sc->stat_IfInRuleCheckerDiscards =
5153                 stats->stat_IfInRuleCheckerDiscards;
5154
5155         sc->stat_IfInFTQDiscards =
5156                 stats->stat_IfInFTQDiscards;
5157
5158         sc->stat_IfInMBUFDiscards =
5159                 stats->stat_IfInMBUFDiscards;
5160
5161         sc->stat_IfInRuleCheckerP4Hit =
5162                 stats->stat_IfInRuleCheckerP4Hit;
5163
5164         sc->stat_CatchupInRuleCheckerDiscards =
5165                 stats->stat_CatchupInRuleCheckerDiscards;
5166
5167         sc->stat_CatchupInFTQDiscards =
5168                 stats->stat_CatchupInFTQDiscards;
5169
5170         sc->stat_CatchupInMBUFDiscards =
5171                 stats->stat_CatchupInMBUFDiscards;
5172
5173         sc->stat_CatchupInRuleCheckerP4Hit =
5174                 stats->stat_CatchupInRuleCheckerP4Hit;
5175
5176         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5177
5178         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5179 }
5180
5181
5182 /****************************************************************************/
5183 /* Periodic function to perform maintenance tasks.                          */
5184 /*                                                                          */
5185 /* Returns:                                                                 */
5186 /*   Nothing.                                                               */
5187 /****************************************************************************/
5188 static void
5189 bce_tick_serialized(struct bce_softc *sc)
5190 {
5191         struct ifnet *ifp = &sc->arpcom.ac_if;
5192         struct mii_data *mii;
5193         uint32_t msg;
5194
5195         ASSERT_SERIALIZED(ifp->if_serializer);
5196
5197         /* Tell the firmware that the driver is still running. */
5198 #ifdef BCE_DEBUG
5199         msg = (uint32_t)BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE;
5200 #else
5201         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5202 #endif
5203         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5204
5205         /* Update the statistics from the hardware statistics block. */
5206         bce_stats_update(sc);
5207
5208         /* Schedule the next tick. */
5209         callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
5210
5211         /* If link is up already up then we're done. */
5212         if (sc->bce_link)
5213                 return;
5214
5215         mii = device_get_softc(sc->bce_miibus);
5216         mii_tick(mii);
5217
5218         /* Check if the link has come up. */
5219         if (!sc->bce_link && (mii->mii_media_status & IFM_ACTIVE) &&
5220             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5221                 sc->bce_link++;
5222                 /* Now that link is up, handle any outstanding TX traffic. */
5223                 if (!ifq_is_empty(&ifp->if_snd))
5224                         if_devstart(ifp);
5225         }
5226 }
5227
5228
5229 static void
5230 bce_tick(void *xsc)
5231 {
5232         struct bce_softc *sc = xsc;
5233         struct ifnet *ifp = &sc->arpcom.ac_if;
5234
5235         lwkt_serialize_enter(ifp->if_serializer);
5236         bce_tick_serialized(sc);
5237         lwkt_serialize_exit(ifp->if_serializer);
5238 }
5239
5240
5241 #ifdef BCE_DEBUG
5242 /****************************************************************************/
5243 /* Allows the driver state to be dumped through the sysctl interface.       */
5244 /*                                                                          */
5245 /* Returns:                                                                 */
5246 /*   0 for success, positive value for failure.                             */
5247 /****************************************************************************/
5248 static int
5249 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5250 {
5251         int error;
5252         int result;
5253         struct bce_softc *sc;
5254
5255         result = -1;
5256         error = sysctl_handle_int(oidp, &result, 0, req);
5257
5258         if (error || !req->newptr)
5259                 return (error);
5260
5261         if (result == 1) {
5262                 sc = (struct bce_softc *)arg1;
5263                 bce_dump_driver_state(sc);
5264         }
5265
5266         return error;
5267 }
5268
5269
5270 /****************************************************************************/
5271 /* Allows the hardware state to be dumped through the sysctl interface.     */
5272 /*                                                                          */
5273 /* Returns:                                                                 */
5274 /*   0 for success, positive value for failure.                             */
5275 /****************************************************************************/
5276 static int
5277 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5278 {
5279         int error;
5280         int result;
5281         struct bce_softc *sc;
5282
5283         result = -1;
5284         error = sysctl_handle_int(oidp, &result, 0, req);
5285
5286         if (error || !req->newptr)
5287                 return (error);
5288
5289         if (result == 1) {
5290                 sc = (struct bce_softc *)arg1;
5291                 bce_dump_hw_state(sc);
5292         }
5293
5294         return error;
5295 }
5296
5297
5298 /****************************************************************************/
5299 /* Provides a sysctl interface to allows dumping the RX chain.              */
5300 /*                                                                          */
5301 /* Returns:                                                                 */
5302 /*   0 for success, positive value for failure.                             */
5303 /****************************************************************************/
5304 static int
5305 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5306 {
5307         int error;
5308         int result;
5309         struct bce_softc *sc;
5310
5311         result = -1;
5312         error = sysctl_handle_int(oidp, &result, 0, req);
5313
5314         if (error || !req->newptr)
5315                 return (error);
5316
5317         if (result == 1) {
5318                 sc = (struct bce_softc *)arg1;
5319                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5320         }
5321
5322         return error;
5323 }
5324
5325
5326 /****************************************************************************/
5327 /* Provides a sysctl interface to allows dumping the TX chain.              */
5328 /*                                                                          */
5329 /* Returns:                                                                 */
5330 /*   0 for success, positive value for failure.                             */
5331 /****************************************************************************/
5332 static int
5333 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5334 {
5335         int error;
5336         int result;
5337         struct bce_softc *sc;
5338
5339         result = -1;
5340         error = sysctl_handle_int(oidp, &result, 0, req);
5341
5342         if (error || !req->newptr)
5343                 return (error);
5344
5345         if (result == 1) {
5346                 sc = (struct bce_softc *)arg1;
5347                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5348         }
5349
5350         return error;
5351 }
5352
5353
5354 /****************************************************************************/
5355 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
5356 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
5357 /*                                                                          */
5358 /* Returns:                                                                 */
5359 /*   0 for success, positive value for failure.                             */
5360 /****************************************************************************/
5361 static int
5362 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5363 {
5364         struct bce_softc *sc;
5365         int error;
5366         uint32_t val, result;
5367
5368         result = -1;
5369         error = sysctl_handle_int(oidp, &result, 0, req);
5370         if (error || (req->newptr == NULL))
5371                 return (error);
5372
5373         /* Make sure the register is accessible. */
5374         if (result < 0x8000) {
5375                 sc = (struct bce_softc *)arg1;
5376                 val = REG_RD(sc, result);
5377                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5378                           result, val);
5379         } else if (result < 0x0280000) {
5380                 sc = (struct bce_softc *)arg1;
5381                 val = REG_RD_IND(sc, result);
5382                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5383                           result, val);
5384         }
5385         return (error);
5386 }
5387
5388
5389 /****************************************************************************/
5390 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */\r
5391 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */\r
5392 /*                                                                          */
5393 /* Returns:                                                                 */
5394 /*   0 for success, positive value for failure.                             */
5395 /****************************************************************************/
5396 static int
5397 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5398 {
5399         struct bce_softc *sc;
5400         device_t dev;
5401         int error, result;
5402         uint16_t val;
5403
5404         result = -1;
5405         error = sysctl_handle_int(oidp, &result, 0, req);
5406         if (error || (req->newptr == NULL))
5407                 return (error);
5408
5409         /* Make sure the register is accessible. */
5410         if (result < 0x20) {
5411                 sc = (struct bce_softc *)arg1;
5412                 dev = sc->bce_dev;
5413                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5414                 if_printf(&sc->arpcom.ac_if,
5415                           "phy 0x%02X = 0x%04X\n", result, val);
5416         }
5417         return (error);
5418 }
5419
5420
5421 /****************************************************************************/
5422 /* Provides a sysctl interface to forcing the driver to dump state and      */\r
5423 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
5424 /*                                                                          */
5425 /* Returns:                                                                 */
5426 /*   0 for success, positive value for failure.                             */
5427 /****************************************************************************/
5428 static int
5429 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5430 {
5431         int error;
5432         int result;
5433         struct bce_softc *sc;
5434
5435         result = -1;
5436         error = sysctl_handle_int(oidp, &result, 0, req);
5437
5438         if (error || !req->newptr)
5439                 return (error);
5440
5441         if (result == 1) {
5442                 sc = (struct bce_softc *)arg1;
5443                 bce_breakpoint(sc);
5444         }
5445
5446         return error;
5447 }
5448 #endif
5449
5450
5451 /****************************************************************************/
5452 /* Adds any sysctl parameters for tuning or debugging purposes.             */
5453 /*                                                                          */
5454 /* Returns:                                                                 */
5455 /*   0 for success, positive value for failure.                             */
5456 /****************************************************************************/
5457 static void
5458 bce_add_sysctls(struct bce_softc *sc)
5459 {
5460         struct sysctl_ctx_list *ctx;
5461         struct sysctl_oid_list *children;
5462
5463         sysctl_ctx_init(&sc->bce_sysctl_ctx);
5464         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5465                                               SYSCTL_STATIC_CHILDREN(_hw),
5466                                               OID_AUTO,
5467                                               device_get_nameunit(sc->bce_dev),
5468                                               CTLFLAG_RD, 0, "");
5469         if (sc->bce_sysctl_tree == NULL) {
5470                 device_printf(sc->bce_dev, "can't add sysctl node\n");
5471                 return;
5472         }
5473
5474         ctx = &sc->bce_sysctl_ctx;
5475         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5476
5477         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
5478                         CTLTYPE_INT | CTLFLAG_RW,
5479                         sc, 0, bce_sysctl_tx_bds_int, "I",
5480                         "Send max coalesced BD count during interrupt");
5481         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
5482                         CTLTYPE_INT | CTLFLAG_RW,
5483                         sc, 0, bce_sysctl_tx_bds, "I",
5484                         "Send max coalesced BD count");
5485         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
5486                         CTLTYPE_INT | CTLFLAG_RW,
5487                         sc, 0, bce_sysctl_tx_ticks_int, "I",
5488                         "Send coalescing ticks during interrupt");
5489         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
5490                         CTLTYPE_INT | CTLFLAG_RW,
5491                         sc, 0, bce_sysctl_tx_ticks, "I",
5492                         "Send coalescing ticks");
5493
5494         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
5495                         CTLTYPE_INT | CTLFLAG_RW,
5496                         sc, 0, bce_sysctl_rx_bds_int, "I",
5497                         "Receive max coalesced BD count during interrupt");
5498         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
5499                         CTLTYPE_INT | CTLFLAG_RW,
5500                         sc, 0, bce_sysctl_rx_bds, "I",
5501                         "Receive max coalesced BD count");
5502         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
5503                         CTLTYPE_INT | CTLFLAG_RW,
5504                         sc, 0, bce_sysctl_rx_ticks_int, "I",
5505                         "Receive coalescing ticks during interrupt");
5506         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
5507                         CTLTYPE_INT | CTLFLAG_RW,
5508                         sc, 0, bce_sysctl_rx_ticks, "I",
5509                         "Receive coalescing ticks");
5510
5511 #ifdef BCE_DEBUG
5512         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5513                 "rx_low_watermark",
5514                 CTLFLAG_RD, &sc->rx_low_watermark,
5515                 0, "Lowest level of free rx_bd's");
5516
5517         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5518                 "rx_empty_count",
5519                 CTLFLAG_RD, &sc->rx_empty_count,
5520                 0, "Number of times the RX chain was empty");
5521
5522         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5523                 "tx_hi_watermark",
5524                 CTLFLAG_RD, &sc->tx_hi_watermark,
5525                 0, "Highest level of used tx_bd's");
5526
5527         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5528                 "tx_full_count",
5529                 CTLFLAG_RD, &sc->tx_full_count,
5530                 0, "Number of times the TX chain was full");
5531
5532         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5533                 "l2fhdr_status_errors",
5534                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
5535                 0, "l2_fhdr status errors");
5536
5537         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5538                 "unexpected_attentions",
5539                 CTLFLAG_RD, &sc->unexpected_attentions,
5540                 0, "unexpected attentions");
5541
5542         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5543                 "lost_status_block_updates",
5544                 CTLFLAG_RD, &sc->lost_status_block_updates,
5545                 0, "lost status block updates");
5546
5547         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5548                 "mbuf_alloc_failed",
5549                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
5550                 0, "mbuf cluster allocation failures");
5551 #endif
5552
5553         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5554                 "stat_IfHCInOctets",
5555                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
5556                 "Bytes received");
5557
5558         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5559                 "stat_IfHCInBadOctets",
5560                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
5561                 "Bad bytes received");
5562
5563         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5564                 "stat_IfHCOutOctets",
5565                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
5566                 "Bytes sent");
5567
5568         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5569                 "stat_IfHCOutBadOctets",
5570                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
5571                 "Bad bytes sent");
5572
5573         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5574                 "stat_IfHCInUcastPkts",
5575                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
5576                 "Unicast packets received");
5577
5578         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5579                 "stat_IfHCInMulticastPkts",
5580                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
5581                 "Multicast packets received");
5582
5583         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5584                 "stat_IfHCInBroadcastPkts",
5585                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
5586                 "Broadcast packets received");
5587
5588         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5589                 "stat_IfHCOutUcastPkts",
5590                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
5591                 "Unicast packets sent");
5592
5593         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5594                 "stat_IfHCOutMulticastPkts",
5595                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
5596                 "Multicast packets sent");
5597
5598         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5599                 "stat_IfHCOutBroadcastPkts",
5600                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
5601                 "Broadcast packets sent");
5602
5603         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5604                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
5605                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
5606                 0, "Internal MAC transmit errors");
5607
5608         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5609                 "stat_Dot3StatsCarrierSenseErrors",
5610                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
5611                 0, "Carrier sense errors");
5612
5613         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5614                 "stat_Dot3StatsFCSErrors",
5615                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
5616                 0, "Frame check sequence errors");
5617
5618         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5619                 "stat_Dot3StatsAlignmentErrors",
5620                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
5621                 0, "Alignment errors");
5622
5623         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5624                 "stat_Dot3StatsSingleCollisionFrames",
5625                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
5626                 0, "Single Collision Frames");
5627
5628         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5629                 "stat_Dot3StatsMultipleCollisionFrames",
5630                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
5631                 0, "Multiple Collision Frames");
5632
5633         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5634                 "stat_Dot3StatsDeferredTransmissions",
5635                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
5636                 0, "Deferred Transmissions");
5637
5638         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5639                 "stat_Dot3StatsExcessiveCollisions",
5640                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
5641                 0, "Excessive Collisions");
5642
5643         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5644                 "stat_Dot3StatsLateCollisions",
5645                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
5646                 0, "Late Collisions");
5647
5648         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5649                 "stat_EtherStatsCollisions",
5650                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
5651                 0, "Collisions");
5652
5653         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5654                 "stat_EtherStatsFragments",
5655                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
5656                 0, "Fragments");
5657
5658         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5659                 "stat_EtherStatsJabbers",
5660                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
5661                 0, "Jabbers");
5662
5663         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5664                 "stat_EtherStatsUndersizePkts",
5665                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
5666                 0, "Undersize packets");
5667
5668         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5669                 "stat_EtherStatsOverrsizePkts",
5670                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
5671                 0, "stat_EtherStatsOverrsizePkts");
5672
5673         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5674                 "stat_EtherStatsPktsRx64Octets",
5675                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
5676                 0, "Bytes received in 64 byte packets");
5677
5678         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5679                 "stat_EtherStatsPktsRx65Octetsto127Octets",
5680                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
5681                 0, "Bytes received in 65 to 127 byte packets");
5682
5683         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5684                 "stat_EtherStatsPktsRx128Octetsto255Octets",
5685                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
5686                 0, "Bytes received in 128 to 255 byte packets");
5687
5688         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5689                 "stat_EtherStatsPktsRx256Octetsto511Octets",
5690                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
5691                 0, "Bytes received in 256 to 511 byte packets");
5692
5693         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5694                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
5695                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
5696                 0, "Bytes received in 512 to 1023 byte packets");
5697
5698         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5699                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
5700                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
5701                 0, "Bytes received in 1024 t0 1522 byte packets");
5702
5703         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5704                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
5705                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
5706                 0, "Bytes received in 1523 to 9022 byte packets");
5707
5708         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5709                 "stat_EtherStatsPktsTx64Octets",
5710                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
5711                 0, "Bytes sent in 64 byte packets");
5712
5713         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5714                 "stat_EtherStatsPktsTx65Octetsto127Octets",
5715                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
5716                 0, "Bytes sent in 65 to 127 byte packets");
5717
5718         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5719                 "stat_EtherStatsPktsTx128Octetsto255Octets",
5720                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
5721                 0, "Bytes sent in 128 to 255 byte packets");
5722
5723         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5724                 "stat_EtherStatsPktsTx256Octetsto511Octets",
5725                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
5726                 0, "Bytes sent in 256 to 511 byte packets");
5727
5728         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5729                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
5730                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
5731                 0, "Bytes sent in 512 to 1023 byte packets");
5732
5733         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5734                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
5735                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
5736                 0, "Bytes sent in 1024 to 1522 byte packets");
5737
5738         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5739                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
5740                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
5741                 0, "Bytes sent in 1523 to 9022 byte packets");
5742
5743         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5744                 "stat_XonPauseFramesReceived",
5745                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
5746                 0, "XON pause frames receved");
5747
5748         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5749                 "stat_XoffPauseFramesReceived",
5750                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
5751                 0, "XOFF pause frames received");
5752
5753         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5754                 "stat_OutXonSent",
5755                 CTLFLAG_RD, &sc->stat_OutXonSent,
5756                 0, "XON pause frames sent");
5757
5758         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5759                 "stat_OutXoffSent",
5760                 CTLFLAG_RD, &sc->stat_OutXoffSent,
5761                 0, "XOFF pause frames sent");
5762
5763         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5764                 "stat_FlowControlDone",
5765                 CTLFLAG_RD, &sc->stat_FlowControlDone,
5766                 0, "Flow control done");
5767
5768         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5769                 "stat_MacControlFramesReceived",
5770                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
5771                 0, "MAC control frames received");
5772
5773         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5774                 "stat_XoffStateEntered",
5775                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
5776                 0, "XOFF state entered");
5777
5778         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5779                 "stat_IfInFramesL2FilterDiscards",
5780                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
5781                 0, "Received L2 packets discarded");
5782
5783         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5784                 "stat_IfInRuleCheckerDiscards",
5785                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
5786                 0, "Received packets discarded by rule");
5787
5788         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5789                 "stat_IfInFTQDiscards",
5790                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
5791                 0, "Received packet FTQ discards");
5792
5793         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5794                 "stat_IfInMBUFDiscards",
5795                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
5796                 0, "Received packets discarded due to lack of controller buffer memory");
5797
5798         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5799                 "stat_IfInRuleCheckerP4Hit",
5800                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
5801                 0, "Received packets rule checker hits");
5802
5803         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5804                 "stat_CatchupInRuleCheckerDiscards",
5805                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
5806                 0, "Received packets discarded in Catchup path");
5807
5808         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5809                 "stat_CatchupInFTQDiscards",
5810                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
5811                 0, "Received packets discarded in FTQ in Catchup path");
5812
5813         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5814                 "stat_CatchupInMBUFDiscards",
5815                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
5816                 0, "Received packets discarded in controller buffer memory in Catchup path");
5817
5818         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5819                 "stat_CatchupInRuleCheckerP4Hit",
5820                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
5821                 0, "Received packets rule checker hits in Catchup path");
5822
5823         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5824                 "com_no_buffers",
5825                 CTLFLAG_RD, &sc->com_no_buffers,
5826                 0, "Valid packets received but no RX buffers available");
5827
5828 #ifdef BCE_DEBUG
5829         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5830                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
5831                 (void *)sc, 0,
5832                 bce_sysctl_driver_state, "I", "Drive state information");
5833
5834         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5835                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
5836                 (void *)sc, 0,
5837                 bce_sysctl_hw_state, "I", "Hardware state information");
5838
5839         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5840                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
5841                 (void *)sc, 0,
5842                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
5843
5844         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5845                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
5846                 (void *)sc, 0,
5847                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
5848
5849         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5850                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
5851                 (void *)sc, 0,
5852                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
5853
5854         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5855                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
5856                 (void *)sc, 0,
5857                 bce_sysctl_reg_read, "I", "Register read");
5858
5859         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, \r
5860                 "phy_read", CTLTYPE_INT | CTLFLAG_RW, \r
5861                 (void *)sc, 0, \r
5862                 bce_sysctl_phy_read, "I", "PHY register read");
5863
5864 #endif
5865
5866 }
5867
5868
5869 /****************************************************************************/
5870 /* BCE Debug Routines                                                       */
5871 /****************************************************************************/
5872 #ifdef BCE_DEBUG
5873
5874 /****************************************************************************/
5875 /* Freezes the controller to allow for a cohesive state dump.               */
5876 /*                                                                          */
5877 /* Returns:                                                                 */
5878 /*   Nothing.                                                               */
5879 /****************************************************************************/
5880 static void
5881 bce_freeze_controller(struct bce_softc *sc)
5882 {
5883         uint32_t val;
5884
5885         val = REG_RD(sc, BCE_MISC_COMMAND);
5886         val |= BCE_MISC_COMMAND_DISABLE_ALL;
5887         REG_WR(sc, BCE_MISC_COMMAND, val);
5888 }
5889
5890
5891 /****************************************************************************/
5892 /* Unfreezes the controller after a freeze operation.  This may not always  */\r
5893 /* work and the controller will require a reset!                            */
5894 /*                                                                          */
5895 /* Returns:                                                                 */
5896 /*   Nothing.                                                               */
5897 /****************************************************************************/
5898 static void
5899 bce_unfreeze_controller(struct bce_softc *sc)
5900 {
5901         uint32_t val;
5902
5903         val = REG_RD(sc, BCE_MISC_COMMAND);
5904         val |= BCE_MISC_COMMAND_ENABLE_ALL;
5905         REG_WR(sc, BCE_MISC_COMMAND, val);
5906 }
5907
5908
5909 /****************************************************************************/
5910 /* Prints out information about an mbuf.                                    */
5911 /*                                                                          */
5912 /* Returns:                                                                 */
5913 /*   Nothing.                                                               */
5914 /****************************************************************************/
5915 static void
5916 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
5917 {
5918         struct ifnet *ifp = &sc->arpcom.ac_if;
5919         uint32_t val_hi, val_lo;
5920         struct mbuf *mp = m;
5921
5922         if (m == NULL) {
5923                 /* Index out of range. */
5924                 if_printf(ifp, "mbuf: null pointer\n");
5925                 return;
5926         }
5927
5928         while (mp) {
5929                 val_hi = BCE_ADDR_HI(mp);
5930                 val_lo = BCE_ADDR_LO(mp);
5931                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
5932                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
5933
5934                 if (mp->m_flags & M_EXT)
5935                         kprintf("M_EXT ");
5936                 if (mp->m_flags & M_PKTHDR)
5937                         kprintf("M_PKTHDR ");
5938                 if (mp->m_flags & M_EOR)
5939                         kprintf("M_EOR ");
5940 #ifdef M_RDONLY
5941                 if (mp->m_flags & M_RDONLY)
5942                         kprintf("M_RDONLY ");
5943 #endif
5944
5945                 val_hi = BCE_ADDR_HI(mp->m_data);
5946                 val_lo = BCE_ADDR_LO(mp->m_data);
5947                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
5948
5949                 if (mp->m_flags & M_PKTHDR) {
5950                         if_printf(ifp, "- m_pkthdr: flags = ( ");
5951                         if (mp->m_flags & M_BCAST)
5952                                 kprintf("M_BCAST ");
5953                         if (mp->m_flags & M_MCAST)
5954                                 kprintf("M_MCAST ");
5955                         if (mp->m_flags & M_FRAG)
5956                                 kprintf("M_FRAG ");
5957                         if (mp->m_flags & M_FIRSTFRAG)
5958                                 kprintf("M_FIRSTFRAG ");
5959                         if (mp->m_flags & M_LASTFRAG)
5960                                 kprintf("M_LASTFRAG ");
5961 #ifdef M_VLANTAG
5962                         if (mp->m_flags & M_VLANTAG)
5963                                 kprintf("M_VLANTAG ");
5964 #endif
5965 #ifdef M_PROMISC
5966                         if (mp->m_flags & M_PROMISC)
5967                                 kprintf("M_PROMISC ");
5968 #endif
5969                         kprintf(") csum_flags = ( ");
5970                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
5971                                 kprintf("CSUM_IP ");
5972                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
5973                                 kprintf("CSUM_TCP ");
5974                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
5975                                 kprintf("CSUM_UDP ");
5976                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
5977                                 kprintf("CSUM_IP_FRAGS ");
5978                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
5979                                 kprintf("CSUM_FRAGMENT ");
5980 #ifdef CSUM_TSO
5981                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
5982                                 kprintf("CSUM_TSO ");
5983 #endif
5984                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
5985                                 kprintf("CSUM_IP_CHECKED ");
5986                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
5987                                 kprintf("CSUM_IP_VALID ");
5988                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
5989                                 kprintf("CSUM_DATA_VALID ");
5990                         kprintf(")\n");
5991                 }
5992
5993                 if (mp->m_flags & M_EXT) {
5994                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
5995                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
5996                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
5997                                   "ext_size = %d\n",
5998                                   val_hi, val_lo, mp->m_ext.ext_size);
5999                 }
6000                 mp = mp->m_next;
6001         }
6002 }
6003
6004
6005 /****************************************************************************/
6006 /* Prints out the mbufs in the TX mbuf chain.                               */
6007 /*                                                                          */
6008 /* Returns:                                                                 */
6009 /*   Nothing.                                                               */
6010 /****************************************************************************/
6011 static void
6012 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6013 {
6014         struct ifnet *ifp = &sc->arpcom.ac_if;
6015         int i;
6016
6017         if_printf(ifp,
6018         "----------------------------"
6019         "  tx mbuf data  "
6020         "----------------------------\n");
6021
6022         for (i = 0; i < count; i++) {
6023                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6024                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6025                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6026         }
6027
6028         if_printf(ifp,
6029         "----------------------------"
6030         "----------------"
6031         "----------------------------\n");
6032 }
6033
6034
6035 /****************************************************************************/
6036 /* Prints out the mbufs in the RX mbuf chain.                               */
6037 /*                                                                          */
6038 /* Returns:                                                                 */
6039 /*   Nothing.                                                               */
6040 /****************************************************************************/
6041 static void
6042 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6043 {
6044         struct ifnet *ifp = &sc->arpcom.ac_if;
6045         int i;
6046
6047         if_printf(ifp,
6048         "----------------------------"
6049         "  rx mbuf data  "
6050         "----------------------------\n");
6051
6052         for (i = 0; i < count; i++) {
6053                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6054                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6055                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6056         }
6057
6058         if_printf(ifp,
6059         "----------------------------"
6060         "----------------"
6061         "----------------------------\n");
6062 }
6063
6064
6065 /****************************************************************************/
6066 /* Prints out a tx_bd structure.                                            */
6067 /*                                                                          */
6068 /* Returns:                                                                 */
6069 /*   Nothing.                                                               */
6070 /****************************************************************************/
6071 static void
6072 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6073 {
6074         struct ifnet *ifp = &sc->arpcom.ac_if;
6075
6076         if (idx > MAX_TX_BD) {
6077                 /* Index out of range. */
6078                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6079         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6080                 /* TX Chain page pointer. */
6081                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6082                           "chain page pointer\n",
6083                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6084         } else {
6085                 /* Normal tx_bd entry. */
6086                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6087                           "nbytes = 0x%08X, "
6088                           "vlan tag= 0x%04X, flags = 0x%04X (",
6089                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6090                           txbd->tx_bd_mss_nbytes,
6091                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6092
6093                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6094                         kprintf(" CONN_FAULT");
6095
6096                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6097                         kprintf(" TCP_UDP_CKSUM");
6098
6099                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6100                         kprintf(" IP_CKSUM");
6101
6102                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6103                         kprintf("  VLAN");
6104
6105                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6106                         kprintf(" COAL_NOW");
6107
6108                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6109                         kprintf(" DONT_GEN_CRC");
6110
6111                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6112                         kprintf(" START");
6113
6114                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6115                         kprintf(" END");
6116
6117                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6118                         kprintf(" LSO");
6119
6120                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6121                         kprintf(" OPTION_WORD");
6122
6123                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6124                         kprintf(" FLAGS");
6125
6126                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6127                         kprintf(" SNAP");
6128
6129                 kprintf(" )\n");
6130         }
6131 }
6132
6133
6134 /****************************************************************************/
6135 /* Prints out a rx_bd structure.                                            */
6136 /*                                                                          */
6137 /* Returns:                                                                 */
6138 /*   Nothing.                                                               */
6139 /****************************************************************************/
6140 static void
6141 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6142 {
6143         struct ifnet *ifp = &sc->arpcom.ac_if;
6144
6145         if (idx > MAX_RX_BD) {
6146                 /* Index out of range. */
6147                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6148         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6149                 /* TX Chain page pointer. */
6150                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6151                           "chain page pointer\n",
6152                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6153         } else {
6154                 /* Normal tx_bd entry. */
6155                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6156                           "nbytes = 0x%08X, flags = 0x%08X\n",
6157                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6158                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6159         }
6160 }
6161
6162
6163 /****************************************************************************/
6164 /* Prints out a l2_fhdr structure.                                          */
6165 /*                                                                          */
6166 /* Returns:                                                                 */
6167 /*   Nothing.                                                               */
6168 /****************************************************************************/
6169 static void
6170 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6171 {
6172         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6173                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6174                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6175                   idx, l2fhdr->l2_fhdr_status,
6176                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6177                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6178 }
6179
6180
6181 /****************************************************************************/
6182 /* Prints out the tx chain.                                                 */
6183 /*                                                                          */
6184 /* Returns:                                                                 */
6185 /*   Nothing.                                                               */
6186 /****************************************************************************/
6187 static void
6188 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6189 {
6190         struct ifnet *ifp = &sc->arpcom.ac_if;
6191         int i;
6192
6193         /* First some info about the tx_bd chain structure. */
6194         if_printf(ifp,
6195         "----------------------------"
6196         "  tx_bd  chain  "
6197         "----------------------------\n");
6198
6199         if_printf(ifp, "page size      = 0x%08X, "
6200                   "tx chain pages        = 0x%08X\n",
6201                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6202
6203         if_printf(ifp, "tx_bd per page = 0x%08X, "
6204                   "usable tx_bd per page = 0x%08X\n",
6205                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6206                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6207
6208         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6209
6210         if_printf(ifp,
6211         "----------------------------"
6212         "  tx_bd data    "
6213         "----------------------------\n");
6214
6215         /* Now print out the tx_bd's themselves. */
6216         for (i = 0; i < count; i++) {
6217                 struct tx_bd *txbd;
6218
6219                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6220                 bce_dump_txbd(sc, tx_prod, txbd);
6221                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6222         }
6223
6224         if_printf(ifp,
6225         "----------------------------"
6226         "----------------"
6227         "----------------------------\n");
6228 }
6229
6230
6231 /****************************************************************************/
6232 /* Prints out the rx chain.                                                 */
6233 /*                                                                          */
6234 /* Returns:                                                                 */
6235 /*   Nothing.                                                               */
6236 /****************************************************************************/
6237 static void
6238 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6239 {
6240         struct ifnet *ifp = &sc->arpcom.ac_if;
6241         int i;
6242
6243         /* First some info about the tx_bd chain structure. */
6244         if_printf(ifp,
6245         "----------------------------"
6246         "  rx_bd  chain  "
6247         "----------------------------\n");
6248
6249         if_printf(ifp, "page size      = 0x%08X, "
6250                   "rx chain pages        = 0x%08X\n",
6251                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6252
6253         if_printf(ifp, "rx_bd per page = 0x%08X, "
6254                   "usable rx_bd per page = 0x%08X\n",
6255                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6256                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6257
6258         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6259
6260         if_printf(ifp,
6261         "----------------------------"
6262         "   rx_bd data   "
6263         "----------------------------\n");
6264
6265         /* Now print out the rx_bd's themselves. */
6266         for (i = 0; i < count; i++) {
6267                 struct rx_bd *rxbd;
6268
6269                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6270                 bce_dump_rxbd(sc, rx_prod, rxbd);
6271                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6272         }
6273
6274         if_printf(ifp,
6275         "----------------------------"
6276         "----------------"
6277         "----------------------------\n");
6278 }
6279
6280
6281 /****************************************************************************/
6282 /* Prints out the status block from host memory.                            */
6283 /*                                                                          */
6284 /* Returns:                                                                 */
6285 /*   Nothing.                                                               */
6286 /****************************************************************************/
6287 static void
6288 bce_dump_status_block(struct bce_softc *sc)
6289 {
6290         struct status_block *sblk = sc->status_block;
6291         struct ifnet *ifp = &sc->arpcom.ac_if;
6292
6293         if_printf(ifp,
6294         "----------------------------"
6295         "  Status Block  "
6296         "----------------------------\n");
6297
6298         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6299
6300         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6301                   sblk->status_attn_bits_ack);
6302
6303         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6304             sblk->status_rx_quick_consumer_index0,
6305             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6306
6307         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6308             sblk->status_tx_quick_consumer_index0,
6309             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6310
6311         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6312
6313         /* Theses indices are not used for normal L2 drivers. */
6314         if (sblk->status_rx_quick_consumer_index1) {
6315                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6316                 sblk->status_rx_quick_consumer_index1,
6317                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6318         }
6319
6320         if (sblk->status_tx_quick_consumer_index1) {
6321                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6322                 sblk->status_tx_quick_consumer_index1,
6323                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6324         }
6325
6326         if (sblk->status_rx_quick_consumer_index2) {
6327                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6328                 sblk->status_rx_quick_consumer_index2,
6329                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6330         }
6331
6332         if (sblk->status_tx_quick_consumer_index2) {
6333                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6334                 sblk->status_tx_quick_consumer_index2,
6335                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6336         }
6337
6338         if (sblk->status_rx_quick_consumer_index3) {
6339                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6340                 sblk->status_rx_quick_consumer_index3,
6341                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6342         }
6343
6344         if (sblk->status_tx_quick_consumer_index3) {
6345                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6346                 sblk->status_tx_quick_consumer_index3,
6347                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6348         }
6349
6350         if (sblk->status_rx_quick_consumer_index4 ||
6351             sblk->status_rx_quick_consumer_index5) {
6352                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
6353                           sblk->status_rx_quick_consumer_index4,
6354                           sblk->status_rx_quick_consumer_index5);
6355         }
6356
6357         if (sblk->status_rx_quick_consumer_index6 ||
6358             sblk->status_rx_quick_consumer_index7) {
6359                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
6360                           sblk->status_rx_quick_consumer_index6,
6361                           sblk->status_rx_quick_consumer_index7);
6362         }
6363
6364         if (sblk->status_rx_quick_consumer_index8 ||
6365             sblk->status_rx_quick_consumer_index9) {
6366                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
6367                           sblk->status_rx_quick_consumer_index8,
6368                           sblk->status_rx_quick_consumer_index9);
6369         }
6370
6371         if (sblk->status_rx_quick_consumer_index10 ||
6372             sblk->status_rx_quick_consumer_index11) {
6373                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
6374                           sblk->status_rx_quick_consumer_index10,
6375                           sblk->status_rx_quick_consumer_index11);
6376         }
6377
6378         if (sblk->status_rx_quick_consumer_index12 ||
6379             sblk->status_rx_quick_consumer_index13) {
6380                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
6381                           sblk->status_rx_quick_consumer_index12,
6382                           sblk->status_rx_quick_consumer_index13);
6383         }
6384
6385         if (sblk->status_rx_quick_consumer_index14 ||
6386             sblk->status_rx_quick_consumer_index15) {
6387                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
6388                           sblk->status_rx_quick_consumer_index14,
6389                           sblk->status_rx_quick_consumer_index15);
6390         }
6391
6392         if (sblk->status_completion_producer_index ||
6393             sblk->status_cmd_consumer_index) {
6394                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
6395                           sblk->status_completion_producer_index,
6396                           sblk->status_cmd_consumer_index);
6397         }
6398
6399         if_printf(ifp,
6400         "----------------------------"
6401         "----------------"
6402         "----------------------------\n");
6403 }
6404
6405
6406 /****************************************************************************/
6407 /* Prints out the statistics block.                                         */
6408 /*                                                                          */
6409 /* Returns:                                                                 */
6410 /*   Nothing.                                                               */
6411 /****************************************************************************/
6412 static void
6413 bce_dump_stats_block(struct bce_softc *sc)
6414 {
6415         struct statistics_block *sblk = sc->stats_block;
6416         struct ifnet *ifp = &sc->arpcom.ac_if;
6417
6418         if_printf(ifp,
6419         "---------------"
6420         " Stats Block  (All Stats Not Shown Are 0) "
6421         "---------------\n");
6422
6423         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6424                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6425                           sblk->stat_IfHCInOctets_hi,
6426                           sblk->stat_IfHCInOctets_lo);
6427         }
6428
6429         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6430                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6431                           sblk->stat_IfHCInBadOctets_hi,
6432                           sblk->stat_IfHCInBadOctets_lo);
6433         }
6434
6435         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6436                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6437                           sblk->stat_IfHCOutOctets_hi,
6438                           sblk->stat_IfHCOutOctets_lo);
6439         }
6440
6441         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6442                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6443                           sblk->stat_IfHCOutBadOctets_hi,
6444                           sblk->stat_IfHCOutBadOctets_lo);
6445         }
6446
6447         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6448                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6449                           sblk->stat_IfHCInUcastPkts_hi,
6450                           sblk->stat_IfHCInUcastPkts_lo);
6451         }
6452
6453         if (sblk->stat_IfHCInBroadcastPkts_hi ||
6454             sblk->stat_IfHCInBroadcastPkts_lo) {
6455                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6456                           sblk->stat_IfHCInBroadcastPkts_hi,
6457                           sblk->stat_IfHCInBroadcastPkts_lo);
6458         }
6459
6460         if (sblk->stat_IfHCInMulticastPkts_hi ||
6461             sblk->stat_IfHCInMulticastPkts_lo) {
6462                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6463                           sblk->stat_IfHCInMulticastPkts_hi,
6464                           sblk->stat_IfHCInMulticastPkts_lo);
6465         }
6466
6467         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6468                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6469                           sblk->stat_IfHCOutUcastPkts_hi,
6470                           sblk->stat_IfHCOutUcastPkts_lo);
6471         }
6472
6473         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6474             sblk->stat_IfHCOutBroadcastPkts_lo) {
6475                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6476                           sblk->stat_IfHCOutBroadcastPkts_hi,
6477                           sblk->stat_IfHCOutBroadcastPkts_lo);
6478         }
6479
6480         if (sblk->stat_IfHCOutMulticastPkts_hi ||
6481             sblk->stat_IfHCOutMulticastPkts_lo) {
6482                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6483                           sblk->stat_IfHCOutMulticastPkts_hi,
6484                           sblk->stat_IfHCOutMulticastPkts_lo);
6485         }
6486
6487         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6488                 if_printf(ifp, "         0x%08X : "
6489                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6490                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6491         }
6492
6493         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6494                 if_printf(ifp, "         0x%08X : "
6495                           "Dot3StatsCarrierSenseErrors\n",
6496                           sblk->stat_Dot3StatsCarrierSenseErrors);
6497         }
6498
6499         if (sblk->stat_Dot3StatsFCSErrors) {
6500                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
6501                           sblk->stat_Dot3StatsFCSErrors);
6502         }
6503
6504         if (sblk->stat_Dot3StatsAlignmentErrors) {
6505                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
6506                           sblk->stat_Dot3StatsAlignmentErrors);
6507         }
6508
6509         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6510                 if_printf(ifp, "         0x%08X : "
6511                           "Dot3StatsSingleCollisionFrames\n",
6512                           sblk->stat_Dot3StatsSingleCollisionFrames);
6513         }
6514
6515         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
6516                 if_printf(ifp, "         0x%08X : "
6517                           "Dot3StatsMultipleCollisionFrames\n",
6518                           sblk->stat_Dot3StatsMultipleCollisionFrames);
6519         }
6520
6521         if (sblk->stat_Dot3StatsDeferredTransmissions) {
6522                 if_printf(ifp, "         0x%08X : "
6523                           "Dot3StatsDeferredTransmissions\n",
6524                           sblk->stat_Dot3StatsDeferredTransmissions);
6525         }
6526
6527         if (sblk->stat_Dot3StatsExcessiveCollisions) {
6528                 if_printf(ifp, "         0x%08X : "
6529                           "Dot3StatsExcessiveCollisions\n",
6530                           sblk->stat_Dot3StatsExcessiveCollisions);
6531         }
6532
6533         if (sblk->stat_Dot3StatsLateCollisions) {
6534                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
6535                           sblk->stat_Dot3StatsLateCollisions);
6536         }
6537
6538         if (sblk->stat_EtherStatsCollisions) {
6539                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
6540                           sblk->stat_EtherStatsCollisions);
6541         }
6542
6543         if (sblk->stat_EtherStatsFragments)  {
6544                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
6545                           sblk->stat_EtherStatsFragments);
6546         }
6547
6548         if (sblk->stat_EtherStatsJabbers) {
6549                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
6550                           sblk->stat_EtherStatsJabbers);
6551         }
6552
6553         if (sblk->stat_EtherStatsUndersizePkts) {
6554                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
6555                           sblk->stat_EtherStatsUndersizePkts);
6556         }
6557
6558         if (sblk->stat_EtherStatsOverrsizePkts) {
6559                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
6560                           sblk->stat_EtherStatsOverrsizePkts);
6561         }
6562
6563         if (sblk->stat_EtherStatsPktsRx64Octets) {
6564                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
6565                           sblk->stat_EtherStatsPktsRx64Octets);
6566         }
6567
6568         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
6569                 if_printf(ifp, "         0x%08X : "
6570                           "EtherStatsPktsRx65Octetsto127Octets\n",
6571                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
6572         }
6573
6574         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
6575                 if_printf(ifp, "         0x%08X : "
6576                           "EtherStatsPktsRx128Octetsto255Octets\n",
6577                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
6578         }
6579
6580         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
6581                 if_printf(ifp, "         0x%08X : "
6582                           "EtherStatsPktsRx256Octetsto511Octets\n",
6583                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
6584         }
6585
6586         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
6587                 if_printf(ifp, "         0x%08X : "
6588                           "EtherStatsPktsRx512Octetsto1023Octets\n",
6589                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
6590         }
6591
6592         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
6593                 if_printf(ifp, "         0x%08X : "
6594                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
6595                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
6596         }
6597
6598         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
6599                 if_printf(ifp, "         0x%08X : "
6600                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
6601                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
6602         }
6603
6604         if (sblk->stat_EtherStatsPktsTx64Octets) {
6605                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
6606                           sblk->stat_EtherStatsPktsTx64Octets);
6607         }
6608
6609         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
6610                 if_printf(ifp, "         0x%08X : "
6611                           "EtherStatsPktsTx65Octetsto127Octets\n",
6612                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
6613         }
6614
6615         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
6616                 if_printf(ifp, "         0x%08X : "
6617                           "EtherStatsPktsTx128Octetsto255Octets\n",
6618                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
6619         }
6620
6621         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
6622                 if_printf(ifp, "         0x%08X : "
6623                           "EtherStatsPktsTx256Octetsto511Octets\n",
6624                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
6625         }
6626
6627         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
6628                 if_printf(ifp, "         0x%08X : "
6629                           "EtherStatsPktsTx512Octetsto1023Octets\n",
6630                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
6631         }
6632
6633         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
6634                 if_printf(ifp, "         0x%08X : "
6635                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
6636                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
6637         }
6638
6639         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
6640                 if_printf(ifp, "         0x%08X : "
6641                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
6642                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
6643         }
6644
6645         if (sblk->stat_XonPauseFramesReceived) {
6646                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
6647                           sblk->stat_XonPauseFramesReceived);
6648         }
6649
6650         if (sblk->stat_XoffPauseFramesReceived) {
6651                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
6652                           sblk->stat_XoffPauseFramesReceived);
6653         }
6654
6655         if (sblk->stat_OutXonSent) {
6656                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
6657                           sblk->stat_OutXonSent);
6658         }
6659
6660         if (sblk->stat_OutXoffSent) {
6661                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
6662                           sblk->stat_OutXoffSent);
6663         }
6664
6665         if (sblk->stat_FlowControlDone) {
6666                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
6667                           sblk->stat_FlowControlDone);
6668         }
6669
6670         if (sblk->stat_MacControlFramesReceived) {
6671                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
6672                           sblk->stat_MacControlFramesReceived);
6673         }
6674
6675         if (sblk->stat_XoffStateEntered) {
6676                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
6677                           sblk->stat_XoffStateEntered);
6678         }
6679
6680         if (sblk->stat_IfInFramesL2FilterDiscards) {
6681                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
6682         }
6683
6684         if (sblk->stat_IfInRuleCheckerDiscards) {
6685                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
6686                           sblk->stat_IfInRuleCheckerDiscards);
6687         }
6688
6689         if (sblk->stat_IfInFTQDiscards) {
6690                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
6691                           sblk->stat_IfInFTQDiscards);
6692         }
6693
6694         if (sblk->stat_IfInMBUFDiscards) {
6695                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
6696                           sblk->stat_IfInMBUFDiscards);
6697         }
6698
6699         if (sblk->stat_IfInRuleCheckerP4Hit) {
6700                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
6701                           sblk->stat_IfInRuleCheckerP4Hit);
6702         }
6703
6704         if (sblk->stat_CatchupInRuleCheckerDiscards) {
6705                 if_printf(ifp, "         0x%08X : "
6706                           "CatchupInRuleCheckerDiscards\n",
6707                           sblk->stat_CatchupInRuleCheckerDiscards);
6708         }
6709
6710         if (sblk->stat_CatchupInFTQDiscards) {
6711                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
6712                           sblk->stat_CatchupInFTQDiscards);
6713         }
6714
6715         if (sblk->stat_CatchupInMBUFDiscards) {
6716                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
6717                           sblk->stat_CatchupInMBUFDiscards);
6718         }
6719
6720         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
6721                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
6722                           sblk->stat_CatchupInRuleCheckerP4Hit);
6723         }
6724
6725         if_printf(ifp,
6726         "----------------------------"
6727         "----------------"
6728         "----------------------------\n");
6729 }
6730
6731
6732 /****************************************************************************/
6733 /* Prints out a summary of the driver state.                                */
6734 /*                                                                          */
6735 /* Returns:                                                                 */
6736 /*   Nothing.                                                               */
6737 /****************************************************************************/
6738 static void
6739 bce_dump_driver_state(struct bce_softc *sc)
6740 {
6741         struct ifnet *ifp = &sc->arpcom.ac_if;
6742         uint32_t val_hi, val_lo;
6743
6744         if_printf(ifp,
6745         "-----------------------------"
6746         " Driver State "
6747         "-----------------------------\n");
6748
6749         val_hi = BCE_ADDR_HI(sc);
6750         val_lo = BCE_ADDR_LO(sc);
6751         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
6752                   "virtual address\n", val_hi, val_lo);
6753
6754         val_hi = BCE_ADDR_HI(sc->status_block);
6755         val_lo = BCE_ADDR_LO(sc->status_block);
6756         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
6757                   "virtual address\n", val_hi, val_lo);
6758
6759         val_hi = BCE_ADDR_HI(sc->stats_block);
6760         val_lo = BCE_ADDR_LO(sc->stats_block);
6761         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
6762                   "virtual address\n", val_hi, val_lo);
6763
6764         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
6765         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
6766         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
6767                   "virtual adddress\n", val_hi, val_lo);
6768
6769         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
6770         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
6771         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
6772                   "virtual address\n", val_hi, val_lo);
6773
6774         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
6775         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
6776         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
6777                   "virtual address\n", val_hi, val_lo);
6778
6779         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
6780         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
6781         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
6782                   "virtual address\n", val_hi, val_lo);
6783
6784         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
6785                   "h/w intrs\n", sc->interrupts_generated);
6786
6787         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
6788                   "rx interrupts handled\n", sc->rx_interrupts);
6789
6790         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
6791                   "tx interrupts handled\n", sc->tx_interrupts);
6792
6793         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
6794                   "status block index\n", sc->last_status_idx);
6795
6796         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
6797                   "tx producer index\n",
6798                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
6799
6800         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
6801                   "tx consumer index\n",
6802                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
6803
6804         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
6805                   "tx producer bseq index\n", sc->tx_prod_bseq);
6806
6807         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
6808                   "rx producer index\n",
6809                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
6810
6811         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
6812                   "rx consumer index\n",
6813                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
6814
6815         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
6816                   "rx producer bseq index\n", sc->rx_prod_bseq);
6817
6818         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
6819                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6820
6821         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
6822                   "free rx_bd's\n", sc->free_rx_bd);
6823
6824         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
6825                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
6826
6827         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
6828                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
6829
6830         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
6831                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6832
6833         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
6834                   sc->used_tx_bd);
6835
6836         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
6837                   sc->tx_hi_watermark, sc->max_tx_bd);
6838
6839         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
6840                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
6841
6842         if_printf(ifp,
6843         "----------------------------"
6844         "----------------"
6845         "----------------------------\n");
6846 }
6847
6848
6849 /****************************************************************************/
6850 /* Prints out the hardware state through a summary of important registers,  */\r
6851 /* followed by a complete register dump.                                    */
6852 /*                                                                          */
6853 /* Returns:                                                                 */
6854 /*   Nothing.                                                               */
6855 /****************************************************************************/
6856 static void
6857 bce_dump_hw_state(struct bce_softc *sc)
6858 {
6859         struct ifnet *ifp = &sc->arpcom.ac_if;
6860         uint32_t val1;
6861         int i;
6862
6863         if_printf(ifp,
6864         "----------------------------"
6865         " Hardware State "
6866         "----------------------------\n");
6867
6868         if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver);
6869
6870         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
6871         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
6872                   val1, BCE_MISC_ENABLE_STATUS_BITS);
6873
6874         val1 = REG_RD(sc, BCE_DMA_STATUS);
6875         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
6876
6877         val1 = REG_RD(sc, BCE_CTX_STATUS);
6878         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
6879
6880         val1 = REG_RD(sc, BCE_EMAC_STATUS);
6881         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
6882                   val1, BCE_EMAC_STATUS);
6883
6884         val1 = REG_RD(sc, BCE_RPM_STATUS);
6885         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
6886
6887         val1 = REG_RD(sc, BCE_TBDR_STATUS);
6888         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
6889                   val1, BCE_TBDR_STATUS);
6890
6891         val1 = REG_RD(sc, BCE_TDMA_STATUS);
6892         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
6893                   val1, BCE_TDMA_STATUS);
6894
6895         val1 = REG_RD(sc, BCE_HC_STATUS);
6896         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
6897
6898         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
6899         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
6900                   val1, BCE_TXP_CPU_STATE);
6901
6902         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
6903         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
6904                   val1, BCE_TPAT_CPU_STATE);
6905
6906         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
6907         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
6908                   val1, BCE_RXP_CPU_STATE);
6909
6910         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
6911         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
6912                   val1, BCE_COM_CPU_STATE);
6913
6914         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
6915         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
6916                   val1, BCE_MCP_CPU_STATE);
6917
6918         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
6919         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
6920                   val1, BCE_CP_CPU_STATE);
6921
6922         if_printf(ifp,
6923         "----------------------------"
6924         "----------------"
6925         "----------------------------\n");
6926
6927         if_printf(ifp,
6928         "----------------------------"
6929         " Register  Dump "
6930         "----------------------------\n");
6931
6932         for (i = 0x400; i < 0x8000; i += 0x10) {
6933                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
6934                           REG_RD(sc, i),
6935                           REG_RD(sc, i + 0x4),
6936                           REG_RD(sc, i + 0x8),
6937                           REG_RD(sc, i + 0xc));
6938         }
6939
6940         if_printf(ifp,
6941         "----------------------------"
6942         "----------------"
6943         "----------------------------\n");
6944 }
6945
6946
6947 /****************************************************************************/
6948 /* Prints out the TXP state.                                                */\r
6949 /*                                                                          */
6950 /* Returns:                                                                 */
6951 /*   Nothing.                                                               */
6952 /****************************************************************************/
6953 static void
6954 bce_dump_txp_state(struct bce_softc *sc)
6955 {
6956         struct ifnet *ifp = &sc->arpcom.ac_if;
6957         uint32_t val1;
6958         int i;
6959
6960         if_printf(ifp,
6961         "----------------------------"
6962         "   TXP  State   "
6963         "----------------------------\n");
6964
6965         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
6966         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
6967                   val1, BCE_TXP_CPU_MODE);
6968
6969         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
6970         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
6971                   val1, BCE_TXP_CPU_STATE);
6972
6973         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
6974         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
6975                   val1, BCE_TXP_CPU_EVENT_MASK);
6976
6977         if_printf(ifp,
6978         "----------------------------"
6979         " Register  Dump "
6980         "----------------------------\n");
6981
6982         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
6983                 /* Skip the big blank spaces */
6984                 if (i < 0x454000 && i > 0x5ffff) {
6985                         if_printf(ifp, "0x%04X: "
6986                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
6987                                   REG_RD_IND(sc, i),
6988                                   REG_RD_IND(sc, i + 0x4),
6989                                   REG_RD_IND(sc, i + 0x8),
6990                                   REG_RD_IND(sc, i + 0xc));
6991                 }
6992         }
6993
6994         if_printf(ifp,
6995         "----------------------------"
6996         "----------------"
6997         "----------------------------\n");
6998 }
6999
7000
7001 /****************************************************************************/
7002 /* Prints out the RXP state.                                                */\r
7003 /*                                                                          */
7004 /* Returns:                                                                 */
7005 /*   Nothing.                                                               */
7006 /****************************************************************************/
7007 static void
7008 bce_dump_rxp_state(struct bce_softc *sc)
7009 {
7010         struct ifnet *ifp = &sc->arpcom.ac_if;
7011         uint32_t val1;
7012         int i;
7013
7014         if_printf(ifp,
7015         "----------------------------"
7016         "   RXP  State   "
7017         "----------------------------\n");
7018
7019         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7020         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7021                   val1, BCE_RXP_CPU_MODE);
7022
7023         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7024         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7025                   val1, BCE_RXP_CPU_STATE);
7026
7027         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7028         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7029                   val1, BCE_RXP_CPU_EVENT_MASK);
7030
7031         if_printf(ifp,
7032         "----------------------------"
7033         " Register  Dump "
7034         "----------------------------\n");
7035
7036         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7037                 /* Skip the big blank sapces */
7038                 if (i < 0xc5400 && i > 0xdffff) {
7039                         if_printf(ifp, "0x%04X: "
7040                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7041                                   REG_RD_IND(sc, i),
7042                                   REG_RD_IND(sc, i + 0x4),
7043                                   REG_RD_IND(sc, i + 0x8),
7044                                   REG_RD_IND(sc, i + 0xc));
7045                 }
7046         }
7047
7048         if_printf(ifp,
7049         "----------------------------"
7050         "----------------"
7051         "----------------------------\n");
7052 }
7053
7054
7055 /****************************************************************************/
7056 /* Prints out the TPAT state.                                               */\r
7057 /*                                                                          */
7058 /* Returns:                                                                 */
7059 /*   Nothing.                                                               */
7060 /****************************************************************************/
7061 static void
7062 bce_dump_tpat_state(struct bce_softc *sc)
7063 {
7064         struct ifnet *ifp = &sc->arpcom.ac_if;
7065         uint32_t val1;
7066         int i;
7067
7068         if_printf(ifp,
7069         "----------------------------"
7070         "   TPAT State   "
7071         "----------------------------\n");
7072
7073         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7074         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7075                   val1, BCE_TPAT_CPU_MODE);
7076
7077         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7078         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7079                   val1, BCE_TPAT_CPU_STATE);
7080
7081         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7082         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7083                   val1, BCE_TPAT_CPU_EVENT_MASK);
7084
7085         if_printf(ifp,
7086         "----------------------------"
7087         " Register  Dump "
7088         "----------------------------\n");
7089
7090         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7091                 /* Skip the big blank spaces */
7092                 if (i < 0x854000 && i > 0x9ffff) {
7093                         if_printf(ifp, "0x%04X: "
7094                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7095                                   REG_RD_IND(sc, i),
7096                                   REG_RD_IND(sc, i + 0x4),
7097                                   REG_RD_IND(sc, i + 0x8),
7098                                   REG_RD_IND(sc, i + 0xc));
7099                 }
7100         }
7101
7102         if_printf(ifp,
7103         "----------------------------"
7104         "----------------"
7105         "----------------------------\n");
7106 }
7107
7108
7109 /****************************************************************************/
7110 /* Prints out the driver state and then enters the debugger.                */
7111 /*                                                                          */
7112 /* Returns:                                                                 */
7113 /*   Nothing.                                                               */
7114 /****************************************************************************/
7115 static void
7116 bce_breakpoint(struct bce_softc *sc)
7117 {
7118 #if 0
7119         bce_freeze_controller(sc);
7120 #endif
7121
7122         bce_dump_driver_state(sc);
7123         bce_dump_status_block(sc);
7124         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7125         bce_dump_hw_state(sc);
7126         bce_dump_txp_state(sc);
7127
7128 #if 0
7129         bce_unfreeze_controller(sc);
7130 #endif
7131
7132         /* Call the debugger. */
7133         breakpoint();
7134 }
7135
7136 #endif  /* BCE_DEBUG */
7137
7138 static int
7139 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7140 {
7141         struct bce_softc *sc = arg1;
7142
7143         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7144                         &sc->bce_tx_quick_cons_trip_int,
7145                         BCE_COALMASK_TX_BDS_INT);
7146 }
7147
7148 static int
7149 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7150 {
7151         struct bce_softc *sc = arg1;
7152
7153         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7154                         &sc->bce_tx_quick_cons_trip,
7155                         BCE_COALMASK_TX_BDS);
7156 }
7157
7158 static int
7159 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7160 {
7161         struct bce_softc *sc = arg1;
7162
7163         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7164                         &sc->bce_tx_ticks_int,
7165                         BCE_COALMASK_TX_TICKS_INT);
7166 }
7167
7168 static int
7169 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7170 {
7171         struct bce_softc *sc = arg1;
7172
7173         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7174                         &sc->bce_tx_ticks,
7175                         BCE_COALMASK_TX_TICKS);
7176 }
7177
7178 static int
7179 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7180 {
7181         struct bce_softc *sc = arg1;
7182
7183         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7184                         &sc->bce_rx_quick_cons_trip_int,
7185                         BCE_COALMASK_RX_BDS_INT);
7186 }
7187
7188 static int
7189 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7190 {
7191         struct bce_softc *sc = arg1;
7192
7193         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7194                         &sc->bce_rx_quick_cons_trip,
7195                         BCE_COALMASK_RX_BDS);
7196 }
7197
7198 static int
7199 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7200 {
7201         struct bce_softc *sc = arg1;
7202
7203         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7204                         &sc->bce_rx_ticks_int,
7205                         BCE_COALMASK_RX_TICKS_INT);
7206 }
7207
7208 static int
7209 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7210 {
7211         struct bce_softc *sc = arg1;
7212
7213         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7214                         &sc->bce_rx_ticks,
7215                         BCE_COALMASK_RX_TICKS);
7216 }
7217
7218 static int
7219 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7220                        uint32_t coalchg_mask)
7221 {
7222         struct bce_softc *sc = arg1;
7223         struct ifnet *ifp = &sc->arpcom.ac_if;
7224         int error = 0, v;
7225
7226         lwkt_serialize_enter(ifp->if_serializer);
7227
7228         v = *coal;
7229         error = sysctl_handle_int(oidp, &v, 0, req);
7230         if (!error && req->newptr != NULL) {
7231                 if (v < 0) {
7232                         error = EINVAL;
7233                 } else {
7234                         *coal = v;
7235                         sc->bce_coalchg_mask |= coalchg_mask;
7236                 }
7237         }
7238
7239         lwkt_serialize_exit(ifp->if_serializer);
7240         return error;
7241 }
7242
7243 static void
7244 bce_coal_change(struct bce_softc *sc)
7245 {
7246         struct ifnet *ifp = &sc->arpcom.ac_if;
7247
7248         ASSERT_SERIALIZED(ifp->if_serializer);
7249
7250         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7251                 sc->bce_coalchg_mask = 0;
7252                 return;
7253         }
7254
7255         if (sc->bce_coalchg_mask &
7256             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7257                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7258                        (sc->bce_tx_quick_cons_trip_int << 16) |
7259                        sc->bce_tx_quick_cons_trip);
7260                 if (bootverbose) {
7261                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7262                                   sc->bce_tx_quick_cons_trip,
7263                                   sc->bce_tx_quick_cons_trip_int);
7264                 }
7265         }
7266
7267         if (sc->bce_coalchg_mask &
7268             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7269                 REG_WR(sc, BCE_HC_TX_TICKS,
7270                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7271                 if (bootverbose) {
7272                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7273                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7274                 }
7275         }
7276
7277         if (sc->bce_coalchg_mask &
7278             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7279                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7280                        (sc->bce_rx_quick_cons_trip_int << 16) |
7281                        sc->bce_rx_quick_cons_trip);
7282                 if (bootverbose) {
7283                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7284                                   sc->bce_rx_quick_cons_trip,
7285                                   sc->bce_rx_quick_cons_trip_int);
7286                 }
7287         }
7288
7289         if (sc->bce_coalchg_mask &
7290             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7291                 REG_WR(sc, BCE_HC_RX_TICKS,
7292                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7293                 if (bootverbose) {
7294                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7295                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7296                 }
7297         }
7298
7299         sc->bce_coalchg_mask = 0;
7300 }