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38 * EM_TXD: Maximum number of Transmit Descriptors
39 * Valid Range: 256 for 82542 and 82543-based adapters
42 * This value is the number of transmit descriptors allocated by the driver.
43 * Increasing this value allows the driver to queue more transmits. Each
44 * descriptor is 16 bytes.
45 * Since TDLEN should be multiple of 128bytes, the number of transmit
46 * desscriptors should meet the following condition.
47 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
49 #define EM_MIN_TXD 256
50 #define EM_MAX_TXD_82543 EM_MIN_TXD
51 #define EM_MAX_TXD 4096
52 #define EM_DEFAULT_TXD 512
55 * EM_RXD - Maximum number of receive Descriptors
56 * Valid Range: 256 for 82542 and 82543-based adapters
59 * This value is the number of receive descriptors allocated by the driver.
60 * Increasing this value allows the driver to buffer more incoming packets.
61 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
62 * descriptor. The maximum MTU size is 16110.
63 * Since TDLEN should be multiple of 128bytes, the number of transmit
64 * desscriptors should meet the following condition.
65 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
67 #define EM_MIN_RXD 256
68 #define EM_MAX_RXD_82543 EM_MIN_RXD
69 #define EM_MAX_RXD 4096
70 #define EM_DEFAULT_RXD 512
73 * EM_TIDV - Transmit Interrupt Delay Value
74 * Valid Range: 0-65535 (0=off)
76 * This value delays the generation of transmit interrupts in units of
77 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
78 * efficiency if properly tuned for specific network traffic. If the
79 * system is reporting dropped transmits, this value may be set too high
80 * causing the driver to run out of available transmit descriptors.
83 * It is not used. In DragonFly the TX interrupt moderation is done by
84 * conditionally setting RS bit in TX descriptors. See the description
90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
92 * Valid Range: 0-65535 (0=off)
94 * This value, in units of 1.024 microseconds, limits the delay in which a
95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
98 * along with EM_TIDV, may improve traffic throughput in specific
102 * It is not used. In DragonFly the TX interrupt moderation is done by
103 * conditionally setting RS bit in TX descriptors. See the description
109 * Receive Interrupt Delay Timer (Packet Timer)
112 * RDTR and RADV are deprecated; use ITR instead. They are only used to
113 * workaround hardware bug on certain 82573 based NICs.
115 #define EM_RDTR_82573 32
118 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
121 * RDTR and RADV are deprecated; use ITR instead. They are only used to
122 * workaround hardware bug on certain 82573 based NICs.
124 #define EM_RADV_82573 64
127 * This parameter controls the duration of transmit watchdog timer.
129 #define EM_TX_TIMEOUT 5
131 /* One for TX csum offloading desc, the other 2 are reserved */
132 #define EM_TX_RESERVED 3
134 /* Large enough for 16K jumbo frame */
135 #define EM_TX_SPARE 8
136 /* Large enough for 64K jumbo frame */
137 #define EM_TX_SPARE_TSO 33
139 #define EM_TX_OACTIVE_MAX 64
141 /* Interrupt throttle rate */
142 #define EM_DEFAULT_ITR 6000
145 * This parameter controls whether or not autonegotation is enabled.
146 * 0 - Disable autonegotiation
147 * 1 - Enable autonegotiation
149 #define DO_AUTO_NEG 1
152 * This parameter control whether or not the driver will wait for
153 * autonegotiation to complete.
154 * 1 - Wait for autonegotiation to complete
155 * 0 - Don't wait for autonegotiation to complete
157 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
159 /* Tunables -- End */
161 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \
162 ADVERTISE_10_FULL | \
163 ADVERTISE_100_HALF | \
164 ADVERTISE_100_FULL | \
167 #define AUTO_ALL_MODES 0
169 /* PHY master/slave setting */
170 #define EM_MASTER_SLAVE e1000_ms_hw_default
173 * Micellaneous constants
175 #define EM_VENDOR_ID 0x8086
177 #define EM_BAR_MEM PCIR_BAR(0)
178 #define EM_BAR_FLASH PCIR_BAR(1)
180 #define EM_JUMBO_PBA 0x00000028
181 #define EM_DEFAULT_PBA 0x00000030
182 #define EM_SMARTSPEED_DOWNSHIFT 3
183 #define EM_SMARTSPEED_MAX 15
184 #define EM_MAX_INTR 10
186 #define MAX_NUM_MULTICAST_ADDRESSES 128
187 #define PCI_ANY_ID (~0U)
188 #define EM_FC_PAUSE_TIME 1000
189 #define EM_EEPROM_APME 0x400;
192 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
193 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
194 * also optimize cache line size effect. H/W supports up to cache line size 128.
196 #define EM_DBA_ALIGN 128
198 #define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
200 /* PCI Config defines */
201 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
202 #define EM_BAR_TYPE_MASK 0x00000001
203 #define EM_BAR_TYPE_MMEM 0x00000000
204 #define EM_BAR_TYPE_IO 0x00000001
205 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
206 #define EM_BAR_MEM_TYPE_MASK 0x00000006
207 #define EM_BAR_MEM_TYPE_32BIT 0x00000000
208 #define EM_BAR_MEM_TYPE_64BIT 0x00000004
210 #define EM_MAX_SCATTER 64
211 #define EM_TSO_SIZE (IP_MAXPACKET + \
212 sizeof(struct ether_vlan_header))
213 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
216 #define EM_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
219 * 82574 has a nonstandard address for EIAC
220 * and since its only used in MSIX, and in
221 * the em driver only 82574 uses MSIX we can
222 * solve it just using this define.
224 #define EM_EIAC 0x000DC
226 /* Used in for 82547 10Mb Half workaround */
227 #define EM_PBA_BYTES_SHIFT 0xA
228 #define EM_TX_HEAD_ADDR_SHIFT 7
229 #define EM_PBA_TX_MASK 0xFFFF0000
230 #define EM_FIFO_HDR 0x10
231 #define EM_82547_PKT_THRESH 0x3e0
234 * Bus dma allocation structure used by
235 * em_dma_malloc and em_dma_free.
237 struct em_dma_alloc {
238 bus_addr_t dma_paddr;
240 bus_dma_tag_t dma_tag;
241 bus_dmamap_t dma_map;
244 /* Our adapter structure */
246 struct arpcom arpcom;
249 #define EM_FLAG_SHARED_INTR 0x0001
250 #define EM_FLAG_HAS_MGMT 0x0002
251 #define EM_FLAG_HAS_AMT 0x0004
252 #define EM_FLAG_HW_CTRL 0x0008
253 #define EM_FLAG_TSO 0x0010
254 #define EM_FLAG_TSO_PULLEX 0x0020
256 /* DragonFly operating-system-specific structures. */
257 struct e1000_osdep osdep;
260 bus_dma_tag_t parent_dtag;
262 struct resource *memory;
264 struct resource *flash;
267 struct resource *ioport;
270 struct resource *intr_res;
275 struct ifmedia media;
276 struct callout timer;
277 struct callout tx_fifo_timer;
282 /* WOL register value */
285 /* Multicast array memory */
288 /* Info about the board itself */
291 uint16_t link_duplex;
293 int int_throttle_ceil;
296 * Transmit definitions
298 * We have an array of num_tx_desc descriptors (handled
299 * by the controller) paired with an array of tx_buffers
300 * (at tx_buffer_area).
301 * The index of the next available descriptor is next_avail_tx_desc.
302 * The number of remaining tx_desc is num_tx_desc_avail.
304 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
305 struct e1000_tx_desc *tx_desc_base;
306 struct em_buffer *tx_buffer_area;
307 uint32_t next_avail_tx_desc;
308 uint32_t next_tx_to_clean;
309 int num_tx_desc_avail;
311 bus_dma_tag_t txtag; /* dma tag for tx */
315 /* Saved csum offloading context information */
320 int csum_thlen; /* TSO */
321 int csum_mss; /* TSO */
322 int csum_pktlen; /* TSO */
324 uint32_t csum_txd_upper;
325 uint32_t csum_txd_lower;
328 * Variables used to reduce TX interrupt rate and
329 * number of device's TX ring write requests.
332 * Number of TX descriptors setup so far.
335 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
336 * in the last TX descriptor of the packet, and
337 * tx_nsegs will be reset to 0. So TX interrupt and
338 * TX ring write request should be generated roughly
339 * every tx_int_nsegs TX descriptors.
342 * Index of the TX descriptors which have RS bit set,
343 * i.e. DD bit will be set on this TX descriptor after
344 * the data of the TX descriptor are transfered to
345 * hardware's internal packet buffer. Only the TX
346 * descriptors listed in tx_dd[] will be checked upon
347 * TX interrupt. This array is used as circular ring.
349 * tx_dd_tail, tx_dd_head:
350 * Tail and head index of valid elements in tx_dd[].
351 * tx_dd_tail == tx_dd_head means there is no valid
352 * elements in tx_dd[]. tx_dd_tail points to the position
353 * which is one beyond the last valid element in tx_dd[].
354 * tx_dd_head points to the first valid element in
361 #define EM_TXDD_MAX 64
362 #define EM_TXDD_SAFE 48 /* must be less than EM_TXDD_MAX */
363 int tx_dd[EM_TXDD_MAX];
366 * Receive definitions
368 * we have an array of num_rx_desc rx_desc (handled by the
369 * controller), and paired with an array of rx_buffers
370 * (at rx_buffer_area).
371 * The next pair to check on receive is at offset next_rx_desc_to_check
373 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
374 struct e1000_rx_desc *rx_desc_base;
375 uint32_t next_rx_desc_to_check;
376 uint32_t rx_buffer_len;
378 struct em_buffer *rx_buffer_area;
380 bus_dmamap_t rx_sparemap;
383 * First/last mbuf pointers, for
384 * collecting multisegment RX packets.
389 /* Misc stats maintained by the driver */
390 unsigned long dropped_pkts;
391 unsigned long mbuf_alloc_failed;
392 unsigned long mbuf_cluster_failed;
393 unsigned long no_tx_desc_avail1;
394 unsigned long no_tx_desc_avail2;
395 unsigned long no_tx_map_avail;
396 unsigned long no_tx_dma_setup;
397 unsigned long watchdog_events;
398 unsigned long rx_overruns;
399 unsigned long rx_irq;
400 unsigned long tx_irq;
401 unsigned long link_irq;
403 /* sysctl tree glue */
404 struct sysctl_ctx_list sysctl_ctx;
405 struct sysctl_oid *sysctl_tree;
407 /* 82547 workaround */
408 uint32_t tx_fifo_size;
409 uint32_t tx_fifo_head;
410 uint32_t tx_fifo_head_addr;
411 uint64_t tx_fifo_reset_cnt;
412 uint64_t tx_fifo_wrk_cnt;
413 uint32_t tx_head_addr;
415 /* For 82544 PCIX Workaround */
416 boolean_t pcix_82544;
418 struct e1000_hw_stats stats;
421 struct em_vendor_info {
430 bus_dmamap_t map; /* bus_dma map for packet */
433 /* For 82544 PCIX Workaround */
434 typedef struct _ADDRESS_LENGTH_PAIR {
437 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
439 typedef struct _DESCRIPTOR_PAIR {
440 ADDRESS_LENGTH_PAIR descriptor[4];
442 } DESC_ARRAY, *PDESC_ARRAY;
444 #define EM_IS_OACTIVE(adapter) \
445 ((adapter)->num_tx_desc_avail <= (adapter)->oact_tx_desc)
447 #define EM_INC_TXDD_IDX(idx) \
449 if (++(idx) == EM_TXDD_MAX) \
453 #endif /* _IF_EM_H_ */