2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 #define MPTABLE_POS_USE_DEFAULT(mpt) \
172 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
176 int mb_type; /* MPTABLE_BUS_ */
177 TAILQ_ENTRY(mptable_bus) mb_link;
180 #define MPTABLE_BUS_ISA 0
181 #define MPTABLE_BUS_PCI 1
183 struct mptable_bus_info {
184 TAILQ_HEAD(, mptable_bus) mbi_list;
187 struct mptable_pci_int {
194 TAILQ_ENTRY(mptable_pci_int) mpci_link;
197 struct mptable_ioapic {
201 TAILQ_ENTRY(mptable_ioapic) mio_link;
204 typedef int (*mptable_iter_func)(void *, const void *, int);
207 * this code MUST be enabled here and in mpboot.s.
208 * it follows the very early stages of AP boot by placing values in CMOS ram.
209 * it NORMALLY will never be needed and thus the primitive method for enabling.
212 #if defined(CHECK_POINTS)
213 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
214 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
216 #define CHECK_INIT(D); \
217 CHECK_WRITE(0x34, (D)); \
218 CHECK_WRITE(0x35, (D)); \
219 CHECK_WRITE(0x36, (D)); \
220 CHECK_WRITE(0x37, (D)); \
221 CHECK_WRITE(0x38, (D)); \
222 CHECK_WRITE(0x39, (D));
224 #define CHECK_PRINT(S); \
225 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
234 #else /* CHECK_POINTS */
236 #define CHECK_INIT(D)
237 #define CHECK_PRINT(S)
239 #endif /* CHECK_POINTS */
242 * Values to send to the POST hardware.
244 #define MP_BOOTADDRESS_POST 0x10
245 #define MP_PROBE_POST 0x11
246 #define MPTABLE_PASS1_POST 0x12
248 #define MP_START_POST 0x13
249 #define MP_ENABLE_POST 0x14
250 #define MPTABLE_PASS2_POST 0x15
252 #define START_ALL_APS_POST 0x16
253 #define INSTALL_AP_TRAMP_POST 0x17
254 #define START_AP_POST 0x18
256 #define MP_ANNOUNCE_POST 0x19
258 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
259 int current_postcode;
261 /** XXX FIXME: what system files declare these??? */
262 extern struct region_descriptor r_gdt, r_idt;
264 int mp_naps; /* # of Applications processors */
265 #ifdef SMP /* APIC-IO */
266 static int mp_nbusses; /* # of busses */
267 int mp_napics; /* # of IO APICs */
268 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
269 u_int32_t *io_apic_versions;
273 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
275 extern int64_t tsc_offsets[];
277 extern u_long ebda_addr;
279 #ifdef SMP /* APIC-IO */
280 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
284 * APIC ID logical/physical mapping structures.
285 * We oversize these to simplify boot-time config.
287 int cpu_num_to_apic_id[NAPICID];
288 #ifdef SMP /* APIC-IO */
289 int io_num_to_apic_id[NAPICID];
291 int apic_id_to_logical[NAPICID];
293 /* AP uses this during bootstrap. Do not staticize. */
297 struct pcb stoppcbs[MAXCPU];
299 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
301 static basetable_entry basetable_entry_types[] =
303 {0, 20, "Processor"},
311 * Local data and functions.
314 static u_int boot_address;
315 static u_int base_memory;
316 static int mp_finish;
318 static void mp_enable(u_int boot_addr);
320 static int mptable_iterate_entries(const mpcth_t,
321 mptable_iter_func, void *);
322 static int mptable_search(void);
323 static long mptable_search_sig(u_int32_t target, int count);
324 static int mptable_hyperthread_fixup(cpumask_t, int);
325 #ifdef SMP /* APIC-IO */
326 static void mptable_pass1(struct mptable_pos *);
327 static void mptable_pass2(struct mptable_pos *);
328 static void mptable_default(int type);
329 static void mptable_fix(void);
331 static int mptable_map(struct mptable_pos *);
332 static void mptable_unmap(struct mptable_pos *);
333 static void mptable_imcr(struct mptable_pos *);
334 static void mptable_bus_info_alloc(const mpcth_t,
335 struct mptable_bus_info *);
336 static void mptable_bus_info_free(struct mptable_bus_info *);
338 static int mptable_lapic_probe(struct lapic_enumerator *);
339 static void mptable_lapic_enumerate(struct lapic_enumerator *);
340 static void mptable_lapic_default(void);
342 static int mptable_ioapic_probe(struct ioapic_enumerator *);
343 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
345 #ifdef SMP /* APIC-IO */
346 static void setup_apic_irq_mapping(void);
347 static int apic_int_is_bus_type(int intr, int bus_type);
349 static int start_all_aps(u_int boot_addr);
351 static void install_ap_tramp(u_int boot_addr);
353 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
354 static int smitest(void);
356 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
357 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
358 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
359 static u_int bootMP_size;
361 static vm_paddr_t mptable_fps_phyaddr;
362 static int mptable_use_default;
363 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
364 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
365 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
366 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
369 * Calculate usable address in base memory for AP trampoline code.
372 mp_bootaddress(u_int basemem)
374 POSTCODE(MP_BOOTADDRESS_POST);
376 base_memory = basemem;
378 bootMP_size = mptramp_end - mptramp_start;
379 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
380 if (((basemem * 1024) - boot_address) < bootMP_size)
381 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
382 /* 3 levels of page table pages */
383 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
385 return mptramp_pagetables;
392 struct mptable_pos mpt;
395 KKASSERT(mptable_fps_phyaddr == 0);
397 mptable_fps_phyaddr = mptable_search();
398 if (mptable_fps_phyaddr == 0)
401 error = mptable_map(&mpt);
403 mptable_fps_phyaddr = 0;
407 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
408 kprintf("MPTABLE: use default configuration\n");
409 mptable_use_default = 1;
414 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
417 * Look for an Intel MP spec table (ie, SMP capable hardware).
425 POSTCODE(MP_PROBE_POST);
427 /* see if EBDA exists */
428 if (ebda_addr != 0) {
429 /* search first 1K of EBDA */
430 target = (u_int32_t)ebda_addr;
431 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
434 /* last 1K of base memory, effective 'top of base' passed in */
435 target = (u_int32_t)(base_memory - 0x400);
436 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
440 /* search the BIOS */
441 target = (u_int32_t)BIOS_BASE;
442 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
445 /* search the extended BIOS */
446 target = (u_int32_t)BIOS_BASE2;
447 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
455 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
457 int count, total_size;
458 const void *position;
460 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
461 total_size = cth->base_table_length - sizeof(struct MPCTH);
462 position = (const uint8_t *)cth + sizeof(struct MPCTH);
463 count = cth->entry_count;
468 KKASSERT(total_size >= 0);
469 if (total_size == 0) {
470 kprintf("invalid base MP table, "
471 "entry count and length mismatch\n");
475 type = *(const uint8_t *)position;
477 case 0: /* processor_entry */
478 case 1: /* bus_entry */
479 case 2: /* io_apic_entry */
480 case 3: /* int_entry */
481 case 4: /* int_entry */
484 kprintf("unknown base MP table entry type %d\n", type);
488 if (total_size < basetable_entry_types[type].length) {
489 kprintf("invalid base MP table length, "
490 "does not contain all entries\n");
493 total_size -= basetable_entry_types[type].length;
495 error = func(arg, position, type);
499 position = (const uint8_t *)position +
500 basetable_entry_types[type].length;
507 * Startup the SMP processors.
512 POSTCODE(MP_START_POST);
513 mp_enable(boot_address);
518 * Print various information about the SMP system hardware and setup.
525 POSTCODE(MP_ANNOUNCE_POST);
527 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
528 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
529 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
530 for (x = 1; x <= mp_naps; ++x) {
531 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
532 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
535 if (apic_io_enable) {
536 for (x = 0; x < mp_napics; ++x) {
537 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
538 kprintf(", version: 0x%08x", io_apic_versions[x]);
539 kprintf(", at 0x%08lx\n", io_apic_address[x]);
542 kprintf(" Warning: APIC I/O disabled\n");
547 * AP cpu's call this to sync up protected mode.
549 * WARNING! %gs is not set up on entry. This routine sets up %gs.
555 int x, myid = bootAP;
557 struct mdglobaldata *md;
558 struct privatespace *ps;
560 ps = &CPU_prvspace[myid];
562 gdt_segs[GPROC0_SEL].ssd_base =
563 (long) &ps->mdglobaldata.gd_common_tss;
564 ps->mdglobaldata.mi.gd_prvspace = ps;
566 /* We fill the 32-bit segment descriptors */
567 for (x = 0; x < NGDT; x++) {
568 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
569 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
571 /* And now a 64-bit one */
572 ssdtosyssd(&gdt_segs[GPROC0_SEL],
573 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
575 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
576 r_gdt.rd_base = (long) &gdt[myid * NGDT];
577 lgdt(&r_gdt); /* does magic intra-segment return */
579 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
580 wrmsr(MSR_FSBASE, 0); /* User value */
581 wrmsr(MSR_GSBASE, (u_int64_t)ps);
582 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
588 mdcpu->gd_currentldt = _default_ldt;
591 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
592 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
594 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
596 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
598 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
600 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
601 md->gd_common_tssd = *md->gd_tss_gdt;
603 /* double fault stack */
604 md->gd_common_tss.tss_ist1 =
605 (long)&md->mi.gd_prvspace->idlestack[
606 sizeof(md->mi.gd_prvspace->idlestack)];
611 * Set to a known state:
612 * Set by mpboot.s: CR0_PG, CR0_PE
613 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
616 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
619 /* Set up the fast syscall stuff */
620 msr = rdmsr(MSR_EFER) | EFER_SCE;
621 wrmsr(MSR_EFER, msr);
622 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
623 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
624 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
625 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
626 wrmsr(MSR_STAR, msr);
627 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
629 pmap_set_opt(); /* PSE/4MB pages, etc */
631 /* Initialize the PAT MSR. */
635 /* set up CPU registers and state */
638 /* set up SSE/NX registers */
641 /* set up FPU state on the AP */
642 npxinit(__INITIAL_NPXCW__);
644 /* disable the APIC, just to be SURE */
645 lapic->svr &= ~APIC_SVR_ENABLE;
647 /* data returned to BSP */
648 cpu_apic_versions[0] = lapic->version;
651 /*******************************************************************
652 * local functions and data
656 * start the SMP system
659 mp_enable(u_int boot_addr)
663 struct mptable_pos mpt;
665 POSTCODE(MP_ENABLE_POST);
672 if (mptable_fps_phyaddr) {
677 if (apic_io_enable) {
679 if (!mptable_fps_phyaddr)
680 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
685 * Examine the MP table for needed info
692 /* Post scan cleanup */
695 setup_apic_irq_mapping();
697 /* fill the LOGICAL io_apic_versions table */
698 for (apic = 0; apic < mp_napics; ++apic) {
699 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
700 io_apic_versions[apic] = ux;
701 io_apic_set_id(apic, IO_TO_ID(apic));
704 /* program each IO APIC in the system */
705 for (apic = 0; apic < mp_napics; ++apic)
706 if (io_apic_setup(apic) < 0)
707 panic("IO APIC setup failure");
712 * These are required for SMP operation
715 /* install a 'Spurious INTerrupt' vector */
716 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
717 SDT_SYSIGT, SEL_KPL, 0);
719 /* install an inter-CPU IPI for TLB invalidation */
720 setidt(XINVLTLB_OFFSET, Xinvltlb,
721 SDT_SYSIGT, SEL_KPL, 0);
723 /* install an inter-CPU IPI for IPIQ messaging */
724 setidt(XIPIQ_OFFSET, Xipiq,
725 SDT_SYSIGT, SEL_KPL, 0);
727 /* install a timer vector */
728 setidt(XTIMER_OFFSET, Xtimer,
729 SDT_SYSIGT, SEL_KPL, 0);
731 /* install an inter-CPU IPI for CPU stop/restart */
732 setidt(XCPUSTOP_OFFSET, Xcpustop,
733 SDT_SYSIGT, SEL_KPL, 0);
735 /* start each Application Processor */
736 start_all_aps(boot_addr);
741 * look for the MP spec signature
744 /* string defined by the Intel MP Spec as identifying the MP table */
745 #define MP_SIG 0x5f504d5f /* _MP_ */
746 #define NEXT(X) ((X) += 4)
748 mptable_search_sig(u_int32_t target, int count)
754 KKASSERT(target != 0);
756 map_size = count * sizeof(u_int32_t);
757 addr = pmap_mapdev((vm_paddr_t)target, map_size);
760 for (x = 0; x < count; NEXT(x)) {
761 if (addr[x] == MP_SIG) {
762 /* make array index a byte index */
763 ret = target + (x * sizeof(u_int32_t));
768 pmap_unmapdev((vm_offset_t)addr, map_size);
773 typedef struct BUSDATA {
775 enum busTypes bus_type;
778 typedef struct INTDATA {
788 typedef struct BUSTYPENAME {
793 static bus_type_name bus_type_table[] =
799 {UNKNOWN_BUSTYPE, "---"},
802 {UNKNOWN_BUSTYPE, "---"},
803 {UNKNOWN_BUSTYPE, "---"},
804 {UNKNOWN_BUSTYPE, "---"},
805 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"},
809 {UNKNOWN_BUSTYPE, "---"},
810 {UNKNOWN_BUSTYPE, "---"},
811 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"}
816 /* from MP spec v1.4, table 5-1 */
817 static int default_data[7][5] =
819 /* nbus, id0, type0, id1, type1 */
820 {1, 0, ISA, 255, 255},
821 {1, 0, EISA, 255, 255},
822 {1, 0, EISA, 255, 255},
823 {1, 0, MCA, 255, 255},
825 {2, 0, EISA, 1, PCI},
830 static bus_datum *bus_data;
832 /* the IO INT data, one entry per possible APIC INTerrupt */
833 static io_int *io_apic_ints;
836 static int processor_entry (const struct PROCENTRY *entry, int cpu);
837 static int bus_entry (const struct BUSENTRY *entry, int bus);
838 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
839 static int int_entry (const struct INTENTRY *entry, int intr);
840 static int lookup_bus_type (char *name);
843 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
845 const struct IOAPICENTRY *ioapic_ent;
848 case 1: /* bus_entry */
852 case 2: /* io_apic_entry */
854 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
855 io_apic_address[mp_napics++] =
856 (vm_offset_t)ioapic_ent->apic_address;
860 case 3: /* int_entry */
868 * 1st pass on motherboard's Intel MP specification table.
877 mptable_pass1(struct mptable_pos *mpt)
882 POSTCODE(MPTABLE_PASS1_POST);
885 KKASSERT(fps != NULL);
887 /* clear various tables */
888 for (x = 0; x < NAPICID; ++x)
889 io_apic_address[x] = ~0; /* IO APIC address table */
895 /* check for use of 'default' configuration */
896 if (fps->mpfb1 != 0) {
897 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
898 mp_nbusses = default_data[fps->mpfb1 - 1][0];
904 error = mptable_iterate_entries(mpt->mp_cth,
905 mptable_ioapic_pass1_callback, NULL);
907 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
911 struct mptable_ioapic2_cbarg {
918 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
920 struct mptable_ioapic2_cbarg *arg = xarg;
924 if (bus_entry(pos, arg->bus))
929 if (io_apic_entry(pos, arg->apic))
934 if (int_entry(pos, arg->intr))
942 * 2nd pass on motherboard's Intel MP specification table.
945 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
946 * IO_TO_ID(N), logical IO to APIC ID table
951 mptable_pass2(struct mptable_pos *mpt)
953 struct mptable_ioapic2_cbarg arg;
957 POSTCODE(MPTABLE_PASS2_POST);
960 KKASSERT(fps != NULL);
962 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
964 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
965 M_DEVBUF, M_WAITOK | M_ZERO);
966 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
968 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
971 for (x = 0; x < mp_napics; x++)
972 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
974 /* clear various tables */
975 for (x = 0; x < NAPICID; ++x) {
976 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
977 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
980 /* clear bus data table */
981 for (x = 0; x < mp_nbusses; ++x)
982 bus_data[x].bus_id = 0xff;
984 /* clear IO APIC INT table */
985 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
986 io_apic_ints[x].int_type = 0xff;
987 io_apic_ints[x].int_vector = 0xff;
990 /* check for use of 'default' configuration */
991 if (fps->mpfb1 != 0) {
992 mptable_default(fps->mpfb1);
996 bzero(&arg, sizeof(arg));
997 error = mptable_iterate_entries(mpt->mp_cth,
998 mptable_ioapic_pass2_callback, &arg);
1000 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1004 * Check if we should perform a hyperthreading "fix-up" to
1005 * enumerate any logical CPU's that aren't already listed
1008 * XXX: We assume that all of the physical CPUs in the
1009 * system have the same number of logical CPUs.
1011 * XXX: We assume that APIC ID's are allocated such that
1012 * the APIC ID's for a physical processor are aligned
1013 * with the number of logical CPU's in the processor.
1016 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
1018 int i, id, lcpus_max, logical_cpus;
1020 if ((cpu_feature & CPUID_HTT) == 0)
1023 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1027 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1029 * INSTRUCTION SET REFERENCE, A-M (#253666)
1030 * Page 3-181, Table 3-20
1031 * "The nearest power-of-2 integer that is not smaller
1032 * than EBX[23:16] is the number of unique initial APIC
1033 * IDs reserved for addressing different logical
1034 * processors in a physical package."
1036 for (i = 0; ; ++i) {
1037 if ((1 << i) >= lcpus_max) {
1044 KKASSERT(cpu_count != 0);
1045 if (cpu_count == lcpus_max) {
1046 /* We have nothing to fix */
1048 } else if (cpu_count == 1) {
1049 /* XXX this may be incorrect */
1050 logical_cpus = lcpus_max;
1052 int cur, prev, dist;
1055 * Calculate the distances between two nearest
1056 * APIC IDs. If all such distances are same,
1057 * then it is the number of missing cpus that
1058 * we are going to fill later.
1060 dist = cur = prev = -1;
1061 for (id = 0; id < MAXCPU; ++id) {
1062 if ((id_mask & CPUMASK(id)) == 0)
1067 int new_dist = cur - prev;
1073 * Make sure that all distances
1074 * between two nearest APIC IDs
1077 if (dist != new_dist)
1085 /* Must be power of 2 */
1086 if (dist & (dist - 1))
1089 /* Can't exceed CPU package capacity */
1090 if (dist > lcpus_max)
1091 logical_cpus = lcpus_max;
1093 logical_cpus = dist;
1097 * For each APIC ID of a CPU that is set in the mask,
1098 * scan the other candidate APIC ID's for this
1099 * physical processor. If any of those ID's are
1100 * already in the table, then kill the fixup.
1102 for (id = 0; id < MAXCPU; id++) {
1103 if ((id_mask & CPUMASK(id)) == 0)
1105 /* First, make sure we are on a logical_cpus boundary. */
1106 if (id % logical_cpus != 0)
1108 for (i = id + 1; i < id + logical_cpus; i++)
1109 if ((id_mask & CPUMASK(i)) != 0)
1112 return logical_cpus;
1116 mptable_map(struct mptable_pos *mpt)
1120 vm_size_t cth_mapsz = 0;
1122 KKASSERT(mptable_fps_phyaddr != 0);
1124 bzero(mpt, sizeof(*mpt));
1126 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1127 if (fps->pap != 0) {
1129 * Map configuration table header to get
1130 * the base table size
1132 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1133 cth_mapsz = cth->base_table_length;
1134 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1136 if (cth_mapsz < sizeof(*cth)) {
1137 kprintf("invalid base MP table length %d\n",
1139 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1144 * Map the base table
1146 cth = pmap_mapdev(fps->pap, cth_mapsz);
1151 mpt->mp_cth_mapsz = cth_mapsz;
1157 mptable_unmap(struct mptable_pos *mpt)
1159 if (mpt->mp_cth != NULL) {
1160 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1162 mpt->mp_cth_mapsz = 0;
1164 if (mpt->mp_fps != NULL) {
1165 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1171 assign_apic_irq(int apic, int intpin, int irq)
1175 if (int_to_apicintpin[irq].ioapic != -1)
1176 panic("assign_apic_irq: inconsistent table");
1178 int_to_apicintpin[irq].ioapic = apic;
1179 int_to_apicintpin[irq].int_pin = intpin;
1180 int_to_apicintpin[irq].apic_address = ioapic[apic];
1181 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1183 for (x = 0; x < nintrs; x++) {
1184 if ((io_apic_ints[x].int_type == 0 ||
1185 io_apic_ints[x].int_type == 3) &&
1186 io_apic_ints[x].int_vector == 0xff &&
1187 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1188 io_apic_ints[x].dst_apic_int == intpin)
1189 io_apic_ints[x].int_vector = irq;
1194 revoke_apic_irq(int irq)
1200 if (int_to_apicintpin[irq].ioapic == -1)
1201 panic("revoke_apic_irq: inconsistent table");
1203 oldapic = int_to_apicintpin[irq].ioapic;
1204 oldintpin = int_to_apicintpin[irq].int_pin;
1206 int_to_apicintpin[irq].ioapic = -1;
1207 int_to_apicintpin[irq].int_pin = 0;
1208 int_to_apicintpin[irq].apic_address = NULL;
1209 int_to_apicintpin[irq].redirindex = 0;
1211 for (x = 0; x < nintrs; x++) {
1212 if ((io_apic_ints[x].int_type == 0 ||
1213 io_apic_ints[x].int_type == 3) &&
1214 io_apic_ints[x].int_vector != 0xff &&
1215 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1216 io_apic_ints[x].dst_apic_int == oldintpin)
1217 io_apic_ints[x].int_vector = 0xff;
1225 allocate_apic_irq(int intr)
1231 if (io_apic_ints[intr].int_vector != 0xff)
1232 return; /* Interrupt handler already assigned */
1234 if (io_apic_ints[intr].int_type != 0 &&
1235 (io_apic_ints[intr].int_type != 3 ||
1236 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1237 io_apic_ints[intr].dst_apic_int == 0)))
1238 return; /* Not INT or ExtInt on != (0, 0) */
1241 while (irq < APIC_INTMAPSIZE &&
1242 int_to_apicintpin[irq].ioapic != -1)
1245 if (irq >= APIC_INTMAPSIZE)
1246 return; /* No free interrupt handlers */
1248 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1249 intpin = io_apic_ints[intr].dst_apic_int;
1251 assign_apic_irq(apic, intpin, irq);
1256 swap_apic_id(int apic, int oldid, int newid)
1263 return; /* Nothing to do */
1265 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1266 apic, oldid, newid);
1268 /* Swap physical APIC IDs in interrupt entries */
1269 for (x = 0; x < nintrs; x++) {
1270 if (io_apic_ints[x].dst_apic_id == oldid)
1271 io_apic_ints[x].dst_apic_id = newid;
1272 else if (io_apic_ints[x].dst_apic_id == newid)
1273 io_apic_ints[x].dst_apic_id = oldid;
1276 /* Swap physical APIC IDs in IO_TO_ID mappings */
1277 for (oapic = 0; oapic < mp_napics; oapic++)
1278 if (IO_TO_ID(oapic) == newid)
1281 if (oapic < mp_napics) {
1282 kprintf("Changing APIC ID for IO APIC #%d from "
1283 "%d to %d in MP table\n",
1284 oapic, newid, oldid);
1285 IO_TO_ID(oapic) = oldid;
1287 IO_TO_ID(apic) = newid;
1292 fix_id_to_io_mapping(void)
1296 for (x = 0; x < NAPICID; x++)
1299 for (x = 0; x <= mp_naps; x++) {
1300 if ((u_int)CPU_TO_ID(x) < NAPICID)
1301 ID_TO_IO(CPU_TO_ID(x)) = x;
1304 for (x = 0; x < mp_napics; x++) {
1305 if ((u_int)IO_TO_ID(x) < NAPICID)
1306 ID_TO_IO(IO_TO_ID(x)) = x;
1312 first_free_apic_id(void)
1316 for (freeid = 0; freeid < NAPICID; freeid++) {
1317 for (x = 0; x <= mp_naps; x++)
1318 if (CPU_TO_ID(x) == freeid)
1322 for (x = 0; x < mp_napics; x++)
1323 if (IO_TO_ID(x) == freeid)
1334 io_apic_id_acceptable(int apic, int id)
1336 int cpu; /* Logical CPU number */
1337 int oapic; /* Logical IO APIC number for other IO APIC */
1339 if ((u_int)id >= NAPICID)
1340 return 0; /* Out of range */
1342 for (cpu = 0; cpu <= mp_naps; cpu++) {
1343 if (CPU_TO_ID(cpu) == id)
1344 return 0; /* Conflict with CPU */
1347 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) {
1348 if (IO_TO_ID(oapic) == id)
1349 return 0; /* Conflict with other APIC */
1352 return 1; /* ID is acceptable for IO APIC */
1357 io_apic_find_int_entry(int apic, int pin)
1361 /* search each of the possible INTerrupt sources */
1362 for (x = 0; x < nintrs; ++x) {
1363 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1364 (pin == io_apic_ints[x].dst_apic_int))
1365 return (&io_apic_ints[x]);
1371 * parse an Intel MP specification table
1378 int apic; /* IO APIC unit number */
1379 int freeid; /* Free physical APIC ID */
1380 int physid; /* Current physical IO APIC ID */
1382 int bus_0 = 0; /* Stop GCC warning */
1383 int bus_pci = 0; /* Stop GCC warning */
1387 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1388 * did it wrong. The MP spec says that when more than 1 PCI bus
1389 * exists the BIOS must begin with bus entries for the PCI bus and use
1390 * actual PCI bus numbering. This implies that when only 1 PCI bus
1391 * exists the BIOS can choose to ignore this ordering, and indeed many
1392 * MP motherboards do ignore it. This causes a problem when the PCI
1393 * sub-system makes requests of the MP sub-system based on PCI bus
1394 * numbers. So here we look for the situation and renumber the
1395 * busses and associated INTs in an effort to "make it right".
1398 /* find bus 0, PCI bus, count the number of PCI busses */
1399 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1400 if (bus_data[x].bus_id == 0) {
1403 if (bus_data[x].bus_type == PCI) {
1409 * bus_0 == slot of bus with ID of 0
1410 * bus_pci == slot of last PCI bus encountered
1413 /* check the 1 PCI bus case for sanity */
1414 /* if it is number 0 all is well */
1415 if (num_pci_bus == 1 &&
1416 bus_data[bus_pci].bus_id != 0) {
1418 /* mis-numbered, swap with whichever bus uses slot 0 */
1420 /* swap the bus entry types */
1421 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1422 bus_data[bus_0].bus_type = PCI;
1424 /* swap each relevant INTerrupt entry */
1425 id = bus_data[bus_pci].bus_id;
1426 for (x = 0; x < nintrs; ++x) {
1427 if (io_apic_ints[x].src_bus_id == id) {
1428 io_apic_ints[x].src_bus_id = 0;
1430 else if (io_apic_ints[x].src_bus_id == 0) {
1431 io_apic_ints[x].src_bus_id = id;
1436 /* Assign IO APIC IDs.
1438 * First try the existing ID. If a conflict is detected, try
1439 * the ID in the MP table. If a conflict is still detected, find
1442 * We cannot use the ID_TO_IO table before all conflicts has been
1443 * resolved and the table has been corrected.
1445 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1447 /* First try to use the value set by the BIOS */
1448 physid = io_apic_get_id(apic);
1449 if (io_apic_id_acceptable(apic, physid)) {
1450 if (IO_TO_ID(apic) != physid)
1451 swap_apic_id(apic, IO_TO_ID(apic), physid);
1455 /* Then check if the value in the MP table is acceptable */
1456 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1459 /* Last resort, find a free APIC ID and use it */
1460 freeid = first_free_apic_id();
1461 if (freeid >= NAPICID)
1462 panic("No free physical APIC IDs found");
1464 if (io_apic_id_acceptable(apic, freeid)) {
1465 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1468 panic("Free physical APIC ID not usable");
1470 fix_id_to_io_mapping();
1472 /* detect and fix broken Compaq MP table */
1473 if (apic_int_type(0, 0) == -1) {
1474 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1475 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1476 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1477 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1478 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1479 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1481 } else if (apic_int_type(0, 0) == 0) {
1482 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1483 for (x = 0; x < nintrs; ++x)
1484 if ((ID_TO_IO(io_apic_ints[x].dst_apic_id) == 0) &&
1485 (io_apic_ints[x].dst_apic_int) == 0) {
1486 io_apic_ints[x].int_type = 3;
1487 io_apic_ints[x].int_vector = 0xff;
1493 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1494 * controllers universally come in pairs. If IRQ 14 is specified
1495 * as an ISA interrupt, then IRQ 15 had better be too.
1497 * [ Shuttle XPC / AMD Athlon X2 ]
1498 * The MPTable is missing an entry for IRQ 15. Note that the
1499 * ACPI table has an entry for both 14 and 15.
1501 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1502 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1503 io14 = io_apic_find_int_entry(0, 14);
1504 io_apic_ints[nintrs] = *io14;
1505 io_apic_ints[nintrs].src_bus_irq = 15;
1506 io_apic_ints[nintrs].dst_apic_int = 15;
1511 /* Assign low level interrupt handlers */
1513 setup_apic_irq_mapping(void)
1519 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1520 int_to_apicintpin[x].ioapic = -1;
1521 int_to_apicintpin[x].int_pin = 0;
1522 int_to_apicintpin[x].apic_address = NULL;
1523 int_to_apicintpin[x].redirindex = 0;
1525 /* Default to masked */
1526 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1529 /* First assign ISA/EISA interrupts */
1530 for (x = 0; x < nintrs; x++) {
1531 int_vector = io_apic_ints[x].src_bus_irq;
1532 if (int_vector < APIC_INTMAPSIZE &&
1533 io_apic_ints[x].int_vector == 0xff &&
1534 int_to_apicintpin[int_vector].ioapic == -1 &&
1535 (apic_int_is_bus_type(x, ISA) ||
1536 apic_int_is_bus_type(x, EISA)) &&
1537 io_apic_ints[x].int_type == 0) {
1538 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1539 io_apic_ints[x].dst_apic_int,
1544 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1545 for (x = 0; x < nintrs; x++) {
1546 if (io_apic_ints[x].dst_apic_int == 0 &&
1547 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1548 io_apic_ints[x].int_vector == 0xff &&
1549 int_to_apicintpin[0].ioapic == -1 &&
1550 io_apic_ints[x].int_type == 3) {
1551 assign_apic_irq(0, 0, 0);
1556 /* Assign PCI interrupts */
1557 for (x = 0; x < nintrs; ++x) {
1558 if (io_apic_ints[x].int_type == 0 &&
1559 io_apic_ints[x].int_vector == 0xff &&
1560 apic_int_is_bus_type(x, PCI))
1561 allocate_apic_irq(x);
1566 mp_set_cpuids(int cpu_id, int apic_id)
1568 CPU_TO_ID(cpu_id) = apic_id;
1569 ID_TO_CPU(apic_id) = cpu_id;
1571 if (apic_id > lapic_id_max)
1572 lapic_id_max = apic_id;
1576 processor_entry(const struct PROCENTRY *entry, int cpu)
1580 /* check for usability */
1581 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1584 /* check for BSP flag */
1585 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1586 mp_set_cpuids(0, entry->apic_id);
1587 return 0; /* its already been counted */
1590 /* add another AP to list, if less than max number of CPUs */
1591 else if (cpu < MAXCPU) {
1592 mp_set_cpuids(cpu, entry->apic_id);
1600 bus_entry(const struct BUSENTRY *entry, int bus)
1605 /* encode the name into an index */
1606 for (x = 0; x < 6; ++x) {
1607 if ((c = entry->bus_type[x]) == ' ')
1613 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1614 panic("unknown bus type: '%s'", name);
1616 bus_data[bus].bus_id = entry->bus_id;
1617 bus_data[bus].bus_type = x;
1623 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1625 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1628 IO_TO_ID(apic) = entry->apic_id;
1629 ID_TO_IO(entry->apic_id) = apic;
1635 lookup_bus_type(char *name)
1639 for (x = 0; x < MAX_BUSTYPE; ++x)
1640 if (strcmp(bus_type_table[x].name, name) == 0)
1641 return bus_type_table[x].type;
1643 return UNKNOWN_BUSTYPE;
1647 int_entry(const struct INTENTRY *entry, int intr)
1651 io_apic_ints[intr].int_type = entry->int_type;
1652 io_apic_ints[intr].int_flags = entry->int_flags;
1653 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1654 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1655 if (entry->dst_apic_id == 255) {
1656 /* This signal goes to all IO APICS. Select an IO APIC
1657 with sufficient number of interrupt pins */
1658 for (apic = 0; apic < mp_napics; apic++)
1659 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1660 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1661 entry->dst_apic_int)
1663 if (apic < mp_napics)
1664 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1666 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1668 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1669 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1675 apic_int_is_bus_type(int intr, int bus_type)
1679 for (bus = 0; bus < mp_nbusses; ++bus)
1680 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1681 && ((int) bus_data[bus].bus_type == bus_type))
1688 * Given a traditional ISA INT mask, return an APIC mask.
1691 isa_apic_mask(u_int isa_mask)
1696 #if defined(SKIP_IRQ15_REDIRECT)
1697 if (isa_mask == (1 << 15)) {
1698 kprintf("skipping ISA IRQ15 redirect\n");
1701 #endif /* SKIP_IRQ15_REDIRECT */
1703 isa_irq = ffs(isa_mask); /* find its bit position */
1704 if (isa_irq == 0) /* doesn't exist */
1706 --isa_irq; /* make it zero based */
1708 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1712 return (1 << apic_pin); /* convert pin# to a mask */
1716 * Determine which APIC pin an ISA/EISA INT is attached to.
1718 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1719 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1720 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1721 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1723 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1725 isa_apic_irq(int isa_irq)
1729 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1730 if (INTTYPE(intr) == 0) { /* standard INT */
1731 if (SRCBUSIRQ(intr) == isa_irq) {
1732 if (apic_int_is_bus_type(intr, ISA) ||
1733 apic_int_is_bus_type(intr, EISA)) {
1734 if (INTIRQ(intr) == 0xff)
1735 return -1; /* unassigned */
1736 return INTIRQ(intr); /* found */
1741 return -1; /* NOT found */
1746 * Determine which APIC pin a PCI INT is attached to.
1748 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1749 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1750 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1752 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1756 --pciInt; /* zero based */
1758 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1759 if ((INTTYPE(intr) == 0) /* standard INT */
1760 && (SRCBUSID(intr) == pciBus)
1761 && (SRCBUSDEVICE(intr) == pciDevice)
1762 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1763 if (apic_int_is_bus_type(intr, PCI)) {
1764 if (INTIRQ(intr) == 0xff) {
1765 kprintf("IOAPIC: pci_apic_irq() "
1767 return -1; /* unassigned */
1769 return INTIRQ(intr); /* exact match */
1774 return -1; /* NOT found */
1778 next_apic_irq(int irq)
1785 for (intr = 0; intr < nintrs; intr++) {
1786 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1788 bus = SRCBUSID(intr);
1789 bustype = apic_bus_type(bus);
1790 if (bustype != ISA &&
1796 if (intr >= nintrs) {
1799 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1800 if (INTTYPE(ointr) != 0)
1802 if (bus != SRCBUSID(ointr))
1804 if (bustype == PCI) {
1805 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1807 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1810 if (bustype == ISA || bustype == EISA) {
1811 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1814 if (INTPIN(intr) == INTPIN(ointr))
1818 if (ointr >= nintrs) {
1821 return INTIRQ(ointr);
1834 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1837 * Exactly what this means is unclear at this point. It is a solution
1838 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1839 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1840 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1844 undirect_isa_irq(int rirq)
1848 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1849 /** FIXME: tickle the MB redirector chip */
1853 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1860 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1863 undirect_pci_irq(int rirq)
1867 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1869 /** FIXME: tickle the MB redirector chip */
1873 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1881 * given a bus ID, return:
1882 * the bus type if found
1886 apic_bus_type(int id)
1890 for (x = 0; x < mp_nbusses; ++x)
1891 if (bus_data[x].bus_id == id)
1892 return bus_data[x].bus_type;
1898 * given a LOGICAL APIC# and pin#, return:
1899 * the associated src bus ID if found
1903 apic_src_bus_id(int apic, int pin)
1907 /* search each of the possible INTerrupt sources */
1908 for (x = 0; x < nintrs; ++x)
1909 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1910 (pin == io_apic_ints[x].dst_apic_int))
1911 return (io_apic_ints[x].src_bus_id);
1913 return -1; /* NOT found */
1917 * given a LOGICAL APIC# and pin#, return:
1918 * the associated src bus IRQ if found
1922 apic_src_bus_irq(int apic, int pin)
1926 for (x = 0; x < nintrs; x++)
1927 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1928 (pin == io_apic_ints[x].dst_apic_int))
1929 return (io_apic_ints[x].src_bus_irq);
1931 return -1; /* NOT found */
1936 * given a LOGICAL APIC# and pin#, return:
1937 * the associated INTerrupt type if found
1941 apic_int_type(int apic, int pin)
1945 /* search each of the possible INTerrupt sources */
1946 for (x = 0; x < nintrs; ++x) {
1947 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1948 (pin == io_apic_ints[x].dst_apic_int))
1949 return (io_apic_ints[x].int_type);
1951 return -1; /* NOT found */
1955 * Return the IRQ associated with an APIC pin
1958 apic_irq(int apic, int pin)
1963 for (x = 0; x < nintrs; ++x) {
1964 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1965 (pin == io_apic_ints[x].dst_apic_int)) {
1966 res = io_apic_ints[x].int_vector;
1969 if (apic != int_to_apicintpin[res].ioapic)
1970 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1971 if (pin != int_to_apicintpin[res].int_pin)
1972 panic("apic_irq inconsistent table (2)");
1981 * given a LOGICAL APIC# and pin#, return:
1982 * the associated trigger mode if found
1986 apic_trigger(int apic, int pin)
1990 /* search each of the possible INTerrupt sources */
1991 for (x = 0; x < nintrs; ++x)
1992 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1993 (pin == io_apic_ints[x].dst_apic_int))
1994 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1996 return -1; /* NOT found */
2001 * given a LOGICAL APIC# and pin#, return:
2002 * the associated 'active' level if found
2006 apic_polarity(int apic, int pin)
2010 /* search each of the possible INTerrupt sources */
2011 for (x = 0; x < nintrs; ++x)
2012 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2013 (pin == io_apic_ints[x].dst_apic_int))
2014 return (io_apic_ints[x].int_flags & 0x03);
2016 return -1; /* NOT found */
2020 * set data according to MP defaults
2021 * FIXME: probably not complete yet...
2024 mptable_default(int type)
2030 kprintf(" MP default config type: %d\n", type);
2033 kprintf(" bus: ISA, APIC: 82489DX\n");
2036 kprintf(" bus: EISA, APIC: 82489DX\n");
2039 kprintf(" bus: EISA, APIC: 82489DX\n");
2042 kprintf(" bus: MCA, APIC: 82489DX\n");
2045 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2048 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2051 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2054 kprintf(" future type\n");
2060 /* one and only IO APIC */
2061 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2064 * sanity check, refer to MP spec section 3.6.6, last paragraph
2065 * necessary as some hardware isn't properly setting up the IO APIC
2067 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2068 if (io_apic_id != 2) {
2070 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2071 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2072 io_apic_set_id(0, 2);
2075 IO_TO_ID(0) = io_apic_id;
2076 ID_TO_IO(io_apic_id) = 0;
2078 /* fill out bus entries */
2087 bus_data[0].bus_id = default_data[type - 1][1];
2088 bus_data[0].bus_type = default_data[type - 1][2];
2089 bus_data[1].bus_id = default_data[type - 1][3];
2090 bus_data[1].bus_type = default_data[type - 1][4];
2093 /* case 4: case 7: MCA NOT supported */
2094 default: /* illegal/reserved */
2095 panic("BAD default MP config: %d", type);
2099 /* general cases from MP v1.4, table 5-2 */
2100 for (pin = 0; pin < 16; ++pin) {
2101 io_apic_ints[pin].int_type = 0;
2102 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2103 io_apic_ints[pin].src_bus_id = 0;
2104 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2105 io_apic_ints[pin].dst_apic_id = io_apic_id;
2106 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2109 /* special cases from MP v1.4, table 5-2 */
2111 io_apic_ints[2].int_type = 0xff; /* N/C */
2112 io_apic_ints[13].int_type = 0xff; /* N/C */
2113 #if !defined(APIC_MIXED_MODE)
2115 panic("sorry, can't support type 2 default yet");
2116 #endif /* APIC_MIXED_MODE */
2119 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2122 io_apic_ints[0].int_type = 0xff; /* N/C */
2124 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2128 * Map a physical memory address representing I/O into KVA. The I/O
2129 * block is assumed not to cross a page boundary.
2132 permanent_io_mapping(vm_paddr_t pa)
2134 KKASSERT(pa < 0x100000000LL);
2136 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2140 * start each AP in our list
2143 start_all_aps(u_int boot_addr)
2145 vm_offset_t va = boot_address + KERNBASE;
2146 u_int64_t *pt4, *pt3, *pt2;
2152 u_char mpbiosreason;
2153 u_long mpbioswarmvec;
2154 struct mdglobaldata *gd;
2155 struct privatespace *ps;
2157 POSTCODE(START_ALL_APS_POST);
2159 /* Initialize BSP's local APIC */
2160 apic_initialize(TRUE);
2163 MachIntrABI.finalize();
2165 /* install the AP 1st level boot code */
2166 pmap_kenter(va, boot_address);
2167 cpu_invlpg((void *)va); /* JG XXX */
2168 bcopy(mptramp_start, (void *)va, bootMP_size);
2170 /* Locate the page tables, they'll be below the trampoline */
2171 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2172 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2173 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2175 /* Create the initial 1GB replicated page tables */
2176 for (i = 0; i < 512; i++) {
2177 /* Each slot of the level 4 pages points to the same level 3 page */
2178 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2179 pt4[i] |= PG_V | PG_RW | PG_U;
2181 /* Each slot of the level 3 pages points to the same level 2 page */
2182 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2183 pt3[i] |= PG_V | PG_RW | PG_U;
2185 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2186 pt2[i] = i * (2 * 1024 * 1024);
2187 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2190 /* save the current value of the warm-start vector */
2191 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2192 outb(CMOS_REG, BIOS_RESET);
2193 mpbiosreason = inb(CMOS_DATA);
2195 /* setup a vector to our boot code */
2196 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2197 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2198 outb(CMOS_REG, BIOS_RESET);
2199 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2202 * If we have a TSC we can figure out the SMI interrupt rate.
2203 * The SMI does not necessarily use a constant rate. Spend
2204 * up to 250ms trying to figure it out.
2207 if (cpu_feature & CPUID_TSC) {
2208 set_apic_timer(275000);
2209 smilast = read_apic_timer();
2210 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2211 smicount = smitest();
2212 if (smibest == 0 || smilast - smicount < smibest)
2213 smibest = smilast - smicount;
2216 if (smibest > 250000)
2219 smibest = smibest * (int64_t)1000000 /
2220 get_apic_timer_frequency();
2224 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2225 1000000 / smibest, smibest);
2227 kprintf("SMP: Starting %d APs: ", mp_naps);
2229 for (x = 1; x <= mp_naps; ++x) {
2231 /* This is a bit verbose, it will go away soon. */
2233 /* first page of AP's private space */
2234 pg = x * x86_64_btop(sizeof(struct privatespace));
2236 /* allocate new private data page(s) */
2237 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2238 MDGLOBALDATA_BASEALLOC_SIZE);
2240 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2241 bzero(gd, sizeof(*gd));
2242 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2244 /* prime data page for it to use */
2245 mi_gdinit(&gd->mi, x);
2247 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2248 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2250 /* setup a vector to our boot code */
2251 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2252 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2253 outb(CMOS_REG, BIOS_RESET);
2254 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2257 * Setup the AP boot stack
2259 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2262 /* attempt to start the Application Processor */
2263 CHECK_INIT(99); /* setup checkpoints */
2264 if (!start_ap(gd, boot_addr, smibest)) {
2265 kprintf("\nAP #%d (PHY# %d) failed!\n",
2267 CHECK_PRINT("trace"); /* show checkpoints */
2268 /* better panic as the AP may be running loose */
2269 kprintf("panic y/n? [y] ");
2270 if (cngetc() != 'n')
2273 CHECK_PRINT("trace"); /* show checkpoints */
2275 /* record its version info */
2276 cpu_apic_versions[x] = cpu_apic_versions[0];
2279 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2282 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2283 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2286 ncpus2_shift = shift;
2287 ncpus2 = 1 << shift;
2288 ncpus2_mask = ncpus2 - 1;
2290 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2291 if ((1 << shift) < ncpus)
2293 ncpus_fit = 1 << shift;
2294 ncpus_fit_mask = ncpus_fit - 1;
2296 /* build our map of 'other' CPUs */
2297 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2298 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2299 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2301 /* fill in our (BSP) APIC version */
2302 cpu_apic_versions[0] = lapic->version;
2304 /* restore the warmstart vector */
2305 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2306 outb(CMOS_REG, BIOS_RESET);
2307 outb(CMOS_DATA, mpbiosreason);
2310 * NOTE! The idlestack for the BSP was setup by locore. Finish
2311 * up, clean out the P==V mapping we did earlier.
2315 /* number of APs actually started */
2321 * load the 1st level AP boot code into base memory.
2324 /* targets for relocation */
2325 extern void bigJump(void);
2326 extern void bootCodeSeg(void);
2327 extern void bootDataSeg(void);
2328 extern void MPentry(void);
2329 extern u_int MP_GDT;
2330 extern u_int mp_gdtbase;
2335 install_ap_tramp(u_int boot_addr)
2338 int size = *(int *) ((u_long) & bootMP_size);
2339 u_char *src = (u_char *) ((u_long) bootMP);
2340 u_char *dst = (u_char *) boot_addr + KERNBASE;
2341 u_int boot_base = (u_int) bootMP;
2346 POSTCODE(INSTALL_AP_TRAMP_POST);
2348 for (x = 0; x < size; ++x)
2352 * modify addresses in code we just moved to basemem. unfortunately we
2353 * need fairly detailed info about mpboot.s for this to work. changes
2354 * to mpboot.s might require changes here.
2357 /* boot code is located in KERNEL space */
2358 dst = (u_char *) boot_addr + KERNBASE;
2360 /* modify the lgdt arg */
2361 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2362 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2364 /* modify the ljmp target for MPentry() */
2365 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2366 *dst32 = ((u_int) MPentry - KERNBASE);
2368 /* modify the target for boot code segment */
2369 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2370 dst8 = (u_int8_t *) (dst16 + 1);
2371 *dst16 = (u_int) boot_addr & 0xffff;
2372 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2374 /* modify the target for boot data segment */
2375 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2376 dst8 = (u_int8_t *) (dst16 + 1);
2377 *dst16 = (u_int) boot_addr & 0xffff;
2378 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2384 * This function starts the AP (application processor) identified
2385 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2386 * to accomplish this. This is necessary because of the nuances
2387 * of the different hardware we might encounter. It ain't pretty,
2388 * but it seems to work.
2390 * NOTE: eventually an AP gets to ap_init(), which is called just
2391 * before the AP goes into the LWKT scheduler's idle loop.
2394 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2398 u_long icr_lo, icr_hi;
2400 POSTCODE(START_AP_POST);
2402 /* get the PHYSICAL APIC ID# */
2403 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2405 /* calculate the vector */
2406 vector = (boot_addr >> 12) & 0xff;
2408 /* We don't want anything interfering */
2411 /* Make sure the target cpu sees everything */
2415 * Try to detect when a SMI has occurred, wait up to 200ms.
2417 * If a SMI occurs during an AP reset but before we issue
2418 * the STARTUP command, the AP may brick. To work around
2419 * this problem we hold off doing the AP startup until
2420 * after we have detected the SMI. Hopefully another SMI
2421 * will not occur before we finish the AP startup.
2423 * Retries don't seem to help. SMIs have a window of opportunity
2424 * and if USB->legacy keyboard emulation is enabled in the BIOS
2425 * the interrupt rate can be quite high.
2427 * NOTE: Don't worry about the L1 cache load, it might bloat
2428 * ldelta a little but ndelta will be so huge when the SMI
2429 * occurs the detection logic will still work fine.
2432 set_apic_timer(200000);
2437 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2438 * and running the target CPU. OR this INIT IPI might be latched (P5
2439 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2442 * see apic/apicreg.h for icr bit definitions.
2444 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2448 * Setup the address for the target AP. We can setup
2449 * icr_hi once and then just trigger operations with
2452 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2453 icr_hi |= (physical_cpu << 24);
2454 icr_lo = lapic->icr_lo & 0xfff00000;
2455 lapic->icr_hi = icr_hi;
2458 * Do an INIT IPI: assert RESET
2460 * Use edge triggered mode to assert INIT
2462 lapic->icr_lo = icr_lo | 0x00004500;
2463 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2467 * The spec calls for a 10ms delay but we may have to use a
2468 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2469 * interrupt. We have other loops here too and dividing by 2
2470 * doesn't seem to be enough even after subtracting 350us,
2471 * so we divide by 4.
2473 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2474 * interrupt was detected we use the full 10ms.
2478 else if (smibest < 150 * 4 + 350)
2480 else if ((smibest - 350) / 4 < 10000)
2481 u_sleep((smibest - 350) / 4);
2486 * Do an INIT IPI: deassert RESET
2488 * Use level triggered mode to deassert. It is unclear
2489 * why we need to do this.
2491 lapic->icr_lo = icr_lo | 0x00008500;
2492 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2494 u_sleep(150); /* wait 150us */
2497 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2498 * latched, (P5 bug) this 1st STARTUP would then terminate
2499 * immediately, and the previously started INIT IPI would continue. OR
2500 * the previous INIT IPI has already run. and this STARTUP IPI will
2501 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2504 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2505 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2507 u_sleep(200); /* wait ~200uS */
2510 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2511 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2512 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2513 * recognized after hardware RESET or INIT IPI.
2515 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2516 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2519 /* Resume normal operation */
2522 /* wait for it to start, see ap_init() */
2523 set_apic_timer(5000000);/* == 5 seconds */
2524 while (read_apic_timer()) {
2525 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2526 return 1; /* return SUCCESS */
2529 return 0; /* return FAILURE */
2544 while (read_apic_timer()) {
2546 for (count = 0; count < 100; ++count)
2547 ntsc = rdtsc(); /* force loop to occur */
2549 ndelta = ntsc - ltsc;
2550 if (ldelta > ndelta)
2552 if (ndelta > ldelta * 2)
2555 ldelta = ntsc - ltsc;
2558 return(read_apic_timer());
2562 * Synchronously flush the TLB on all other CPU's. The current cpu's
2563 * TLB is not flushed. If the caller wishes to flush the current cpu's
2564 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2566 * NOTE: If for some reason we were unable to start all cpus we cannot
2567 * safely use broadcast IPIs.
2570 static cpumask_t smp_invltlb_req;
2572 #define SMP_INVLTLB_DEBUG
2578 struct mdglobaldata *md = mdcpu;
2579 #ifdef SMP_INVLTLB_DEBUG
2584 crit_enter_gd(&md->mi);
2585 md->gd_invltlb_ret = 0;
2586 ++md->mi.gd_cnt.v_smpinvltlb;
2587 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2588 #ifdef SMP_INVLTLB_DEBUG
2591 if (smp_startup_mask == smp_active_mask) {
2592 all_but_self_ipi(XINVLTLB_OFFSET);
2594 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2595 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2598 #ifdef SMP_INVLTLB_DEBUG
2600 kprintf("smp_invltlb: ipi sent\n");
2602 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2603 (smp_active_mask & ~md->mi.gd_cpumask)) {
2606 #ifdef SMP_INVLTLB_DEBUG
2608 if (++count == 400000000) {
2609 print_backtrace(-1);
2610 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2611 "rflags %016jx retry",
2612 (long)md->gd_invltlb_ret,
2613 (long)smp_invltlb_req,
2614 (intmax_t)read_rflags());
2615 __asm __volatile ("sti");
2618 lwkt_process_ipiq();
2620 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2621 ~md->mi.gd_cpumask &
2625 kprintf("bcpu %d\n", bcpu);
2626 xgd = globaldata_find(bcpu);
2627 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2630 Debugger("giving up");
2636 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2637 crit_exit_gd(&md->mi);
2644 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2645 * bother to bump the critical section count or nested interrupt count
2646 * so only do very low level operations here.
2649 smp_invltlb_intr(void)
2651 struct mdglobaldata *md = mdcpu;
2652 struct mdglobaldata *omd;
2657 mask = smp_invltlb_req;
2660 cpu = BSFCPUMASK(mask);
2661 mask &= ~CPUMASK(cpu);
2662 omd = (struct mdglobaldata *)globaldata_find(cpu);
2663 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2670 * When called the executing CPU will send an IPI to all other CPUs
2671 * requesting that they halt execution.
2673 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2675 * - Signals all CPUs in map to stop.
2676 * - Waits for each to stop.
2683 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2684 * from executing at same time.
2687 stop_cpus(cpumask_t map)
2689 map &= smp_active_mask;
2691 /* send the Xcpustop IPI to all CPUs in map */
2692 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2694 while ((stopped_cpus & map) != map)
2702 * Called by a CPU to restart stopped CPUs.
2704 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2706 * - Signals all CPUs in map to restart.
2707 * - Waits for each to restart.
2715 restart_cpus(cpumask_t map)
2717 /* signal other cpus to restart */
2718 started_cpus = map & smp_active_mask;
2720 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2727 * This is called once the mpboot code has gotten us properly relocated
2728 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2729 * and when it returns the scheduler will call the real cpu_idle() main
2730 * loop for the idlethread. Interrupts are disabled on entry and should
2731 * remain disabled at return.
2739 * Adjust smp_startup_mask to signal the BSP that we have started
2740 * up successfully. Note that we do not yet hold the BGL. The BSP
2741 * is waiting for our signal.
2743 * We can't set our bit in smp_active_mask yet because we are holding
2744 * interrupts physically disabled and remote cpus could deadlock
2745 * trying to send us an IPI.
2747 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2751 * Interlock for finalization. Wait until mp_finish is non-zero,
2752 * then get the MP lock.
2754 * Note: We are in a critical section.
2756 * Note: we are the idle thread, we can only spin.
2758 * Note: The load fence is memory volatile and prevents the compiler
2759 * from improperly caching mp_finish, and the cpu from improperly
2762 while (mp_finish == 0)
2764 while (try_mplock() == 0)
2767 if (cpu_feature & CPUID_TSC) {
2769 * The BSP is constantly updating tsc0_offset, figure out
2770 * the relative difference to synchronize ktrdump.
2772 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2775 /* BSP may have changed PTD while we're waiting for the lock */
2778 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2782 /* Build our map of 'other' CPUs. */
2783 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2785 kprintf(" %d", mycpu->gd_cpuid);
2787 /* A quick check from sanity claus */
2788 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
2789 if (mycpu->gd_cpuid != apic_id) {
2790 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2791 kprintf("SMP: apic_id = %d lapicid %d\n",
2792 apic_id, (lapic->id & 0xff000000) >> 24);
2794 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2796 panic("cpuid mismatch! boom!!");
2799 /* Initialize AP's local APIC for irq's */
2800 apic_initialize(FALSE);
2802 /* Set memory range attributes for this CPU to match the BSP */
2803 mem_range_AP_init();
2806 * Once we go active we must process any IPIQ messages that may
2807 * have been queued, because no actual IPI will occur until we
2808 * set our bit in the smp_active_mask. If we don't the IPI
2809 * message interlock could be left set which would also prevent
2812 * The idle loop doesn't expect the BGL to be held and while
2813 * lwkt_switch() normally cleans things up this is a special case
2814 * because we returning almost directly into the idle loop.
2816 * The idle thread is never placed on the runq, make sure
2817 * nothing we've done put it there.
2819 KKASSERT(get_mplock_count(curthread) == 1);
2820 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2823 * Enable interrupts here. idle_restore will also do it, but
2824 * doing it here lets us clean up any strays that got posted to
2825 * the CPU during the AP boot while we are still in a critical
2828 __asm __volatile("sti; pause; pause"::);
2829 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2831 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2832 lwkt_process_ipiq();
2835 * Releasing the mp lock lets the BSP finish up the SMP init
2838 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2842 * Get SMP fully working before we start initializing devices.
2850 kprintf("Finish MP startup\n");
2851 if (cpu_feature & CPUID_TSC)
2852 tsc0_offset = rdtsc();
2855 while (smp_active_mask != smp_startup_mask) {
2857 if (cpu_feature & CPUID_TSC)
2858 tsc0_offset = rdtsc();
2860 while (try_mplock() == 0)
2864 kprintf("Active CPU Mask: %016jx\n",
2865 (uintmax_t)smp_active_mask);
2869 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2872 cpu_send_ipiq(int dcpu)
2874 if (CPUMASK(dcpu) & smp_active_mask)
2875 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2878 #if 0 /* single_apic_ipi_passive() not working yet */
2880 * Returns 0 on failure, 1 on success
2883 cpu_send_ipiq_passive(int dcpu)
2886 if (CPUMASK(dcpu) & smp_active_mask) {
2887 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2888 APIC_DELMODE_FIXED);
2895 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2897 struct mptable_bus_info *bus_info = xarg;
2898 const struct BUSENTRY *ent;
2899 struct mptable_bus *bus;
2905 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2906 if (bus->mb_id == ent->bus_id) {
2907 kprintf("mptable_bus_info_alloc: duplicated bus id "
2908 "(%d)\n", bus->mb_id);
2914 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2915 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2916 bus->mb_type = MPTABLE_BUS_PCI;
2917 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2918 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2919 bus->mb_type = MPTABLE_BUS_ISA;
2923 bus->mb_id = ent->bus_id;
2924 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2930 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2934 bzero(bus_info, sizeof(*bus_info));
2935 TAILQ_INIT(&bus_info->mbi_list);
2937 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2939 mptable_bus_info_free(bus_info);
2943 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2945 struct mptable_bus *bus;
2947 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2948 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2953 struct mptable_lapic_cbarg1 {
2956 u_int ht_apicid_mask;
2960 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2962 const struct PROCENTRY *ent;
2963 struct mptable_lapic_cbarg1 *arg = xarg;
2969 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2973 if (ent->apic_id < 32) {
2974 arg->ht_apicid_mask |= 1 << ent->apic_id;
2975 } else if (arg->ht_fixup) {
2976 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2982 struct mptable_lapic_cbarg2 {
2989 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2991 const struct PROCENTRY *ent;
2992 struct mptable_lapic_cbarg2 *arg = xarg;
2998 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2999 KKASSERT(!arg->found_bsp);
3003 if (processor_entry(ent, arg->cpu))
3006 if (arg->logical_cpus) {
3007 struct PROCENTRY proc;
3011 * Create fake mptable processor entries
3012 * and feed them to processor_entry() to
3013 * enumerate the logical CPUs.
3015 bzero(&proc, sizeof(proc));
3017 proc.cpu_flags = PROCENTRY_FLAG_EN;
3018 proc.apic_id = ent->apic_id;
3020 for (i = 1; i < arg->logical_cpus; i++) {
3022 processor_entry(&proc, arg->cpu);
3030 mptable_imcr(struct mptable_pos *mpt)
3032 /* record whether PIC or virtual-wire mode */
3033 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
3034 mpt->mp_fps->mpfb2 & 0x80);
3038 mptable_lapic_default(void)
3040 int ap_apicid, bsp_apicid;
3042 mp_naps = 1; /* exclude BSP */
3044 /* Map local apic before the id field is accessed */
3045 lapic_map(DEFAULT_APIC_BASE);
3047 bsp_apicid = APIC_ID(lapic->id);
3048 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3051 mp_set_cpuids(0, bsp_apicid);
3052 /* one and only AP */
3053 mp_set_cpuids(1, ap_apicid);
3059 * ID_TO_CPU(N), APIC ID to logical CPU table
3060 * CPU_TO_ID(N), logical CPU to APIC ID table
3063 mptable_lapic_enumerate(struct lapic_enumerator *e)
3065 struct mptable_pos mpt;
3066 struct mptable_lapic_cbarg1 arg1;
3067 struct mptable_lapic_cbarg2 arg2;
3069 int error, logical_cpus = 0;
3070 vm_offset_t lapic_addr;
3072 if (mptable_use_default) {
3073 mptable_lapic_default();
3077 error = mptable_map(&mpt);
3079 panic("mptable_lapic_enumerate mptable_map failed\n");
3080 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3084 /* Save local apic address */
3085 lapic_addr = (vm_offset_t)cth->apic_address;
3086 KKASSERT(lapic_addr != 0);
3089 * Find out how many CPUs do we have
3091 bzero(&arg1, sizeof(arg1));
3092 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3094 error = mptable_iterate_entries(cth,
3095 mptable_lapic_pass1_callback, &arg1);
3097 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3098 KKASSERT(arg1.cpu_count != 0);
3100 /* See if we need to fixup HT logical CPUs. */
3101 if (arg1.ht_fixup) {
3102 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3104 if (logical_cpus != 0)
3105 arg1.cpu_count *= logical_cpus;
3107 mp_naps = arg1.cpu_count;
3109 /* Qualify the numbers again, after possible HT fixup */
3110 if (mp_naps > MAXCPU) {
3111 kprintf("Warning: only using %d of %d available CPUs!\n",
3117 --mp_naps; /* subtract the BSP */
3120 * Link logical CPU id to local apic id
3122 bzero(&arg2, sizeof(arg2));
3124 arg2.logical_cpus = logical_cpus;
3126 error = mptable_iterate_entries(cth,
3127 mptable_lapic_pass2_callback, &arg2);
3129 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3130 KKASSERT(arg2.found_bsp);
3132 /* Map local apic */
3133 lapic_map(lapic_addr);
3135 mptable_unmap(&mpt);
3138 struct mptable_lapic_probe_cbarg {
3144 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3146 const struct PROCENTRY *ent;
3147 struct mptable_lapic_probe_cbarg *arg = xarg;
3153 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3157 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3158 if (arg->found_bsp) {
3159 kprintf("more than one BSP in base MP table\n");
3168 mptable_lapic_probe(struct lapic_enumerator *e)
3170 struct mptable_pos mpt;
3171 struct mptable_lapic_probe_cbarg arg;
3175 if (mptable_fps_phyaddr == 0)
3178 if (mptable_use_default)
3181 error = mptable_map(&mpt);
3184 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3189 if (cth->apic_address == 0)
3192 bzero(&arg, sizeof(arg));
3193 error = mptable_iterate_entries(cth,
3194 mptable_lapic_probe_callback, &arg);
3196 if (arg.cpu_count == 0) {
3197 kprintf("MP table contains no processor entries\n");
3199 } else if (!arg.found_bsp) {
3200 kprintf("MP table does not contains BSP entry\n");
3205 mptable_unmap(&mpt);
3209 static struct lapic_enumerator mptable_lapic_enumerator = {
3210 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3211 .lapic_probe = mptable_lapic_probe,
3212 .lapic_enumerate = mptable_lapic_enumerate
3216 mptable_lapic_enum_register(void)
3218 lapic_enumerator_register(&mptable_lapic_enumerator);
3220 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3221 mptable_lapic_enum_register, 0);
3224 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
3226 const struct IOAPICENTRY *ent;
3227 struct mptable_ioapic *nioapic, *ioapic;
3233 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3236 if (ent->apic_address == 0) {
3237 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
3241 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3242 if (ioapic->mio_apic_id == ent->apic_id) {
3243 kprintf("mptable_ioapic_create_list: duplicated "
3244 "apic id %d\n", ioapic->mio_apic_id);
3247 if (ioapic->mio_addr == ent->apic_address) {
3248 kprintf("mptable_ioapic_create_list: overlapped "
3249 "IOAPIC addr 0x%08x", ioapic->mio_addr);
3254 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3255 nioapic->mio_apic_id = ent->apic_id;
3256 nioapic->mio_addr = ent->apic_address;
3259 * Create IOAPIC list in ascending order of APIC ID
3261 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
3262 mptable_ioapic_list, mio_link) {
3263 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
3264 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
3265 ioapic, nioapic, mio_link);
3270 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
3276 mptable_ioapic_create_list(void)
3278 struct mptable_ioapic *ioapic;
3279 struct mptable_pos mpt;
3282 if (mptable_fps_phyaddr == 0)
3285 if (mptable_use_default) {
3286 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3287 ioapic->mio_idx = 0;
3288 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
3289 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
3291 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
3295 error = mptable_map(&mpt);
3297 panic("mptable_ioapic_create_list: mptable_map failed\n");
3298 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3300 error = mptable_iterate_entries(mpt.mp_cth,
3301 mptable_ioapic_list_callback, NULL);
3303 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
3304 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
3305 kfree(ioapic, M_DEVBUF);
3311 * Assign index number for each IOAPIC
3314 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3315 ioapic->mio_idx = idx;
3319 mptable_unmap(&mpt);
3321 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
3322 mptable_ioapic_create_list, 0);
3325 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3327 const struct mptable_bus_info *bus_info = xarg;
3328 const struct mptable_ioapic *ioapic;
3329 const struct mptable_bus *bus;
3330 struct mptable_pci_int *pci_int;
3331 const struct INTENTRY *ent;
3332 int pci_pin, pci_dev;
3338 if (ent->int_type != 0)
3341 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3342 if (bus->mb_type == MPTABLE_BUS_PCI &&
3343 bus->mb_id == ent->src_bus_id)
3349 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3350 if (ioapic->mio_apic_id == ent->dst_apic_id)
3353 if (ioapic == NULL) {
3354 kprintf("MPTABLE: warning PCI int dst apic id %d "
3355 "does not exist\n", ent->dst_apic_id);
3359 pci_pin = ent->src_bus_irq & 0x3;
3360 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3362 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3363 if (pci_int->mpci_bus == ent->src_bus_id &&
3364 pci_int->mpci_dev == pci_dev &&
3365 pci_int->mpci_pin == pci_pin) {
3366 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
3367 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3368 kprintf("MPTABLE: warning duplicated "
3369 "PCI int entry for "
3370 "bus %d, dev %d, pin %d\n",
3376 kprintf("mptable_pci_int_register: "
3377 "conflict PCI int entry for "
3378 "bus %d, dev %d, pin %d, "
3379 "IOAPIC %d.%d -> %d.%d\n",
3383 pci_int->mpci_ioapic_idx,
3384 pci_int->mpci_ioapic_pin,
3392 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3394 pci_int->mpci_bus = ent->src_bus_id;
3395 pci_int->mpci_dev = pci_dev;
3396 pci_int->mpci_pin = pci_pin;
3397 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
3398 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3400 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3406 mptable_pci_int_register(void)
3408 struct mptable_bus_info bus_info;
3409 const struct mptable_bus *bus;
3410 struct mptable_pci_int *pci_int;
3411 struct mptable_pos mpt;
3412 int error, force_pci0, npcibus;
3415 if (mptable_fps_phyaddr == 0)
3418 if (mptable_use_default)
3421 if (TAILQ_EMPTY(&mptable_ioapic_list))
3424 error = mptable_map(&mpt);
3426 panic("mptable_pci_int_register: mptable_map failed\n");
3427 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3431 mptable_bus_info_alloc(cth, &bus_info);
3432 if (TAILQ_EMPTY(&bus_info.mbi_list))
3436 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3437 if (bus->mb_type == MPTABLE_BUS_PCI)
3441 mptable_bus_info_free(&bus_info);
3443 } else if (npcibus == 1) {
3447 error = mptable_iterate_entries(cth,
3448 mptable_pci_int_callback, &bus_info);
3450 mptable_bus_info_free(&bus_info);
3453 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3454 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3455 kfree(pci_int, M_DEVBUF);
3461 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3462 pci_int->mpci_bus = 0;
3465 mptable_unmap(&mpt);
3467 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3468 mptable_pci_int_register, 0);
3470 struct mptable_ioapic_probe_cbarg {
3471 const struct mptable_bus_info *bus_info;
3475 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3477 struct mptable_ioapic_probe_cbarg *arg = xarg;
3478 const struct mptable_ioapic *ioapic;
3479 const struct mptable_bus *bus;
3480 const struct INTENTRY *ent;
3486 if (ent->int_type != 0)
3489 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3490 if (bus->mb_type == MPTABLE_BUS_ISA &&
3491 bus->mb_id == ent->src_bus_id)
3497 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3498 if (ioapic->mio_apic_id == ent->dst_apic_id)
3501 if (ioapic == NULL) {
3502 kprintf("MPTABLE: warning ISA int dst apic id %d "
3503 "does not exist\n", ent->dst_apic_id);
3507 /* XXX magic number */
3508 if (ent->src_bus_irq >= 16) {
3509 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
3517 mptable_ioapic_probe(struct ioapic_enumerator *e)
3519 struct mptable_ioapic_probe_cbarg arg;
3520 struct mptable_bus_info bus_info;
3521 struct mptable_pos mpt;
3525 if (mptable_fps_phyaddr == 0)
3528 if (mptable_use_default)
3531 if (TAILQ_EMPTY(&mptable_ioapic_list))
3534 error = mptable_map(&mpt);
3536 panic("mptable_ioapic_probe: mptable_map failed\n");
3537 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3541 mptable_bus_info_alloc(cth, &bus_info);
3543 bzero(&arg, sizeof(arg));
3544 arg.bus_info = &bus_info;
3546 error = mptable_iterate_entries(cth,
3547 mptable_ioapic_probe_callback, &arg);
3549 mptable_bus_info_free(&bus_info);
3550 mptable_unmap(&mpt);
3555 struct mptable_ioapic_int_cbarg {
3556 const struct mptable_bus_info *bus_info;
3561 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3563 struct mptable_ioapic_int_cbarg *arg = xarg;
3564 const struct mptable_bus *bus;
3565 const struct INTENTRY *ent;
3573 if (ent->int_type != 0)
3576 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3577 if (bus->mb_type == MPTABLE_BUS_ISA &&
3578 bus->mb_id == ent->src_bus_id)
3584 /* XXX rough estimation */
3585 if (ent->src_bus_irq != ent->dst_apic_int) {
3587 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3588 ent->src_bus_irq, ent->dst_apic_int);
3595 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3597 struct mptable_bus_info bus_info;
3598 const struct mptable_ioapic *ioapic;
3599 struct mptable_pos mpt;
3603 KKASSERT(mptable_fps_phyaddr != 0);
3604 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
3606 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3608 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
3609 "apic id %d, idx %d\n",
3611 ioapic->mio_apic_id, ioapic->mio_idx);
3616 if (mptable_use_default) {
3618 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3619 /* TODO default intsrc */
3623 error = mptable_map(&mpt);
3625 panic("mptable_ioapic_probe: mptable_map failed\n");
3626 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3630 mptable_bus_info_alloc(cth, &bus_info);
3632 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3634 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3635 /* TODO default intsrc */
3637 struct mptable_ioapic_int_cbarg arg;
3639 bzero(&arg, sizeof(arg));
3640 arg.bus_info = &bus_info;
3642 error = mptable_iterate_entries(cth,
3643 mptable_ioapic_int_callback, &arg);
3645 panic("mptable_ioapic_int failed\n");
3647 if (arg.ioapic_nint == 0) {
3649 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3652 /* TODO default intsrc */
3656 mptable_bus_info_free(&bus_info);
3658 mptable_unmap(&mpt);
3661 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3662 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3663 .ioapic_probe = mptable_ioapic_probe,
3664 .ioapic_enumerate = mptable_ioapic_enumerate
3668 mptable_ioapic_enum_register(void)
3670 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3672 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3673 mptable_ioapic_enum_register, 0);