3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.21 2005/12/31 14:08:00 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
117 #include <sys/endian.h>
118 #include <sys/systm.h>
119 #include <sys/sockio.h>
120 #include <sys/mbuf.h>
121 #include <sys/malloc.h>
122 #include <sys/module.h>
123 #include <sys/kernel.h>
124 #include <sys/socket.h>
125 #include <sys/serialize.h>
126 #include <sys/thread2.h>
129 #include <net/ifq_var.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/vlan/if_vlan_var.h>
139 #include <machine/bus_pio.h>
140 #include <machine/bus_memio.h>
141 #include <machine/bus.h>
142 #include <machine/resource.h>
144 #include <sys/rman.h>
146 #include <dev/netif/mii_layer/mii.h>
147 #include <dev/netif/mii_layer/miivar.h>
149 #include <bus/pci/pcireg.h>
150 #include <bus/pci/pcivar.h>
152 /* "controller miibus0" required. See GENERIC if you get errors here. */
153 #include "miibus_if.h"
155 #include <dev/netif/re/if_rereg.h>
158 * The hardware supports checksumming but, as usual, some chipsets screw it
159 * all up and produce bogus packets, so we disable it by default.
161 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
162 #define RE_DISABLE_HWCSUM
165 * Various supported device vendors/types and their names.
167 static struct re_type re_devs[] = {
168 { DLINK_VENDORID, DLINK_DEVICEID_528T, RE_HWREV_8169S,
169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
170 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS,
171 "RealTek 8139C+ 10/100BaseTX" },
172 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169,
173 "RealTek 8169 Gigabit Ethernet" },
174 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S,
175 "RealTek 8169S Single-chip Gigabit Ethernet" },
176 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S,
177 "RealTek 8110S Single-chip Gigabit Ethernet" },
181 static struct re_hwrev re_hwrevs[] = {
182 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"},
183 { RE_HWREV_8169, RE_8169, "8169"},
184 { RE_HWREV_8169S, RE_8169, "8169S"},
185 { RE_HWREV_8110S, RE_8169, "8110S"},
189 static int re_probe(device_t);
190 static int re_attach(device_t);
191 static int re_detach(device_t);
193 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
195 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
196 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
198 static int re_allocmem(device_t, struct re_softc *);
199 static int re_newbuf(struct re_softc *, int, struct mbuf *);
200 static int re_rx_list_init(struct re_softc *);
201 static int re_tx_list_init(struct re_softc *);
202 static void re_rxeof(struct re_softc *);
203 static void re_txeof(struct re_softc *);
204 static void re_intr(void *);
205 static void re_tick(void *);
206 static void re_tick_serialized(void *);
207 static void re_start(struct ifnet *);
208 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
209 static void re_init(void *);
210 static void re_stop(struct re_softc *);
211 static void re_watchdog(struct ifnet *);
212 static int re_suspend(device_t);
213 static int re_resume(device_t);
214 static void re_shutdown(device_t);
215 static int re_ifmedia_upd(struct ifnet *);
216 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
218 static void re_eeprom_putbyte(struct re_softc *, int);
219 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
220 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int);
221 static int re_gmii_readreg(device_t, int, int);
222 static int re_gmii_writereg(device_t, int, int, int);
224 static int re_miibus_readreg(device_t, int, int);
225 static int re_miibus_writereg(device_t, int, int, int);
226 static void re_miibus_statchg(device_t);
228 static void re_setmulti(struct re_softc *);
229 static void re_reset(struct re_softc *);
231 static int re_diag(struct re_softc *);
232 #ifdef DEVICE_POLLING
233 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
236 static device_method_t re_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_probe, re_probe),
239 DEVMETHOD(device_attach, re_attach),
240 DEVMETHOD(device_detach, re_detach),
241 DEVMETHOD(device_suspend, re_suspend),
242 DEVMETHOD(device_resume, re_resume),
243 DEVMETHOD(device_shutdown, re_shutdown),
246 DEVMETHOD(bus_print_child, bus_generic_print_child),
247 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
250 DEVMETHOD(miibus_readreg, re_miibus_readreg),
251 DEVMETHOD(miibus_writereg, re_miibus_writereg),
252 DEVMETHOD(miibus_statchg, re_miibus_statchg),
257 static driver_t re_driver = {
260 sizeof(struct re_softc)
263 static devclass_t re_devclass;
265 DECLARE_DUMMY_MODULE(if_re);
266 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
267 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
268 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
271 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
274 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
277 * Send a read command and address to the EEPROM, check for ACK.
280 re_eeprom_putbyte(struct re_softc *sc, int addr)
284 d = addr | sc->re_eecmd_read;
287 * Feed in each bit and strobe the clock.
289 for (i = 0x400; i != 0; i >>= 1) {
291 EE_SET(RE_EE_DATAIN);
293 EE_CLR(RE_EE_DATAIN);
303 * Read a word of data stored in the EEPROM at address 'addr.'
306 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
311 /* Enter EEPROM access mode. */
312 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
315 * Send address of word we want to read.
317 re_eeprom_putbyte(sc, addr);
319 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
322 * Start reading bits from EEPROM.
324 for (i = 0x8000; i != 0; i >>= 1) {
327 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
333 /* Turn off EEPROM access mode. */
334 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
340 * Read a sequence of words from the EEPROM.
343 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap)
346 uint16_t word = 0, *ptr;
348 for (i = 0; i < cnt; i++) {
349 re_eeprom_getword(sc, off + i, &word);
350 ptr = (u_int16_t *)(dest + (i * 2));
352 *ptr = be16toh(word);
359 re_gmii_readreg(device_t dev, int phy, int reg)
361 struct re_softc *sc = device_get_softc(dev);
368 /* Let the rgephy driver read the GMEDIASTAT register */
370 if (reg == RE_GMEDIASTAT)
371 return(CSR_READ_1(sc, RE_GMEDIASTAT));
373 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
376 for (i = 0; i < RE_TIMEOUT; i++) {
377 rval = CSR_READ_4(sc, RE_PHYAR);
378 if (rval & RE_PHYAR_BUSY)
383 if (i == RE_TIMEOUT) {
384 device_printf(dev, "PHY read failed\n");
388 return(rval & RE_PHYAR_PHYDATA);
392 re_gmii_writereg(device_t dev, int phy, int reg, int data)
394 struct re_softc *sc = device_get_softc(dev);
398 CSR_WRITE_4(sc, RE_PHYAR,
399 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
402 for (i = 0; i < RE_TIMEOUT; i++) {
403 rval = CSR_READ_4(sc, RE_PHYAR);
404 if ((rval & RE_PHYAR_BUSY) == 0)
410 device_printf(dev, "PHY write failed\n");
416 re_miibus_readreg(device_t dev, int phy, int reg)
418 struct re_softc *sc = device_get_softc(dev);
420 uint16_t re8139_reg = 0;
422 if (sc->re_type == RE_8169) {
423 rval = re_gmii_readreg(dev, phy, reg);
427 /* Pretend the internal PHY is only at address 0 */
433 re8139_reg = RE_BMCR;
436 re8139_reg = RE_BMSR;
439 re8139_reg = RE_ANAR;
442 re8139_reg = RE_ANER;
445 re8139_reg = RE_LPAR;
451 * Allow the rlphy driver to read the media status
452 * register. If we have a link partner which does not
453 * support NWAY, this is the register which will tell
454 * us the results of parallel detection.
457 return(CSR_READ_1(sc, RE_MEDIASTAT));
459 device_printf(dev, "bad phy register\n");
462 rval = CSR_READ_2(sc, re8139_reg);
467 re_miibus_writereg(device_t dev, int phy, int reg, int data)
469 struct re_softc *sc= device_get_softc(dev);
470 u_int16_t re8139_reg = 0;
472 if (sc->re_type == RE_8169)
473 return(re_gmii_writereg(dev, phy, reg, data));
475 /* Pretend the internal PHY is only at address 0 */
481 re8139_reg = RE_BMCR;
484 re8139_reg = RE_BMSR;
487 re8139_reg = RE_ANAR;
490 re8139_reg = RE_ANER;
493 re8139_reg = RE_LPAR;
499 device_printf(dev, "bad phy register\n");
502 CSR_WRITE_2(sc, re8139_reg, data);
507 re_miibus_statchg(device_t dev)
512 * Program the 64-bit multicast hash filter.
515 re_setmulti(struct re_softc *sc)
517 struct ifnet *ifp = &sc->arpcom.ac_if;
519 uint32_t hashes[2] = { 0, 0 };
520 struct ifmultiaddr *ifma;
524 rxfilt = CSR_READ_4(sc, RE_RXCFG);
526 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
527 rxfilt |= RE_RXCFG_RX_MULTI;
528 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
529 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
530 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
534 /* first, zot all the existing hash bits */
535 CSR_WRITE_4(sc, RE_MAR0, 0);
536 CSR_WRITE_4(sc, RE_MAR4, 0);
538 /* now program new ones */
539 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
540 if (ifma->ifma_addr->sa_family != AF_LINK)
542 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
543 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
545 hashes[0] |= (1 << h);
547 hashes[1] |= (1 << (h - 32));
552 rxfilt |= RE_RXCFG_RX_MULTI;
554 rxfilt &= ~RE_RXCFG_RX_MULTI;
556 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
557 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
558 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
562 re_reset(struct re_softc *sc)
566 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
568 for (i = 0; i < RE_TIMEOUT; i++) {
570 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
574 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
576 CSR_WRITE_1(sc, 0x82, 1);
580 * The following routine is designed to test for a defect on some
581 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
582 * lines connected to the bus, however for a 32-bit only card, they
583 * should be pulled high. The result of this defect is that the
584 * NIC will not work right if you plug it into a 64-bit slot: DMA
585 * operations will be done with 64-bit transfers, which will fail
586 * because the 64-bit data lines aren't connected.
588 * There's no way to work around this (short of talking a soldering
589 * iron to the board), however we can detect it. The method we use
590 * here is to put the NIC into digital loopback mode, set the receiver
591 * to promiscuous mode, and then try to send a frame. We then compare
592 * the frame data we sent to what was received. If the data matches,
593 * then the NIC is working correctly, otherwise we know the user has
594 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
595 * slot. In the latter case, there's no way the NIC can work correctly,
596 * so we print out a message on the console and abort the device attach.
600 re_diag(struct re_softc *sc)
602 struct ifnet *ifp = &sc->arpcom.ac_if;
604 struct ether_header *eh;
605 struct re_desc *cur_rx;
608 int total_len, i, error = 0;
609 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
610 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
612 /* Allocate a single mbuf */
614 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
619 * Initialize the NIC in test mode. This sets the chip up
620 * so that it can send and receive frames, but performs the
621 * following special functions:
622 * - Puts receiver in promiscuous mode
623 * - Enables digital loopback mode
624 * - Leaves interrupts turned off
627 ifp->if_flags |= IFF_PROMISC;
634 /* Put some data in the mbuf */
636 eh = mtod(m0, struct ether_header *);
637 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
638 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
639 eh->ether_type = htons(ETHERTYPE_IP);
640 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
643 * Queue the packet, start transmission.
644 * Note: ifq_handoff() ultimately calls re_start() for us.
647 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
648 error = ifq_handoff(ifp, m0, NULL);
655 /* Wait for it to propagate through the chip */
658 for (i = 0; i < RE_TIMEOUT; i++) {
659 status = CSR_READ_2(sc, RE_ISR);
660 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
661 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
666 if (i == RE_TIMEOUT) {
667 if_printf(ifp, "diagnostic failed to receive packet "
668 "in loopback mode\n");
674 * The packet should have been dumped into the first
675 * entry in the RX DMA ring. Grab it from there.
678 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
679 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
680 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
681 BUS_DMASYNC_POSTWRITE);
682 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
684 m0 = sc->re_ldata.re_rx_mbuf[0];
685 sc->re_ldata.re_rx_mbuf[0] = NULL;
686 eh = mtod(m0, struct ether_header *);
688 cur_rx = &sc->re_ldata.re_rx_list[0];
689 total_len = RE_RXBYTES(cur_rx);
690 rxstat = le32toh(cur_rx->re_cmdstat);
692 if (total_len != ETHER_MIN_LEN) {
693 if_printf(ifp, "diagnostic failed, received short packet\n");
698 /* Test that the received packet data matches what we sent. */
700 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
701 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
702 be16toh(eh->ether_type) != ETHERTYPE_IP) {
703 if_printf(ifp, "WARNING, DMA FAILURE!\n");
704 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
705 dst, ":", src, ":", ETHERTYPE_IP);
706 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
707 eh->ether_dhost, ":", eh->ether_shost, ":",
708 ntohs(eh->ether_type));
709 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
710 "into a 64-bit PCI slot.\n");
711 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
712 "for proper operation.\n");
713 if_printf(ifp, "Read the re(4) man page for more details.\n");
718 /* Turn interface off, release resources */
721 ifp->if_flags &= ~IFF_PROMISC;
730 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
731 * IDs against our list and return a device name if we find a match.
734 re_probe(device_t dev)
740 uint16_t vendor, product;
744 vendor = pci_get_vendor(dev);
745 product = pci_get_device(dev);
747 for (t = re_devs; t->re_name != NULL; t++) {
748 if (product == t->re_did && vendor == t->re_vid)
753 * Check if we found a RealTek device.
755 if (t->re_name == NULL)
759 * Temporarily map the I/O space so we can read the chip ID register.
761 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
763 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
765 if (sc->re_res == NULL) {
766 device_printf(dev, "couldn't map ports/memory\n");
771 sc->re_btag = rman_get_bustag(sc->re_res);
772 sc->re_bhandle = rman_get_bushandle(sc->re_res);
774 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
775 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
779 * and continue matching for the specific chip...
781 for (; t->re_name != NULL; t++) {
782 if (product == t->re_did && vendor == t->re_vid &&
783 t->re_basetype == hwrev) {
784 device_set_desc(dev, t->re_name);
792 * This routine takes the segment list provided as the result of
793 * a bus_dma_map_load() operation and assigns the addresses/lengths
794 * to RealTek DMA descriptors. This can be called either by the RX
795 * code or the TX code. In the RX case, we'll probably wind up mapping
796 * at most one segment. For the TX case, there could be any number of
797 * segments since TX packets may span multiple mbufs. In either case,
798 * if the number of segments is larger than the re_maxsegs limit
799 * specified by the caller, we abort the mapping operation. Sadly,
800 * whoever designed the buffer mapping API did not provide a way to
801 * return an error from here, so we have to fake it a bit.
805 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
806 bus_size_t mapsize, int error)
808 struct re_dmaload_arg *ctx;
809 struct re_desc *d = NULL;
818 /* Signal error to caller if there's too many segments */
819 if (nseg > ctx->re_maxsegs) {
825 * Map the segment array into descriptors. Note that we set the
826 * start-of-frame and end-of-frame markers for either TX or RX, but
827 * they really only have meaning in the TX case. (In the RX case,
828 * it's the chip that tells us where packets begin and end.)
829 * We also keep track of the end of the ring and set the
830 * end-of-ring bits as needed, and we set the ownership bits
831 * in all except the very first descriptor. (The caller will
832 * set this descriptor later when it start transmission or
837 d = &ctx->re_ring[idx];
838 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
842 cmdstat = segs[i].ds_len;
843 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
844 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
846 cmdstat |= RE_TDESC_CMD_SOF;
848 cmdstat |= RE_TDESC_CMD_OWN;
849 if (idx == (RE_RX_DESC_CNT - 1))
850 cmdstat |= RE_TDESC_CMD_EOR;
851 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
858 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
859 ctx->re_maxsegs = nseg;
864 * Map a single buffer address.
868 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
875 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
877 *addr = segs->ds_addr;
881 re_allocmem(device_t dev, struct re_softc *sc)
886 * Allocate map for RX mbufs.
889 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
890 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
891 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
892 &sc->re_ldata.re_mtag);
894 device_printf(dev, "could not allocate dma tag\n");
899 * Allocate map for TX descriptor list.
901 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
902 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
903 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
904 &sc->re_ldata.re_tx_list_tag);
906 device_printf(dev, "could not allocate dma tag\n");
910 /* Allocate DMA'able memory for the TX ring */
912 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
913 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
914 &sc->re_ldata.re_tx_list_map);
916 device_printf(dev, "could not allocate TX ring\n");
920 /* Load the map for the TX ring. */
922 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
923 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
924 RE_TX_LIST_SZ, re_dma_map_addr,
925 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
927 device_printf(dev, "could not get addres of TX ring\n");
931 /* Create DMA maps for TX buffers */
933 for (i = 0; i < RE_TX_DESC_CNT; i++) {
934 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
935 &sc->re_ldata.re_tx_dmamap[i]);
937 device_printf(dev, "can't create DMA map for TX\n");
943 * Allocate map for RX descriptor list.
945 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
946 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
947 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
948 &sc->re_ldata.re_rx_list_tag);
950 device_printf(dev, "could not allocate dma tag\n");
954 /* Allocate DMA'able memory for the RX ring */
956 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
957 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
958 &sc->re_ldata.re_rx_list_map);
960 device_printf(dev, "could not allocate RX ring\n");
964 /* Load the map for the RX ring. */
966 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
967 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
968 RE_TX_LIST_SZ, re_dma_map_addr,
969 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
971 device_printf(dev, "could not get address of RX ring\n");
975 /* Create DMA maps for RX buffers */
977 for (i = 0; i < RE_RX_DESC_CNT; i++) {
978 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
979 &sc->re_ldata.re_rx_dmamap[i]);
981 device_printf(dev, "can't create DMA map for RX\n");
990 * Attach the interface. Allocate softc structures, do ifmedia
991 * setup and ethernet/BPF attach.
994 re_attach(device_t dev)
996 struct re_softc *sc = device_get_softc(dev);
998 struct re_hwrev *hw_rev;
999 uint8_t eaddr[ETHER_ADDR_LEN];
1001 u_int16_t re_did = 0;
1002 int error = 0, rid, i;
1004 callout_init(&sc->re_timer);
1006 #ifndef BURN_BRIDGES
1008 * Handle power management nonsense.
1011 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1012 uint32_t membase, irq;
1014 /* Save important PCI config data. */
1015 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1016 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1018 /* Reset the power state. */
1019 device_printf(dev, "chip is is in D%d power mode "
1020 "-- setting to D0\n", pci_get_powerstate(dev));
1022 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1024 /* Restore PCI config data. */
1025 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1026 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1030 * Map control/status registers.
1032 pci_enable_busmaster(dev);
1035 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1038 if (sc->re_res == NULL) {
1039 device_printf(dev, "couldn't map ports/memory\n");
1044 sc->re_btag = rman_get_bustag(sc->re_res);
1045 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1047 /* Allocate interrupt */
1049 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1050 RF_SHAREABLE | RF_ACTIVE);
1052 if (sc->re_irq == NULL) {
1053 device_printf(dev, "couldn't map interrupt\n");
1058 /* Reset the adapter. */
1061 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1062 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1063 if (hw_rev->re_rev == hwrev) {
1064 sc->re_type = hw_rev->re_type;
1069 if (sc->re_type == RE_8169) {
1070 /* Set RX length mask */
1071 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1073 /* Force station address autoload from the EEPROM */
1074 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD);
1075 for (i = 0; i < RE_TIMEOUT; i++) {
1076 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0)
1080 if (i == RE_TIMEOUT)
1081 device_printf(dev, "eeprom autoload timed out\n");
1083 for (i = 0; i < ETHER_ADDR_LEN; i++)
1084 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
1088 /* Set RX length mask */
1089 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1091 sc->re_eecmd_read = RE_EECMD_READ_6BIT;
1092 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1093 if (re_did != 0x8129)
1094 sc->re_eecmd_read = RE_EECMD_READ_8BIT;
1097 * Get station address from the EEPROM.
1099 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0);
1100 for (i = 0; i < 3; i++) {
1101 eaddr[(i * 2) + 0] = as[i] & 0xff;
1102 eaddr[(i * 2) + 1] = as[i] >> 8;
1107 * Allocate the parent bus DMA tag appropriate for PCI.
1109 #define RE_NSEG_NEW 32
1110 error = bus_dma_tag_create(NULL, /* parent */
1111 1, 0, /* alignment, boundary */
1112 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1113 BUS_SPACE_MAXADDR, /* highaddr */
1114 NULL, NULL, /* filter, filterarg */
1115 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1116 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1117 BUS_DMA_ALLOCNOW, /* flags */
1118 &sc->re_parent_tag);
1122 error = re_allocmem(dev, sc);
1128 if (mii_phy_probe(dev, &sc->re_miibus,
1129 re_ifmedia_upd, re_ifmedia_sts)) {
1130 device_printf(dev, "MII without any phy!\n");
1135 ifp = &sc->arpcom.ac_if;
1137 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1138 ifp->if_mtu = ETHERMTU;
1139 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1140 ifp->if_ioctl = re_ioctl;
1141 ifp->if_capabilities = IFCAP_VLAN_MTU;
1142 ifp->if_start = re_start;
1143 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1144 #ifdef DEVICE_POLLING
1145 ifp->if_poll = re_poll;
1147 ifp->if_watchdog = re_watchdog;
1148 ifp->if_init = re_init;
1149 if (sc->re_type == RE_8169)
1150 ifp->if_baudrate = 1000000000;
1152 ifp->if_baudrate = 100000000;
1153 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1154 ifq_set_ready(&ifp->if_snd);
1155 #ifdef RE_DISABLE_HWCSUM
1156 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1157 ifp->if_hwassist = 0;
1159 ifp->if_capenable = ifp->if_capabilities;
1160 ifp->if_hwassist = RE_CSUM_FEATURES;
1164 * Call MI attach routine.
1166 ether_ifattach(ifp, eaddr, NULL);
1168 lwkt_serialize_enter(ifp->if_serializer);
1169 /* Perform hardware diagnostic. */
1170 error = re_diag(sc);
1171 lwkt_serialize_exit(ifp->if_serializer);
1174 device_printf(dev, "hardware diagnostic failure\n");
1175 ether_ifdetach(ifp);
1179 /* Hook interrupt last to avoid having to lock softc */
1180 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1181 &sc->re_intrhand, ifp->if_serializer);
1184 device_printf(dev, "couldn't set up irq\n");
1185 ether_ifdetach(ifp);
1197 * Shutdown hardware and free up resources. This can be called any
1198 * time after the mutex has been initialized. It is called in both
1199 * the error case in attach and the normal detach case so it needs
1200 * to be careful about only freeing resources that have actually been
1204 re_detach(device_t dev)
1206 struct re_softc *sc = device_get_softc(dev);
1207 struct ifnet *ifp = &sc->arpcom.ac_if;
1210 /* These should only be active if attach succeeded */
1211 if (device_is_attached(dev)) {
1212 lwkt_serialize_enter(ifp->if_serializer);
1214 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1215 lwkt_serialize_exit(ifp->if_serializer);
1217 ether_ifdetach(ifp);
1220 device_delete_child(dev, sc->re_miibus);
1221 bus_generic_detach(dev);
1224 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1226 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1230 /* Unload and free the RX DMA ring memory and map */
1232 if (sc->re_ldata.re_rx_list_tag) {
1233 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1234 sc->re_ldata.re_rx_list_map);
1235 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1236 sc->re_ldata.re_rx_list,
1237 sc->re_ldata.re_rx_list_map);
1238 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1241 /* Unload and free the TX DMA ring memory and map */
1243 if (sc->re_ldata.re_tx_list_tag) {
1244 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1245 sc->re_ldata.re_tx_list_map);
1246 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1247 sc->re_ldata.re_tx_list,
1248 sc->re_ldata.re_tx_list_map);
1249 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1252 /* Destroy all the RX and TX buffer maps */
1254 if (sc->re_ldata.re_mtag) {
1255 for (i = 0; i < RE_TX_DESC_CNT; i++)
1256 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1257 sc->re_ldata.re_tx_dmamap[i]);
1258 for (i = 0; i < RE_RX_DESC_CNT; i++)
1259 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1260 sc->re_ldata.re_rx_dmamap[i]);
1261 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1264 /* Unload and free the stats buffer and map */
1266 if (sc->re_ldata.re_stag) {
1267 bus_dmamap_unload(sc->re_ldata.re_stag,
1268 sc->re_ldata.re_rx_list_map);
1269 bus_dmamem_free(sc->re_ldata.re_stag,
1270 sc->re_ldata.re_stats,
1271 sc->re_ldata.re_smap);
1272 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1275 if (sc->re_parent_tag)
1276 bus_dma_tag_destroy(sc->re_parent_tag);
1282 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1284 struct re_dmaload_arg arg;
1285 struct mbuf *n = NULL;
1289 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1294 m->m_data = m->m_ext.ext_buf;
1297 * Initialize mbuf length fields and fixup
1298 * alignment so that the frame payload is
1301 m->m_len = m->m_pkthdr.len = MCLBYTES;
1302 m_adj(m, ETHER_ALIGN);
1308 arg.re_ring = sc->re_ldata.re_rx_list;
1310 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1311 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1312 &arg, BUS_DMA_NOWAIT);
1313 if (error || arg.re_maxsegs != 1) {
1319 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1320 sc->re_ldata.re_rx_mbuf[idx] = m;
1322 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1323 BUS_DMASYNC_PREREAD);
1329 re_tx_list_init(struct re_softc *sc)
1331 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1332 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1334 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1335 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1336 sc->re_ldata.re_tx_prodidx = 0;
1337 sc->re_ldata.re_tx_considx = 0;
1338 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1344 re_rx_list_init(struct re_softc *sc)
1348 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1349 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1351 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1352 error = re_newbuf(sc, i, NULL);
1357 /* Flush the RX descriptors */
1359 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1360 sc->re_ldata.re_rx_list_map,
1361 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1363 sc->re_ldata.re_rx_prodidx = 0;
1364 sc->re_head = sc->re_tail = NULL;
1370 * RX handler for C+ and 8169. For the gigE chips, we support
1371 * the reception of jumbo frames that have been fragmented
1372 * across multiple 2K mbuf cluster buffers.
1375 re_rxeof(struct re_softc *sc)
1377 struct ifnet *ifp = &sc->arpcom.ac_if;
1379 struct re_desc *cur_rx;
1380 uint32_t rxstat, rxvlan;
1383 /* Invalidate the descriptor memory */
1385 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1386 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1388 for (i = sc->re_ldata.re_rx_prodidx;
1389 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1390 cur_rx = &sc->re_ldata.re_rx_list[i];
1391 m = sc->re_ldata.re_rx_mbuf[i];
1392 total_len = RE_RXBYTES(cur_rx);
1393 rxstat = le32toh(cur_rx->re_cmdstat);
1394 rxvlan = le32toh(cur_rx->re_vlanctl);
1396 /* Invalidate the RX mbuf and unload its map */
1398 bus_dmamap_sync(sc->re_ldata.re_mtag,
1399 sc->re_ldata.re_rx_dmamap[i],
1400 BUS_DMASYNC_POSTWRITE);
1401 bus_dmamap_unload(sc->re_ldata.re_mtag,
1402 sc->re_ldata.re_rx_dmamap[i]);
1404 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1405 m->m_len = MCLBYTES - ETHER_ALIGN;
1406 if (sc->re_head == NULL) {
1407 sc->re_head = sc->re_tail = m;
1409 sc->re_tail->m_next = m;
1412 re_newbuf(sc, i, NULL);
1417 * NOTE: for the 8139C+, the frame length field
1418 * is always 12 bits in size, but for the gigE chips,
1419 * it is 13 bits (since the max RX frame length is 16K).
1420 * Unfortunately, all 32 bits in the status word
1421 * were already used, so to make room for the extra
1422 * length bit, RealTek took out the 'frame alignment
1423 * error' bit and shifted the other status bits
1424 * over one slot. The OWN, EOR, FS and LS bits are
1425 * still in the same places. We have already extracted
1426 * the frame length and checked the OWN bit, so rather
1427 * than using an alternate bit mapping, we shift the
1428 * status bits one space to the right so we can evaluate
1429 * them using the 8169 status as though it was in the
1430 * same format as that of the 8139C+.
1432 if (sc->re_type == RE_8169)
1435 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1438 * If this is part of a multi-fragment packet,
1439 * discard all the pieces.
1441 if (sc->re_head != NULL) {
1442 m_freem(sc->re_head);
1443 sc->re_head = sc->re_tail = NULL;
1445 re_newbuf(sc, i, m);
1450 * If allocating a replacement mbuf fails,
1451 * reload the current one.
1454 if (re_newbuf(sc, i, NULL)) {
1456 if (sc->re_head != NULL) {
1457 m_freem(sc->re_head);
1458 sc->re_head = sc->re_tail = NULL;
1460 re_newbuf(sc, i, m);
1464 if (sc->re_head != NULL) {
1465 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1467 * Special case: if there's 4 bytes or less
1468 * in this buffer, the mbuf can be discarded:
1469 * the last 4 bytes is the CRC, which we don't
1470 * care about anyway.
1472 if (m->m_len <= ETHER_CRC_LEN) {
1473 sc->re_tail->m_len -=
1474 (ETHER_CRC_LEN - m->m_len);
1477 m->m_len -= ETHER_CRC_LEN;
1478 sc->re_tail->m_next = m;
1481 sc->re_head = sc->re_tail = NULL;
1482 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1484 m->m_pkthdr.len = m->m_len =
1485 (total_len - ETHER_CRC_LEN);
1488 m->m_pkthdr.rcvif = ifp;
1490 /* Do RX checksumming if enabled */
1492 if (ifp->if_capenable & IFCAP_RXCSUM) {
1494 /* Check IP header checksum */
1495 if (rxstat & RE_RDESC_STAT_PROTOID)
1496 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1497 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1498 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1500 /* Check TCP/UDP checksum */
1501 if ((RE_TCPPKT(rxstat) &&
1502 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1503 (RE_UDPPKT(rxstat) &&
1504 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1505 m->m_pkthdr.csum_flags |=
1506 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1507 m->m_pkthdr.csum_data = 0xffff;
1511 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1513 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1515 ifp->if_input(ifp, m);
1519 /* Flush the RX DMA ring */
1521 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1522 sc->re_ldata.re_rx_list_map,
1523 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1525 sc->re_ldata.re_rx_prodidx = i;
1529 re_txeof(struct re_softc *sc)
1531 struct ifnet *ifp = &sc->arpcom.ac_if;
1535 /* Invalidate the TX descriptor list */
1537 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1538 sc->re_ldata.re_tx_list_map,
1539 BUS_DMASYNC_POSTREAD);
1541 for (idx = sc->re_ldata.re_tx_considx;
1542 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) {
1543 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1544 if (txstat & RE_TDESC_CMD_OWN)
1548 * We only stash mbufs in the last descriptor
1549 * in a fragment chain, which also happens to
1550 * be the only place where the TX status bits
1553 if (txstat & RE_TDESC_CMD_EOF) {
1554 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1555 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1556 bus_dmamap_unload(sc->re_ldata.re_mtag,
1557 sc->re_ldata.re_tx_dmamap[idx]);
1558 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1559 RE_TDESC_STAT_COLCNT))
1560 ifp->if_collisions++;
1561 if (txstat & RE_TDESC_STAT_TXERRSUM)
1566 sc->re_ldata.re_tx_free++;
1569 /* No changes made to the TX ring, so no flush needed */
1570 if (idx != sc->re_ldata.re_tx_considx) {
1571 sc->re_ldata.re_tx_considx = idx;
1572 ifp->if_flags &= ~IFF_OACTIVE;
1577 * If not all descriptors have been released reaped yet,
1578 * reload the timer so that we will eventually get another
1579 * interrupt that will cause us to re-enter this routine.
1580 * This is done in case the transmitter has gone idle.
1582 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
1583 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1589 struct re_softc *sc = xsc;
1591 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1592 re_tick_serialized(xsc);
1593 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1597 re_tick_serialized(void *xsc)
1599 struct re_softc *sc = xsc;
1600 struct mii_data *mii;
1602 mii = device_get_softc(sc->re_miibus);
1605 callout_reset(&sc->re_timer, hz, re_tick, sc);
1608 #ifdef DEVICE_POLLING
1611 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1613 struct re_softc *sc = ifp->if_softc;
1617 /* disable interrupts */
1618 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1620 case POLL_DEREGISTER:
1621 /* enable interrupts */
1622 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1625 sc->rxcycles = count;
1629 if (!ifq_is_empty(&ifp->if_snd))
1630 (*ifp->if_start)(ifp);
1632 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1635 status = CSR_READ_2(sc, RE_ISR);
1636 if (status == 0xffff)
1639 CSR_WRITE_2(sc, RE_ISR, status);
1642 * XXX check behaviour on receiver stalls.
1645 if (status & RE_ISR_SYSTEM_ERR) {
1653 #endif /* DEVICE_POLLING */
1658 struct re_softc *sc = arg;
1659 struct ifnet *ifp = &sc->arpcom.ac_if;
1662 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1666 status = CSR_READ_2(sc, RE_ISR);
1667 /* If the card has gone away the read returns 0xffff. */
1668 if (status == 0xffff)
1671 CSR_WRITE_2(sc, RE_ISR, status);
1673 if ((status & RE_INTRS_CPLUS) == 0)
1676 if (status & RE_ISR_RX_OK)
1679 if (status & RE_ISR_RX_ERR)
1682 if ((status & RE_ISR_TIMEOUT_EXPIRED) ||
1683 (status & RE_ISR_TX_ERR) ||
1684 (status & RE_ISR_TX_DESC_UNAVAIL))
1687 if (status & RE_ISR_SYSTEM_ERR) {
1692 if (status & RE_ISR_LINKCHG)
1693 re_tick_serialized(sc);
1696 if (!ifq_is_empty(&ifp->if_snd))
1697 (*ifp->if_start)(ifp);
1701 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1703 struct ifnet *ifp = &sc->arpcom.ac_if;
1704 struct mbuf *m, *m_new = NULL;
1705 struct re_dmaload_arg arg;
1710 if (sc->re_ldata.re_tx_free <= 4)
1716 * Set up checksum offload. Note: checksum offload bits must
1717 * appear in all descriptors of a multi-descriptor transmit
1718 * attempt. (This is according to testing done with an 8169
1719 * chip. I'm not sure if this is a requirement or a bug.)
1724 if (m->m_pkthdr.csum_flags & CSUM_IP)
1725 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1726 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1727 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1728 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1729 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1733 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1734 if (arg.re_maxsegs > 4)
1735 arg.re_maxsegs -= 4;
1736 arg.re_ring = sc->re_ldata.re_tx_list;
1738 map = sc->re_ldata.re_tx_dmamap[*idx];
1739 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1740 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1742 if (error && error != EFBIG) {
1743 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1747 /* Too many segments to map, coalesce into a single mbuf */
1749 if (error || arg.re_maxsegs == 0) {
1750 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1761 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1762 arg.re_ring = sc->re_ldata.re_tx_list;
1764 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1765 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1768 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1774 * Insure that the map for this transmission
1775 * is placed at the array index of the last descriptor
1778 sc->re_ldata.re_tx_dmamap[*idx] =
1779 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1780 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1782 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1783 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1786 * Set up hardware VLAN tagging. Note: vlan tag info must
1787 * appear in the first descriptor of a multi-descriptor
1788 * transmission attempt.
1791 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1792 m->m_pkthdr.rcvif != NULL &&
1793 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1795 ifv = m->m_pkthdr.rcvif->if_softc;
1797 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1798 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1801 /* Transfer ownership of packet to the chip. */
1803 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1804 htole32(RE_TDESC_CMD_OWN);
1805 if (*idx != arg.re_idx)
1806 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1807 htole32(RE_TDESC_CMD_OWN);
1809 RE_DESC_INC(arg.re_idx);
1816 * Main transmit routine for C+ and gigE NICs.
1820 re_start(struct ifnet *ifp)
1822 struct re_softc *sc = ifp->if_softc;
1823 struct mbuf *m_head;
1824 struct mbuf *m_head2;
1825 int called_defrag, idx, need_trans;
1827 idx = sc->re_ldata.re_tx_prodidx;
1830 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1831 m_head = ifq_poll(&ifp->if_snd);
1835 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
1837 * If we could not encapsulate the defragged packet,
1838 * the returned m_head2 is garbage and we must dequeue
1839 * and throw away the original packet.
1841 if (called_defrag) {
1842 ifq_dequeue(&ifp->if_snd, m_head);
1845 ifp->if_flags |= IFF_OACTIVE;
1850 * Clean out the packet we encapsulated. If we defragged
1851 * the packet the m_head2 is the one that got encapsulated
1852 * and the original must be thrown away. Otherwise m_head2
1853 * *IS* the original.
1855 ifq_dequeue(&ifp->if_snd, m_head);
1861 * If there's a BPF listener, bounce a copy of this frame
1864 BPF_MTAP(ifp, m_head2);
1871 /* Flush the TX descriptors */
1872 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1873 sc->re_ldata.re_tx_list_map,
1874 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1876 sc->re_ldata.re_tx_prodidx = idx;
1879 * RealTek put the TX poll request register in a different
1880 * location on the 8169 gigE chip. I don't know why.
1882 if (sc->re_type == RE_8169)
1883 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START);
1885 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START);
1888 * Use the countdown timer for interrupt moderation.
1889 * 'TX done' interrupts are disabled. Instead, we reset the
1890 * countdown timer, which will begin counting until it hits
1891 * the value in the TIMERINT register, and then trigger an
1892 * interrupt. Each time we write to the TIMERCNT register,
1893 * the timer count is reset to 0.
1895 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1898 * Set a timeout in case the chip goes out to lunch.
1906 struct re_softc *sc = xsc;
1907 struct ifnet *ifp = &sc->arpcom.ac_if;
1908 struct mii_data *mii;
1911 mii = device_get_softc(sc->re_miibus);
1914 * Cancel pending I/O and free all RX/TX buffers.
1919 * Enable C+ RX and TX mode, as well as VLAN stripping and
1920 * RX checksum offload. We must configure the C+ register
1921 * before all others.
1923 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
1924 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
1925 (ifp->if_capenable & IFCAP_RXCSUM ?
1926 RE_CPLUSCMD_RXCSUM_ENB : 0));
1929 * Init our MAC address. Even though the chipset
1930 * documentation doesn't mention it, we need to enter "Config
1931 * register write enable" mode to modify the ID registers.
1933 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
1934 CSR_WRITE_STREAM_4(sc, RE_IDR0,
1935 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1936 CSR_WRITE_STREAM_4(sc, RE_IDR4,
1937 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1938 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
1941 * For C+ mode, initialize the RX descriptors and mbufs.
1943 re_rx_list_init(sc);
1944 re_tx_list_init(sc);
1947 * Enable transmit and receive.
1949 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1952 * Set the initial TX and RX configuration.
1954 if (sc->re_testmode) {
1955 if (sc->re_type == RE_8169)
1956 CSR_WRITE_4(sc, RE_TXCFG,
1957 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
1959 CSR_WRITE_4(sc, RE_TXCFG,
1960 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
1962 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
1963 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
1965 /* Set the individual bit to receive frames for this host only. */
1966 rxcfg = CSR_READ_4(sc, RE_RXCFG);
1967 rxcfg |= RE_RXCFG_RX_INDIV;
1969 /* If we want promiscuous mode, set the allframes bit. */
1970 if (ifp->if_flags & IFF_PROMISC) {
1971 rxcfg |= RE_RXCFG_RX_ALLPHYS;
1972 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1974 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
1975 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1979 * Set capture broadcast bit to capture broadcast frames.
1981 if (ifp->if_flags & IFF_BROADCAST) {
1982 rxcfg |= RE_RXCFG_RX_BROAD;
1983 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1985 rxcfg &= ~RE_RXCFG_RX_BROAD;
1986 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1990 * Program the multicast filter, if necessary.
1994 #ifdef DEVICE_POLLING
1996 * Disable interrupts if we are polling.
1998 if (ifp->if_flags & IFF_POLLING)
1999 CSR_WRITE_2(sc, RE_IMR, 0);
2000 else /* otherwise ... */
2001 #endif /* DEVICE_POLLING */
2003 * Enable interrupts.
2005 if (sc->re_testmode)
2006 CSR_WRITE_2(sc, RE_IMR, 0);
2008 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
2010 /* Set initial TX threshold */
2011 sc->re_txthresh = RE_TX_THRESH_INIT;
2013 /* Start RX/TX process. */
2014 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2016 /* Enable receiver and transmitter. */
2017 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2020 * Load the addresses of the RX and TX lists into the chip.
2023 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2024 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2025 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2026 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2028 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2029 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2030 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2031 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2033 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2036 * Initialize the timer interrupt register so that
2037 * a timer interrupt will be generated once the timer
2038 * reaches a certain number of ticks. The timer is
2039 * reloaded on each transmit. This gives us TX interrupt
2040 * moderation, which dramatically improves TX frame rate.
2043 if (sc->re_type == RE_8169)
2044 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2046 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2049 * For 8169 gigE NICs, set the max allowed RX packet
2050 * size so we can receive jumbo frames.
2052 if (sc->re_type == RE_8169)
2053 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2055 if (sc->re_testmode) {
2061 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2063 ifp->if_flags |= IFF_RUNNING;
2064 ifp->if_flags &= ~IFF_OACTIVE;
2066 callout_reset(&sc->re_timer, hz, re_tick, sc);
2070 * Set media options.
2073 re_ifmedia_upd(struct ifnet *ifp)
2075 struct re_softc *sc = ifp->if_softc;
2076 struct mii_data *mii;
2078 mii = device_get_softc(sc->re_miibus);
2085 * Report current media status.
2088 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2090 struct re_softc *sc = ifp->if_softc;
2091 struct mii_data *mii;
2093 mii = device_get_softc(sc->re_miibus);
2096 ifmr->ifm_active = mii->mii_media_active;
2097 ifmr->ifm_status = mii->mii_media_status;
2101 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2103 struct re_softc *sc = ifp->if_softc;
2104 struct ifreq *ifr = (struct ifreq *) data;
2105 struct mii_data *mii;
2110 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2112 ifp->if_mtu = ifr->ifr_mtu;
2115 if (ifp->if_flags & IFF_UP)
2117 else if (ifp->if_flags & IFF_RUNNING)
2128 mii = device_get_softc(sc->re_miibus);
2129 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2132 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2133 ifp->if_capenable |=
2134 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2135 if (ifp->if_capenable & IFCAP_TXCSUM)
2136 ifp->if_hwassist = RE_CSUM_FEATURES;
2138 ifp->if_hwassist = 0;
2139 if (ifp->if_flags & IFF_RUNNING)
2143 error = ether_ioctl(ifp, command, data);
2150 re_watchdog(struct ifnet *ifp)
2152 struct re_softc *sc = ifp->if_softc;
2154 if_printf(ifp, "watchdog timeout\n");
2163 if (!ifq_is_empty(&ifp->if_snd))
2168 * Stop the adapter and free any mbufs allocated to the
2172 re_stop(struct re_softc *sc)
2174 struct ifnet *ifp = &sc->arpcom.ac_if;
2178 callout_stop(&sc->re_timer);
2180 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2182 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2183 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2185 if (sc->re_head != NULL) {
2186 m_freem(sc->re_head);
2187 sc->re_head = sc->re_tail = NULL;
2190 /* Free the TX list buffers. */
2191 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2192 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2193 bus_dmamap_unload(sc->re_ldata.re_mtag,
2194 sc->re_ldata.re_tx_dmamap[i]);
2195 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2196 sc->re_ldata.re_tx_mbuf[i] = NULL;
2200 /* Free the RX list buffers. */
2201 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2202 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2203 bus_dmamap_unload(sc->re_ldata.re_mtag,
2204 sc->re_ldata.re_rx_dmamap[i]);
2205 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2206 sc->re_ldata.re_rx_mbuf[i] = NULL;
2212 * Device suspend routine. Stop the interface and save some PCI
2213 * settings in case the BIOS doesn't restore them properly on
2217 re_suspend(device_t dev)
2219 #ifndef BURN_BRIDGES
2222 struct re_softc *sc = device_get_softc(dev);
2226 #ifndef BURN_BRIDGES
2227 for (i = 0; i < 5; i++)
2228 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2229 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2230 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2231 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2232 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2241 * Device resume routine. Restore some PCI settings in case the BIOS
2242 * doesn't, re-enable busmastering, and restart the interface if
2246 re_resume(device_t dev)
2248 struct re_softc *sc = device_get_softc(dev);
2249 struct ifnet *ifp = &sc->arpcom.ac_if;
2250 #ifndef BURN_BRIDGES
2254 #ifndef BURN_BRIDGES
2255 /* better way to do this? */
2256 for (i = 0; i < 5; i++)
2257 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2258 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2259 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2260 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2261 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2263 /* reenable busmastering */
2264 pci_enable_busmaster(dev);
2265 pci_enable_io(dev, SYS_RES_IOPORT);
2268 /* reinitialize interface if necessary */
2269 if (ifp->if_flags & IFF_UP)
2278 * Stop all chip I/O so that the kernel's probe routines don't
2279 * get confused by errant DMAs when rebooting.
2282 re_shutdown(device_t dev)
2284 struct re_softc *sc = device_get_softc(dev);