sys/dev/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/atombios_crtc.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <uapi_drm/radeon_drm.h>
  32 #include <drm/drm_fixed.h>
  33 #include "radeon.h"
  34 #include "atom.h"
  35 #include "atom-bits.h"
  36
  37 static void atombios_overscan_setup(struct drm_crtc *crtc,
  38                                     struct drm_display_mode *mode,
  39                                     struct drm_display_mode *adjusted_mode)
  40 {
  41         struct drm_device *dev = crtc->dev;
  42         struct radeon_device *rdev = dev->dev_private;
  43         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  44         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  45         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  46         int a1, a2;
  47
  48         memset(&args, 0, sizeof(args));
  49
  50         args.ucCRTC = radeon_crtc->crtc_id;
  51
  52         switch (radeon_crtc->rmx_type) {
  53         case RMX_CENTER:
  54                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  55                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  56                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  57                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  58                 break;
  59         case RMX_ASPECT:
  60                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  61                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  62
  63                 if (a1 > a2) {
  64                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  65                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  66                 } else if (a2 > a1) {
  67                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  68                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  69                 }
  70                 break;
  71         case RMX_FULL:
  72         default:
  73                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
  74                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
  75                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
  76                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
  77                 break;
  78         }
  79         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  80 }
  81
  82 static void atombios_scaler_setup(struct drm_crtc *crtc)
  83 {
  84         struct drm_device *dev = crtc->dev;
  85         struct radeon_device *rdev = dev->dev_private;
  86         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  87         ENABLE_SCALER_PS_ALLOCATION args;
  88         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  89         struct radeon_encoder *radeon_encoder =
  90                 to_radeon_encoder(radeon_crtc->encoder);
  91         /* fixme - fill in enc_priv for atom dac */
  92         enum radeon_tv_std tv_std = TV_STD_NTSC;
  93         bool is_tv = false, is_cv = false;
  94
  95         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  96                 return;
  97
  98         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
  99                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 100                 tv_std = tv_dac->tv_std;
 101                 is_tv = true;
 102         }
 103
 104         memset(&args, 0, sizeof(args));
 105
 106         args.ucScaler = radeon_crtc->crtc_id;
 107
 108         if (is_tv) {
 109                 switch (tv_std) {
 110                 case TV_STD_NTSC:
 111                 default:
 112                         args.ucTVStandard = ATOM_TV_NTSC;
 113                         break;
 114                 case TV_STD_PAL:
 115                         args.ucTVStandard = ATOM_TV_PAL;
 116                         break;
 117                 case TV_STD_PAL_M:
 118                         args.ucTVStandard = ATOM_TV_PALM;
 119                         break;
 120                 case TV_STD_PAL_60:
 121                         args.ucTVStandard = ATOM_TV_PAL60;
 122                         break;
 123                 case TV_STD_NTSC_J:
 124                         args.ucTVStandard = ATOM_TV_NTSCJ;
 125                         break;
 126                 case TV_STD_SCART_PAL:
 127                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 128                         break;
 129                 case TV_STD_SECAM:
 130                         args.ucTVStandard = ATOM_TV_SECAM;
 131                         break;
 132                 case TV_STD_PAL_CN:
 133                         args.ucTVStandard = ATOM_TV_PALCN;
 134                         break;
 135                 }
 136                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 137         } else if (is_cv) {
 138                 args.ucTVStandard = ATOM_TV_CV;
 139                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 140         } else {
 141                 switch (radeon_crtc->rmx_type) {
 142                 case RMX_FULL:
 143                         args.ucEnable = ATOM_SCALER_EXPANSION;
 144                         break;
 145                 case RMX_CENTER:
 146                         args.ucEnable = ATOM_SCALER_CENTER;
 147                         break;
 148                 case RMX_ASPECT:
 149                         args.ucEnable = ATOM_SCALER_EXPANSION;
 150                         break;
 151                 default:
 152                         if (ASIC_IS_AVIVO(rdev))
 153                                 args.ucEnable = ATOM_SCALER_DISABLE;
 154                         else
 155                                 args.ucEnable = ATOM_SCALER_CENTER;
 156                         break;
 157                 }
 158         }
 159         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 160         if ((is_tv || is_cv)
 161             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 162                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 163         }
 164 }
 165
 166 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 167 {
 168         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 169         struct drm_device *dev = crtc->dev;
 170         struct radeon_device *rdev = dev->dev_private;
 171         int index =
 172             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 173         ENABLE_CRTC_PS_ALLOCATION args;
 174
 175         memset(&args, 0, sizeof(args));
 176
 177         args.ucCRTC = radeon_crtc->crtc_id;
 178         args.ucEnable = lock;
 179
 180         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 181 }
 182
 183 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 184 {
 185         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 186         struct drm_device *dev = crtc->dev;
 187         struct radeon_device *rdev = dev->dev_private;
 188         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 189         ENABLE_CRTC_PS_ALLOCATION args;
 190
 191         memset(&args, 0, sizeof(args));
 192
 193         args.ucCRTC = radeon_crtc->crtc_id;
 194         args.ucEnable = state;
 195
 196         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 197 }
 198
 199 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 200 {
 201         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 202         struct drm_device *dev = crtc->dev;
 203         struct radeon_device *rdev = dev->dev_private;
 204         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 205         ENABLE_CRTC_PS_ALLOCATION args;
 206
 207         memset(&args, 0, sizeof(args));
 208
 209         args.ucCRTC = radeon_crtc->crtc_id;
 210         args.ucEnable = state;
 211
 212         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 213 }
 214
 215 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 216 {
 217         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 218         struct drm_device *dev = crtc->dev;
 219         struct radeon_device *rdev = dev->dev_private;
 220         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 221         BLANK_CRTC_PS_ALLOCATION args;
 222
 223         memset(&args, 0, sizeof(args));
 224
 225         args.ucCRTC = radeon_crtc->crtc_id;
 226         args.ucBlanking = state;
 227
 228         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 229 }
 230
 231 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 232 {
 233         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 234         struct drm_device *dev = crtc->dev;
 235         struct radeon_device *rdev = dev->dev_private;
 236         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 237         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 238
 239         memset(&args, 0, sizeof(args));
 240
 241         args.ucDispPipeId = radeon_crtc->crtc_id;
 242         args.ucEnable = state;
 243
 244         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 245 }
 246
 247 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 248 {
 249         struct drm_device *dev = crtc->dev;
 250         struct radeon_device *rdev = dev->dev_private;
 251         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 252
 253         switch (mode) {
 254         case DRM_MODE_DPMS_ON:
 255                 radeon_crtc->enabled = true;
 256                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 257                 radeon_pm_compute_clocks(rdev);
 258                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 259                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 260                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 261                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 262                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 263                 radeon_crtc_load_lut(crtc);
 264                 break;
 265         case DRM_MODE_DPMS_STANDBY:
 266         case DRM_MODE_DPMS_SUSPEND:
 267         case DRM_MODE_DPMS_OFF:
 268                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 269                 if (radeon_crtc->enabled)
 270                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 271                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 272                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 273                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 274                 radeon_crtc->enabled = false;
 275                 /* adjust pm to dpms changes AFTER disabling crtcs */
 276                 radeon_pm_compute_clocks(rdev);
 277                 break;
 278         }
 279 }
 280
 281 static void
 282 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 283                              struct drm_display_mode *mode)
 284 {
 285         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 286         struct drm_device *dev = crtc->dev;
 287         struct radeon_device *rdev = dev->dev_private;
 288         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 289         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 290         u16 misc = 0;
 291
 292         memset(&args, 0, sizeof(args));
 293         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 294         args.usH_Blanking_Time =
 295                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 296         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 297         args.usV_Blanking_Time =
 298                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 299         args.usH_SyncOffset =
 300                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 301         args.usH_SyncWidth =
 302                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 303         args.usV_SyncOffset =
 304                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 305         args.usV_SyncWidth =
 306                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 307         args.ucH_Border = radeon_crtc->h_border;
 308         args.ucV_Border = radeon_crtc->v_border;
 309
 310         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 311                 misc |= ATOM_VSYNC_POLARITY;
 312         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 313                 misc |= ATOM_HSYNC_POLARITY;
 314         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 315                 misc |= ATOM_COMPOSITESYNC;
 316         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 317                 misc |= ATOM_INTERLACE;
 318         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 319                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 320
 321         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 322         args.ucCRTC = radeon_crtc->crtc_id;
 323
 324         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 325 }
 326
 327 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 328                                      struct drm_display_mode *mode)
 329 {
 330         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 331         struct drm_device *dev = crtc->dev;
 332         struct radeon_device *rdev = dev->dev_private;
 333         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 334         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 335         u16 misc = 0;
 336
 337         memset(&args, 0, sizeof(args));
 338         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 339         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 340         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 341         args.usH_SyncWidth =
 342                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 343         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 344         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 345         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 346         args.usV_SyncWidth =
 347                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 348
 349         args.ucOverscanRight = radeon_crtc->h_border;
 350         args.ucOverscanLeft = radeon_crtc->h_border;
 351         args.ucOverscanBottom = radeon_crtc->v_border;
 352         args.ucOverscanTop = radeon_crtc->v_border;
 353
 354         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 355                 misc |= ATOM_VSYNC_POLARITY;
 356         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 357                 misc |= ATOM_HSYNC_POLARITY;
 358         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 359                 misc |= ATOM_COMPOSITESYNC;
 360         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 361                 misc |= ATOM_INTERLACE;
 362         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 363                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 364
 365         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 366         args.ucCRTC = radeon_crtc->crtc_id;
 367
 368         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 369 }
 370
 371 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 372 {
 373         u32 ss_cntl;
 374
 375         if (ASIC_IS_DCE4(rdev)) {
 376                 switch (pll_id) {
 377                 case ATOM_PPLL1:
 378                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 379                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 380                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 381                         break;
 382                 case ATOM_PPLL2:
 383                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 384                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 385                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 386                         break;
 387                 case ATOM_DCPLL:
 388                 case ATOM_PPLL_INVALID:
 389                         return;
 390                 }
 391         } else if (ASIC_IS_AVIVO(rdev)) {
 392                 switch (pll_id) {
 393                 case ATOM_PPLL1:
 394                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 395                         ss_cntl &= ~1;
 396                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 397                         break;
 398                 case ATOM_PPLL2:
 399                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 400                         ss_cntl &= ~1;
 401                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 402                         break;
 403                 case ATOM_DCPLL:
 404                 case ATOM_PPLL_INVALID:
 405                         return;
 406                 }
 407         }
 408 }
 409
 410
 411 union atom_enable_ss {
 412         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 413         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 414         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 415         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 416         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 417 };
 418
 419 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 420                                      int enable,
 421                                      int pll_id,
 422                                      int crtc_id,
 423                                      struct radeon_atom_ss *ss)
 424 {
 425         unsigned i;
 426         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 427         union atom_enable_ss args;
 428
 429         if (!enable) {
 430                 for (i = 0; i < rdev->num_crtc; i++) {
 431                         if (rdev->mode_info.crtcs[i] &&
 432                             rdev->mode_info.crtcs[i]->enabled &&
 433                             i != crtc_id &&
 434                             pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 435                                 /* one other crtc is using this pll don't turn
 436                                  * off spread spectrum as it might turn off
 437                                  * display on active crtc
 438                                  */
 439                                 return;
 440                         }
 441                 }
 442         }
 443
 444         memset(&args, 0, sizeof(args));
 445
 446         if (ASIC_IS_DCE5(rdev)) {
 447                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 448                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 449                 switch (pll_id) {
 450                 case ATOM_PPLL1:
 451                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 452                         break;
 453                 case ATOM_PPLL2:
 454                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 455                         break;
 456                 case ATOM_DCPLL:
 457                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 458                         break;
 459                 case ATOM_PPLL_INVALID:
 460                         return;
 461                 }
 462                 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 463                 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 464                 args.v3.ucEnable = enable;
 465                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
 466                         args.v3.ucEnable = ATOM_DISABLE;
 467         } else if (ASIC_IS_DCE4(rdev)) {
 468                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 469                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 470                 switch (pll_id) {
 471                 case ATOM_PPLL1:
 472                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 473                         break;
 474                 case ATOM_PPLL2:
 475                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 476                         break;
 477                 case ATOM_DCPLL:
 478                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 479                         break;
 480                 case ATOM_PPLL_INVALID:
 481                         return;
 482                 }
 483                 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 484                 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 485                 args.v2.ucEnable = enable;
 486                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
 487                         args.v2.ucEnable = ATOM_DISABLE;
 488         } else if (ASIC_IS_DCE3(rdev)) {
 489                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 490                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 491                 args.v1.ucSpreadSpectrumStep = ss->step;
 492                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 493                 args.v1.ucSpreadSpectrumRange = ss->range;
 494                 args.v1.ucPpll = pll_id;
 495                 args.v1.ucEnable = enable;
 496         } else if (ASIC_IS_AVIVO(rdev)) {
 497                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 498                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 499                         atombios_disable_ss(rdev, pll_id);
 500                         return;
 501                 }
 502                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 503                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 504                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 505                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 506                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 507                 args.lvds_ss_2.ucEnable = enable;
 508         } else {
 509                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 510                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 511                         atombios_disable_ss(rdev, pll_id);
 512                         return;
 513                 }
 514                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 515                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 516                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 517                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 518                 args.lvds_ss.ucEnable = enable;
 519         }
 520         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 521 }
 522
 523 union adjust_pixel_clock {
 524         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 525         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 526 };
 527
 528 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 529                                struct drm_display_mode *mode)
 530 {
 531         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 532         struct drm_device *dev = crtc->dev;
 533         struct radeon_device *rdev = dev->dev_private;
 534         struct drm_encoder *encoder = radeon_crtc->encoder;
 535         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 536         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 537         u32 adjusted_clock = mode->clock;
 538         int encoder_mode = atombios_get_encoder_mode(encoder);
 539         u32 dp_clock = mode->clock;
 540         int bpc = radeon_get_monitor_bpc(connector);
 541         bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 542
 543         /* reset the pll flags */
 544         radeon_crtc->pll_flags = 0;
 545
 546         if (ASIC_IS_AVIVO(rdev)) {
 547                 if ((rdev->family == CHIP_RS600) ||
 548                     (rdev->family == CHIP_RS690) ||
 549                     (rdev->family == CHIP_RS740))
 550                         radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 551                                 RADEON_PLL_PREFER_CLOSEST_LOWER);
 552
 553                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 554                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 555                 else
 556                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 557
 558                 if (rdev->family < CHIP_RV770)
 559                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 560                 /* use frac fb div on APUs */
 561                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
 562                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 563                 /* use frac fb div on RS780/RS880 */
 564                 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 565                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 566                 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
 567                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 568         } else {
 569                 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
 570
 571                 if (mode->clock > 200000)       /* range limits??? */
 572                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 573                 else
 574                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 575         }
 576
 577         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 578             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 579                 if (connector) {
 580                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 581                         struct radeon_connector_atom_dig *dig_connector =
 582                                 radeon_connector->con_priv;
 583
 584                         dp_clock = dig_connector->dp_clock;
 585                 }
 586         }
 587
 588         /* use recommended ref_div for ss */
 589         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 590                 if (radeon_crtc->ss_enabled) {
 591                         if (radeon_crtc->ss.refdiv) {
 592                                 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 593                                 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
 594                                 if (ASIC_IS_AVIVO(rdev))
 595                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 596                         }
 597                 }
 598         }
 599
 600         if (ASIC_IS_AVIVO(rdev)) {
 601                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 602                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 603                         adjusted_clock = mode->clock * 2;
 604                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 605                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 606                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 607                         radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
 608         } else {
 609                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 610                         radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 611                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 612                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 613         }
 614
 615         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 616          * accordingly based on the encoder/transmitter to work around
 617          * special hw requirements.
 618          */
 619         if (ASIC_IS_DCE3(rdev)) {
 620                 union adjust_pixel_clock args;
 621                 u8 frev, crev;
 622                 int index;
 623
 624                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 625                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 626                                            &crev))
 627                         return adjusted_clock;
 628
 629                 memset(&args, 0, sizeof(args));
 630
 631                 switch (frev) {
 632                 case 1:
 633                         switch (crev) {
 634                         case 1:
 635                         case 2:
 636                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 637                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 638                                 args.v1.ucEncodeMode = encoder_mode;
 639                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 640                                         args.v1.ucConfig |=
 641                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 642
 643                                 atom_execute_table(rdev->mode_info.atom_context,
 644                                                    index, (uint32_t *)&args);
 645                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 646                                 break;
 647                         case 3:
 648                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 649                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 650                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 651                                 args.v3.sInput.ucDispPllConfig = 0;
 652                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 653                                         args.v3.sInput.ucDispPllConfig |=
 654                                                 DISPPLL_CONFIG_SS_ENABLE;
 655                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
 656                                         args.v3.sInput.ucDispPllConfig |=
 657                                                 DISPPLL_CONFIG_COHERENT_MODE;
 658                                         /* 16200 or 27000 */
 659                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 660                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 661                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 662                                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
 663                                                 /* deep color support */
 664                                                 args.v3.sInput.usPixelClock =
 665                                                         cpu_to_le16((mode->clock * bpc / 8) / 10);
 666                                         if (dig->coherent_mode)
 667                                                 args.v3.sInput.ucDispPllConfig |=
 668                                                         DISPPLL_CONFIG_COHERENT_MODE;
 669                                         if (is_duallink)
 670                                                 args.v3.sInput.ucDispPllConfig |=
 671                                                         DISPPLL_CONFIG_DUAL_LINK;
 672                                 }
 673                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 674                                     ENCODER_OBJECT_ID_NONE)
 675                                         args.v3.sInput.ucExtTransmitterID =
 676                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
 677                                 else
 678                                         args.v3.sInput.ucExtTransmitterID = 0;
 679
 680                                 atom_execute_table(rdev->mode_info.atom_context,
 681                                                    index, (uint32_t *)&args);
 682                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 683                                 if (args.v3.sOutput.ucRefDiv) {
 684                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 685                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 686                                         radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
 687                                 }
 688                                 if (args.v3.sOutput.ucPostDiv) {
 689                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 690                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
 691                                         radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
 692                                 }
 693                                 break;
 694                         default:
 695                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 696                                 return adjusted_clock;
 697                         }
 698                         break;
 699                 default:
 700                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 701                         return adjusted_clock;
 702                 }
 703         }
 704         return adjusted_clock;
 705 }
 706
 707 union set_pixel_clock {
 708         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 709         PIXEL_CLOCK_PARAMETERS v1;
 710         PIXEL_CLOCK_PARAMETERS_V2 v2;
 711         PIXEL_CLOCK_PARAMETERS_V3 v3;
 712         PIXEL_CLOCK_PARAMETERS_V5 v5;
 713         PIXEL_CLOCK_PARAMETERS_V6 v6;
 714 };
 715
 716 /* on DCE5, make sure the voltage is high enough to support the
 717  * required disp clk.
 718  */
 719 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 720                                     u32 dispclk)
 721 {
 722         u8 frev, crev;
 723         int index;
 724         union set_pixel_clock args;
 725
 726         memset(&args, 0, sizeof(args));
 727
 728         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 729         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 730                                    &crev))
 731                 return;
 732
 733         switch (frev) {
 734         case 1:
 735                 switch (crev) {
 736                 case 5:
 737                         /* if the default dcpll clock is specified,
 738                          * SetPixelClock provides the dividers
 739                          */
 740                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 741                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 742                         args.v5.ucPpll = ATOM_DCPLL;
 743                         break;
 744                 case 6:
 745                         /* if the default dcpll clock is specified,
 746                          * SetPixelClock provides the dividers
 747                          */
 748                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 749                         if (ASIC_IS_DCE61(rdev))
 750                                 args.v6.ucPpll = ATOM_EXT_PLL1;
 751                         else if (ASIC_IS_DCE6(rdev))
 752                                 args.v6.ucPpll = ATOM_PPLL0;
 753                         else
 754                                 args.v6.ucPpll = ATOM_DCPLL;
 755                         break;
 756                 default:
 757                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 758                         return;
 759                 }
 760                 break;
 761         default:
 762                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 763                 return;
 764         }
 765         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 766 }
 767
 768 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 769                                       u32 crtc_id,
 770                                       int pll_id,
 771                                       u32 encoder_mode,
 772                                       u32 encoder_id,
 773                                       u32 clock,
 774                                       u32 ref_div,
 775                                       u32 fb_div,
 776                                       u32 frac_fb_div,
 777                                       u32 post_div,
 778                                       int bpc,
 779                                       bool ss_enabled,
 780                                       struct radeon_atom_ss *ss)
 781 {
 782         struct drm_device *dev = crtc->dev;
 783         struct radeon_device *rdev = dev->dev_private;
 784         u8 frev, crev;
 785         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 786         union set_pixel_clock args;
 787
 788         memset(&args, 0, sizeof(args));
 789
 790         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 791                                    &crev))
 792                 return;
 793
 794         switch (frev) {
 795         case 1:
 796                 switch (crev) {
 797                 case 1:
 798                         if (clock == ATOM_DISABLE)
 799                                 return;
 800                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 801                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 802                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 803                         args.v1.ucFracFbDiv = frac_fb_div;
 804                         args.v1.ucPostDiv = post_div;
 805                         args.v1.ucPpll = pll_id;
 806                         args.v1.ucCRTC = crtc_id;
 807                         args.v1.ucRefDivSrc = 1;
 808                         break;
 809                 case 2:
 810                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 811                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 812                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 813                         args.v2.ucFracFbDiv = frac_fb_div;
 814                         args.v2.ucPostDiv = post_div;
 815                         args.v2.ucPpll = pll_id;
 816                         args.v2.ucCRTC = crtc_id;
 817                         args.v2.ucRefDivSrc = 1;
 818                         break;
 819                 case 3:
 820                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 821                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 822                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 823                         args.v3.ucFracFbDiv = frac_fb_div;
 824                         args.v3.ucPostDiv = post_div;
 825                         args.v3.ucPpll = pll_id;
 826                         if (crtc_id == ATOM_CRTC2)
 827                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 828                         else
 829                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 830                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 831                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 832                         args.v3.ucTransmitterId = encoder_id;
 833                         args.v3.ucEncoderMode = encoder_mode;
 834                         break;
 835                 case 5:
 836                         args.v5.ucCRTC = crtc_id;
 837                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 838                         args.v5.ucRefDiv = ref_div;
 839                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 840                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 841                         args.v5.ucPostDiv = post_div;
 842                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 843                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 844                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 845                         switch (bpc) {
 846                         case 8:
 847                         default:
 848                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 849                                 break;
 850                         case 10:
 851                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 852                                 break;
 853                         }
 854                         args.v5.ucTransmitterID = encoder_id;
 855                         args.v5.ucEncoderMode = encoder_mode;
 856                         args.v5.ucPpll = pll_id;
 857                         break;
 858                 case 6:
 859                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 860                         args.v6.ucRefDiv = ref_div;
 861                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 862                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 863                         args.v6.ucPostDiv = post_div;
 864                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 865                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 866                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 867                         switch (bpc) {
 868                         case 8:
 869                         default:
 870                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 871                                 break;
 872                         case 10:
 873                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
 874                                 break;
 875                         case 12:
 876                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
 877                                 break;
 878                         case 16:
 879                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 880                                 break;
 881                         }
 882                         args.v6.ucTransmitterID = encoder_id;
 883                         args.v6.ucEncoderMode = encoder_mode;
 884                         args.v6.ucPpll = pll_id;
 885                         break;
 886                 default:
 887                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 888                         return;
 889                 }
 890                 break;
 891         default:
 892                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 893                 return;
 894         }
 895
 896         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 897 }
 898
 899 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 900 {
 901         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 902         struct drm_device *dev = crtc->dev;
 903         struct radeon_device *rdev = dev->dev_private;
 904         struct radeon_encoder *radeon_encoder =
 905                 to_radeon_encoder(radeon_crtc->encoder);
 906         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 907
 908         radeon_crtc->bpc = 8;
 909         radeon_crtc->ss_enabled = false;
 910
 911         if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 912             (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
 913                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 914                 struct drm_connector *connector =
 915                         radeon_get_connector_for_encoder(radeon_crtc->encoder);
 916                 struct radeon_connector *radeon_connector =
 917                         to_radeon_connector(connector);
 918                 struct radeon_connector_atom_dig *dig_connector =
 919                         radeon_connector->con_priv;
 920                 int dp_clock;
 921                 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
 922
 923                 switch (encoder_mode) {
 924                 case ATOM_ENCODER_MODE_DP_MST:
 925                 case ATOM_ENCODER_MODE_DP:
 926                         /* DP/eDP */
 927                         dp_clock = dig_connector->dp_clock / 10;
 928                         if (ASIC_IS_DCE4(rdev))
 929                                 radeon_crtc->ss_enabled =
 930                                         radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 931                                                                          ASIC_INTERNAL_SS_ON_DP,
 932                                                                          dp_clock);
 933                         else {
 934                                 if (dp_clock == 16200) {
 935                                         radeon_crtc->ss_enabled =
 936                                                 radeon_atombios_get_ppll_ss_info(rdev,
 937                                                                                  &radeon_crtc->ss,
 938                                                                                  ATOM_DP_SS_ID2);
 939                                         if (!radeon_crtc->ss_enabled)
 940                                                 radeon_crtc->ss_enabled =
 941                                                         radeon_atombios_get_ppll_ss_info(rdev,
 942                                                                                          &radeon_crtc->ss,
 943                                                                                          ATOM_DP_SS_ID1);
 944                                 } else
 945                                         radeon_crtc->ss_enabled =
 946                                                 radeon_atombios_get_ppll_ss_info(rdev,
 947                                                                                  &radeon_crtc->ss,
 948                                                                                  ATOM_DP_SS_ID1);
 949                         }
 950                         break;
 951                 case ATOM_ENCODER_MODE_LVDS:
 952                         if (ASIC_IS_DCE4(rdev))
 953                                 radeon_crtc->ss_enabled =
 954                                         radeon_atombios_get_asic_ss_info(rdev,
 955                                                                          &radeon_crtc->ss,
 956                                                                          dig->lcd_ss_id,
 957                                                                          mode->clock / 10);
 958                         else
 959                                 radeon_crtc->ss_enabled =
 960                                         radeon_atombios_get_ppll_ss_info(rdev,
 961                                                                          &radeon_crtc->ss,
 962                                                                          dig->lcd_ss_id);
 963                         break;
 964                 case ATOM_ENCODER_MODE_DVI:
 965                         if (ASIC_IS_DCE4(rdev))
 966                                 radeon_crtc->ss_enabled =
 967                                         radeon_atombios_get_asic_ss_info(rdev,
 968                                                                          &radeon_crtc->ss,
 969                                                                          ASIC_INTERNAL_SS_ON_TMDS,
 970                                                                          mode->clock / 10);
 971                         break;
 972                 case ATOM_ENCODER_MODE_HDMI:
 973                         if (ASIC_IS_DCE4(rdev))
 974                                 radeon_crtc->ss_enabled =
 975                                         radeon_atombios_get_asic_ss_info(rdev,
 976                                                                          &radeon_crtc->ss,
 977                                                                          ASIC_INTERNAL_SS_ON_HDMI,
 978                                                                          mode->clock / 10);
 979                         break;
 980                 default:
 981                         break;
 982                 }
 983         }
 984
 985         /* adjust pixel clock as needed */
 986         radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
 987
 988         return true;
 989 }
 990
 991 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 992 {
 993         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 994         struct drm_device *dev = crtc->dev;
 995         struct radeon_device *rdev = dev->dev_private;
 996         struct radeon_encoder *radeon_encoder =
 997                 to_radeon_encoder(radeon_crtc->encoder);
 998         u32 pll_clock = mode->clock;
 999         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1000         struct radeon_pll *pll;
1001         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1002
1003         switch (radeon_crtc->pll_id) {
1004         case ATOM_PPLL1:
1005                 pll = &rdev->clock.p1pll;
1006                 break;
1007         case ATOM_PPLL2:
1008                 pll = &rdev->clock.p2pll;
1009                 break;
1010         case ATOM_DCPLL:
1011         case ATOM_PPLL_INVALID:
1012         default:
1013                 pll = &rdev->clock.dcpll;
1014                 break;
1015         }
1016
1017         /* update pll params */
1018         pll->flags = radeon_crtc->pll_flags;
1019         pll->reference_div = radeon_crtc->pll_reference_div;
1020         pll->post_div = radeon_crtc->pll_post_div;
1021
1022         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1023                 /* TV seems to prefer the legacy algo on some boards */
1024                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1025                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1026         else if (ASIC_IS_AVIVO(rdev))
1027                 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1028                                          &fb_div, &frac_fb_div, &ref_div, &post_div);
1029         else
1030                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1031                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1032
1033         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1034                                  radeon_crtc->crtc_id, &radeon_crtc->ss);
1035
1036         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1037                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
1038                                   ref_div, fb_div, frac_fb_div, post_div,
1039                                   radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1040
1041         if (radeon_crtc->ss_enabled) {
1042                 /* calculate ss amount and step size */
1043                 if (ASIC_IS_DCE4(rdev)) {
1044                         u32 step_size;
1045                         u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000;
1046                         radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1047                         radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1048                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1049                         if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1050                                 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1051                                         (125 * 25 * pll->reference_freq / 100);
1052                         else
1053                                 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1054                                         (125 * 25 * pll->reference_freq / 100);
1055                         radeon_crtc->ss.step = step_size;
1056                 }
1057
1058                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1059                                          radeon_crtc->crtc_id, &radeon_crtc->ss);
1060         }
1061 }
1062
1063 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1064                                  struct drm_framebuffer *fb,
1065                                  int x, int y, int atomic)
1066 {
1067         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1068         struct drm_device *dev = crtc->dev;
1069         struct radeon_device *rdev = dev->dev_private;
1070         struct radeon_framebuffer *radeon_fb;
1071         struct drm_framebuffer *target_fb;
1072         struct drm_gem_object *obj;
1073         struct radeon_bo *rbo;
1074         uint64_t fb_location;
1075         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1076         unsigned bankw, bankh, mtaspect, tile_split;
1077         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1078         u32 tmp, viewport_w, viewport_h;
1079         int r;
1080
1081         /* no fb bound */
1082         if (!atomic && !crtc->fb) {
1083                 DRM_DEBUG_KMS("No FB bound\n");
1084                 return 0;
1085         }
1086
1087         if (atomic) {
1088                 radeon_fb = to_radeon_framebuffer(fb);
1089                 target_fb = fb;
1090         }
1091         else {
1092                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1093                 target_fb = crtc->fb;
1094         }
1095
1096         /* If atomic, assume fb object is pinned & idle & fenced and
1097          * just update base pointers
1098          */
1099         obj = radeon_fb->obj;
1100         rbo = gem_to_radeon_bo(obj);
1101         r = radeon_bo_reserve(rbo, false);
1102         if (unlikely(r != 0))
1103                 return r;
1104
1105         if (atomic)
1106                 fb_location = radeon_bo_gpu_offset(rbo);
1107         else {
1108                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1109                 if (unlikely(r != 0)) {
1110                         radeon_bo_unreserve(rbo);
1111                         return -EINVAL;
1112                 }
1113         }
1114
1115         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1116         radeon_bo_unreserve(rbo);
1117
1118         switch (target_fb->bits_per_pixel) {
1119         case 8:
1120                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1121                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1122                 break;
1123         case 15:
1124                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1125                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1126                 break;
1127         case 16:
1128                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1129                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1130 #ifdef __BIG_ENDIAN
1131                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1132 #endif
1133                 break;
1134         case 24:
1135         case 32:
1136                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1137                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1138 #ifdef __BIG_ENDIAN
1139                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1140 #endif
1141                 break;
1142         default:
1143                 DRM_ERROR("Unsupported screen depth %d\n",
1144                           target_fb->bits_per_pixel);
1145                 return -EINVAL;
1146         }
1147
1148         if (tiling_flags & RADEON_TILING_MACRO) {
1149                 if (rdev->family >= CHIP_TAHITI)
1150                         tmp = rdev->config.si.tile_config;
1151                 else if (rdev->family >= CHIP_CAYMAN)
1152                         tmp = rdev->config.cayman.tile_config;
1153                 else
1154                         tmp = rdev->config.evergreen.tile_config;
1155
1156                 switch ((tmp & 0xf0) >> 4) {
1157                 case 0: /* 4 banks */
1158                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1159                         break;
1160                 case 1: /* 8 banks */
1161                 default:
1162                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1163                         break;
1164                 case 2: /* 16 banks */
1165                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1166                         break;
1167                 }
1168
1169                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1170
1171                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1172                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1173                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1174                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1175                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1176         } else if (tiling_flags & RADEON_TILING_MICRO)
1177                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1178
1179         if ((rdev->family == CHIP_TAHITI) ||
1180             (rdev->family == CHIP_PITCAIRN))
1181                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1182         else if (rdev->family == CHIP_VERDE)
1183                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1184
1185         switch (radeon_crtc->crtc_id) {
1186         case 0:
1187                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1188                 break;
1189         case 1:
1190                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1191                 break;
1192         case 2:
1193                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1194                 break;
1195         case 3:
1196                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1197                 break;
1198         case 4:
1199                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1200                 break;
1201         case 5:
1202                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1203                 break;
1204         default:
1205                 break;
1206         }
1207
1208         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1209                upper_32_bits(fb_location));
1210         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1211                upper_32_bits(fb_location));
1212         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1213                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1214         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1215                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1216         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1217         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1218
1219         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1220         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1221         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1222         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1223         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1224         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1225
1226         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1227         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1228         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1229
1230         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1231                target_fb->height);
1232         x &= ~3;
1233         y &= ~1;
1234         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1235                (x << 16) | y);
1236         viewport_w = crtc->mode.hdisplay;
1237         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1238         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1239                (viewport_w << 16) | viewport_h);
1240
1241         /* pageflip setup */
1242         /* make sure flip is at vb rather than hb */
1243         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1244         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1245         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1246
1247         /* set pageflip to happen anywhere in vblank interval */
1248         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1249
1250         if (!atomic && fb && fb != crtc->fb) {
1251                 radeon_fb = to_radeon_framebuffer(fb);
1252                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1253                 r = radeon_bo_reserve(rbo, false);
1254                 if (unlikely(r != 0))
1255                         return r;
1256                 radeon_bo_unpin(rbo);
1257                 radeon_bo_unreserve(rbo);
1258         }
1259
1260         /* Bytes per pixel may have changed */
1261         radeon_bandwidth_update(rdev);
1262
1263         return 0;
1264 }
1265
1266 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1267                                   struct drm_framebuffer *fb,
1268                                   int x, int y, int atomic)
1269 {
1270         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1271         struct drm_device *dev = crtc->dev;
1272         struct radeon_device *rdev = dev->dev_private;
1273         struct radeon_framebuffer *radeon_fb;
1274         struct drm_gem_object *obj;
1275         struct radeon_bo *rbo;
1276         struct drm_framebuffer *target_fb;
1277         uint64_t fb_location;
1278         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1279         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1280         u32 tmp, viewport_w, viewport_h;
1281         int r;
1282
1283         /* no fb bound */
1284         if (!atomic && !crtc->fb) {
1285                 DRM_DEBUG_KMS("No FB bound\n");
1286                 return 0;
1287         }
1288
1289         if (atomic) {
1290                 radeon_fb = to_radeon_framebuffer(fb);
1291                 target_fb = fb;
1292         }
1293         else {
1294                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1295                 target_fb = crtc->fb;
1296         }
1297
1298         obj = radeon_fb->obj;
1299         rbo = gem_to_radeon_bo(obj);
1300         r = radeon_bo_reserve(rbo, false);
1301         if (unlikely(r != 0))
1302                 return r;
1303
1304         /* If atomic, assume fb object is pinned & idle & fenced and
1305          * just update base pointers
1306          */
1307         if (atomic)
1308                 fb_location = radeon_bo_gpu_offset(rbo);
1309         else {
1310                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1311                 if (unlikely(r != 0)) {
1312                         radeon_bo_unreserve(rbo);
1313                         return -EINVAL;
1314                 }
1315         }
1316         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1317         radeon_bo_unreserve(rbo);
1318
1319         switch (target_fb->bits_per_pixel) {
1320         case 8:
1321                 fb_format =
1322                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1323                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1324                 break;
1325         case 15:
1326                 fb_format =
1327                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1328                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1329                 break;
1330         case 16:
1331                 fb_format =
1332                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1333                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1334 #ifdef __BIG_ENDIAN
1335                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1336 #endif
1337                 break;
1338         case 24:
1339         case 32:
1340                 fb_format =
1341                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1342                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1343 #ifdef __BIG_ENDIAN
1344                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1345 #endif
1346                 break;
1347         default:
1348                 DRM_ERROR("Unsupported screen depth %d\n",
1349                           target_fb->bits_per_pixel);
1350                 return -EINVAL;
1351         }
1352
1353         if (rdev->family >= CHIP_R600) {
1354                 if (tiling_flags & RADEON_TILING_MACRO)
1355                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1356                 else if (tiling_flags & RADEON_TILING_MICRO)
1357                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1358         } else {
1359                 if (tiling_flags & RADEON_TILING_MACRO)
1360                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1361
1362                 if (tiling_flags & RADEON_TILING_MICRO)
1363                         fb_format |= AVIVO_D1GRPH_TILED;
1364         }
1365
1366         if (radeon_crtc->crtc_id == 0)
1367                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1368         else
1369                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1370
1371         if (rdev->family >= CHIP_RV770) {
1372                 if (radeon_crtc->crtc_id) {
1373                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1374                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1375                 } else {
1376                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1377                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1378                 }
1379         }
1380         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1381                (u32) fb_location);
1382         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1383                radeon_crtc->crtc_offset, (u32) fb_location);
1384         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1385         if (rdev->family >= CHIP_R600)
1386                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1387
1388         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1389         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1390         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1391         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1392         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1393         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1394
1395         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1396         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1397         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1398
1399         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1400                target_fb->height);
1401         x &= ~3;
1402         y &= ~1;
1403         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1404                (x << 16) | y);
1405         viewport_w = crtc->mode.hdisplay;
1406         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1407         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1408                (viewport_w << 16) | viewport_h);
1409
1410         /* pageflip setup */
1411         /* make sure flip is at vb rather than hb */
1412         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1413         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1414         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1415
1416         /* set pageflip to happen anywhere in vblank interval */
1417         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1418
1419         if (!atomic && fb && fb != crtc->fb) {
1420                 radeon_fb = to_radeon_framebuffer(fb);
1421                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1422                 r = radeon_bo_reserve(rbo, false);
1423                 if (unlikely(r != 0))
1424                         return r;
1425                 radeon_bo_unpin(rbo);
1426                 radeon_bo_unreserve(rbo);
1427         }
1428
1429         /* Bytes per pixel may have changed */
1430         radeon_bandwidth_update(rdev);
1431
1432         return 0;
1433 }
1434
1435 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1436                            struct drm_framebuffer *old_fb)
1437 {
1438         struct drm_device *dev = crtc->dev;
1439         struct radeon_device *rdev = dev->dev_private;
1440
1441         if (ASIC_IS_DCE4(rdev))
1442                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1443         else if (ASIC_IS_AVIVO(rdev))
1444                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1445         else
1446                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1447 }
1448
1449 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1450                                   struct drm_framebuffer *fb,
1451                                   int x, int y, enum mode_set_atomic state)
1452 {
1453        struct drm_device *dev = crtc->dev;
1454        struct radeon_device *rdev = dev->dev_private;
1455
1456         if (ASIC_IS_DCE4(rdev))
1457                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1458         else if (ASIC_IS_AVIVO(rdev))
1459                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1460         else
1461                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1462 }
1463
1464 /* properly set additional regs when using atombios */
1465 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1466 {
1467         struct drm_device *dev = crtc->dev;
1468         struct radeon_device *rdev = dev->dev_private;
1469         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1470         u32 disp_merge_cntl;
1471
1472         switch (radeon_crtc->crtc_id) {
1473         case 0:
1474                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1475                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1476                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1477                 break;
1478         case 1:
1479                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1480                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1481                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1482                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1483                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1484                 break;
1485         }
1486 }
1487
1488 /**
1489  * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1490  *
1491  * @crtc: drm crtc
1492  *
1493  * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1494  */
1495 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1496 {
1497         struct drm_device *dev = crtc->dev;
1498         struct drm_crtc *test_crtc;
1499         struct radeon_crtc *test_radeon_crtc;
1500         u32 pll_in_use = 0;
1501
1502         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1503                 if (crtc == test_crtc)
1504                         continue;
1505
1506                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1507                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1508                         pll_in_use |= (1 << test_radeon_crtc->pll_id);
1509         }
1510         return pll_in_use;
1511 }
1512
1513 /**
1514  * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1515  *
1516  * @crtc: drm crtc
1517  *
1518  * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1519  * also in DP mode.  For DP, a single PPLL can be used for all DP
1520  * crtcs/encoders.
1521  */
1522 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1523 {
1524         struct drm_device *dev = crtc->dev;
1525         struct drm_crtc *test_crtc;
1526         struct radeon_crtc *test_radeon_crtc;
1527
1528         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1529                 if (crtc == test_crtc)
1530                         continue;
1531                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1532                 if (test_radeon_crtc->encoder &&
1533                     ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1534                         /* for DP use the same PLL for all */
1535                         if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1536                                 return test_radeon_crtc->pll_id;
1537                 }
1538         }
1539         return ATOM_PPLL_INVALID;
1540 }
1541
1542 /**
1543  * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1544  *
1545  * @crtc: drm crtc
1546  * @encoder: drm encoder
1547  *
1548  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1549  * be shared (i.e., same clock).
1550  */
1551 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1552 {
1553         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1554         struct drm_device *dev = crtc->dev;
1555         struct drm_crtc *test_crtc;
1556         struct radeon_crtc *test_radeon_crtc;
1557         u32 adjusted_clock, test_adjusted_clock;
1558
1559         adjusted_clock = radeon_crtc->adjusted_clock;
1560
1561         if (adjusted_clock == 0)
1562                 return ATOM_PPLL_INVALID;
1563
1564         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1565                 if (crtc == test_crtc)
1566                         continue;
1567                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1568                 if (test_radeon_crtc->encoder &&
1569                     !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1570                         /* check if we are already driving this connector with another crtc */
1571                         if (test_radeon_crtc->connector == radeon_crtc->connector) {
1572                                 /* if we are, return that pll */
1573                                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1574                                         return test_radeon_crtc->pll_id;
1575                         }
1576                         /* for non-DP check the clock */
1577                         test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1578                         if ((crtc->mode.clock == test_crtc->mode.clock) &&
1579                             (adjusted_clock == test_adjusted_clock) &&
1580                             (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1581                             (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1582                                 return test_radeon_crtc->pll_id;
1583                 }
1584         }
1585         return ATOM_PPLL_INVALID;
1586 }
1587
1588 /**
1589  * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1590  *
1591  * @crtc: drm crtc
1592  *
1593  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
1594  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
1595  * monitors a dedicated PPLL must be used.  If a particular board has
1596  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1597  * as there is no need to program the PLL itself.  If we are not able to
1598  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1599  * avoid messing up an existing monitor.
1600  *
1601  * Asic specific PLL information
1602  *
1603  * DCE 6.1
1604  * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1605  * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1606  *
1607  * DCE 6.0
1608  * - PPLL0 is available to all UNIPHY (DP only)
1609  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1610  *
1611  * DCE 5.0
1612  * - DCPLL is available to all UNIPHY (DP only)
1613  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1614  *
1615  * DCE 3.0/4.0/4.1
1616  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1617  *
1618  */
1619 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1620 {
1621         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1622         struct drm_device *dev = crtc->dev;
1623         struct radeon_device *rdev = dev->dev_private;
1624         struct radeon_encoder *radeon_encoder =
1625                 to_radeon_encoder(radeon_crtc->encoder);
1626         u32 pll_in_use;
1627         int pll;
1628
1629         if (ASIC_IS_DCE61(rdev)) {
1630                 struct radeon_encoder_atom_dig *dig =
1631                         radeon_encoder->enc_priv;
1632
1633                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1634                     (dig->linkb == false))
1635                         /* UNIPHY A uses PPLL2 */
1636                         return ATOM_PPLL2;
1637                 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1638                         /* UNIPHY B/C/D/E/F */
1639                         if (rdev->clock.dp_extclk)
1640                                 /* skip PPLL programming if using ext clock */
1641                                 return ATOM_PPLL_INVALID;
1642                         else {
1643                                 /* use the same PPLL for all DP monitors */
1644                                 pll = radeon_get_shared_dp_ppll(crtc);
1645                                 if (pll != ATOM_PPLL_INVALID)
1646                                         return pll;
1647                         }
1648                 } else {
1649                         /* use the same PPLL for all monitors with the same clock */
1650                         pll = radeon_get_shared_nondp_ppll(crtc);
1651                         if (pll != ATOM_PPLL_INVALID)
1652                                 return pll;
1653                 }
1654                 /* UNIPHY B/C/D/E/F */
1655                 pll_in_use = radeon_get_pll_use_mask(crtc);
1656                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1657                         return ATOM_PPLL0;
1658                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1659                         return ATOM_PPLL1;
1660                 DRM_ERROR("unable to allocate a PPLL\n");
1661                 return ATOM_PPLL_INVALID;
1662         } else if (ASIC_IS_DCE4(rdev)) {
1663                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1664                  * depending on the asic:
1665                  * DCE4: PPLL or ext clock
1666                  * DCE5: PPLL, DCPLL, or ext clock
1667                  * DCE6: PPLL, PPLL0, or ext clock
1668                  *
1669                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1670                  * PPLL/DCPLL programming and only program the DP DTO for the
1671                  * crtc virtual pixel clock.
1672                  */
1673                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1674                         if (rdev->clock.dp_extclk)
1675                                 /* skip PPLL programming if using ext clock */
1676                                 return ATOM_PPLL_INVALID;
1677                         else if (ASIC_IS_DCE6(rdev))
1678                                 /* use PPLL0 for all DP */
1679                                 return ATOM_PPLL0;
1680                         else if (ASIC_IS_DCE5(rdev))
1681                                 /* use DCPLL for all DP */
1682                                 return ATOM_DCPLL;
1683                         else {
1684                                 /* use the same PPLL for all DP monitors */
1685                                 pll = radeon_get_shared_dp_ppll(crtc);
1686                                 if (pll != ATOM_PPLL_INVALID)
1687                                         return pll;
1688                         }
1689                 } else {
1690                         /* use the same PPLL for all monitors with the same clock */
1691                         pll = radeon_get_shared_nondp_ppll(crtc);
1692                         if (pll != ATOM_PPLL_INVALID)
1693                                 return pll;
1694                 }
1695                 /* all other cases */
1696                 pll_in_use = radeon_get_pll_use_mask(crtc);
1697                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1698                         return ATOM_PPLL1;
1699                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1700                         return ATOM_PPLL2;
1701                 DRM_ERROR("unable to allocate a PPLL\n");
1702                 return ATOM_PPLL_INVALID;
1703         } else {
1704                 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1705                 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1706                  * the matching btw pll and crtc is done through
1707                  * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1708                  * pll (1 or 2) to select which register to write. ie if using
1709                  * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1710                  * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1711                  * choose which value to write. Which is reverse order from
1712                  * register logic. So only case that works is when pllid is
1713                  * same as crtcid or when both pll and crtc are enabled and
1714                  * both use same clock.
1715                  *
1716                  * So just return crtc id as if crtc and pll were hard linked
1717                  * together even if they aren't
1718                  */
1719                 return radeon_crtc->crtc_id;
1720         }
1721 }
1722
1723 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1724 {
1725         /* always set DCPLL */
1726         if (ASIC_IS_DCE6(rdev))
1727                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1728         else if (ASIC_IS_DCE4(rdev)) {
1729                 struct radeon_atom_ss ss;
1730                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1731                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1732                                                                    rdev->clock.default_dispclk);
1733                 if (ss_enabled)
1734                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1735                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1736                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1737                 if (ss_enabled)
1738                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1739         }
1740
1741 }
1742
1743 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1744                            struct drm_display_mode *mode,
1745                            struct drm_display_mode *adjusted_mode,
1746                            int x, int y, struct drm_framebuffer *old_fb)
1747 {
1748         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1749         struct drm_device *dev = crtc->dev;
1750         struct radeon_device *rdev = dev->dev_private;
1751         struct radeon_encoder *radeon_encoder =
1752                 to_radeon_encoder(radeon_crtc->encoder);
1753         bool is_tvcv = false;
1754
1755         if (radeon_encoder->active_device &
1756             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1757                 is_tvcv = true;
1758
1759         atombios_crtc_set_pll(crtc, adjusted_mode);
1760
1761         if (ASIC_IS_DCE4(rdev))
1762                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1763         else if (ASIC_IS_AVIVO(rdev)) {
1764                 if (is_tvcv)
1765                         atombios_crtc_set_timing(crtc, adjusted_mode);
1766                 else
1767                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1768         } else {
1769                 atombios_crtc_set_timing(crtc, adjusted_mode);
1770                 if (radeon_crtc->crtc_id == 0)
1771                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1772                 radeon_legacy_atom_fixup(crtc);
1773         }
1774         atombios_crtc_set_base(crtc, x, y, old_fb);
1775         atombios_overscan_setup(crtc, mode, adjusted_mode);
1776         atombios_scaler_setup(crtc);
1777         return 0;
1778 }
1779
1780 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1781                                      const struct drm_display_mode *mode,
1782                                      struct drm_display_mode *adjusted_mode)
1783 {
1784         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1785         struct drm_device *dev = crtc->dev;
1786         struct drm_encoder *encoder;
1787
1788         /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1789         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1790                 if (encoder->crtc == crtc) {
1791                         radeon_crtc->encoder = encoder;
1792                         radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1793                         break;
1794                 }
1795         }
1796         if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1797                 radeon_crtc->encoder = NULL;
1798                 radeon_crtc->connector = NULL;
1799                 return false;
1800         }
1801         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1802                 return false;
1803         if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1804                 return false;
1805         /* pick pll */
1806         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1807         /* if we can't get a PPLL for a non-DP encoder, fail */
1808         if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1809             !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1810                 return false;
1811
1812         return true;
1813 }
1814
1815 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1816 {
1817         struct drm_device *dev = crtc->dev;
1818         struct radeon_device *rdev = dev->dev_private;
1819
1820         /* disable crtc pair power gating before programming */
1821         if (ASIC_IS_DCE6(rdev))
1822                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1823
1824         atombios_lock_crtc(crtc, ATOM_ENABLE);
1825         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1826 }
1827
1828 static void atombios_crtc_commit(struct drm_crtc *crtc)
1829 {
1830         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1831         atombios_lock_crtc(crtc, ATOM_DISABLE);
1832 }
1833
1834 static void atombios_crtc_disable(struct drm_crtc *crtc)
1835 {
1836         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1837         struct drm_device *dev = crtc->dev;
1838         struct radeon_device *rdev = dev->dev_private;
1839         struct radeon_atom_ss ss;
1840         int i;
1841
1842         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1843         if (ASIC_IS_DCE6(rdev))
1844                 atombios_powergate_crtc(crtc, ATOM_ENABLE);
1845
1846         for (i = 0; i < rdev->num_crtc; i++) {
1847                 if (rdev->mode_info.crtcs[i] &&
1848                     rdev->mode_info.crtcs[i]->enabled &&
1849                     i != radeon_crtc->crtc_id &&
1850                     radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1851                         /* one other crtc is using this pll don't turn
1852                          * off the pll
1853                          */
1854                         goto done;
1855                 }
1856         }
1857
1858         switch (radeon_crtc->pll_id) {
1859         case ATOM_PPLL1:
1860         case ATOM_PPLL2:
1861                 /* disable the ppll */
1862                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1863                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1864                 break;
1865         case ATOM_PPLL0:
1866                 /* disable the ppll */
1867                 if (ASIC_IS_DCE61(rdev))
1868                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1869                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1870                 break;
1871         default:
1872                 break;
1873         }
1874 done:
1875         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1876         radeon_crtc->adjusted_clock = 0;
1877         radeon_crtc->encoder = NULL;
1878         radeon_crtc->connector = NULL;
1879 }
1880
1881 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1882         .dpms = atombios_crtc_dpms,
1883         .mode_fixup = atombios_crtc_mode_fixup,
1884         .mode_set = atombios_crtc_mode_set,
1885         .mode_set_base = atombios_crtc_set_base,
1886         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1887         .prepare = atombios_crtc_prepare,
1888         .commit = atombios_crtc_commit,
1889         .load_lut = radeon_crtc_load_lut,
1890         .disable = atombios_crtc_disable,
1891 };
1892
1893 void radeon_atombios_init_crtc(struct drm_device *dev,
1894                                struct radeon_crtc *radeon_crtc)
1895 {
1896         struct radeon_device *rdev = dev->dev_private;
1897
1898         if (ASIC_IS_DCE4(rdev)) {
1899                 switch (radeon_crtc->crtc_id) {
1900                 case 0:
1901                 default:
1902                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1903                         break;
1904                 case 1:
1905                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1906                         break;
1907                 case 2:
1908                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1909                         break;
1910                 case 3:
1911                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1912                         break;
1913                 case 4:
1914                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1915                         break;
1916                 case 5:
1917                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1918                         break;
1919                 }
1920         } else {
1921                 if (radeon_crtc->crtc_id == 1)
1922                         radeon_crtc->crtc_offset =
1923                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1924                 else
1925                         radeon_crtc->crtc_offset = 0;
1926         }
1927         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1928         radeon_crtc->adjusted_clock = 0;
1929         radeon_crtc->encoder = NULL;
1930         radeon_crtc->connector = NULL;
1931         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1932 }