sys/dev/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *
  28  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_asic.c 254885 2013-08-25 19:37:15Z dumbbell $
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <uapi_drm/radeon_drm.h>
  34 #include "radeon_reg.h"
  35 #include "radeon.h"
  36 #include "radeon_asic.h"
  37 #include "atom.h"
  38
  39 /*
  40  * Registers accessors functions.
  41  */
  42 /**
  43  * radeon_invalid_rreg - dummy reg read function
  44  *
  45  * @rdev: radeon device pointer
  46  * @reg: offset of register
  47  *
  48  * Dummy register read function.  Used for register blocks
  49  * that certain asics don't have (all asics).
  50  * Returns the value in the register.
  51  */
  52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  53 {
  54         panic("Invalid callback to read register 0x%04X\n", reg);
  55         return 0;
  56 }
  57
  58 /**
  59  * radeon_invalid_wreg - dummy reg write function
  60  *
  61  * @rdev: radeon device pointer
  62  * @reg: offset of register
  63  * @v: value to write to the register
  64  *
  65  * Dummy register read function.  Used for register blocks
  66  * that certain asics don't have (all asics).
  67  */
  68 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  69 {
  70         panic("Invalid callback to write register 0x%04X with 0x%08X\n",
  71                   reg, v);
  72 }
  73
  74 /**
  75  * radeon_register_accessor_init - sets up the register accessor callbacks
  76  *
  77  * @rdev: radeon device pointer
  78  *
  79  * Sets up the register accessor callbacks for various register
  80  * apertures.  Not all asics have all apertures (all asics).
  81  */
  82 static void radeon_register_accessor_init(struct radeon_device *rdev)
  83 {
  84         rdev->mc_rreg = &radeon_invalid_rreg;
  85         rdev->mc_wreg = &radeon_invalid_wreg;
  86         rdev->pll_rreg = &radeon_invalid_rreg;
  87         rdev->pll_wreg = &radeon_invalid_wreg;
  88         rdev->pciep_rreg = &radeon_invalid_rreg;
  89         rdev->pciep_wreg = &radeon_invalid_wreg;
  90
  91         /* Don't change order as we are overridding accessor. */
  92         if (rdev->family < CHIP_RV515) {
  93                 rdev->pcie_reg_mask = 0xff;
  94         } else {
  95                 rdev->pcie_reg_mask = 0x7ff;
  96         }
  97         /* FIXME: not sure here */
  98         if (rdev->family <= CHIP_R580) {
  99                 rdev->pll_rreg = &r100_pll_rreg;
 100                 rdev->pll_wreg = &r100_pll_wreg;
 101         }
 102         if (rdev->family >= CHIP_R420) {
 103                 rdev->mc_rreg = &r420_mc_rreg;
 104                 rdev->mc_wreg = &r420_mc_wreg;
 105         }
 106         if (rdev->family >= CHIP_RV515) {
 107                 rdev->mc_rreg = &rv515_mc_rreg;
 108                 rdev->mc_wreg = &rv515_mc_wreg;
 109         }
 110         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 111                 rdev->mc_rreg = &rs400_mc_rreg;
 112                 rdev->mc_wreg = &rs400_mc_wreg;
 113         }
 114         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 115                 rdev->mc_rreg = &rs690_mc_rreg;
 116                 rdev->mc_wreg = &rs690_mc_wreg;
 117         }
 118         if (rdev->family == CHIP_RS600) {
 119                 rdev->mc_rreg = &rs600_mc_rreg;
 120                 rdev->mc_wreg = &rs600_mc_wreg;
 121         }
 122         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 123                 rdev->mc_rreg = &rs780_mc_rreg;
 124                 rdev->mc_wreg = &rs780_mc_wreg;
 125         }
 126         if (rdev->family >= CHIP_R600) {
 127                 rdev->pciep_rreg = &r600_pciep_rreg;
 128                 rdev->pciep_wreg = &r600_pciep_wreg;
 129         }
 130 }
 131
 132
 133 /* helper to disable agp */
 134 /**
 135  * radeon_agp_disable - AGP disable helper function
 136  *
 137  * @rdev: radeon device pointer
 138  *
 139  * Removes AGP flags and changes the gart callbacks on AGP
 140  * cards when using the internal gart rather than AGP (all asics).
 141  */
 142 void radeon_agp_disable(struct radeon_device *rdev)
 143 {
 144         rdev->flags &= ~RADEON_IS_AGP;
 145         if (rdev->family >= CHIP_R600) {
 146                 DRM_INFO("Forcing AGP to PCIE mode\n");
 147                 rdev->flags |= RADEON_IS_PCIE;
 148         } else if (rdev->family >= CHIP_RV515 ||
 149                         rdev->family == CHIP_RV380 ||
 150                         rdev->family == CHIP_RV410 ||
 151                         rdev->family == CHIP_R423) {
 152                 DRM_INFO("Forcing AGP to PCIE mode\n");
 153                 rdev->flags |= RADEON_IS_PCIE;
 154                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 155                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 156         } else {
 157                 DRM_INFO("Forcing AGP to PCI mode\n");
 158                 rdev->flags |= RADEON_IS_PCI;
 159                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 160                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 161         }
 162         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 163 }
 164
 165 /*
 166  * ASIC
 167  */
 168 static struct radeon_asic r100_asic = {
 169         .init = &r100_init,
 170         .fini = &r100_fini,
 171         .suspend = &r100_suspend,
 172         .resume = &r100_resume,
 173         .vga_set_state = &r100_vga_set_state,
 174         .asic_reset = &r100_asic_reset,
 175         .ioctl_wait_idle = NULL,
 176         .gui_idle = &r100_gui_idle,
 177         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 178         .gart = {
 179                 .tlb_flush = &r100_pci_gart_tlb_flush,
 180                 .set_page = &r100_pci_gart_set_page,
 181         },
 182         .ring = {
 183                 [RADEON_RING_TYPE_GFX_INDEX] = {
 184                         .ib_execute = &r100_ring_ib_execute,
 185                         .emit_fence = &r100_fence_ring_emit,
 186                         .emit_semaphore = &r100_semaphore_ring_emit,
 187                         .cs_parse = &r100_cs_parse,
 188                         .ring_start = &r100_ring_start,
 189                         .ring_test = &r100_ring_test,
 190                         .ib_test = &r100_ib_test,
 191                         .is_lockup = &r100_gpu_is_lockup,
 192                 }
 193         },
 194         .irq = {
 195                 .set = &r100_irq_set,
 196                 .process = &r100_irq_process,
 197         },
 198         .display = {
 199                 .bandwidth_update = &r100_bandwidth_update,
 200                 .get_vblank_counter = &r100_get_vblank_counter,
 201                 .wait_for_vblank = &r100_wait_for_vblank,
 202                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 203                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 204         },
 205         .copy = {
 206                 .blit = &r100_copy_blit,
 207                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 208                 .dma = NULL,
 209                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 210                 .copy = &r100_copy_blit,
 211                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 212         },
 213         .surface = {
 214                 .set_reg = r100_set_surface_reg,
 215                 .clear_reg = r100_clear_surface_reg,
 216         },
 217         .hpd = {
 218                 .init = &r100_hpd_init,
 219                 .fini = &r100_hpd_fini,
 220                 .sense = &r100_hpd_sense,
 221                 .set_polarity = &r100_hpd_set_polarity,
 222         },
 223         .pm = {
 224                 .misc = &r100_pm_misc,
 225                 .prepare = &r100_pm_prepare,
 226                 .finish = &r100_pm_finish,
 227                 .init_profile = &r100_pm_init_profile,
 228                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 229                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 230                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 231                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 232                 .set_memory_clock = NULL,
 233                 .get_pcie_lanes = NULL,
 234                 .set_pcie_lanes = NULL,
 235                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 236         },
 237         .pflip = {
 238                 .pre_page_flip = &r100_pre_page_flip,
 239                 .page_flip = &r100_page_flip,
 240                 .post_page_flip = &r100_post_page_flip,
 241         },
 242 };
 243
 244 static struct radeon_asic r200_asic = {
 245         .init = &r100_init,
 246         .fini = &r100_fini,
 247         .suspend = &r100_suspend,
 248         .resume = &r100_resume,
 249         .vga_set_state = &r100_vga_set_state,
 250         .asic_reset = &r100_asic_reset,
 251         .ioctl_wait_idle = NULL,
 252         .gui_idle = &r100_gui_idle,
 253         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 254         .gart = {
 255                 .tlb_flush = &r100_pci_gart_tlb_flush,
 256                 .set_page = &r100_pci_gart_set_page,
 257         },
 258         .ring = {
 259                 [RADEON_RING_TYPE_GFX_INDEX] = {
 260                         .ib_execute = &r100_ring_ib_execute,
 261                         .emit_fence = &r100_fence_ring_emit,
 262                         .emit_semaphore = &r100_semaphore_ring_emit,
 263                         .cs_parse = &r100_cs_parse,
 264                         .ring_start = &r100_ring_start,
 265                         .ring_test = &r100_ring_test,
 266                         .ib_test = &r100_ib_test,
 267                         .is_lockup = &r100_gpu_is_lockup,
 268                 }
 269         },
 270         .irq = {
 271                 .set = &r100_irq_set,
 272                 .process = &r100_irq_process,
 273         },
 274         .display = {
 275                 .bandwidth_update = &r100_bandwidth_update,
 276                 .get_vblank_counter = &r100_get_vblank_counter,
 277                 .wait_for_vblank = &r100_wait_for_vblank,
 278                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 279                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 280         },
 281         .copy = {
 282                 .blit = &r100_copy_blit,
 283                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 284                 .dma = &r200_copy_dma,
 285                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 286                 .copy = &r100_copy_blit,
 287                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 288         },
 289         .surface = {
 290                 .set_reg = r100_set_surface_reg,
 291                 .clear_reg = r100_clear_surface_reg,
 292         },
 293         .hpd = {
 294                 .init = &r100_hpd_init,
 295                 .fini = &r100_hpd_fini,
 296                 .sense = &r100_hpd_sense,
 297                 .set_polarity = &r100_hpd_set_polarity,
 298         },
 299         .pm = {
 300                 .misc = &r100_pm_misc,
 301                 .prepare = &r100_pm_prepare,
 302                 .finish = &r100_pm_finish,
 303                 .init_profile = &r100_pm_init_profile,
 304                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 305                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 306                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 307                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 308                 .set_memory_clock = NULL,
 309                 .get_pcie_lanes = NULL,
 310                 .set_pcie_lanes = NULL,
 311                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 312         },
 313         .pflip = {
 314                 .pre_page_flip = &r100_pre_page_flip,
 315                 .page_flip = &r100_page_flip,
 316                 .post_page_flip = &r100_post_page_flip,
 317         },
 318 };
 319
 320 static struct radeon_asic r300_asic = {
 321         .init = &r300_init,
 322         .fini = &r300_fini,
 323         .suspend = &r300_suspend,
 324         .resume = &r300_resume,
 325         .vga_set_state = &r100_vga_set_state,
 326         .asic_reset = &r300_asic_reset,
 327         .ioctl_wait_idle = NULL,
 328         .gui_idle = &r100_gui_idle,
 329         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 330         .gart = {
 331                 .tlb_flush = &r100_pci_gart_tlb_flush,
 332                 .set_page = &r100_pci_gart_set_page,
 333         },
 334         .ring = {
 335                 [RADEON_RING_TYPE_GFX_INDEX] = {
 336                         .ib_execute = &r100_ring_ib_execute,
 337                         .emit_fence = &r300_fence_ring_emit,
 338                         .emit_semaphore = &r100_semaphore_ring_emit,
 339                         .cs_parse = &r300_cs_parse,
 340                         .ring_start = &r300_ring_start,
 341                         .ring_test = &r100_ring_test,
 342                         .ib_test = &r100_ib_test,
 343                         .is_lockup = &r100_gpu_is_lockup,
 344                 }
 345         },
 346         .irq = {
 347                 .set = &r100_irq_set,
 348                 .process = &r100_irq_process,
 349         },
 350         .display = {
 351                 .bandwidth_update = &r100_bandwidth_update,
 352                 .get_vblank_counter = &r100_get_vblank_counter,
 353                 .wait_for_vblank = &r100_wait_for_vblank,
 354                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 355                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 356         },
 357         .copy = {
 358                 .blit = &r100_copy_blit,
 359                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 360                 .dma = &r200_copy_dma,
 361                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 362                 .copy = &r100_copy_blit,
 363                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 364         },
 365         .surface = {
 366                 .set_reg = r100_set_surface_reg,
 367                 .clear_reg = r100_clear_surface_reg,
 368         },
 369         .hpd = {
 370                 .init = &r100_hpd_init,
 371                 .fini = &r100_hpd_fini,
 372                 .sense = &r100_hpd_sense,
 373                 .set_polarity = &r100_hpd_set_polarity,
 374         },
 375         .pm = {
 376                 .misc = &r100_pm_misc,
 377                 .prepare = &r100_pm_prepare,
 378                 .finish = &r100_pm_finish,
 379                 .init_profile = &r100_pm_init_profile,
 380                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 381                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 382                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 383                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 384                 .set_memory_clock = NULL,
 385                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 386                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 387                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 388         },
 389         .pflip = {
 390                 .pre_page_flip = &r100_pre_page_flip,
 391                 .page_flip = &r100_page_flip,
 392                 .post_page_flip = &r100_post_page_flip,
 393         },
 394 };
 395
 396 static struct radeon_asic r300_asic_pcie = {
 397         .init = &r300_init,
 398         .fini = &r300_fini,
 399         .suspend = &r300_suspend,
 400         .resume = &r300_resume,
 401         .vga_set_state = &r100_vga_set_state,
 402         .asic_reset = &r300_asic_reset,
 403         .ioctl_wait_idle = NULL,
 404         .gui_idle = &r100_gui_idle,
 405         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 406         .gart = {
 407                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 408                 .set_page = &rv370_pcie_gart_set_page,
 409         },
 410         .ring = {
 411                 [RADEON_RING_TYPE_GFX_INDEX] = {
 412                         .ib_execute = &r100_ring_ib_execute,
 413                         .emit_fence = &r300_fence_ring_emit,
 414                         .emit_semaphore = &r100_semaphore_ring_emit,
 415                         .cs_parse = &r300_cs_parse,
 416                         .ring_start = &r300_ring_start,
 417                         .ring_test = &r100_ring_test,
 418                         .ib_test = &r100_ib_test,
 419                         .is_lockup = &r100_gpu_is_lockup,
 420                 }
 421         },
 422         .irq = {
 423                 .set = &r100_irq_set,
 424                 .process = &r100_irq_process,
 425         },
 426         .display = {
 427                 .bandwidth_update = &r100_bandwidth_update,
 428                 .get_vblank_counter = &r100_get_vblank_counter,
 429                 .wait_for_vblank = &r100_wait_for_vblank,
 430                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 431                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 432         },
 433         .copy = {
 434                 .blit = &r100_copy_blit,
 435                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 436                 .dma = &r200_copy_dma,
 437                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 438                 .copy = &r100_copy_blit,
 439                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 440         },
 441         .surface = {
 442                 .set_reg = r100_set_surface_reg,
 443                 .clear_reg = r100_clear_surface_reg,
 444         },
 445         .hpd = {
 446                 .init = &r100_hpd_init,
 447                 .fini = &r100_hpd_fini,
 448                 .sense = &r100_hpd_sense,
 449                 .set_polarity = &r100_hpd_set_polarity,
 450         },
 451         .pm = {
 452                 .misc = &r100_pm_misc,
 453                 .prepare = &r100_pm_prepare,
 454                 .finish = &r100_pm_finish,
 455                 .init_profile = &r100_pm_init_profile,
 456                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 457                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 458                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 459                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 460                 .set_memory_clock = NULL,
 461                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 462                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 463                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 464         },
 465         .pflip = {
 466                 .pre_page_flip = &r100_pre_page_flip,
 467                 .page_flip = &r100_page_flip,
 468                 .post_page_flip = &r100_post_page_flip,
 469         },
 470 };
 471
 472 static struct radeon_asic r420_asic = {
 473         .init = &r420_init,
 474         .fini = &r420_fini,
 475         .suspend = &r420_suspend,
 476         .resume = &r420_resume,
 477         .vga_set_state = &r100_vga_set_state,
 478         .asic_reset = &r300_asic_reset,
 479         .ioctl_wait_idle = NULL,
 480         .gui_idle = &r100_gui_idle,
 481         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 482         .gart = {
 483                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 484                 .set_page = &rv370_pcie_gart_set_page,
 485         },
 486         .ring = {
 487                 [RADEON_RING_TYPE_GFX_INDEX] = {
 488                         .ib_execute = &r100_ring_ib_execute,
 489                         .emit_fence = &r300_fence_ring_emit,
 490                         .emit_semaphore = &r100_semaphore_ring_emit,
 491                         .cs_parse = &r300_cs_parse,
 492                         .ring_start = &r300_ring_start,
 493                         .ring_test = &r100_ring_test,
 494                         .ib_test = &r100_ib_test,
 495                         .is_lockup = &r100_gpu_is_lockup,
 496                 }
 497         },
 498         .irq = {
 499                 .set = &r100_irq_set,
 500                 .process = &r100_irq_process,
 501         },
 502         .display = {
 503                 .bandwidth_update = &r100_bandwidth_update,
 504                 .get_vblank_counter = &r100_get_vblank_counter,
 505                 .wait_for_vblank = &r100_wait_for_vblank,
 506                 .set_backlight_level = &atombios_set_backlight_level,
 507                 .get_backlight_level = &atombios_get_backlight_level,
 508         },
 509         .copy = {
 510                 .blit = &r100_copy_blit,
 511                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 512                 .dma = &r200_copy_dma,
 513                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 514                 .copy = &r100_copy_blit,
 515                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 516         },
 517         .surface = {
 518                 .set_reg = r100_set_surface_reg,
 519                 .clear_reg = r100_clear_surface_reg,
 520         },
 521         .hpd = {
 522                 .init = &r100_hpd_init,
 523                 .fini = &r100_hpd_fini,
 524                 .sense = &r100_hpd_sense,
 525                 .set_polarity = &r100_hpd_set_polarity,
 526         },
 527         .pm = {
 528                 .misc = &r100_pm_misc,
 529                 .prepare = &r100_pm_prepare,
 530                 .finish = &r100_pm_finish,
 531                 .init_profile = &r420_pm_init_profile,
 532                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 533                 .get_engine_clock = &radeon_atom_get_engine_clock,
 534                 .set_engine_clock = &radeon_atom_set_engine_clock,
 535                 .get_memory_clock = &radeon_atom_get_memory_clock,
 536                 .set_memory_clock = &radeon_atom_set_memory_clock,
 537                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 538                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 539                 .set_clock_gating = &radeon_atom_set_clock_gating,
 540         },
 541         .pflip = {
 542                 .pre_page_flip = &r100_pre_page_flip,
 543                 .page_flip = &r100_page_flip,
 544                 .post_page_flip = &r100_post_page_flip,
 545         },
 546 };
 547
 548 static struct radeon_asic rs400_asic = {
 549         .init = &rs400_init,
 550         .fini = &rs400_fini,
 551         .suspend = &rs400_suspend,
 552         .resume = &rs400_resume,
 553         .vga_set_state = &r100_vga_set_state,
 554         .asic_reset = &r300_asic_reset,
 555         .ioctl_wait_idle = NULL,
 556         .gui_idle = &r100_gui_idle,
 557         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 558         .gart = {
 559                 .tlb_flush = &rs400_gart_tlb_flush,
 560                 .set_page = &rs400_gart_set_page,
 561         },
 562         .ring = {
 563                 [RADEON_RING_TYPE_GFX_INDEX] = {
 564                         .ib_execute = &r100_ring_ib_execute,
 565                         .emit_fence = &r300_fence_ring_emit,
 566                         .emit_semaphore = &r100_semaphore_ring_emit,
 567                         .cs_parse = &r300_cs_parse,
 568                         .ring_start = &r300_ring_start,
 569                         .ring_test = &r100_ring_test,
 570                         .ib_test = &r100_ib_test,
 571                         .is_lockup = &r100_gpu_is_lockup,
 572                 }
 573         },
 574         .irq = {
 575                 .set = &r100_irq_set,
 576                 .process = &r100_irq_process,
 577         },
 578         .display = {
 579                 .bandwidth_update = &r100_bandwidth_update,
 580                 .get_vblank_counter = &r100_get_vblank_counter,
 581                 .wait_for_vblank = &r100_wait_for_vblank,
 582                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 583                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 584         },
 585         .copy = {
 586                 .blit = &r100_copy_blit,
 587                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 588                 .dma = &r200_copy_dma,
 589                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 590                 .copy = &r100_copy_blit,
 591                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 592         },
 593         .surface = {
 594                 .set_reg = r100_set_surface_reg,
 595                 .clear_reg = r100_clear_surface_reg,
 596         },
 597         .hpd = {
 598                 .init = &r100_hpd_init,
 599                 .fini = &r100_hpd_fini,
 600                 .sense = &r100_hpd_sense,
 601                 .set_polarity = &r100_hpd_set_polarity,
 602         },
 603         .pm = {
 604                 .misc = &r100_pm_misc,
 605                 .prepare = &r100_pm_prepare,
 606                 .finish = &r100_pm_finish,
 607                 .init_profile = &r100_pm_init_profile,
 608                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 609                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 610                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 611                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 612                 .set_memory_clock = NULL,
 613                 .get_pcie_lanes = NULL,
 614                 .set_pcie_lanes = NULL,
 615                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 616         },
 617         .pflip = {
 618                 .pre_page_flip = &r100_pre_page_flip,
 619                 .page_flip = &r100_page_flip,
 620                 .post_page_flip = &r100_post_page_flip,
 621         },
 622 };
 623
 624 static struct radeon_asic rs600_asic = {
 625         .init = &rs600_init,
 626         .fini = &rs600_fini,
 627         .suspend = &rs600_suspend,
 628         .resume = &rs600_resume,
 629         .vga_set_state = &r100_vga_set_state,
 630         .asic_reset = &rs600_asic_reset,
 631         .ioctl_wait_idle = NULL,
 632         .gui_idle = &r100_gui_idle,
 633         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 634         .gart = {
 635                 .tlb_flush = &rs600_gart_tlb_flush,
 636                 .set_page = &rs600_gart_set_page,
 637         },
 638         .ring = {
 639                 [RADEON_RING_TYPE_GFX_INDEX] = {
 640                         .ib_execute = &r100_ring_ib_execute,
 641                         .emit_fence = &r300_fence_ring_emit,
 642                         .emit_semaphore = &r100_semaphore_ring_emit,
 643                         .cs_parse = &r300_cs_parse,
 644                         .ring_start = &r300_ring_start,
 645                         .ring_test = &r100_ring_test,
 646                         .ib_test = &r100_ib_test,
 647                         .is_lockup = &r100_gpu_is_lockup,
 648                 }
 649         },
 650         .irq = {
 651                 .set = &rs600_irq_set,
 652                 .process = &rs600_irq_process,
 653         },
 654         .display = {
 655                 .bandwidth_update = &rs600_bandwidth_update,
 656                 .get_vblank_counter = &rs600_get_vblank_counter,
 657                 .wait_for_vblank = &avivo_wait_for_vblank,
 658                 .set_backlight_level = &atombios_set_backlight_level,
 659                 .get_backlight_level = &atombios_get_backlight_level,
 660                 .hdmi_enable = &r600_hdmi_enable,
 661                 .hdmi_setmode = &r600_hdmi_setmode,
 662         },
 663         .copy = {
 664                 .blit = &r100_copy_blit,
 665                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 666                 .dma = &r200_copy_dma,
 667                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 668                 .copy = &r100_copy_blit,
 669                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 670         },
 671         .surface = {
 672                 .set_reg = r100_set_surface_reg,
 673                 .clear_reg = r100_clear_surface_reg,
 674         },
 675         .hpd = {
 676                 .init = &rs600_hpd_init,
 677                 .fini = &rs600_hpd_fini,
 678                 .sense = &rs600_hpd_sense,
 679                 .set_polarity = &rs600_hpd_set_polarity,
 680         },
 681         .pm = {
 682                 .misc = &rs600_pm_misc,
 683                 .prepare = &rs600_pm_prepare,
 684                 .finish = &rs600_pm_finish,
 685                 .init_profile = &r420_pm_init_profile,
 686                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 687                 .get_engine_clock = &radeon_atom_get_engine_clock,
 688                 .set_engine_clock = &radeon_atom_set_engine_clock,
 689                 .get_memory_clock = &radeon_atom_get_memory_clock,
 690                 .set_memory_clock = &radeon_atom_set_memory_clock,
 691                 .get_pcie_lanes = NULL,
 692                 .set_pcie_lanes = NULL,
 693                 .set_clock_gating = &radeon_atom_set_clock_gating,
 694         },
 695         .pflip = {
 696                 .pre_page_flip = &rs600_pre_page_flip,
 697                 .page_flip = &rs600_page_flip,
 698                 .post_page_flip = &rs600_post_page_flip,
 699         },
 700 };
 701
 702 static struct radeon_asic rs690_asic = {
 703         .init = &rs690_init,
 704         .fini = &rs690_fini,
 705         .suspend = &rs690_suspend,
 706         .resume = &rs690_resume,
 707         .vga_set_state = &r100_vga_set_state,
 708         .asic_reset = &rs600_asic_reset,
 709         .ioctl_wait_idle = NULL,
 710         .gui_idle = &r100_gui_idle,
 711         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 712         .gart = {
 713                 .tlb_flush = &rs400_gart_tlb_flush,
 714                 .set_page = &rs400_gart_set_page,
 715         },
 716         .ring = {
 717                 [RADEON_RING_TYPE_GFX_INDEX] = {
 718                         .ib_execute = &r100_ring_ib_execute,
 719                         .emit_fence = &r300_fence_ring_emit,
 720                         .emit_semaphore = &r100_semaphore_ring_emit,
 721                         .cs_parse = &r300_cs_parse,
 722                         .ring_start = &r300_ring_start,
 723                         .ring_test = &r100_ring_test,
 724                         .ib_test = &r100_ib_test,
 725                         .is_lockup = &r100_gpu_is_lockup,
 726                 }
 727         },
 728         .irq = {
 729                 .set = &rs600_irq_set,
 730                 .process = &rs600_irq_process,
 731         },
 732         .display = {
 733                 .get_vblank_counter = &rs600_get_vblank_counter,
 734                 .bandwidth_update = &rs690_bandwidth_update,
 735                 .wait_for_vblank = &avivo_wait_for_vblank,
 736                 .set_backlight_level = &atombios_set_backlight_level,
 737                 .get_backlight_level = &atombios_get_backlight_level,
 738                 .hdmi_enable = &r600_hdmi_enable,
 739                 .hdmi_setmode = &r600_hdmi_setmode,
 740         },
 741         .copy = {
 742                 .blit = &r100_copy_blit,
 743                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 744                 .dma = &r200_copy_dma,
 745                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 746                 .copy = &r200_copy_dma,
 747                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 748         },
 749         .surface = {
 750                 .set_reg = r100_set_surface_reg,
 751                 .clear_reg = r100_clear_surface_reg,
 752         },
 753         .hpd = {
 754                 .init = &rs600_hpd_init,
 755                 .fini = &rs600_hpd_fini,
 756                 .sense = &rs600_hpd_sense,
 757                 .set_polarity = &rs600_hpd_set_polarity,
 758         },
 759         .pm = {
 760                 .misc = &rs600_pm_misc,
 761                 .prepare = &rs600_pm_prepare,
 762                 .finish = &rs600_pm_finish,
 763                 .init_profile = &r420_pm_init_profile,
 764                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 765                 .get_engine_clock = &radeon_atom_get_engine_clock,
 766                 .set_engine_clock = &radeon_atom_set_engine_clock,
 767                 .get_memory_clock = &radeon_atom_get_memory_clock,
 768                 .set_memory_clock = &radeon_atom_set_memory_clock,
 769                 .get_pcie_lanes = NULL,
 770                 .set_pcie_lanes = NULL,
 771                 .set_clock_gating = &radeon_atom_set_clock_gating,
 772         },
 773         .pflip = {
 774                 .pre_page_flip = &rs600_pre_page_flip,
 775                 .page_flip = &rs600_page_flip,
 776                 .post_page_flip = &rs600_post_page_flip,
 777         },
 778 };
 779
 780 static struct radeon_asic rv515_asic = {
 781         .init = &rv515_init,
 782         .fini = &rv515_fini,
 783         .suspend = &rv515_suspend,
 784         .resume = &rv515_resume,
 785         .vga_set_state = &r100_vga_set_state,
 786         .asic_reset = &rs600_asic_reset,
 787         .ioctl_wait_idle = NULL,
 788         .gui_idle = &r100_gui_idle,
 789         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 790         .gart = {
 791                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 792                 .set_page = &rv370_pcie_gart_set_page,
 793         },
 794         .ring = {
 795                 [RADEON_RING_TYPE_GFX_INDEX] = {
 796                         .ib_execute = &r100_ring_ib_execute,
 797                         .emit_fence = &r300_fence_ring_emit,
 798                         .emit_semaphore = &r100_semaphore_ring_emit,
 799                         .cs_parse = &r300_cs_parse,
 800                         .ring_start = &rv515_ring_start,
 801                         .ring_test = &r100_ring_test,
 802                         .ib_test = &r100_ib_test,
 803                         .is_lockup = &r100_gpu_is_lockup,
 804                 }
 805         },
 806         .irq = {
 807                 .set = &rs600_irq_set,
 808                 .process = &rs600_irq_process,
 809         },
 810         .display = {
 811                 .get_vblank_counter = &rs600_get_vblank_counter,
 812                 .bandwidth_update = &rv515_bandwidth_update,
 813                 .wait_for_vblank = &avivo_wait_for_vblank,
 814                 .set_backlight_level = &atombios_set_backlight_level,
 815                 .get_backlight_level = &atombios_get_backlight_level,
 816         },
 817         .copy = {
 818                 .blit = &r100_copy_blit,
 819                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 820                 .dma = &r200_copy_dma,
 821                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 822                 .copy = &r100_copy_blit,
 823                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 824         },
 825         .surface = {
 826                 .set_reg = r100_set_surface_reg,
 827                 .clear_reg = r100_clear_surface_reg,
 828         },
 829         .hpd = {
 830                 .init = &rs600_hpd_init,
 831                 .fini = &rs600_hpd_fini,
 832                 .sense = &rs600_hpd_sense,
 833                 .set_polarity = &rs600_hpd_set_polarity,
 834         },
 835         .pm = {
 836                 .misc = &rs600_pm_misc,
 837                 .prepare = &rs600_pm_prepare,
 838                 .finish = &rs600_pm_finish,
 839                 .init_profile = &r420_pm_init_profile,
 840                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 841                 .get_engine_clock = &radeon_atom_get_engine_clock,
 842                 .set_engine_clock = &radeon_atom_set_engine_clock,
 843                 .get_memory_clock = &radeon_atom_get_memory_clock,
 844                 .set_memory_clock = &radeon_atom_set_memory_clock,
 845                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 846                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 847                 .set_clock_gating = &radeon_atom_set_clock_gating,
 848         },
 849         .pflip = {
 850                 .pre_page_flip = &rs600_pre_page_flip,
 851                 .page_flip = &rs600_page_flip,
 852                 .post_page_flip = &rs600_post_page_flip,
 853         },
 854 };
 855
 856 static struct radeon_asic r520_asic = {
 857         .init = &r520_init,
 858         .fini = &rv515_fini,
 859         .suspend = &rv515_suspend,
 860         .resume = &r520_resume,
 861         .vga_set_state = &r100_vga_set_state,
 862         .asic_reset = &rs600_asic_reset,
 863         .ioctl_wait_idle = NULL,
 864         .gui_idle = &r100_gui_idle,
 865         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 866         .gart = {
 867                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 868                 .set_page = &rv370_pcie_gart_set_page,
 869         },
 870         .ring = {
 871                 [RADEON_RING_TYPE_GFX_INDEX] = {
 872                         .ib_execute = &r100_ring_ib_execute,
 873                         .emit_fence = &r300_fence_ring_emit,
 874                         .emit_semaphore = &r100_semaphore_ring_emit,
 875                         .cs_parse = &r300_cs_parse,
 876                         .ring_start = &rv515_ring_start,
 877                         .ring_test = &r100_ring_test,
 878                         .ib_test = &r100_ib_test,
 879                         .is_lockup = &r100_gpu_is_lockup,
 880                 }
 881         },
 882         .irq = {
 883                 .set = &rs600_irq_set,
 884                 .process = &rs600_irq_process,
 885         },
 886         .display = {
 887                 .bandwidth_update = &rv515_bandwidth_update,
 888                 .get_vblank_counter = &rs600_get_vblank_counter,
 889                 .wait_for_vblank = &avivo_wait_for_vblank,
 890                 .set_backlight_level = &atombios_set_backlight_level,
 891                 .get_backlight_level = &atombios_get_backlight_level,
 892         },
 893         .copy = {
 894                 .blit = &r100_copy_blit,
 895                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 896                 .dma = &r200_copy_dma,
 897                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 898                 .copy = &r100_copy_blit,
 899                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 900         },
 901         .surface = {
 902                 .set_reg = r100_set_surface_reg,
 903                 .clear_reg = r100_clear_surface_reg,
 904         },
 905         .hpd = {
 906                 .init = &rs600_hpd_init,
 907                 .fini = &rs600_hpd_fini,
 908                 .sense = &rs600_hpd_sense,
 909                 .set_polarity = &rs600_hpd_set_polarity,
 910         },
 911         .pm = {
 912                 .misc = &rs600_pm_misc,
 913                 .prepare = &rs600_pm_prepare,
 914                 .finish = &rs600_pm_finish,
 915                 .init_profile = &r420_pm_init_profile,
 916                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 917                 .get_engine_clock = &radeon_atom_get_engine_clock,
 918                 .set_engine_clock = &radeon_atom_set_engine_clock,
 919                 .get_memory_clock = &radeon_atom_get_memory_clock,
 920                 .set_memory_clock = &radeon_atom_set_memory_clock,
 921                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 922                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 923                 .set_clock_gating = &radeon_atom_set_clock_gating,
 924         },
 925         .pflip = {
 926                 .pre_page_flip = &rs600_pre_page_flip,
 927                 .page_flip = &rs600_page_flip,
 928                 .post_page_flip = &rs600_post_page_flip,
 929         },
 930 };
 931
 932 static struct radeon_asic r600_asic = {
 933         .init = &r600_init,
 934         .fini = &r600_fini,
 935         .suspend = &r600_suspend,
 936         .resume = &r600_resume,
 937         .vga_set_state = &r600_vga_set_state,
 938         .asic_reset = &r600_asic_reset,
 939         .ioctl_wait_idle = r600_ioctl_wait_idle,
 940         .gui_idle = &r600_gui_idle,
 941         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 942         .get_xclk = &r600_get_xclk,
 943         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 944         .gart = {
 945                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 946                 .set_page = &rs600_gart_set_page,
 947         },
 948         .ring = {
 949                 [RADEON_RING_TYPE_GFX_INDEX] = {
 950                         .ib_execute = &r600_ring_ib_execute,
 951                         .emit_fence = &r600_fence_ring_emit,
 952                         .emit_semaphore = &r600_semaphore_ring_emit,
 953                         .cs_parse = &r600_cs_parse,
 954                         .ring_test = &r600_ring_test,
 955                         .ib_test = &r600_ib_test,
 956                         .is_lockup = &r600_gfx_is_lockup,
 957                 },
 958                 [R600_RING_TYPE_DMA_INDEX] = {
 959                         .ib_execute = &r600_dma_ring_ib_execute,
 960                         .emit_fence = &r600_dma_fence_ring_emit,
 961                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 962                         .cs_parse = &r600_dma_cs_parse,
 963                         .ring_test = &r600_dma_ring_test,
 964                         .ib_test = &r600_dma_ib_test,
 965                         .is_lockup = &r600_dma_is_lockup,
 966                 }
 967         },
 968         .irq = {
 969                 .set = &r600_irq_set,
 970                 .process = &r600_irq_process,
 971         },
 972         .display = {
 973                 .bandwidth_update = &rv515_bandwidth_update,
 974                 .get_vblank_counter = &rs600_get_vblank_counter,
 975                 .wait_for_vblank = &avivo_wait_for_vblank,
 976                 .set_backlight_level = &atombios_set_backlight_level,
 977                 .get_backlight_level = &atombios_get_backlight_level,
 978                 .hdmi_enable = &r600_hdmi_enable,
 979                 .hdmi_setmode = &r600_hdmi_setmode,
 980         },
 981         .copy = {
 982                 .blit = &r600_copy_blit,
 983                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 984                 .dma = &r600_copy_dma,
 985                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 986                 .copy = &r600_copy_dma,
 987                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
 988         },
 989         .surface = {
 990                 .set_reg = r600_set_surface_reg,
 991                 .clear_reg = r600_clear_surface_reg,
 992         },
 993         .hpd = {
 994                 .init = &r600_hpd_init,
 995                 .fini = &r600_hpd_fini,
 996                 .sense = &r600_hpd_sense,
 997                 .set_polarity = &r600_hpd_set_polarity,
 998         },
 999         .pm = {
1000                 .misc = &r600_pm_misc,
1001                 .prepare = &rs600_pm_prepare,
1002                 .finish = &rs600_pm_finish,
1003                 .init_profile = &r600_pm_init_profile,
1004                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1005                 .get_engine_clock = &radeon_atom_get_engine_clock,
1006                 .set_engine_clock = &radeon_atom_set_engine_clock,
1007                 .get_memory_clock = &radeon_atom_get_memory_clock,
1008                 .set_memory_clock = &radeon_atom_set_memory_clock,
1009                 .get_pcie_lanes = &r600_get_pcie_lanes,
1010                 .set_pcie_lanes = &r600_set_pcie_lanes,
1011                 .set_clock_gating = NULL,
1012         },
1013         .pflip = {
1014                 .pre_page_flip = &rs600_pre_page_flip,
1015                 .page_flip = &rs600_page_flip,
1016                 .post_page_flip = &rs600_post_page_flip,
1017         },
1018 };
1019
1020 static struct radeon_asic rs780_asic = {
1021         .init = &r600_init,
1022         .fini = &r600_fini,
1023         .suspend = &r600_suspend,
1024         .resume = &r600_resume,
1025         .vga_set_state = &r600_vga_set_state,
1026         .asic_reset = &r600_asic_reset,
1027         .ioctl_wait_idle = r600_ioctl_wait_idle,
1028         .gui_idle = &r600_gui_idle,
1029         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1030         .get_xclk = &r600_get_xclk,
1031         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1032         .gart = {
1033                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1034                 .set_page = &rs600_gart_set_page,
1035         },
1036         .ring = {
1037                 [RADEON_RING_TYPE_GFX_INDEX] = {
1038                         .ib_execute = &r600_ring_ib_execute,
1039                         .emit_fence = &r600_fence_ring_emit,
1040                         .emit_semaphore = &r600_semaphore_ring_emit,
1041                         .cs_parse = &r600_cs_parse,
1042                         .ring_test = &r600_ring_test,
1043                         .ib_test = &r600_ib_test,
1044                         .is_lockup = &r600_gfx_is_lockup,
1045                 },
1046                 [R600_RING_TYPE_DMA_INDEX] = {
1047                         .ib_execute = &r600_dma_ring_ib_execute,
1048                         .emit_fence = &r600_dma_fence_ring_emit,
1049                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1050                         .cs_parse = &r600_dma_cs_parse,
1051                         .ring_test = &r600_dma_ring_test,
1052                         .ib_test = &r600_dma_ib_test,
1053                         .is_lockup = &r600_dma_is_lockup,
1054                 }
1055         },
1056         .irq = {
1057                 .set = &r600_irq_set,
1058                 .process = &r600_irq_process,
1059         },
1060         .display = {
1061                 .bandwidth_update = &rs690_bandwidth_update,
1062                 .get_vblank_counter = &rs600_get_vblank_counter,
1063                 .wait_for_vblank = &avivo_wait_for_vblank,
1064                 .set_backlight_level = &atombios_set_backlight_level,
1065                 .get_backlight_level = &atombios_get_backlight_level,
1066                 .hdmi_enable = &r600_hdmi_enable,
1067                 .hdmi_setmode = &r600_hdmi_setmode,
1068         },
1069         .copy = {
1070                 .blit = &r600_copy_blit,
1071                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1072                 .dma = &r600_copy_dma,
1073                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1074                 .copy = &r600_copy_dma,
1075                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1076         },
1077         .surface = {
1078                 .set_reg = r600_set_surface_reg,
1079                 .clear_reg = r600_clear_surface_reg,
1080         },
1081         .hpd = {
1082                 .init = &r600_hpd_init,
1083                 .fini = &r600_hpd_fini,
1084                 .sense = &r600_hpd_sense,
1085                 .set_polarity = &r600_hpd_set_polarity,
1086         },
1087         .pm = {
1088                 .misc = &r600_pm_misc,
1089                 .prepare = &rs600_pm_prepare,
1090                 .finish = &rs600_pm_finish,
1091                 .init_profile = &rs780_pm_init_profile,
1092                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1093                 .get_engine_clock = &radeon_atom_get_engine_clock,
1094                 .set_engine_clock = &radeon_atom_set_engine_clock,
1095                 .get_memory_clock = NULL,
1096                 .set_memory_clock = NULL,
1097                 .get_pcie_lanes = NULL,
1098                 .set_pcie_lanes = NULL,
1099                 .set_clock_gating = NULL,
1100         },
1101         .pflip = {
1102                 .pre_page_flip = &rs600_pre_page_flip,
1103                 .page_flip = &rs600_page_flip,
1104                 .post_page_flip = &rs600_post_page_flip,
1105         },
1106 };
1107
1108 static struct radeon_asic rv770_asic = {
1109         .init = &rv770_init,
1110         .fini = &rv770_fini,
1111         .suspend = &rv770_suspend,
1112         .resume = &rv770_resume,
1113         .asic_reset = &r600_asic_reset,
1114         .vga_set_state = &r600_vga_set_state,
1115         .ioctl_wait_idle = r600_ioctl_wait_idle,
1116         .gui_idle = &r600_gui_idle,
1117         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1118         .get_xclk = &rv770_get_xclk,
1119         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1120         .gart = {
1121                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1122                 .set_page = &rs600_gart_set_page,
1123         },
1124         .ring = {
1125                 [RADEON_RING_TYPE_GFX_INDEX] = {
1126                         .ib_execute = &r600_ring_ib_execute,
1127                         .emit_fence = &r600_fence_ring_emit,
1128                         .emit_semaphore = &r600_semaphore_ring_emit,
1129                         .cs_parse = &r600_cs_parse,
1130                         .ring_test = &r600_ring_test,
1131                         .ib_test = &r600_ib_test,
1132                         .is_lockup = &r600_gfx_is_lockup,
1133                 },
1134                 [R600_RING_TYPE_DMA_INDEX] = {
1135                         .ib_execute = &r600_dma_ring_ib_execute,
1136                         .emit_fence = &r600_dma_fence_ring_emit,
1137                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1138                         .cs_parse = &r600_dma_cs_parse,
1139                         .ring_test = &r600_dma_ring_test,
1140                         .ib_test = &r600_dma_ib_test,
1141                         .is_lockup = &r600_dma_is_lockup,
1142                 },
1143                 [R600_RING_TYPE_UVD_INDEX] = {
1144                         .ib_execute = &r600_uvd_ib_execute,
1145                         .emit_fence = &r600_uvd_fence_emit,
1146                         .emit_semaphore = &r600_uvd_semaphore_emit,
1147                         .cs_parse = &radeon_uvd_cs_parse,
1148                         .ring_test = &r600_uvd_ring_test,
1149                         .ib_test = &r600_uvd_ib_test,
1150                         .is_lockup = &radeon_ring_test_lockup,
1151                 }
1152         },
1153         .irq = {
1154                 .set = &r600_irq_set,
1155                 .process = &r600_irq_process,
1156         },
1157         .display = {
1158                 .bandwidth_update = &rv515_bandwidth_update,
1159                 .get_vblank_counter = &rs600_get_vblank_counter,
1160                 .wait_for_vblank = &avivo_wait_for_vblank,
1161                 .set_backlight_level = &atombios_set_backlight_level,
1162                 .get_backlight_level = &atombios_get_backlight_level,
1163                 .hdmi_enable = &r600_hdmi_enable,
1164                 .hdmi_setmode = &r600_hdmi_setmode,
1165         },
1166         .copy = {
1167                 .blit = &r600_copy_blit,
1168                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1169                 .dma = &rv770_copy_dma,
1170                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1171                 .copy = &rv770_copy_dma,
1172                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1173         },
1174         .surface = {
1175                 .set_reg = r600_set_surface_reg,
1176                 .clear_reg = r600_clear_surface_reg,
1177         },
1178         .hpd = {
1179                 .init = &r600_hpd_init,
1180                 .fini = &r600_hpd_fini,
1181                 .sense = &r600_hpd_sense,
1182                 .set_polarity = &r600_hpd_set_polarity,
1183         },
1184         .pm = {
1185                 .misc = &rv770_pm_misc,
1186                 .prepare = &rs600_pm_prepare,
1187                 .finish = &rs600_pm_finish,
1188                 .init_profile = &r600_pm_init_profile,
1189                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1190                 .get_engine_clock = &radeon_atom_get_engine_clock,
1191                 .set_engine_clock = &radeon_atom_set_engine_clock,
1192                 .get_memory_clock = &radeon_atom_get_memory_clock,
1193                 .set_memory_clock = &radeon_atom_set_memory_clock,
1194                 .get_pcie_lanes = &r600_get_pcie_lanes,
1195                 .set_pcie_lanes = &r600_set_pcie_lanes,
1196                 .set_clock_gating = &radeon_atom_set_clock_gating,
1197                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1198         },
1199         .pflip = {
1200                 .pre_page_flip = &rs600_pre_page_flip,
1201                 .page_flip = &rv770_page_flip,
1202                 .post_page_flip = &rs600_post_page_flip,
1203         },
1204 };
1205
1206 static struct radeon_asic evergreen_asic = {
1207         .init = &evergreen_init,
1208         .fini = &evergreen_fini,
1209         .suspend = &evergreen_suspend,
1210         .resume = &evergreen_resume,
1211         .asic_reset = &evergreen_asic_reset,
1212         .vga_set_state = &r600_vga_set_state,
1213         .ioctl_wait_idle = r600_ioctl_wait_idle,
1214         .gui_idle = &r600_gui_idle,
1215         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1216         .get_xclk = &rv770_get_xclk,
1217         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1218         .gart = {
1219                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1220                 .set_page = &rs600_gart_set_page,
1221         },
1222         .ring = {
1223                 [RADEON_RING_TYPE_GFX_INDEX] = {
1224                         .ib_execute = &evergreen_ring_ib_execute,
1225                         .emit_fence = &r600_fence_ring_emit,
1226                         .emit_semaphore = &r600_semaphore_ring_emit,
1227                         .cs_parse = &evergreen_cs_parse,
1228                         .ring_test = &r600_ring_test,
1229                         .ib_test = &r600_ib_test,
1230                         .is_lockup = &evergreen_gfx_is_lockup,
1231                 },
1232                 [R600_RING_TYPE_DMA_INDEX] = {
1233                         .ib_execute = &evergreen_dma_ring_ib_execute,
1234                         .emit_fence = &evergreen_dma_fence_ring_emit,
1235                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1236                         .cs_parse = &evergreen_dma_cs_parse,
1237                         .ring_test = &r600_dma_ring_test,
1238                         .ib_test = &r600_dma_ib_test,
1239                         .is_lockup = &evergreen_dma_is_lockup,
1240                 },
1241                 [R600_RING_TYPE_UVD_INDEX] = {
1242                         .ib_execute = &r600_uvd_ib_execute,
1243                         .emit_fence = &r600_uvd_fence_emit,
1244                         .emit_semaphore = &r600_uvd_semaphore_emit,
1245                         .cs_parse = &radeon_uvd_cs_parse,
1246                         .ring_test = &r600_uvd_ring_test,
1247                         .ib_test = &r600_uvd_ib_test,
1248                         .is_lockup = &radeon_ring_test_lockup,
1249                 }
1250         },
1251         .irq = {
1252                 .set = &evergreen_irq_set,
1253                 .process = &evergreen_irq_process,
1254         },
1255         .display = {
1256                 .bandwidth_update = &evergreen_bandwidth_update,
1257                 .get_vblank_counter = &evergreen_get_vblank_counter,
1258                 .wait_for_vblank = &dce4_wait_for_vblank,
1259                 .set_backlight_level = &atombios_set_backlight_level,
1260                 .get_backlight_level = &atombios_get_backlight_level,
1261                 .hdmi_enable = &evergreen_hdmi_enable,
1262                 .hdmi_setmode = &evergreen_hdmi_setmode,
1263         },
1264         .copy = {
1265                 .blit = &r600_copy_blit,
1266                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1267                 .dma = &evergreen_copy_dma,
1268                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1269                 .copy = &evergreen_copy_dma,
1270                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1271         },
1272         .surface = {
1273                 .set_reg = r600_set_surface_reg,
1274                 .clear_reg = r600_clear_surface_reg,
1275         },
1276         .hpd = {
1277                 .init = &evergreen_hpd_init,
1278                 .fini = &evergreen_hpd_fini,
1279                 .sense = &evergreen_hpd_sense,
1280                 .set_polarity = &evergreen_hpd_set_polarity,
1281         },
1282         .pm = {
1283                 .misc = &evergreen_pm_misc,
1284                 .prepare = &evergreen_pm_prepare,
1285                 .finish = &evergreen_pm_finish,
1286                 .init_profile = &r600_pm_init_profile,
1287                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1288                 .get_engine_clock = &radeon_atom_get_engine_clock,
1289                 .set_engine_clock = &radeon_atom_set_engine_clock,
1290                 .get_memory_clock = &radeon_atom_get_memory_clock,
1291                 .set_memory_clock = &radeon_atom_set_memory_clock,
1292                 .get_pcie_lanes = &r600_get_pcie_lanes,
1293                 .set_pcie_lanes = &r600_set_pcie_lanes,
1294                 .set_clock_gating = NULL,
1295                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1296         },
1297         .pflip = {
1298                 .pre_page_flip = &evergreen_pre_page_flip,
1299                 .page_flip = &evergreen_page_flip,
1300                 .post_page_flip = &evergreen_post_page_flip,
1301         },
1302 };
1303
1304 static struct radeon_asic sumo_asic = {
1305         .init = &evergreen_init,
1306         .fini = &evergreen_fini,
1307         .suspend = &evergreen_suspend,
1308         .resume = &evergreen_resume,
1309         .asic_reset = &evergreen_asic_reset,
1310         .vga_set_state = &r600_vga_set_state,
1311         .ioctl_wait_idle = r600_ioctl_wait_idle,
1312         .gui_idle = &r600_gui_idle,
1313         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1314         .get_xclk = &r600_get_xclk,
1315         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1316         .gart = {
1317                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1318                 .set_page = &rs600_gart_set_page,
1319         },
1320         .ring = {
1321                 [RADEON_RING_TYPE_GFX_INDEX] = {
1322                         .ib_execute = &evergreen_ring_ib_execute,
1323                         .emit_fence = &r600_fence_ring_emit,
1324                         .emit_semaphore = &r600_semaphore_ring_emit,
1325                         .cs_parse = &evergreen_cs_parse,
1326                         .ring_test = &r600_ring_test,
1327                         .ib_test = &r600_ib_test,
1328                         .is_lockup = &evergreen_gfx_is_lockup,
1329                 },
1330                 [R600_RING_TYPE_DMA_INDEX] = {
1331                         .ib_execute = &evergreen_dma_ring_ib_execute,
1332                         .emit_fence = &evergreen_dma_fence_ring_emit,
1333                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1334                         .cs_parse = &evergreen_dma_cs_parse,
1335                         .ring_test = &r600_dma_ring_test,
1336                         .ib_test = &r600_dma_ib_test,
1337                         .is_lockup = &evergreen_dma_is_lockup,
1338                 },
1339                 [R600_RING_TYPE_UVD_INDEX] = {
1340                         .ib_execute = &r600_uvd_ib_execute,
1341                         .emit_fence = &r600_uvd_fence_emit,
1342                         .emit_semaphore = &r600_uvd_semaphore_emit,
1343                         .cs_parse = &radeon_uvd_cs_parse,
1344                         .ring_test = &r600_uvd_ring_test,
1345                         .ib_test = &r600_uvd_ib_test,
1346                         .is_lockup = &radeon_ring_test_lockup,
1347                 }
1348         },
1349         .irq = {
1350                 .set = &evergreen_irq_set,
1351                 .process = &evergreen_irq_process,
1352         },
1353         .display = {
1354                 .bandwidth_update = &evergreen_bandwidth_update,
1355                 .get_vblank_counter = &evergreen_get_vblank_counter,
1356                 .wait_for_vblank = &dce4_wait_for_vblank,
1357                 .set_backlight_level = &atombios_set_backlight_level,
1358                 .get_backlight_level = &atombios_get_backlight_level,
1359                 .hdmi_enable = &evergreen_hdmi_enable,
1360                 .hdmi_setmode = &evergreen_hdmi_setmode,
1361         },
1362         .copy = {
1363                 .blit = &r600_copy_blit,
1364                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1365                 .dma = &evergreen_copy_dma,
1366                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1367                 .copy = &evergreen_copy_dma,
1368                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1369         },
1370         .surface = {
1371                 .set_reg = r600_set_surface_reg,
1372                 .clear_reg = r600_clear_surface_reg,
1373         },
1374         .hpd = {
1375                 .init = &evergreen_hpd_init,
1376                 .fini = &evergreen_hpd_fini,
1377                 .sense = &evergreen_hpd_sense,
1378                 .set_polarity = &evergreen_hpd_set_polarity,
1379         },
1380         .pm = {
1381                 .misc = &evergreen_pm_misc,
1382                 .prepare = &evergreen_pm_prepare,
1383                 .finish = &evergreen_pm_finish,
1384                 .init_profile = &sumo_pm_init_profile,
1385                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1386                 .get_engine_clock = &radeon_atom_get_engine_clock,
1387                 .set_engine_clock = &radeon_atom_set_engine_clock,
1388                 .get_memory_clock = NULL,
1389                 .set_memory_clock = NULL,
1390                 .get_pcie_lanes = NULL,
1391                 .set_pcie_lanes = NULL,
1392                 .set_clock_gating = NULL,
1393                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1394         },
1395         .pflip = {
1396                 .pre_page_flip = &evergreen_pre_page_flip,
1397                 .page_flip = &evergreen_page_flip,
1398                 .post_page_flip = &evergreen_post_page_flip,
1399         },
1400 };
1401
1402 static struct radeon_asic btc_asic = {
1403         .init = &evergreen_init,
1404         .fini = &evergreen_fini,
1405         .suspend = &evergreen_suspend,
1406         .resume = &evergreen_resume,
1407         .asic_reset = &evergreen_asic_reset,
1408         .vga_set_state = &r600_vga_set_state,
1409         .ioctl_wait_idle = r600_ioctl_wait_idle,
1410         .gui_idle = &r600_gui_idle,
1411         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1412         .get_xclk = &rv770_get_xclk,
1413         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1414         .gart = {
1415                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1416                 .set_page = &rs600_gart_set_page,
1417         },
1418         .ring = {
1419                 [RADEON_RING_TYPE_GFX_INDEX] = {
1420                         .ib_execute = &evergreen_ring_ib_execute,
1421                         .emit_fence = &r600_fence_ring_emit,
1422                         .emit_semaphore = &r600_semaphore_ring_emit,
1423                         .cs_parse = &evergreen_cs_parse,
1424                         .ring_test = &r600_ring_test,
1425                         .ib_test = &r600_ib_test,
1426                         .is_lockup = &evergreen_gfx_is_lockup,
1427                 },
1428                 [R600_RING_TYPE_DMA_INDEX] = {
1429                         .ib_execute = &evergreen_dma_ring_ib_execute,
1430                         .emit_fence = &evergreen_dma_fence_ring_emit,
1431                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1432                         .cs_parse = &evergreen_dma_cs_parse,
1433                         .ring_test = &r600_dma_ring_test,
1434                         .ib_test = &r600_dma_ib_test,
1435                         .is_lockup = &evergreen_dma_is_lockup,
1436                 },
1437                 [R600_RING_TYPE_UVD_INDEX] = {
1438                         .ib_execute = &r600_uvd_ib_execute,
1439                         .emit_fence = &r600_uvd_fence_emit,
1440                         .emit_semaphore = &r600_uvd_semaphore_emit,
1441                         .cs_parse = &radeon_uvd_cs_parse,
1442                         .ring_test = &r600_uvd_ring_test,
1443                         .ib_test = &r600_uvd_ib_test,
1444                         .is_lockup = &radeon_ring_test_lockup,
1445                 }
1446         },
1447         .irq = {
1448                 .set = &evergreen_irq_set,
1449                 .process = &evergreen_irq_process,
1450         },
1451         .display = {
1452                 .bandwidth_update = &evergreen_bandwidth_update,
1453                 .get_vblank_counter = &evergreen_get_vblank_counter,
1454                 .wait_for_vblank = &dce4_wait_for_vblank,
1455                 .set_backlight_level = &atombios_set_backlight_level,
1456                 .get_backlight_level = &atombios_get_backlight_level,
1457                 .hdmi_enable = &evergreen_hdmi_enable,
1458                 .hdmi_setmode = &evergreen_hdmi_setmode,
1459         },
1460         .copy = {
1461                 .blit = &r600_copy_blit,
1462                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1463                 .dma = &evergreen_copy_dma,
1464                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1465                 .copy = &evergreen_copy_dma,
1466                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1467         },
1468         .surface = {
1469                 .set_reg = r600_set_surface_reg,
1470                 .clear_reg = r600_clear_surface_reg,
1471         },
1472         .hpd = {
1473                 .init = &evergreen_hpd_init,
1474                 .fini = &evergreen_hpd_fini,
1475                 .sense = &evergreen_hpd_sense,
1476                 .set_polarity = &evergreen_hpd_set_polarity,
1477         },
1478         .pm = {
1479                 .misc = &evergreen_pm_misc,
1480                 .prepare = &evergreen_pm_prepare,
1481                 .finish = &evergreen_pm_finish,
1482                 .init_profile = &btc_pm_init_profile,
1483                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1484                 .get_engine_clock = &radeon_atom_get_engine_clock,
1485                 .set_engine_clock = &radeon_atom_set_engine_clock,
1486                 .get_memory_clock = &radeon_atom_get_memory_clock,
1487                 .set_memory_clock = &radeon_atom_set_memory_clock,
1488                 .get_pcie_lanes = &r600_get_pcie_lanes,
1489                 .set_pcie_lanes = &r600_set_pcie_lanes,
1490                 .set_clock_gating = NULL,
1491                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1492         },
1493         .pflip = {
1494                 .pre_page_flip = &evergreen_pre_page_flip,
1495                 .page_flip = &evergreen_page_flip,
1496                 .post_page_flip = &evergreen_post_page_flip,
1497         },
1498 };
1499
1500 static struct radeon_asic cayman_asic = {
1501         .init = &cayman_init,
1502         .fini = &cayman_fini,
1503         .suspend = &cayman_suspend,
1504         .resume = &cayman_resume,
1505         .asic_reset = &cayman_asic_reset,
1506         .vga_set_state = &r600_vga_set_state,
1507         .ioctl_wait_idle = r600_ioctl_wait_idle,
1508         .gui_idle = &r600_gui_idle,
1509         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1510         .get_xclk = &rv770_get_xclk,
1511         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1512         .gart = {
1513                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1514                 .set_page = &rs600_gart_set_page,
1515         },
1516         .vm = {
1517                 .init = &cayman_vm_init,
1518                 .fini = &cayman_vm_fini,
1519                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1520                 .set_page = &cayman_vm_set_page,
1521         },
1522         .ring = {
1523                 [RADEON_RING_TYPE_GFX_INDEX] = {
1524                         .ib_execute = &cayman_ring_ib_execute,
1525                         .ib_parse = &evergreen_ib_parse,
1526                         .emit_fence = &cayman_fence_ring_emit,
1527                         .emit_semaphore = &r600_semaphore_ring_emit,
1528                         .cs_parse = &evergreen_cs_parse,
1529                         .ring_test = &r600_ring_test,
1530                         .ib_test = &r600_ib_test,
1531                         .is_lockup = &cayman_gfx_is_lockup,
1532                         .vm_flush = &cayman_vm_flush,
1533                 },
1534                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1535                         .ib_execute = &cayman_ring_ib_execute,
1536                         .ib_parse = &evergreen_ib_parse,
1537                         .emit_fence = &cayman_fence_ring_emit,
1538                         .emit_semaphore = &r600_semaphore_ring_emit,
1539                         .cs_parse = &evergreen_cs_parse,
1540                         .ring_test = &r600_ring_test,
1541                         .ib_test = &r600_ib_test,
1542                         .is_lockup = &cayman_gfx_is_lockup,
1543                         .vm_flush = &cayman_vm_flush,
1544                 },
1545                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1546                         .ib_execute = &cayman_ring_ib_execute,
1547                         .ib_parse = &evergreen_ib_parse,
1548                         .emit_fence = &cayman_fence_ring_emit,
1549                         .emit_semaphore = &r600_semaphore_ring_emit,
1550                         .cs_parse = &evergreen_cs_parse,
1551                         .ring_test = &r600_ring_test,
1552                         .ib_test = &r600_ib_test,
1553                         .is_lockup = &cayman_gfx_is_lockup,
1554                         .vm_flush = &cayman_vm_flush,
1555                 },
1556                 [R600_RING_TYPE_DMA_INDEX] = {
1557                         .ib_execute = &cayman_dma_ring_ib_execute,
1558                         .ib_parse = &evergreen_dma_ib_parse,
1559                         .emit_fence = &evergreen_dma_fence_ring_emit,
1560                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1561                         .cs_parse = &evergreen_dma_cs_parse,
1562                         .ring_test = &r600_dma_ring_test,
1563                         .ib_test = &r600_dma_ib_test,
1564                         .is_lockup = &cayman_dma_is_lockup,
1565                         .vm_flush = &cayman_dma_vm_flush,
1566                 },
1567                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1568                         .ib_execute = &cayman_dma_ring_ib_execute,
1569                         .ib_parse = &evergreen_dma_ib_parse,
1570                         .emit_fence = &evergreen_dma_fence_ring_emit,
1571                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1572                         .cs_parse = &evergreen_dma_cs_parse,
1573                         .ring_test = &r600_dma_ring_test,
1574                         .ib_test = &r600_dma_ib_test,
1575                         .is_lockup = &cayman_dma_is_lockup,
1576                         .vm_flush = &cayman_dma_vm_flush,
1577                 },
1578                 [R600_RING_TYPE_UVD_INDEX] = {
1579                         .ib_execute = &r600_uvd_ib_execute,
1580                         .emit_fence = &r600_uvd_fence_emit,
1581                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1582                         .cs_parse = &radeon_uvd_cs_parse,
1583                         .ring_test = &r600_uvd_ring_test,
1584                         .ib_test = &r600_uvd_ib_test,
1585                         .is_lockup = &radeon_ring_test_lockup,
1586                 }
1587         },
1588         .irq = {
1589                 .set = &evergreen_irq_set,
1590                 .process = &evergreen_irq_process,
1591         },
1592         .display = {
1593                 .bandwidth_update = &evergreen_bandwidth_update,
1594                 .get_vblank_counter = &evergreen_get_vblank_counter,
1595                 .wait_for_vblank = &dce4_wait_for_vblank,
1596                 .set_backlight_level = &atombios_set_backlight_level,
1597                 .get_backlight_level = &atombios_get_backlight_level,
1598                 .hdmi_enable = &evergreen_hdmi_enable,
1599                 .hdmi_setmode = &evergreen_hdmi_setmode,
1600         },
1601         .copy = {
1602                 .blit = &r600_copy_blit,
1603                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1604                 .dma = &evergreen_copy_dma,
1605                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1606                 .copy = &evergreen_copy_dma,
1607                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1608         },
1609         .surface = {
1610                 .set_reg = r600_set_surface_reg,
1611                 .clear_reg = r600_clear_surface_reg,
1612         },
1613         .hpd = {
1614                 .init = &evergreen_hpd_init,
1615                 .fini = &evergreen_hpd_fini,
1616                 .sense = &evergreen_hpd_sense,
1617                 .set_polarity = &evergreen_hpd_set_polarity,
1618         },
1619         .pm = {
1620                 .misc = &evergreen_pm_misc,
1621                 .prepare = &evergreen_pm_prepare,
1622                 .finish = &evergreen_pm_finish,
1623                 .init_profile = &btc_pm_init_profile,
1624                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1625                 .get_engine_clock = &radeon_atom_get_engine_clock,
1626                 .set_engine_clock = &radeon_atom_set_engine_clock,
1627                 .get_memory_clock = &radeon_atom_get_memory_clock,
1628                 .set_memory_clock = &radeon_atom_set_memory_clock,
1629                 .get_pcie_lanes = &r600_get_pcie_lanes,
1630                 .set_pcie_lanes = &r600_set_pcie_lanes,
1631                 .set_clock_gating = NULL,
1632                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1633         },
1634         .pflip = {
1635                 .pre_page_flip = &evergreen_pre_page_flip,
1636                 .page_flip = &evergreen_page_flip,
1637                 .post_page_flip = &evergreen_post_page_flip,
1638         },
1639 };
1640
1641 static struct radeon_asic trinity_asic = {
1642         .init = &cayman_init,
1643         .fini = &cayman_fini,
1644         .suspend = &cayman_suspend,
1645         .resume = &cayman_resume,
1646         .asic_reset = &cayman_asic_reset,
1647         .vga_set_state = &r600_vga_set_state,
1648         .ioctl_wait_idle = r600_ioctl_wait_idle,
1649         .gui_idle = &r600_gui_idle,
1650         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1651         .get_xclk = &r600_get_xclk,
1652         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1653         .gart = {
1654                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1655                 .set_page = &rs600_gart_set_page,
1656         },
1657         .vm = {
1658                 .init = &cayman_vm_init,
1659                 .fini = &cayman_vm_fini,
1660                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1661                 .set_page = &cayman_vm_set_page,
1662         },
1663         .ring = {
1664                 [RADEON_RING_TYPE_GFX_INDEX] = {
1665                         .ib_execute = &cayman_ring_ib_execute,
1666                         .ib_parse = &evergreen_ib_parse,
1667                         .emit_fence = &cayman_fence_ring_emit,
1668                         .emit_semaphore = &r600_semaphore_ring_emit,
1669                         .cs_parse = &evergreen_cs_parse,
1670                         .ring_test = &r600_ring_test,
1671                         .ib_test = &r600_ib_test,
1672                         .is_lockup = &cayman_gfx_is_lockup,
1673                         .vm_flush = &cayman_vm_flush,
1674                 },
1675                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1676                         .ib_execute = &cayman_ring_ib_execute,
1677                         .ib_parse = &evergreen_ib_parse,
1678                         .emit_fence = &cayman_fence_ring_emit,
1679                         .emit_semaphore = &r600_semaphore_ring_emit,
1680                         .cs_parse = &evergreen_cs_parse,
1681                         .ring_test = &r600_ring_test,
1682                         .ib_test = &r600_ib_test,
1683                         .is_lockup = &cayman_gfx_is_lockup,
1684                         .vm_flush = &cayman_vm_flush,
1685                 },
1686                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1687                         .ib_execute = &cayman_ring_ib_execute,
1688                         .ib_parse = &evergreen_ib_parse,
1689                         .emit_fence = &cayman_fence_ring_emit,
1690                         .emit_semaphore = &r600_semaphore_ring_emit,
1691                         .cs_parse = &evergreen_cs_parse,
1692                         .ring_test = &r600_ring_test,
1693                         .ib_test = &r600_ib_test,
1694                         .is_lockup = &cayman_gfx_is_lockup,
1695                         .vm_flush = &cayman_vm_flush,
1696                 },
1697                 [R600_RING_TYPE_DMA_INDEX] = {
1698                         .ib_execute = &cayman_dma_ring_ib_execute,
1699                         .ib_parse = &evergreen_dma_ib_parse,
1700                         .emit_fence = &evergreen_dma_fence_ring_emit,
1701                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1702                         .cs_parse = &evergreen_dma_cs_parse,
1703                         .ring_test = &r600_dma_ring_test,
1704                         .ib_test = &r600_dma_ib_test,
1705                         .is_lockup = &cayman_dma_is_lockup,
1706                         .vm_flush = &cayman_dma_vm_flush,
1707                 },
1708                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1709                         .ib_execute = &cayman_dma_ring_ib_execute,
1710                         .ib_parse = &evergreen_dma_ib_parse,
1711                         .emit_fence = &evergreen_dma_fence_ring_emit,
1712                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1713                         .cs_parse = &evergreen_dma_cs_parse,
1714                         .ring_test = &r600_dma_ring_test,
1715                         .ib_test = &r600_dma_ib_test,
1716                         .is_lockup = &cayman_dma_is_lockup,
1717                         .vm_flush = &cayman_dma_vm_flush,
1718                 },
1719                 [R600_RING_TYPE_UVD_INDEX] = {
1720                         .ib_execute = &r600_uvd_ib_execute,
1721                         .emit_fence = &r600_uvd_fence_emit,
1722                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1723                         .cs_parse = &radeon_uvd_cs_parse,
1724                         .ring_test = &r600_uvd_ring_test,
1725                         .ib_test = &r600_uvd_ib_test,
1726                         .is_lockup = &radeon_ring_test_lockup,
1727                 }
1728         },
1729         .irq = {
1730                 .set = &evergreen_irq_set,
1731                 .process = &evergreen_irq_process,
1732         },
1733         .display = {
1734                 .bandwidth_update = &dce6_bandwidth_update,
1735                 .get_vblank_counter = &evergreen_get_vblank_counter,
1736                 .wait_for_vblank = &dce4_wait_for_vblank,
1737                 .set_backlight_level = &atombios_set_backlight_level,
1738                 .get_backlight_level = &atombios_get_backlight_level,
1739         },
1740         .copy = {
1741                 .blit = &r600_copy_blit,
1742                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1743                 .dma = &evergreen_copy_dma,
1744                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1745                 .copy = &evergreen_copy_dma,
1746                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1747         },
1748         .surface = {
1749                 .set_reg = r600_set_surface_reg,
1750                 .clear_reg = r600_clear_surface_reg,
1751         },
1752         .hpd = {
1753                 .init = &evergreen_hpd_init,
1754                 .fini = &evergreen_hpd_fini,
1755                 .sense = &evergreen_hpd_sense,
1756                 .set_polarity = &evergreen_hpd_set_polarity,
1757         },
1758         .pm = {
1759                 .misc = &evergreen_pm_misc,
1760                 .prepare = &evergreen_pm_prepare,
1761                 .finish = &evergreen_pm_finish,
1762                 .init_profile = &sumo_pm_init_profile,
1763                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1764                 .get_engine_clock = &radeon_atom_get_engine_clock,
1765                 .set_engine_clock = &radeon_atom_set_engine_clock,
1766                 .get_memory_clock = NULL,
1767                 .set_memory_clock = NULL,
1768                 .get_pcie_lanes = NULL,
1769                 .set_pcie_lanes = NULL,
1770                 .set_clock_gating = NULL,
1771                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1772         },
1773         .pflip = {
1774                 .pre_page_flip = &evergreen_pre_page_flip,
1775                 .page_flip = &evergreen_page_flip,
1776                 .post_page_flip = &evergreen_post_page_flip,
1777         },
1778 };
1779
1780 static struct radeon_asic si_asic = {
1781         .init = &si_init,
1782         .fini = &si_fini,
1783         .suspend = &si_suspend,
1784         .resume = &si_resume,
1785         .asic_reset = &si_asic_reset,
1786         .vga_set_state = &r600_vga_set_state,
1787         .ioctl_wait_idle = r600_ioctl_wait_idle,
1788         .gui_idle = &r600_gui_idle,
1789         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1790         .get_xclk = &si_get_xclk,
1791         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1792         .gart = {
1793                 .tlb_flush = &si_pcie_gart_tlb_flush,
1794                 .set_page = &rs600_gart_set_page,
1795         },
1796         .vm = {
1797                 .init = &si_vm_init,
1798                 .fini = &si_vm_fini,
1799                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1800                 .set_page = &si_vm_set_page,
1801         },
1802         .ring = {
1803                 [RADEON_RING_TYPE_GFX_INDEX] = {
1804                         .ib_execute = &si_ring_ib_execute,
1805                         .ib_parse = &si_ib_parse,
1806                         .emit_fence = &si_fence_ring_emit,
1807                         .emit_semaphore = &r600_semaphore_ring_emit,
1808                         .cs_parse = NULL,
1809                         .ring_test = &r600_ring_test,
1810                         .ib_test = &r600_ib_test,
1811                         .is_lockup = &si_gfx_is_lockup,
1812                         .vm_flush = &si_vm_flush,
1813                 },
1814                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1815                         .ib_execute = &si_ring_ib_execute,
1816                         .ib_parse = &si_ib_parse,
1817                         .emit_fence = &si_fence_ring_emit,
1818                         .emit_semaphore = &r600_semaphore_ring_emit,
1819                         .cs_parse = NULL,
1820                         .ring_test = &r600_ring_test,
1821                         .ib_test = &r600_ib_test,
1822                         .is_lockup = &si_gfx_is_lockup,
1823                         .vm_flush = &si_vm_flush,
1824                 },
1825                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1826                         .ib_execute = &si_ring_ib_execute,
1827                         .ib_parse = &si_ib_parse,
1828                         .emit_fence = &si_fence_ring_emit,
1829                         .emit_semaphore = &r600_semaphore_ring_emit,
1830                         .cs_parse = NULL,
1831                         .ring_test = &r600_ring_test,
1832                         .ib_test = &r600_ib_test,
1833                         .is_lockup = &si_gfx_is_lockup,
1834                         .vm_flush = &si_vm_flush,
1835                 },
1836                 [R600_RING_TYPE_DMA_INDEX] = {
1837                         .ib_execute = &cayman_dma_ring_ib_execute,
1838                         .ib_parse = &evergreen_dma_ib_parse,
1839                         .emit_fence = &evergreen_dma_fence_ring_emit,
1840                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1841                         .cs_parse = NULL,
1842                         .ring_test = &r600_dma_ring_test,
1843                         .ib_test = &r600_dma_ib_test,
1844                         .is_lockup = &si_dma_is_lockup,
1845                         .vm_flush = &si_dma_vm_flush,
1846                 },
1847                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1848                         .ib_execute = &cayman_dma_ring_ib_execute,
1849                         .ib_parse = &evergreen_dma_ib_parse,
1850                         .emit_fence = &evergreen_dma_fence_ring_emit,
1851                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1852                         .cs_parse = NULL,
1853                         .ring_test = &r600_dma_ring_test,
1854                         .ib_test = &r600_dma_ib_test,
1855                         .is_lockup = &si_dma_is_lockup,
1856                         .vm_flush = &si_dma_vm_flush,
1857                 },
1858                 [R600_RING_TYPE_UVD_INDEX] = {
1859                         .ib_execute = &r600_uvd_ib_execute,
1860                         .emit_fence = &r600_uvd_fence_emit,
1861                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1862                         .cs_parse = &radeon_uvd_cs_parse,
1863                         .ring_test = &r600_uvd_ring_test,
1864                         .ib_test = &r600_uvd_ib_test,
1865                         .is_lockup = &radeon_ring_test_lockup,
1866                 }
1867         },
1868         .irq = {
1869                 .set = &si_irq_set,
1870                 .process = &si_irq_process,
1871         },
1872         .display = {
1873                 .bandwidth_update = &dce6_bandwidth_update,
1874                 .get_vblank_counter = &evergreen_get_vblank_counter,
1875                 .wait_for_vblank = &dce4_wait_for_vblank,
1876                 .set_backlight_level = &atombios_set_backlight_level,
1877                 .get_backlight_level = &atombios_get_backlight_level,
1878         },
1879         .copy = {
1880                 .blit = NULL,
1881                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1882                 .dma = &si_copy_dma,
1883                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1884                 .copy = &si_copy_dma,
1885                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1886         },
1887         .surface = {
1888                 .set_reg = r600_set_surface_reg,
1889                 .clear_reg = r600_clear_surface_reg,
1890         },
1891         .hpd = {
1892                 .init = &evergreen_hpd_init,
1893                 .fini = &evergreen_hpd_fini,
1894                 .sense = &evergreen_hpd_sense,
1895                 .set_polarity = &evergreen_hpd_set_polarity,
1896         },
1897         .pm = {
1898                 .misc = &evergreen_pm_misc,
1899                 .prepare = &evergreen_pm_prepare,
1900                 .finish = &evergreen_pm_finish,
1901                 .init_profile = &sumo_pm_init_profile,
1902                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1903                 .get_engine_clock = &radeon_atom_get_engine_clock,
1904                 .set_engine_clock = &radeon_atom_set_engine_clock,
1905                 .get_memory_clock = &radeon_atom_get_memory_clock,
1906                 .set_memory_clock = &radeon_atom_set_memory_clock,
1907                 .get_pcie_lanes = &r600_get_pcie_lanes,
1908                 .set_pcie_lanes = &r600_set_pcie_lanes,
1909                 .set_clock_gating = NULL,
1910                 .set_uvd_clocks = &si_set_uvd_clocks,
1911         },
1912         .pflip = {
1913                 .pre_page_flip = &evergreen_pre_page_flip,
1914                 .page_flip = &evergreen_page_flip,
1915                 .post_page_flip = &evergreen_post_page_flip,
1916         },
1917 };
1918
1919 /**
1920  * radeon_asic_init - register asic specific callbacks
1921  *
1922  * @rdev: radeon device pointer
1923  *
1924  * Registers the appropriate asic specific callbacks for each
1925  * chip family.  Also sets other asics specific info like the number
1926  * of crtcs and the register aperture accessors (all asics).
1927  * Returns 0 for success.
1928  */
1929 int radeon_asic_init(struct radeon_device *rdev)
1930 {
1931         radeon_register_accessor_init(rdev);
1932
1933         /* set the number of crtcs */
1934         if (rdev->flags & RADEON_SINGLE_CRTC)
1935                 rdev->num_crtc = 1;
1936         else
1937                 rdev->num_crtc = 2;
1938
1939         rdev->has_uvd = false;
1940
1941         switch (rdev->family) {
1942         case CHIP_R100:
1943         case CHIP_RV100:
1944         case CHIP_RS100:
1945         case CHIP_RV200:
1946         case CHIP_RS200:
1947                 rdev->asic = &r100_asic;
1948                 break;
1949         case CHIP_R200:
1950         case CHIP_RV250:
1951         case CHIP_RS300:
1952         case CHIP_RV280:
1953                 rdev->asic = &r200_asic;
1954                 break;
1955         case CHIP_R300:
1956         case CHIP_R350:
1957         case CHIP_RV350:
1958         case CHIP_RV380:
1959                 if (rdev->flags & RADEON_IS_PCIE)
1960                         rdev->asic = &r300_asic_pcie;
1961                 else
1962                         rdev->asic = &r300_asic;
1963                 break;
1964         case CHIP_R420:
1965         case CHIP_R423:
1966         case CHIP_RV410:
1967                 rdev->asic = &r420_asic;
1968                 /* handle macs */
1969                 if (rdev->bios == NULL) {
1970                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1971                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1972                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1973                         rdev->asic->pm.set_memory_clock = NULL;
1974                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1975                 }
1976                 break;
1977         case CHIP_RS400:
1978         case CHIP_RS480:
1979                 rdev->asic = &rs400_asic;
1980                 break;
1981         case CHIP_RS600:
1982                 rdev->asic = &rs600_asic;
1983                 break;
1984         case CHIP_RS690:
1985         case CHIP_RS740:
1986                 rdev->asic = &rs690_asic;
1987                 break;
1988         case CHIP_RV515:
1989                 rdev->asic = &rv515_asic;
1990                 break;
1991         case CHIP_R520:
1992         case CHIP_RV530:
1993         case CHIP_RV560:
1994         case CHIP_RV570:
1995         case CHIP_R580:
1996                 rdev->asic = &r520_asic;
1997                 break;
1998         case CHIP_R600:
1999         case CHIP_RV610:
2000         case CHIP_RV630:
2001         case CHIP_RV620:
2002         case CHIP_RV635:
2003         case CHIP_RV670:
2004                 rdev->asic = &r600_asic;
2005                 if (rdev->family == CHIP_R600)
2006                         rdev->has_uvd = false;
2007                 else
2008                         rdev->has_uvd = true;
2009                 break;
2010         case CHIP_RS780:
2011         case CHIP_RS880:
2012                 rdev->asic = &rs780_asic;
2013                 rdev->has_uvd = true;
2014                 break;
2015         case CHIP_RV770:
2016         case CHIP_RV730:
2017         case CHIP_RV710:
2018         case CHIP_RV740:
2019                 rdev->asic = &rv770_asic;
2020                 rdev->has_uvd = true;
2021                 break;
2022         case CHIP_CEDAR:
2023         case CHIP_REDWOOD:
2024         case CHIP_JUNIPER:
2025         case CHIP_CYPRESS:
2026         case CHIP_HEMLOCK:
2027                 /* set num crtcs */
2028                 if (rdev->family == CHIP_CEDAR)
2029                         rdev->num_crtc = 4;
2030                 else
2031                         rdev->num_crtc = 6;
2032                 rdev->asic = &evergreen_asic;
2033                 rdev->has_uvd = true;
2034                 break;
2035         case CHIP_PALM:
2036         case CHIP_SUMO:
2037         case CHIP_SUMO2:
2038                 rdev->asic = &sumo_asic;
2039                 rdev->has_uvd = true;
2040                 break;
2041         case CHIP_BARTS:
2042         case CHIP_TURKS:
2043         case CHIP_CAICOS:
2044                 /* set num crtcs */
2045                 if (rdev->family == CHIP_CAICOS)
2046                         rdev->num_crtc = 4;
2047                 else
2048                         rdev->num_crtc = 6;
2049                 rdev->asic = &btc_asic;
2050                 rdev->has_uvd = true;
2051                 break;
2052         case CHIP_CAYMAN:
2053                 rdev->asic = &cayman_asic;
2054                 /* set num crtcs */
2055                 rdev->num_crtc = 6;
2056                 rdev->has_uvd = true;
2057                 break;
2058         case CHIP_ARUBA:
2059                 rdev->asic = &trinity_asic;
2060                 /* set num crtcs */
2061                 rdev->num_crtc = 4;
2062                 rdev->has_uvd = true;
2063                 break;
2064         case CHIP_TAHITI:
2065         case CHIP_PITCAIRN:
2066         case CHIP_VERDE:
2067         case CHIP_OLAND:
2068         case CHIP_HAINAN:
2069                 rdev->asic = &si_asic;
2070                 /* set num crtcs */
2071                 if (rdev->family == CHIP_HAINAN)
2072                         rdev->num_crtc = 0;
2073                 else if (rdev->family == CHIP_OLAND)
2074                         rdev->num_crtc = 2;
2075                 else
2076                         rdev->num_crtc = 6;
2077                 if (rdev->family == CHIP_HAINAN)
2078                         rdev->has_uvd = false;
2079                 else
2080                         rdev->has_uvd = true;
2081                 break;
2082         default:
2083                 /* FIXME: not supported yet */
2084                 return -EINVAL;
2085         }
2086
2087         if (rdev->flags & RADEON_IS_IGP) {
2088                 rdev->asic->pm.get_memory_clock = NULL;
2089                 rdev->asic->pm.set_memory_clock = NULL;
2090         }
2091
2092         return 0;
2093 }
2094