sys/dev/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *
  28  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "atom.h"
  35
  36 /*
  37  * BIOS.
  38  */
  39
  40 /* If you boot an IGP board with a discrete card as the primary,
  41  * the IGP rom is not accessible via the rom bar as the IGP rom is
  42  * part of the system bios.  On boot, the system bios puts a
  43  * copy of the igp rom at the start of vram if a discrete card is
  44  * present.
  45  */
  46 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  47 {
  48         drm_local_map_t bios_map;
  49         uint8_t __iomem *bios;
  50         resource_size_t vram_base;
  51         resource_size_t size = 256 * 1024; /* ??? */
  52
  53         DRM_INFO("%s: ===> Try IGP's VRAM...\n", __func__);
  54
  55         if (!(rdev->flags & RADEON_IS_IGP))
  56                 if (!radeon_card_posted(rdev)) {
  57                         DRM_INFO("%s: not POSTed discrete card detected, skipping this method...\n",
  58                             __func__);
  59                         return false;
  60                 }
  61
  62         rdev->bios = NULL;
  63         vram_base = drm_get_resource_start(rdev->ddev, 0);
  64         DRM_INFO("%s: VRAM base address: 0x%jx\n", __func__, (uintmax_t)vram_base);
  65
  66         bios_map.offset = vram_base;
  67         bios_map.size   = size;
  68         bios_map.type   = 0;
  69         bios_map.flags  = 0;
  70         bios_map.mtrr   = 0;
  71         drm_core_ioremap(&bios_map, rdev->ddev);
  72         if (bios_map.handle == NULL) {
  73                 DRM_INFO("%s: failed to ioremap\n", __func__);
  74                 return false;
  75         }
  76         bios = bios_map.handle;
  77         size = bios_map.size;
  78         DRM_INFO("%s: Map address: %p (%ju bytes)\n", __func__, bios, (uintmax_t)size);
  79
  80         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  81                 if (size == 0) {
  82                         DRM_INFO("%s: Incorrect BIOS size\n", __func__);
  83                 } else {
  84                         DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
  85                             __func__, bios[0], bios[1]);
  86                 }
  87                 drm_core_ioremapfree(&bios_map, rdev->ddev);
  88                 return false;
  89         }
  90         rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
  91         if (rdev->bios == NULL) {
  92                 drm_core_ioremapfree(&bios_map, rdev->ddev);
  93                 return false;
  94         }
  95         memcpy_fromio(rdev->bios, bios, size);
  96         drm_core_ioremapfree(&bios_map, rdev->ddev);
  97         return true;
  98 }
  99
 100 static bool radeon_read_bios(struct radeon_device *rdev)
 101 {
 102         device_t vga_dev;
 103         uint8_t __iomem *bios;
 104         size_t size;
 105
 106         DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__);
 107
 108         vga_dev = device_get_parent(rdev->dev);
 109         rdev->bios = NULL;
 110         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
 111         bios = vga_pci_map_bios(vga_dev, &size);
 112         if (!bios) {
 113                 return false;
 114         }
 115         DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size);
 116
 117         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
 118                 if (size == 0) {
 119                         DRM_INFO("%s: Incorrect BIOS size\n", __func__);
 120                 } else {
 121                         DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
 122                             __func__, bios[0], bios[1]);
 123                 }
 124                 vga_pci_unmap_bios(vga_dev, bios);
 125                 return false;
 126         }
 127         rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
 128         memcpy(rdev->bios, bios, size);
 129         vga_pci_unmap_bios(vga_dev, bios);
 130         return true;
 131 }
 132
 133 static bool radeon_read_platform_bios(struct radeon_device *rdev)
 134 {
 135         uint8_t __iomem *bios;
 136         size_t size;
 137
 138         rdev->bios = NULL;
 139
 140         #if 0
 141         // XXX: FIXME
 142         bios = pci_platform_rom(rdev->pdev, &size);
 143         #else
 144         size = 0;
 145         bios = NULL;
 146         #endif
 147         if (!bios) {
 148                 return false;
 149         }
 150
 151         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
 152                 return false;
 153         }
 154         rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
 155         if (rdev->bios == NULL) {
 156                 return false;
 157         }
 158         memcpy(rdev->bios, bios, size);
 159         return true;
 160 }
 161
 162 /* ATRM is used to get the BIOS on the discrete cards in
 163  * dual-gpu systems.
 164  */
 165 /* retrieve the ROM in 4k blocks */
 166 #define ATRM_BIOS_PAGE 4096
 167 /**
 168  * radeon_atrm_call - fetch a chunk of the vbios
 169  *
 170  * @atrm_handle: acpi ATRM handle
 171  * @bios: vbios image pointer
 172  * @offset: offset of vbios image data to fetch
 173  * @len: length of vbios image data to fetch
 174  *
 175  * Executes ATRM to fetch a chunk of the discrete
 176  * vbios image on PX systems (all asics).
 177  * Returns the length of the buffer fetched.
 178  */
 179 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios,
 180                             int offset, int len)
 181 {
 182         ACPI_STATUS status;
 183         ACPI_OBJECT atrm_arg_elements[2], *obj;
 184         ACPI_OBJECT_LIST atrm_arg;
 185         ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 186
 187         atrm_arg.Count = 2;
 188         atrm_arg.Pointer = &atrm_arg_elements[0];
 189
 190         atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER;
 191         atrm_arg_elements[0].Integer.Value = offset;
 192
 193         atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER;
 194         atrm_arg_elements[1].Integer.Value = len;
 195
 196         status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer);
 197         if (ACPI_FAILURE(status)) {
 198                 DRM_ERROR("failed to evaluate ATRM got %s\n", AcpiFormatException(status));
 199                 return -ENODEV;
 200         }
 201
 202         obj = (ACPI_OBJECT *)buffer.Pointer;
 203         memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length);
 204         len = obj->Buffer.Length;
 205         AcpiOsFree(buffer.Pointer);
 206         return len;
 207 }
 208
 209 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 210 {
 211         int ret;
 212         int size = 256 * 1024;
 213         int i;
 214         device_t dev;
 215         ACPI_HANDLE dhandle, atrm_handle;
 216         ACPI_STATUS status;
 217         bool found = false;
 218
 219         DRM_INFO("%s: ===> Try ATRM...\n", __func__);
 220
 221         /* ATRM is for the discrete card only */
 222         if (rdev->flags & RADEON_IS_IGP) {
 223                 DRM_INFO("%s: IGP card detected, skipping this method...\n",
 224                     __func__);
 225                 return false;
 226         }
 227
 228 #ifdef DUMBBELL_WIP
 229         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
 230 #endif /* DUMBBELL_WIP */
 231         if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) {
 232                 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n",
 233                     __func__,
 234                     pci_get_domain(dev),
 235                     pci_get_bus(dev),
 236                     pci_get_slot(dev),
 237                     pci_get_function(dev),
 238                     pci_get_vendor(dev),
 239                     pci_get_device(dev));
 240                 DRM_INFO("%s: Get ACPI device handle\n", __func__);
 241                 dhandle = acpi_get_handle(dev);
 242 #ifdef DUMBBELL_WIP
 243                 if (!dhandle)
 244                         continue;
 245 #endif /* DUMBBELL_WIP */
 246                 if (!dhandle)
 247                         return false;
 248
 249                 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__);
 250                 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle);
 251                 if (!ACPI_FAILURE(status)) {
 252                         found = true;
 253 #ifdef DUMBBELL_WIP
 254                         break;
 255 #endif /* DUMBBELL_WIP */
 256                 } else {
 257                         DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n",
 258                             __func__, AcpiFormatException(status));
 259                 }
 260         }
 261
 262         if (!found)
 263                 return false;
 264
 265         rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
 266         if (!rdev->bios) {
 267                 DRM_ERROR("Unable to allocate bios\n");
 268                 return false;
 269         }
 270
 271         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 272                 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__);
 273                 ret = radeon_atrm_call(atrm_handle,
 274                                        rdev->bios,
 275                                        (i * ATRM_BIOS_PAGE),
 276                                        ATRM_BIOS_PAGE);
 277                 if (ret < ATRM_BIOS_PAGE)
 278                         break;
 279         }
 280
 281         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 282                 if (i == 0) {
 283                         DRM_INFO("%s: Incorrect BIOS size\n", __func__);
 284                 } else {
 285                         DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
 286                             __func__, rdev->bios[0], rdev->bios[1]);
 287                 }
 288                 drm_free(rdev->bios, M_DRM);
 289                 return false;
 290         }
 291         return true;
 292 }
 293
 294 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 295 {
 296         u32 bus_cntl;
 297         u32 d1vga_control;
 298         u32 d2vga_control;
 299         u32 vga_render_control;
 300         u32 rom_cntl;
 301         bool r;
 302
 303         DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__);
 304
 305         bus_cntl = RREG32(R600_BUS_CNTL);
 306         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 307         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 308         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 309         rom_cntl = RREG32(R600_ROM_CNTL);
 310
 311         /* enable the rom */
 312         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 313         if (!ASIC_IS_NODCE(rdev)) {
 314                 /* Disable VGA mode */
 315                 WREG32(AVIVO_D1VGA_CONTROL,
 316                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 317                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 318                 WREG32(AVIVO_D2VGA_CONTROL,
 319                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 320                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 321                 WREG32(AVIVO_VGA_RENDER_CONTROL,
 322                        (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 323         }
 324         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 325
 326         r = radeon_read_bios(rdev);
 327
 328         /* restore regs */
 329         WREG32(R600_BUS_CNTL, bus_cntl);
 330         if (!ASIC_IS_NODCE(rdev)) {
 331                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 332                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 333                 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 334         }
 335         WREG32(R600_ROM_CNTL, rom_cntl);
 336         return r;
 337 }
 338
 339 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 340 {
 341         uint32_t viph_control;
 342         uint32_t bus_cntl;
 343         uint32_t d1vga_control;
 344         uint32_t d2vga_control;
 345         uint32_t vga_render_control;
 346         uint32_t rom_cntl;
 347         uint32_t cg_spll_func_cntl = 0;
 348         uint32_t cg_spll_status;
 349         bool r;
 350
 351         DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__);
 352
 353         viph_control = RREG32(RADEON_VIPH_CONTROL);
 354         bus_cntl = RREG32(R600_BUS_CNTL);
 355         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 356         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 357         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 358         rom_cntl = RREG32(R600_ROM_CNTL);
 359
 360         /* disable VIP */
 361         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 362         /* enable the rom */
 363         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 364         /* Disable VGA mode */
 365         WREG32(AVIVO_D1VGA_CONTROL,
 366                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 367                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 368         WREG32(AVIVO_D2VGA_CONTROL,
 369                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 370                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 371         WREG32(AVIVO_VGA_RENDER_CONTROL,
 372                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 373
 374         if (rdev->family == CHIP_RV730) {
 375                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 376
 377                 /* enable bypass mode */
 378                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 379                                                 R600_SPLL_BYPASS_EN));
 380
 381                 /* wait for SPLL_CHG_STATUS to change to 1 */
 382                 cg_spll_status = 0;
 383                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 384                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 385
 386                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 387         } else
 388                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 389
 390         r = radeon_read_bios(rdev);
 391
 392         /* restore regs */
 393         if (rdev->family == CHIP_RV730) {
 394                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 395
 396                 /* wait for SPLL_CHG_STATUS to change to 1 */
 397                 cg_spll_status = 0;
 398                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 399                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 400         }
 401         WREG32(RADEON_VIPH_CONTROL, viph_control);
 402         WREG32(R600_BUS_CNTL, bus_cntl);
 403         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 404         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 405         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 406         WREG32(R600_ROM_CNTL, rom_cntl);
 407         return r;
 408 }
 409
 410 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 411 {
 412         uint32_t viph_control;
 413         uint32_t bus_cntl;
 414         uint32_t d1vga_control;
 415         uint32_t d2vga_control;
 416         uint32_t vga_render_control;
 417         uint32_t rom_cntl;
 418         uint32_t general_pwrmgt;
 419         uint32_t low_vid_lower_gpio_cntl;
 420         uint32_t medium_vid_lower_gpio_cntl;
 421         uint32_t high_vid_lower_gpio_cntl;
 422         uint32_t ctxsw_vid_lower_gpio_cntl;
 423         uint32_t lower_gpio_enable;
 424         bool r;
 425
 426         DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__);
 427
 428         viph_control = RREG32(RADEON_VIPH_CONTROL);
 429         bus_cntl = RREG32(R600_BUS_CNTL);
 430         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 431         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 432         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 433         rom_cntl = RREG32(R600_ROM_CNTL);
 434         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 435         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 436         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 437         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 438         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 439         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 440
 441         /* disable VIP */
 442         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 443         /* enable the rom */
 444         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 445         /* Disable VGA mode */
 446         WREG32(AVIVO_D1VGA_CONTROL,
 447                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 448                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 449         WREG32(AVIVO_D2VGA_CONTROL,
 450                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 451                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 452         WREG32(AVIVO_VGA_RENDER_CONTROL,
 453                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 454
 455         WREG32(R600_ROM_CNTL,
 456                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 457                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 458                 R600_SCK_OVERWRITE));
 459
 460         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 461         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 462                (low_vid_lower_gpio_cntl & ~0x400));
 463         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 464                (medium_vid_lower_gpio_cntl & ~0x400));
 465         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 466                (high_vid_lower_gpio_cntl & ~0x400));
 467         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 468                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 469         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 470
 471         r = radeon_read_bios(rdev);
 472
 473         /* restore regs */
 474         WREG32(RADEON_VIPH_CONTROL, viph_control);
 475         WREG32(R600_BUS_CNTL, bus_cntl);
 476         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 477         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 478         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 479         WREG32(R600_ROM_CNTL, rom_cntl);
 480         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 481         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 482         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 483         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 484         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 485         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 486         return r;
 487 }
 488
 489 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 490 {
 491         uint32_t seprom_cntl1;
 492         uint32_t viph_control;
 493         uint32_t bus_cntl;
 494         uint32_t d1vga_control;
 495         uint32_t d2vga_control;
 496         uint32_t vga_render_control;
 497         uint32_t gpiopad_a;
 498         uint32_t gpiopad_en;
 499         uint32_t gpiopad_mask;
 500         bool r;
 501
 502         DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__);
 503
 504         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 505         viph_control = RREG32(RADEON_VIPH_CONTROL);
 506         bus_cntl = RREG32(RV370_BUS_CNTL);
 507         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 508         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 509         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 510         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 511         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 512         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 513
 514         WREG32(RADEON_SEPROM_CNTL1,
 515                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 516                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 517         WREG32(RADEON_GPIOPAD_A, 0);
 518         WREG32(RADEON_GPIOPAD_EN, 0);
 519         WREG32(RADEON_GPIOPAD_MASK, 0);
 520
 521         /* disable VIP */
 522         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 523
 524         /* enable the rom */
 525         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 526
 527         /* Disable VGA mode */
 528         WREG32(AVIVO_D1VGA_CONTROL,
 529                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 530                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 531         WREG32(AVIVO_D2VGA_CONTROL,
 532                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 533                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 534         WREG32(AVIVO_VGA_RENDER_CONTROL,
 535                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 536
 537         r = radeon_read_bios(rdev);
 538
 539         /* restore regs */
 540         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 541         WREG32(RADEON_VIPH_CONTROL, viph_control);
 542         WREG32(RV370_BUS_CNTL, bus_cntl);
 543         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 544         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 545         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 546         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 547         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 548         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 549         return r;
 550 }
 551
 552 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 553 {
 554         uint32_t seprom_cntl1;
 555         uint32_t viph_control;
 556         uint32_t bus_cntl;
 557         uint32_t crtc_gen_cntl;
 558         uint32_t crtc2_gen_cntl;
 559         uint32_t crtc_ext_cntl;
 560         uint32_t fp2_gen_cntl;
 561         bool r;
 562
 563         DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__);
 564
 565         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 566         viph_control = RREG32(RADEON_VIPH_CONTROL);
 567         if (rdev->flags & RADEON_IS_PCIE)
 568                 bus_cntl = RREG32(RV370_BUS_CNTL);
 569         else
 570                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 571         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 572         crtc2_gen_cntl = 0;
 573         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 574         fp2_gen_cntl = 0;
 575
 576 #define PCI_DEVICE_ID_ATI_RADEON_QY     0x5159
 577
 578         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 579                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 580         }
 581
 582         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 583                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 584         }
 585
 586         WREG32(RADEON_SEPROM_CNTL1,
 587                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 588                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 589
 590         /* disable VIP */
 591         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 592
 593         /* enable the rom */
 594         if (rdev->flags & RADEON_IS_PCIE)
 595                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 596         else
 597                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 598
 599         /* Turn off mem requests and CRTC for both controllers */
 600         WREG32(RADEON_CRTC_GEN_CNTL,
 601                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 602                 (RADEON_CRTC_DISP_REQ_EN_B |
 603                  RADEON_CRTC_EXT_DISP_EN)));
 604         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 605                 WREG32(RADEON_CRTC2_GEN_CNTL,
 606                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 607                         RADEON_CRTC2_DISP_REQ_EN_B));
 608         }
 609         /* Turn off CRTC */
 610         WREG32(RADEON_CRTC_EXT_CNTL,
 611                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 612                 (RADEON_CRTC_SYNC_TRISTAT |
 613                  RADEON_CRTC_DISPLAY_DIS)));
 614
 615         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 616                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 617         }
 618
 619         r = radeon_read_bios(rdev);
 620
 621         /* restore regs */
 622         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 623         WREG32(RADEON_VIPH_CONTROL, viph_control);
 624         if (rdev->flags & RADEON_IS_PCIE)
 625                 WREG32(RV370_BUS_CNTL, bus_cntl);
 626         else
 627                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 628         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 629         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 630                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 631         }
 632         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 633         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 634                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 635         }
 636         return r;
 637 }
 638
 639 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 640 {
 641         if (rdev->flags & RADEON_IS_IGP)
 642                 return igp_read_bios_from_vram(rdev);
 643         else if (rdev->family >= CHIP_BARTS)
 644                 return ni_read_disabled_bios(rdev);
 645         else if (rdev->family >= CHIP_RV770)
 646                 return r700_read_disabled_bios(rdev);
 647         else if (rdev->family >= CHIP_R600)
 648                 return r600_read_disabled_bios(rdev);
 649         else if (rdev->family >= CHIP_RS600)
 650                 return avivo_read_disabled_bios(rdev);
 651         else
 652                 return legacy_read_disabled_bios(rdev);
 653 }
 654
 655 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 656 {
 657         bool ret = false;
 658         ACPI_TABLE_HEADER *hdr;
 659         ACPI_SIZE tbl_size;
 660         UEFI_ACPI_VFCT *vfct;
 661         GOP_VBIOS_CONTENT *vbios;
 662         VFCT_IMAGE_HEADER *vhdr;
 663         ACPI_STATUS status;
 664
 665         DRM_INFO("%s: ===> Try VFCT...\n", __func__);
 666
 667         DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__);
 668         status = AcpiGetTable("VFCT", 1, &hdr);
 669         if (!ACPI_SUCCESS(status)) {
 670                 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n",
 671                     __func__, AcpiFormatException(status));
 672                 return false;
 673         }
 674         tbl_size = hdr->Length;
 675         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 676                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 677                 goto out_unmap;
 678         }
 679
 680         vfct = (UEFI_ACPI_VFCT *)hdr;
 681         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
 682                 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 683                 goto out_unmap;
 684         }
 685
 686         vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
 687         vhdr = &vbios->VbiosHeader;
 688         DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
 689                         vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
 690                         vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
 691
 692         if (vhdr->PCIBus != rdev->ddev->pci_bus ||
 693             vhdr->PCIDevice != rdev->ddev->pci_slot ||
 694             vhdr->PCIFunction != rdev->ddev->pci_func ||
 695             vhdr->VendorID != rdev->ddev->pci_vendor ||
 696             vhdr->DeviceID != rdev->ddev->pci_device) {
 697                 DRM_INFO("ACPI VFCT table is not for this card\n");
 698                 goto out_unmap;
 699         }
 700
 701         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
 702                 DRM_ERROR("ACPI VFCT image truncated\n");
 703                 goto out_unmap;
 704         }
 705
 706         rdev->bios = kmalloc(vhdr->ImageLength, M_DRM, M_WAITOK);
 707         memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength);
 708         ret = !!rdev->bios;
 709
 710 out_unmap:
 711         return ret;
 712 }
 713
 714 bool radeon_get_bios(struct radeon_device *rdev)
 715 {
 716         bool r;
 717         uint16_t tmp;
 718
 719         r = radeon_atrm_get_bios(rdev);
 720         if (r == false)
 721                 r = radeon_acpi_vfct_bios(rdev);
 722         if (r == false)
 723                 r = igp_read_bios_from_vram(rdev);
 724         if (r == false)
 725                 r = radeon_read_bios(rdev);
 726         if (r == false) {
 727                 r = radeon_read_disabled_bios(rdev);
 728         }
 729         if (r == false) {
 730                 r = radeon_read_platform_bios(rdev);
 731         }
 732         if (r == false || rdev->bios == NULL) {
 733                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 734                 rdev->bios = NULL;
 735                 return false;
 736         }
 737         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 738                 DRM_ERROR("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 739                 goto free_bios;
 740         }
 741
 742         tmp = RBIOS16(0x18);
 743         if (RBIOS8(tmp + 0x14) != 0x0) {
 744                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 745                 goto free_bios;
 746         }
 747
 748         rdev->bios_header_start = RBIOS16(0x48);
 749         if (!rdev->bios_header_start) {
 750                 goto free_bios;
 751         }
 752         tmp = rdev->bios_header_start + 4;
 753         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 754             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 755                 rdev->is_atom_bios = true;
 756         } else {
 757                 rdev->is_atom_bios = false;
 758         }
 759
 760         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 761         return true;
 762 free_bios:
 763         drm_free(rdev->bios, M_DRM);
 764         rdev->bios = NULL;
 765         return false;
 766 }