sys/dev/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *
  28  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_kms.c 254885 2013-08-25 19:37:15Z dumbbell $
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include "radeon.h"
  33 #include <uapi_drm/radeon_drm.h>
  34 #include "radeon_asic.h"
  35 #include "radeon_kms.h"
  36
  37 /**
  38  * radeon_driver_unload_kms - Main unload function for KMS.
  39  *
  40  * @dev: drm dev pointer
  41  *
  42  * This is the main unload function for KMS (all asics).
  43  * It calls radeon_modeset_fini() to tear down the
  44  * displays, and radeon_device_fini() to tear down
  45  * the rest of the device (CP, writeback, etc.).
  46  * Returns 0 on success.
  47  */
  48 int radeon_driver_unload_kms(struct drm_device *dev)
  49 {
  50         struct radeon_device *rdev = dev->dev_private;
  51
  52         if (rdev == NULL)
  53                 return 0;
  54         if (rdev->rmmio == NULL)
  55                 goto done_free;
  56         radeon_acpi_fini(rdev);
  57         radeon_modeset_fini(rdev);
  58         radeon_device_fini(rdev);
  59
  60 done_free:
  61         drm_free(rdev, M_DRM);
  62         dev->dev_private = NULL;
  63         return 0;
  64 }
  65
  66 /**
  67  * radeon_driver_load_kms - Main load function for KMS.
  68  *
  69  * @dev: drm dev pointer
  70  * @flags: device flags
  71  *
  72  * This is the main load function for KMS (all asics).
  73  * It calls radeon_device_init() to set up the non-display
  74  * parts of the chip (asic init, CP, writeback, etc.), and
  75  * radeon_modeset_init() to set up the display parts
  76  * (crtcs, encoders, hotplug detect, etc.).
  77  * Returns 0 on success, error on failure.
  78  */
  79 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  80 {
  81         struct radeon_device *rdev;
  82         int r, acpi_status;
  83
  84         rdev = kmalloc(sizeof(struct radeon_device), M_DRM,
  85                        M_ZERO | M_WAITOK);
  86         if (rdev == NULL) {
  87                 return -ENOMEM;
  88         }
  89         dev->dev_private = (void *)rdev;
  90
  91         /* update BUS flag */
  92         if (drm_device_is_agp(dev)) {
  93                 DRM_INFO("RADEON_IS_AGP\n");
  94                 flags |= RADEON_IS_AGP;
  95         } else if (drm_device_is_pcie(dev)) {
  96                 DRM_INFO("RADEON_IS_PCIE\n");
  97                 flags |= RADEON_IS_PCIE;
  98         } else {
  99                 DRM_INFO("RADEON_IS_PCI\n");
 100                 flags |= RADEON_IS_PCI;
 101         }
 102
 103         /* radeon_device_init should report only fatal error
 104          * like memory allocation failure or iomapping failure,
 105          * or memory manager initialization failure, it must
 106          * properly initialize the GPU MC controller and permit
 107          * VRAM allocation
 108          */
 109         r = radeon_device_init(rdev, dev, flags);
 110         if (r) {
 111                 dev_err(dev->dev, "Fatal error during GPU init\n");
 112                 goto out;
 113         }
 114
 115         /* Again modeset_init should fail only on fatal error
 116          * otherwise it should provide enough functionalities
 117          * for shadowfb to run
 118          */
 119         r = radeon_modeset_init(rdev);
 120         if (r)
 121                 dev_err(dev->dev, "Fatal error during modeset init\n");
 122
 123         /* Call ACPI methods: require modeset init
 124          * but failure is not fatal
 125          */
 126         if (!r) {
 127                 acpi_status = radeon_acpi_init(rdev);
 128                 if (acpi_status)
 129                 dev_dbg(dev->dev,
 130                                 "Error during ACPI methods call\n");
 131         }
 132
 133 out:
 134         if (r)
 135                 radeon_driver_unload_kms(dev);
 136         return r;
 137 }
 138
 139 /**
 140  * radeon_set_filp_rights - Set filp right.
 141  *
 142  * @dev: drm dev pointer
 143  * @owner: drm file
 144  * @applier: drm file
 145  * @value: value
 146  *
 147  * Sets the filp rights for the device (all asics).
 148  */
 149 static void radeon_set_filp_rights(struct drm_device *dev,
 150                                    struct drm_file **owner,
 151                                    struct drm_file *applier,
 152                                    uint32_t *value)
 153 {
 154         DRM_LOCK(dev);
 155         if (*value == 1) {
 156                 /* wants rights */
 157                 if (!*owner)
 158                         *owner = applier;
 159         } else if (*value == 0) {
 160                 /* revokes rights */
 161                 if (*owner == applier)
 162                         *owner = NULL;
 163         }
 164         *value = *owner == applier ? 1 : 0;
 165         DRM_UNLOCK(dev);
 166 }
 167
 168 /*
 169  * Userspace get information ioctl
 170  */
 171 /**
 172  * radeon_info_ioctl - answer a device specific request.
 173  *
 174  * @rdev: radeon device pointer
 175  * @data: request object
 176  * @filp: drm filp
 177  *
 178  * This function is used to pass device specific parameters to the userspace
 179  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 180  * etc. (all asics).
 181  * Returns 0 on success, -EINVAL on failure.
 182  */
 183 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 184 {
 185         struct radeon_device *rdev = dev->dev_private;
 186         struct drm_radeon_info *info = data;
 187         struct radeon_mode_info *minfo = &rdev->mode_info;
 188         uint32_t *value, value_tmp, *value_ptr, value_size;
 189         uint64_t value64;
 190         struct drm_crtc *crtc;
 191         int i, found;
 192
 193         value_ptr = (uint32_t *)((unsigned long)info->value);
 194         value = &value_tmp;
 195         value_size = sizeof(uint32_t);
 196
 197         switch (info->request) {
 198         case RADEON_INFO_DEVICE_ID:
 199                 *value = dev->pci_device;
 200                 break;
 201         case RADEON_INFO_NUM_GB_PIPES:
 202                 *value = rdev->num_gb_pipes;
 203                 break;
 204         case RADEON_INFO_NUM_Z_PIPES:
 205                 *value = rdev->num_z_pipes;
 206                 break;
 207         case RADEON_INFO_ACCEL_WORKING:
 208                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 209                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 210                         *value = false;
 211                 else
 212                         *value = rdev->accel_working;
 213                 break;
 214         case RADEON_INFO_CRTC_FROM_ID:
 215                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 216                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 217                         return -EFAULT;
 218                 }
 219                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 220                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 221                         if (crtc && crtc->base.id == *value) {
 222                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 223                                 *value = radeon_crtc->crtc_id;
 224                                 found = 1;
 225                                 break;
 226                         }
 227                 }
 228                 if (!found) {
 229                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 230                         return -EINVAL;
 231                 }
 232                 break;
 233         case RADEON_INFO_ACCEL_WORKING2:
 234                 *value = rdev->accel_working;
 235                 break;
 236         case RADEON_INFO_TILING_CONFIG:
 237                 if (rdev->family >= CHIP_TAHITI)
 238                         *value = rdev->config.si.tile_config;
 239                 else if (rdev->family >= CHIP_CAYMAN)
 240                         *value = rdev->config.cayman.tile_config;
 241                 else if (rdev->family >= CHIP_CEDAR)
 242                         *value = rdev->config.evergreen.tile_config;
 243                 else if (rdev->family >= CHIP_RV770)
 244                         *value = rdev->config.rv770.tile_config;
 245                 else if (rdev->family >= CHIP_R600)
 246                         *value = rdev->config.r600.tile_config;
 247                 else {
 248                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 249                         return -EINVAL;
 250                 }
 251                 break;
 252         case RADEON_INFO_WANT_HYPERZ:
 253                 /* The "value" here is both an input and output parameter.
 254                  * If the input value is 1, filp requests hyper-z access.
 255                  * If the input value is 0, filp revokes its hyper-z access.
 256                  *
 257                  * When returning, the value is 1 if filp owns hyper-z access,
 258                  * 0 otherwise. */
 259                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 260                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 261                         return -EFAULT;
 262                 }
 263                 if (*value >= 2) {
 264                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 265                         return -EINVAL;
 266                 }
 267                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 268                 break;
 269         case RADEON_INFO_WANT_CMASK:
 270                 /* The same logic as Hyper-Z. */
 271                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 272                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 273                         return -EFAULT;
 274                 }
 275                 if (*value >= 2) {
 276                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 277                         return -EINVAL;
 278                 }
 279                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 280                 break;
 281         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 282                 /* return clock value in KHz */
 283                 if (rdev->asic->get_xclk)
 284                         *value = radeon_get_xclk(rdev) * 10;
 285                 else
 286                         *value = rdev->clock.spll.reference_freq * 10;
 287                 break;
 288         case RADEON_INFO_NUM_BACKENDS:
 289                 if (rdev->family >= CHIP_TAHITI)
 290                         *value = rdev->config.si.max_backends_per_se *
 291                                 rdev->config.si.max_shader_engines;
 292                 else if (rdev->family >= CHIP_CAYMAN)
 293                         *value = rdev->config.cayman.max_backends_per_se *
 294                                 rdev->config.cayman.max_shader_engines;
 295                 else if (rdev->family >= CHIP_CEDAR)
 296                         *value = rdev->config.evergreen.max_backends;
 297                 else if (rdev->family >= CHIP_RV770)
 298                         *value = rdev->config.rv770.max_backends;
 299                 else if (rdev->family >= CHIP_R600)
 300                         *value = rdev->config.r600.max_backends;
 301                 else {
 302                         return -EINVAL;
 303                 }
 304                 break;
 305         case RADEON_INFO_NUM_TILE_PIPES:
 306                 if (rdev->family >= CHIP_TAHITI)
 307                         *value = rdev->config.si.max_tile_pipes;
 308                 else if (rdev->family >= CHIP_CAYMAN)
 309                         *value = rdev->config.cayman.max_tile_pipes;
 310                 else if (rdev->family >= CHIP_CEDAR)
 311                         *value = rdev->config.evergreen.max_tile_pipes;
 312                 else if (rdev->family >= CHIP_RV770)
 313                         *value = rdev->config.rv770.max_tile_pipes;
 314                 else if (rdev->family >= CHIP_R600)
 315                         *value = rdev->config.r600.max_tile_pipes;
 316                 else {
 317                         return -EINVAL;
 318                 }
 319                 break;
 320         case RADEON_INFO_FUSION_GART_WORKING:
 321                 *value = 1;
 322                 break;
 323         case RADEON_INFO_BACKEND_MAP:
 324                 if (rdev->family >= CHIP_TAHITI)
 325                         *value = rdev->config.si.backend_map;
 326                 else if (rdev->family >= CHIP_CAYMAN)
 327                         *value = rdev->config.cayman.backend_map;
 328                 else if (rdev->family >= CHIP_CEDAR)
 329                         *value = rdev->config.evergreen.backend_map;
 330                 else if (rdev->family >= CHIP_RV770)
 331                         *value = rdev->config.rv770.backend_map;
 332                 else if (rdev->family >= CHIP_R600)
 333                         *value = rdev->config.r600.backend_map;
 334                 else {
 335                         return -EINVAL;
 336                 }
 337                 break;
 338         case RADEON_INFO_VA_START:
 339                 /* this is where we report if vm is supported or not */
 340                 if (rdev->family < CHIP_CAYMAN)
 341                         return -EINVAL;
 342                 *value = RADEON_VA_RESERVED_SIZE;
 343                 break;
 344         case RADEON_INFO_IB_VM_MAX_SIZE:
 345                 /* this is where we report if vm is supported or not */
 346                 if (rdev->family < CHIP_CAYMAN)
 347                         return -EINVAL;
 348                 *value = RADEON_IB_VM_MAX_SIZE;
 349                 break;
 350         case RADEON_INFO_MAX_PIPES:
 351                 if (rdev->family >= CHIP_TAHITI)
 352                         *value = rdev->config.si.max_cu_per_sh;
 353                 else if (rdev->family >= CHIP_CAYMAN)
 354                         *value = rdev->config.cayman.max_pipes_per_simd;
 355                 else if (rdev->family >= CHIP_CEDAR)
 356                         *value = rdev->config.evergreen.max_pipes;
 357                 else if (rdev->family >= CHIP_RV770)
 358                         *value = rdev->config.rv770.max_pipes;
 359                 else if (rdev->family >= CHIP_R600)
 360                         *value = rdev->config.r600.max_pipes;
 361                 else {
 362                         return -EINVAL;
 363                 }
 364                 break;
 365         case RADEON_INFO_TIMESTAMP:
 366                 if (rdev->family < CHIP_R600) {
 367                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 368                         return -EINVAL;
 369                 }
 370                 value = (uint32_t*)&value64;
 371                 value_size = sizeof(uint64_t);
 372                 value64 = radeon_get_gpu_clock_counter(rdev);
 373                 break;
 374         case RADEON_INFO_MAX_SE:
 375                 if (rdev->family >= CHIP_TAHITI)
 376                         *value = rdev->config.si.max_shader_engines;
 377                 else if (rdev->family >= CHIP_CAYMAN)
 378                         *value = rdev->config.cayman.max_shader_engines;
 379                 else if (rdev->family >= CHIP_CEDAR)
 380                         *value = rdev->config.evergreen.num_ses;
 381                 else
 382                         *value = 1;
 383                 break;
 384         case RADEON_INFO_MAX_SH_PER_SE:
 385                 if (rdev->family >= CHIP_TAHITI)
 386                         *value = rdev->config.si.max_sh_per_se;
 387                 else
 388                         return -EINVAL;
 389                 break;
 390         case RADEON_INFO_FASTFB_WORKING:
 391                 *value = rdev->fastfb_working;
 392                 break;
 393         case RADEON_INFO_RING_WORKING:
 394                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 395                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 396                         return -EFAULT;
 397                 }
 398                 switch (*value) {
 399                 case RADEON_CS_RING_GFX:
 400                 case RADEON_CS_RING_COMPUTE:
 401                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 402                         break;
 403                 case RADEON_CS_RING_DMA:
 404                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 405                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 406                         break;
 407                 case RADEON_CS_RING_UVD:
 408                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 409                         break;
 410                 default:
 411                         return -EINVAL;
 412                 }
 413                 break;
 414         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 415                 if (rdev->family < CHIP_TAHITI) {
 416                         DRM_DEBUG_KMS("tile mode array is si only!\n");
 417                         return -EINVAL;
 418                 }
 419                 value = rdev->config.si.tile_mode_array;
 420                 value_size = sizeof(uint32_t)*32;
 421                 break;
 422         default:
 423                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 424                 return -EINVAL;
 425         }
 426         if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) {
 427                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 428                 return -EFAULT;
 429         }
 430         return 0;
 431 }
 432
 433
 434 /*
 435  * Outdated mess for old drm with Xorg being in charge (void function now).
 436  */
 437 /**
 438  * radeon_driver_firstopen_kms - drm callback for first open
 439  *
 440  * @dev: drm dev pointer
 441  *
 442  * Nothing to be done for KMS (all asics).
 443  * Returns 0 on success.
 444  */
 445 int radeon_driver_firstopen_kms(struct drm_device *dev)
 446 {
 447         return 0;
 448 }
 449
 450 /**
 451  * radeon_driver_firstopen_kms - drm callback for last close
 452  *
 453  * @dev: drm dev pointer
 454  *
 455  * Switch vga switcheroo state after last close (all asics).
 456  */
 457 void radeon_driver_lastclose_kms(struct drm_device *dev)
 458 {
 459 #ifdef DUMBBELL_WIP
 460         vga_switcheroo_process_delayed_switch();
 461 #endif /* DUMBBELL_WIP */
 462 }
 463
 464 /**
 465  * radeon_driver_open_kms - drm callback for open
 466  *
 467  * @dev: drm dev pointer
 468  * @file_priv: drm file
 469  *
 470  * On device open, init vm on cayman+ (all asics).
 471  * Returns 0 on success, error on failure.
 472  */
 473 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 474 {
 475         struct radeon_device *rdev = dev->dev_private;
 476
 477         file_priv->driver_priv = NULL;
 478
 479         /* new gpu have virtual address space support */
 480         if (rdev->family >= CHIP_CAYMAN) {
 481                 struct radeon_fpriv *fpriv;
 482                 struct radeon_bo_va *bo_va;
 483                 int r;
 484
 485                 fpriv = kmalloc(sizeof(*fpriv), M_DRM,
 486                                 M_ZERO | M_WAITOK);
 487                 if (unlikely(!fpriv)) {
 488                         return -ENOMEM;
 489                 }
 490
 491                 radeon_vm_init(rdev, &fpriv->vm);
 492
 493                 /* map the ib pool buffer read only into
 494                  * virtual address space */
 495                 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
 496                                          rdev->ring_tmp_bo.bo);
 497                 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
 498                                           RADEON_VM_PAGE_READABLE |
 499                                           RADEON_VM_PAGE_SNOOPED);
 500                 if (r) {
 501                         radeon_vm_fini(rdev, &fpriv->vm);
 502                         drm_free(fpriv, M_DRM);
 503                         return r;
 504                 }
 505
 506                 file_priv->driver_priv = fpriv;
 507         }
 508         return 0;
 509 }
 510
 511 /**
 512  * radeon_driver_postclose_kms - drm callback for post close
 513  *
 514  * @dev: drm dev pointer
 515  * @file_priv: drm file
 516  *
 517  * On device post close, tear down vm on cayman+ (all asics).
 518  */
 519 void radeon_driver_postclose_kms(struct drm_device *dev,
 520                                  struct drm_file *file_priv)
 521 {
 522         struct radeon_device *rdev = dev->dev_private;
 523
 524         /* new gpu have virtual address space support */
 525         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 526                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 527                 struct radeon_bo_va *bo_va;
 528                 int r;
 529
 530                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 531                 if (!r) {
 532                         bo_va = radeon_vm_bo_find(&fpriv->vm,
 533                                                   rdev->ring_tmp_bo.bo);
 534                         if (bo_va)
 535                                 radeon_vm_bo_rmv(rdev, bo_va);
 536                         radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 537                 }
 538
 539                 radeon_vm_fini(rdev, &fpriv->vm);
 540                 drm_free(fpriv, M_DRM);
 541                 file_priv->driver_priv = NULL;
 542         }
 543 }
 544
 545 /**
 546  * radeon_driver_preclose_kms - drm callback for pre close
 547  *
 548  * @dev: drm dev pointer
 549  * @file_priv: drm file
 550  *
 551  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
 552  * (all asics).
 553  */
 554 void radeon_driver_preclose_kms(struct drm_device *dev,
 555                                 struct drm_file *file_priv)
 556 {
 557         struct radeon_device *rdev = dev->dev_private;
 558         if (rdev->hyperz_filp == file_priv)
 559                 rdev->hyperz_filp = NULL;
 560         if (rdev->cmask_filp == file_priv)
 561                 rdev->cmask_filp = NULL;
 562         radeon_uvd_free_handles(rdev, file_priv);
 563 }
 564
 565 /*
 566  * VBlank related functions.
 567  */
 568 /**
 569  * radeon_get_vblank_counter_kms - get frame count
 570  *
 571  * @dev: drm dev pointer
 572  * @crtc: crtc to get the frame count from
 573  *
 574  * Gets the frame count on the requested crtc (all asics).
 575  * Returns frame count on success, -EINVAL on failure.
 576  */
 577 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 578 {
 579         struct radeon_device *rdev = dev->dev_private;
 580
 581         if (crtc < 0 || crtc >= rdev->num_crtc) {
 582                 DRM_ERROR("Invalid crtc %d\n", crtc);
 583                 return -EINVAL;
 584         }
 585
 586         return radeon_get_vblank_counter(rdev, crtc);
 587 }
 588
 589 /**
 590  * radeon_enable_vblank_kms - enable vblank interrupt
 591  *
 592  * @dev: drm dev pointer
 593  * @crtc: crtc to enable vblank interrupt for
 594  *
 595  * Enable the interrupt on the requested crtc (all asics).
 596  * Returns 0 on success, -EINVAL on failure.
 597  */
 598 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 599 {
 600         struct radeon_device *rdev = dev->dev_private;
 601         int r;
 602
 603         if (crtc < 0 || crtc >= rdev->num_crtc) {
 604                 DRM_ERROR("Invalid crtc %d\n", crtc);
 605                 return -EINVAL;
 606         }
 607
 608         lockmgr(&rdev->irq.lock, LK_EXCLUSIVE);
 609         rdev->irq.crtc_vblank_int[crtc] = true;
 610         r = radeon_irq_set(rdev);
 611         lockmgr(&rdev->irq.lock, LK_RELEASE);
 612         return r;
 613 }
 614
 615 /**
 616  * radeon_disable_vblank_kms - disable vblank interrupt
 617  *
 618  * @dev: drm dev pointer
 619  * @crtc: crtc to disable vblank interrupt for
 620  *
 621  * Disable the interrupt on the requested crtc (all asics).
 622  */
 623 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 624 {
 625         struct radeon_device *rdev = dev->dev_private;
 626
 627         if (crtc < 0 || crtc >= rdev->num_crtc) {
 628                 DRM_ERROR("Invalid crtc %d\n", crtc);
 629                 return;
 630         }
 631
 632         lockmgr(&rdev->irq.lock, LK_EXCLUSIVE);
 633         rdev->irq.crtc_vblank_int[crtc] = false;
 634         radeon_irq_set(rdev);
 635         lockmgr(&rdev->irq.lock, LK_RELEASE);
 636 }
 637
 638 /**
 639  * radeon_get_vblank_timestamp_kms - get vblank timestamp
 640  *
 641  * @dev: drm dev pointer
 642  * @crtc: crtc to get the timestamp for
 643  * @max_error: max error
 644  * @vblank_time: time value
 645  * @flags: flags passed to the driver
 646  *
 647  * Gets the timestamp on the requested crtc based on the
 648  * scanout position.  (all asics).
 649  * Returns postive status flags on success, negative error on failure.
 650  */
 651 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 652                                     int *max_error,
 653                                     struct timeval *vblank_time,
 654                                     unsigned flags)
 655 {
 656         struct drm_crtc *drmcrtc;
 657         struct radeon_device *rdev = dev->dev_private;
 658
 659         if (crtc < 0 || crtc >= dev->num_crtcs) {
 660                 DRM_ERROR("Invalid crtc %d\n", crtc);
 661                 return -EINVAL;
 662         }
 663
 664         /* Get associated drm_crtc: */
 665         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 666
 667         /* Helper routine in DRM core does all the work: */
 668         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 669                                                      vblank_time, flags,
 670                                                      drmcrtc);
 671 }
 672
 673 /*
 674  * IOCTL.
 675  */
 676 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
 677                          struct drm_file *file_priv)
 678 {
 679         /* Not valid in KMS. */
 680         return -EINVAL;
 681 }
 682
 683 #define KMS_INVALID_IOCTL(name)                                         \
 684 static int                                                              \
 685 name(struct drm_device *dev, void *data, struct drm_file *file_priv)    \
 686 {                                                                       \
 687         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 688         return -EINVAL;                                                 \
 689 }
 690
 691 /*
 692  * All these ioctls are invalid in kms world.
 693  */
 694 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 695 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 696 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 697 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 698 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 699 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 700 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 701 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 702 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 703 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 704 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 705 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 706 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 707 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 708 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 709 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 710 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 711 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 712 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 713 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 714 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 715 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 716 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 717 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 718 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 719 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 720 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 721
 722
 723 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 724         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 725         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 726         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 727         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 728         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 729         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 730         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 731         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 732         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 733         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 734         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 735         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 736         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 737         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 738         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 739         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 740         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 741         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 742         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 743         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 744         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 745         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 746         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 747         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 748         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 749         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 750         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 751         /* KMS */
 752         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 753         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
 754         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
 755         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
 756         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 757         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 758         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
 759         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
 760         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 761         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 762         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 763         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
 764         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
 765 };
 766 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);