sys/dev/drm/radeon/sid.h

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  *
  24  * $FreeBSD: head/sys/dev/drm2/radeon/sid.h 254885 2013-08-25 19:37:15Z dumbbell $
  25  */
  26 #ifndef SI_H
  27 #define SI_H
  28
  29 #define TAHITI_RB_BITMAP_WIDTH_PER_SH  2
  30
  31 #define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
  32 #define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002
  33 #define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001
  34
  35 /* discrete uvd clocks */
  36 #define CG_UPLL_FUNC_CNTL                               0x634
  37 #       define UPLL_RESET_MASK                          0x00000001
  38 #       define UPLL_SLEEP_MASK                          0x00000002
  39 #       define UPLL_BYPASS_EN_MASK                      0x00000004
  40 #       define UPLL_CTLREQ_MASK                         0x00000008
  41 #       define UPLL_VCO_MODE_MASK                       0x00000600
  42 #       define UPLL_REF_DIV_MASK                        0x003F0000
  43 #       define UPLL_CTLACK_MASK                         0x40000000
  44 #       define UPLL_CTLACK2_MASK                        0x80000000
  45 #define CG_UPLL_FUNC_CNTL_2                             0x638
  46 #       define UPLL_PDIV_A(x)                           ((x) << 0)
  47 #       define UPLL_PDIV_A_MASK                         0x0000007F
  48 #       define UPLL_PDIV_B(x)                           ((x) << 8)
  49 #       define UPLL_PDIV_B_MASK                         0x00007F00
  50 #       define VCLK_SRC_SEL(x)                          ((x) << 20)
  51 #       define VCLK_SRC_SEL_MASK                        0x01F00000
  52 #       define DCLK_SRC_SEL(x)                          ((x) << 25)
  53 #       define DCLK_SRC_SEL_MASK                        0x3E000000
  54 #define CG_UPLL_FUNC_CNTL_3                             0x63C
  55 #       define UPLL_FB_DIV(x)                           ((x) << 0)
  56 #       define UPLL_FB_DIV_MASK                         0x01FFFFFF
  57 #define CG_UPLL_FUNC_CNTL_4                             0x644
  58 #       define UPLL_SPARE_ISPARE9                       0x00020000
  59 #define CG_UPLL_FUNC_CNTL_5                             0x648
  60 #       define RESET_ANTI_MUX_MASK                      0x00000200
  61 #define CG_UPLL_SPREAD_SPECTRUM                         0x650
  62 #       define SSEN_MASK                                0x00000001
  63
  64 #define CG_MULT_THERMAL_STATUS                                  0x714
  65 #define         ASIC_MAX_TEMP(x)                                ((x) << 0)
  66 #define         ASIC_MAX_TEMP_MASK                              0x000001ff
  67 #define         ASIC_MAX_TEMP_SHIFT                             0
  68 #define         CTF_TEMP(x)                                     ((x) << 9)
  69 #define         CTF_TEMP_MASK                                   0x0003fe00
  70 #define         CTF_TEMP_SHIFT                                  9
  71
  72 #define SI_MAX_SH_GPRS           256
  73 #define SI_MAX_TEMP_GPRS         16
  74 #define SI_MAX_SH_THREADS        256
  75 #define SI_MAX_SH_STACK_ENTRIES  4096
  76 #define SI_MAX_FRC_EOV_CNT       16384
  77 #define SI_MAX_BACKENDS          8
  78 #define SI_MAX_BACKENDS_MASK     0xFF
  79 #define SI_MAX_BACKENDS_PER_SE_MASK     0x0F
  80 #define SI_MAX_SIMDS             12
  81 #define SI_MAX_SIMDS_MASK        0x0FFF
  82 #define SI_MAX_SIMDS_PER_SE_MASK        0x00FF
  83 #define SI_MAX_PIPES             8
  84 #define SI_MAX_PIPES_MASK        0xFF
  85 #define SI_MAX_PIPES_PER_SIMD_MASK      0x3F
  86 #define SI_MAX_LDS_NUM           0xFFFF
  87 #define SI_MAX_TCC               16
  88 #define SI_MAX_TCC_MASK          0xFFFF
  89
  90 #define VGA_HDP_CONTROL                                 0x328
  91 #define         VGA_MEMORY_DISABLE                              (1 << 4)
  92
  93 #define CG_CLKPIN_CNTL                                    0x660
  94 #       define XTALIN_DIVIDE                              (1 << 1)
  95 #define CG_CLKPIN_CNTL_2                                  0x664
  96 #       define MUX_TCLK_TO_XCLK                           (1 << 8)
  97
  98 #define DMIF_ADDR_CONFIG                                0xBD4
  99
 100 #define DMIF_ADDR_CALC                                  0xC00
 101
 102 #define SRBM_STATUS                                     0xE50
 103 #define         GRBM_RQ_PENDING                         (1 << 5)
 104 #define         VMC_BUSY                                (1 << 8)
 105 #define         MCB_BUSY                                (1 << 9)
 106 #define         MCB_NON_DISPLAY_BUSY                    (1 << 10)
 107 #define         MCC_BUSY                                (1 << 11)
 108 #define         MCD_BUSY                                (1 << 12)
 109 #define         SEM_BUSY                                (1 << 14)
 110 #define         IH_BUSY                                 (1 << 17)
 111
 112 #define SRBM_SOFT_RESET                                 0x0E60
 113 #define         SOFT_RESET_BIF                          (1 << 1)
 114 #define         SOFT_RESET_DC                           (1 << 5)
 115 #define         SOFT_RESET_DMA1                         (1 << 6)
 116 #define         SOFT_RESET_GRBM                         (1 << 8)
 117 #define         SOFT_RESET_HDP                          (1 << 9)
 118 #define         SOFT_RESET_IH                           (1 << 10)
 119 #define         SOFT_RESET_MC                           (1 << 11)
 120 #define         SOFT_RESET_ROM                          (1 << 14)
 121 #define         SOFT_RESET_SEM                          (1 << 15)
 122 #define         SOFT_RESET_VMC                          (1 << 17)
 123 #define         SOFT_RESET_DMA                          (1 << 20)
 124 #define         SOFT_RESET_TST                          (1 << 21)
 125 #define         SOFT_RESET_REGBB                        (1 << 22)
 126 #define         SOFT_RESET_ORB                          (1 << 23)
 127
 128 #define CC_SYS_RB_BACKEND_DISABLE                       0xe80
 129 #define GC_USER_SYS_RB_BACKEND_DISABLE                  0xe84
 130
 131 #define SRBM_STATUS2                                    0x0EC4
 132 #define         DMA_BUSY                                (1 << 5)
 133 #define         DMA1_BUSY                               (1 << 6)
 134
 135 #define VM_L2_CNTL                                      0x1400
 136 #define         ENABLE_L2_CACHE                                 (1 << 0)
 137 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
 138 #define         L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)                ((x) << 2)
 139 #define         L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)                ((x) << 4)
 140 #define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
 141 #define         ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE        (1 << 10)
 142 #define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 15)
 143 #define         CONTEXT1_IDENTITY_ACCESS_MODE(x)                (((x) & 3) << 19)
 144 #define VM_L2_CNTL2                                     0x1404
 145 #define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
 146 #define         INVALIDATE_L2_CACHE                             (1 << 1)
 147 #define         INVALIDATE_CACHE_MODE(x)                        ((x) << 26)
 148 #define                 INVALIDATE_PTE_AND_PDE_CACHES           0
 149 #define                 INVALIDATE_ONLY_PTE_CACHES              1
 150 #define                 INVALIDATE_ONLY_PDE_CACHES              2
 151 #define VM_L2_CNTL3                                     0x1408
 152 #define         BANK_SELECT(x)                                  ((x) << 0)
 153 #define         L2_CACHE_UPDATE_MODE(x)                         ((x) << 6)
 154 #define         L2_CACHE_BIGK_FRAGMENT_SIZE(x)                  ((x) << 15)
 155 #define         L2_CACHE_BIGK_ASSOCIATIVITY                     (1 << 20)
 156 #define VM_L2_STATUS                                    0x140C
 157 #define         L2_BUSY                                         (1 << 0)
 158 #define VM_CONTEXT0_CNTL                                0x1410
 159 #define         ENABLE_CONTEXT                                  (1 << 0)
 160 #define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
 161 #define         RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT         (1 << 3)
 162 #define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
 163 #define         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT    (1 << 6)
 164 #define         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT      (1 << 7)
 165 #define         PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT          (1 << 9)
 166 #define         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT            (1 << 10)
 167 #define         VALID_PROTECTION_FAULT_ENABLE_INTERRUPT         (1 << 12)
 168 #define         VALID_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 13)
 169 #define         READ_PROTECTION_FAULT_ENABLE_INTERRUPT          (1 << 15)
 170 #define         READ_PROTECTION_FAULT_ENABLE_DEFAULT            (1 << 16)
 171 #define         WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT         (1 << 18)
 172 #define         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 19)
 173 #define VM_CONTEXT1_CNTL                                0x1414
 174 #define VM_CONTEXT0_CNTL2                               0x1430
 175 #define VM_CONTEXT1_CNTL2                               0x1434
 176 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR                0x1438
 177 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR                0x143c
 178 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR               0x1440
 179 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR               0x1444
 180 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR               0x1448
 181 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR               0x144c
 182 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR               0x1450
 183 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR               0x1454
 184
 185 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR               0x14FC
 186 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS             0x14DC
 187
 188 #define VM_INVALIDATE_REQUEST                           0x1478
 189 #define VM_INVALIDATE_RESPONSE                          0x147c
 190
 191 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
 192 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR       0x151c
 193
 194 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153c
 195 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR                0x1540
 196 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR                0x1544
 197 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR                0x1548
 198 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR                0x154c
 199 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR                0x1550
 200 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR                0x1554
 201 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR                0x1558
 202 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155c
 203 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR               0x1560
 204
 205 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
 206 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR                 0x1580
 207
 208 #define MC_SHARED_CHMAP                                         0x2004
 209 #define         NOOFCHAN_SHIFT                                  12
 210 #define         NOOFCHAN_MASK                                   0x0000f000
 211 #define MC_SHARED_CHREMAP                                       0x2008
 212
 213 #define MC_VM_FB_LOCATION                               0x2024
 214 #define MC_VM_AGP_TOP                                   0x2028
 215 #define MC_VM_AGP_BOT                                   0x202C
 216 #define MC_VM_AGP_BASE                                  0x2030
 217 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
 218 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
 219 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
 220
 221 #define MC_VM_MX_L1_TLB_CNTL                            0x2064
 222 #define         ENABLE_L1_TLB                                   (1 << 0)
 223 #define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
 224 #define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
 225 #define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
 226 #define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
 227 #define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
 228 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
 229 #define         ENABLE_ADVANCED_DRIVER_MODEL                    (1 << 6)
 230
 231 #define MC_SHARED_BLACKOUT_CNTL                         0x20ac
 232
 233 #define MC_ARB_RAMCFG                                   0x2760
 234 #define         NOOFBANK_SHIFT                                  0
 235 #define         NOOFBANK_MASK                                   0x00000003
 236 #define         NOOFRANK_SHIFT                                  2
 237 #define         NOOFRANK_MASK                                   0x00000004
 238 #define         NOOFROWS_SHIFT                                  3
 239 #define         NOOFROWS_MASK                                   0x00000038
 240 #define         NOOFCOLS_SHIFT                                  6
 241 #define         NOOFCOLS_MASK                                   0x000000C0
 242 #define         CHANSIZE_SHIFT                                  8
 243 #define         CHANSIZE_MASK                                   0x00000100
 244 #define         CHANSIZE_OVERRIDE                               (1 << 11)
 245 #define         NOOFGROUPS_SHIFT                                12
 246 #define         NOOFGROUPS_MASK                                 0x00001000
 247
 248 #define MC_SEQ_TRAIN_WAKEUP_CNTL                        0x2808
 249 #define         TRAIN_DONE_D0                           (1 << 30)
 250 #define         TRAIN_DONE_D1                           (1 << 31)
 251
 252 #define MC_SEQ_SUP_CNTL                                 0x28c8
 253 #define         RUN_MASK                                (1 << 0)
 254 #define MC_SEQ_SUP_PGM                                  0x28cc
 255
 256 #define MC_IO_PAD_CNTL_D0                               0x29d0
 257 #define         MEM_FALL_OUT_CMD                        (1 << 8)
 258
 259 #define MC_SEQ_IO_DEBUG_INDEX                           0x2a44
 260 #define MC_SEQ_IO_DEBUG_DATA                            0x2a48
 261
 262 #define HDP_HOST_PATH_CNTL                              0x2C00
 263 #define HDP_NONSURFACE_BASE                             0x2C04
 264 #define HDP_NONSURFACE_INFO                             0x2C08
 265 #define HDP_NONSURFACE_SIZE                             0x2C0C
 266
 267 #define HDP_ADDR_CONFIG                                 0x2F48
 268 #define HDP_MISC_CNTL                                   0x2F4C
 269 #define         HDP_FLUSH_INVALIDATE_CACHE                      (1 << 0)
 270
 271 #define IH_RB_CNTL                                        0x3e00
 272 #       define IH_RB_ENABLE                               (1 << 0)
 273 #       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
 274 #       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
 275 #       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
 276 #       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
 277 #       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
 278 #       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
 279 #define IH_RB_BASE                                        0x3e04
 280 #define IH_RB_RPTR                                        0x3e08
 281 #define IH_RB_WPTR                                        0x3e0c
 282 #       define RB_OVERFLOW                                (1 << 0)
 283 #       define WPTR_OFFSET_MASK                           0x3fffc
 284 #define IH_RB_WPTR_ADDR_HI                                0x3e10
 285 #define IH_RB_WPTR_ADDR_LO                                0x3e14
 286 #define IH_CNTL                                           0x3e18
 287 #       define ENABLE_INTR                                (1 << 0)
 288 #       define IH_MC_SWAP(x)                              ((x) << 1)
 289 #       define IH_MC_SWAP_NONE                            0
 290 #       define IH_MC_SWAP_16BIT                           1
 291 #       define IH_MC_SWAP_32BIT                           2
 292 #       define IH_MC_SWAP_64BIT                           3
 293 #       define RPTR_REARM                                 (1 << 4)
 294 #       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
 295 #       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
 296 #       define MC_VMID(x)                                 ((x) << 25)
 297
 298 #define CONFIG_MEMSIZE                                  0x5428
 299
 300 #define INTERRUPT_CNTL                                    0x5468
 301 #       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)
 302 #       define IH_DUMMY_RD_EN                             (1 << 1)
 303 #       define IH_REQ_NONSNOOP_EN                         (1 << 3)
 304 #       define GEN_IH_INT_EN                              (1 << 8)
 305 #define INTERRUPT_CNTL2                                   0x546c
 306
 307 #define HDP_MEM_COHERENCY_FLUSH_CNTL                    0x5480
 308
 309 #define BIF_FB_EN                                               0x5490
 310 #define         FB_READ_EN                                      (1 << 0)
 311 #define         FB_WRITE_EN                                     (1 << 1)
 312
 313 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
 314
 315 #define DC_LB_MEMORY_SPLIT                                      0x6b0c
 316 #define         DC_LB_MEMORY_CONFIG(x)                          ((x) << 20)
 317
 318 #define PRIORITY_A_CNT                                          0x6b18
 319 #define         PRIORITY_MARK_MASK                              0x7fff
 320 #define         PRIORITY_OFF                                    (1 << 16)
 321 #define         PRIORITY_ALWAYS_ON                              (1 << 20)
 322 #define PRIORITY_B_CNT                                          0x6b1c
 323
 324 #define DPG_PIPE_ARBITRATION_CONTROL3                           0x6cc8
 325 #       define LATENCY_WATERMARK_MASK(x)                        ((x) << 16)
 326 #define DPG_PIPE_LATENCY_CONTROL                                0x6ccc
 327 #       define LATENCY_LOW_WATERMARK(x)                         ((x) << 0)
 328 #       define LATENCY_HIGH_WATERMARK(x)                        ((x) << 16)
 329
 330 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
 331 #define VLINE_STATUS                                    0x6bb8
 332 #       define VLINE_OCCURRED                           (1 << 0)
 333 #       define VLINE_ACK                                (1 << 4)
 334 #       define VLINE_STAT                               (1 << 12)
 335 #       define VLINE_INTERRUPT                          (1 << 16)
 336 #       define VLINE_INTERRUPT_TYPE                     (1 << 17)
 337 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
 338 #define VBLANK_STATUS                                   0x6bbc
 339 #       define VBLANK_OCCURRED                          (1 << 0)
 340 #       define VBLANK_ACK                               (1 << 4)
 341 #       define VBLANK_STAT                              (1 << 12)
 342 #       define VBLANK_INTERRUPT                         (1 << 16)
 343 #       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
 344
 345 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
 346 #define INT_MASK                                        0x6b40
 347 #       define VBLANK_INT_MASK                          (1 << 0)
 348 #       define VLINE_INT_MASK                           (1 << 4)
 349
 350 #define DISP_INTERRUPT_STATUS                           0x60f4
 351 #       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
 352 #       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
 353 #       define DC_HPD1_INTERRUPT                        (1 << 17)
 354 #       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
 355 #       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
 356 #       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
 357 #       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
 358 #       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
 359 #define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
 360 #       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
 361 #       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
 362 #       define DC_HPD2_INTERRUPT                        (1 << 17)
 363 #       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
 364 #       define DISP_TIMER_INTERRUPT                     (1 << 24)
 365 #define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
 366 #       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
 367 #       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
 368 #       define DC_HPD3_INTERRUPT                        (1 << 17)
 369 #       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
 370 #define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
 371 #       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
 372 #       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
 373 #       define DC_HPD4_INTERRUPT                        (1 << 17)
 374 #       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
 375 #define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
 376 #       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
 377 #       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
 378 #       define DC_HPD5_INTERRUPT                        (1 << 17)
 379 #       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
 380 #define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150
 381 #       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
 382 #       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
 383 #       define DC_HPD6_INTERRUPT                        (1 << 17)
 384 #       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
 385
 386 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
 387 #define GRPH_INT_STATUS                                 0x6858
 388 #       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
 389 #       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
 390 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
 391 #define GRPH_INT_CONTROL                                0x685c
 392 #       define GRPH_PFLIP_INT_MASK                      (1 << 0)
 393 #       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
 394
 395 #define DACA_AUTODETECT_INT_CONTROL                     0x66c8
 396
 397 #define DC_HPD1_INT_STATUS                              0x601c
 398 #define DC_HPD2_INT_STATUS                              0x6028
 399 #define DC_HPD3_INT_STATUS                              0x6034
 400 #define DC_HPD4_INT_STATUS                              0x6040
 401 #define DC_HPD5_INT_STATUS                              0x604c
 402 #define DC_HPD6_INT_STATUS                              0x6058
 403 #       define DC_HPDx_INT_STATUS                       (1 << 0)
 404 #       define DC_HPDx_SENSE                            (1 << 1)
 405 #       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
 406
 407 #define DC_HPD1_INT_CONTROL                             0x6020
 408 #define DC_HPD2_INT_CONTROL                             0x602c
 409 #define DC_HPD3_INT_CONTROL                             0x6038
 410 #define DC_HPD4_INT_CONTROL                             0x6044
 411 #define DC_HPD5_INT_CONTROL                             0x6050
 412 #define DC_HPD6_INT_CONTROL                             0x605c
 413 #       define DC_HPDx_INT_ACK                          (1 << 0)
 414 #       define DC_HPDx_INT_POLARITY                     (1 << 8)
 415 #       define DC_HPDx_INT_EN                           (1 << 16)
 416 #       define DC_HPDx_RX_INT_ACK                       (1 << 20)
 417 #       define DC_HPDx_RX_INT_EN                        (1 << 24)
 418
 419 #define DC_HPD1_CONTROL                                   0x6024
 420 #define DC_HPD2_CONTROL                                   0x6030
 421 #define DC_HPD3_CONTROL                                   0x603c
 422 #define DC_HPD4_CONTROL                                   0x6048
 423 #define DC_HPD5_CONTROL                                   0x6054
 424 #define DC_HPD6_CONTROL                                   0x6060
 425 #       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
 426 #       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
 427 #       define DC_HPDx_EN                                 (1 << 28)
 428
 429 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
 430 #define CRTC_STATUS_FRAME_COUNT                         0x6e98
 431
 432 #define GRBM_CNTL                                       0x8000
 433 #define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
 434
 435 #define GRBM_STATUS2                                    0x8008
 436 #define         RLC_RQ_PENDING                                  (1 << 0)
 437 #define         RLC_BUSY                                        (1 << 8)
 438 #define         TC_BUSY                                         (1 << 9)
 439
 440 #define GRBM_STATUS                                     0x8010
 441 #define         CMDFIFO_AVAIL_MASK                              0x0000000F
 442 #define         RING2_RQ_PENDING                                (1 << 4)
 443 #define         SRBM_RQ_PENDING                                 (1 << 5)
 444 #define         RING1_RQ_PENDING                                (1 << 6)
 445 #define         CF_RQ_PENDING                                   (1 << 7)
 446 #define         PF_RQ_PENDING                                   (1 << 8)
 447 #define         GDS_DMA_RQ_PENDING                              (1 << 9)
 448 #define         GRBM_EE_BUSY                                    (1 << 10)
 449 #define         DB_CLEAN                                        (1 << 12)
 450 #define         CB_CLEAN                                        (1 << 13)
 451 #define         TA_BUSY                                         (1 << 14)
 452 #define         GDS_BUSY                                        (1 << 15)
 453 #define         VGT_BUSY                                        (1 << 17)
 454 #define         IA_BUSY_NO_DMA                                  (1 << 18)
 455 #define         IA_BUSY                                         (1 << 19)
 456 #define         SX_BUSY                                         (1 << 20)
 457 #define         SPI_BUSY                                        (1 << 22)
 458 #define         BCI_BUSY                                        (1 << 23)
 459 #define         SC_BUSY                                         (1 << 24)
 460 #define         PA_BUSY                                         (1 << 25)
 461 #define         DB_BUSY                                         (1 << 26)
 462 #define         CP_COHERENCY_BUSY                               (1 << 28)
 463 #define         CP_BUSY                                         (1 << 29)
 464 #define         CB_BUSY                                         (1 << 30)
 465 #define         GUI_ACTIVE                                      (1 << 31)
 466 #define GRBM_STATUS_SE0                                 0x8014
 467 #define GRBM_STATUS_SE1                                 0x8018
 468 #define         SE_DB_CLEAN                                     (1 << 1)
 469 #define         SE_CB_CLEAN                                     (1 << 2)
 470 #define         SE_BCI_BUSY                                     (1 << 22)
 471 #define         SE_VGT_BUSY                                     (1 << 23)
 472 #define         SE_PA_BUSY                                      (1 << 24)
 473 #define         SE_TA_BUSY                                      (1 << 25)
 474 #define         SE_SX_BUSY                                      (1 << 26)
 475 #define         SE_SPI_BUSY                                     (1 << 27)
 476 #define         SE_SC_BUSY                                      (1 << 29)
 477 #define         SE_DB_BUSY                                      (1 << 30)
 478 #define         SE_CB_BUSY                                      (1 << 31)
 479
 480 #define GRBM_SOFT_RESET                                 0x8020
 481 #define         SOFT_RESET_CP                                   (1 << 0)
 482 #define         SOFT_RESET_CB                                   (1 << 1)
 483 #define         SOFT_RESET_RLC                                  (1 << 2)
 484 #define         SOFT_RESET_DB                                   (1 << 3)
 485 #define         SOFT_RESET_GDS                                  (1 << 4)
 486 #define         SOFT_RESET_PA                                   (1 << 5)
 487 #define         SOFT_RESET_SC                                   (1 << 6)
 488 #define         SOFT_RESET_BCI                                  (1 << 7)
 489 #define         SOFT_RESET_SPI                                  (1 << 8)
 490 #define         SOFT_RESET_SX                                   (1 << 10)
 491 #define         SOFT_RESET_TC                                   (1 << 11)
 492 #define         SOFT_RESET_TA                                   (1 << 12)
 493 #define         SOFT_RESET_VGT                                  (1 << 14)
 494 #define         SOFT_RESET_IA                                   (1 << 15)
 495
 496 #define GRBM_GFX_INDEX                                  0x802C
 497 #define         INSTANCE_INDEX(x)                       ((x) << 0)
 498 #define         SH_INDEX(x)                             ((x) << 8)
 499 #define         SE_INDEX(x)                             ((x) << 16)
 500 #define         SH_BROADCAST_WRITES                     (1 << 29)
 501 #define         INSTANCE_BROADCAST_WRITES               (1 << 30)
 502 #define         SE_BROADCAST_WRITES                     (1 << 31)
 503
 504 #define GRBM_INT_CNTL                                   0x8060
 505 #       define RDERR_INT_ENABLE                         (1 << 0)
 506 #       define GUI_IDLE_INT_ENABLE                      (1 << 19)
 507
 508 #define CP_STRMOUT_CNTL                                 0x84FC
 509 #define SCRATCH_REG0                                    0x8500
 510 #define SCRATCH_REG1                                    0x8504
 511 #define SCRATCH_REG2                                    0x8508
 512 #define SCRATCH_REG3                                    0x850C
 513 #define SCRATCH_REG4                                    0x8510
 514 #define SCRATCH_REG5                                    0x8514
 515 #define SCRATCH_REG6                                    0x8518
 516 #define SCRATCH_REG7                                    0x851C
 517
 518 #define SCRATCH_UMSK                                    0x8540
 519 #define SCRATCH_ADDR                                    0x8544
 520
 521 #define CP_SEM_WAIT_TIMER                               0x85BC
 522
 523 #define CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
 524
 525 #define CP_ME_CNTL                                      0x86D8
 526 #define         CP_CE_HALT                                      (1 << 24)
 527 #define         CP_PFP_HALT                                     (1 << 26)
 528 #define         CP_ME_HALT                                      (1 << 28)
 529
 530 #define CP_COHER_CNTL2                                  0x85E8
 531
 532 #define CP_RB2_RPTR                                     0x86f8
 533 #define CP_RB1_RPTR                                     0x86fc
 534 #define CP_RB0_RPTR                                     0x8700
 535 #define CP_RB_WPTR_DELAY                                0x8704
 536
 537 #define CP_QUEUE_THRESHOLDS                             0x8760
 538 #define         ROQ_IB1_START(x)                                ((x) << 0)
 539 #define         ROQ_IB2_START(x)                                ((x) << 8)
 540 #define CP_MEQ_THRESHOLDS                               0x8764
 541 #define         MEQ1_START(x)                           ((x) << 0)
 542 #define         MEQ2_START(x)                           ((x) << 8)
 543
 544 #define CP_PERFMON_CNTL                                 0x87FC
 545
 546 #define VGT_VTX_VECT_EJECT_REG                          0x88B0
 547
 548 #define VGT_CACHE_INVALIDATION                          0x88C4
 549 #define         CACHE_INVALIDATION(x)                           ((x) << 0)
 550 #define                 VC_ONLY                                         0
 551 #define                 TC_ONLY                                         1
 552 #define                 VC_AND_TC                                       2
 553 #define         AUTO_INVLD_EN(x)                                ((x) << 6)
 554 #define                 NO_AUTO                                         0
 555 #define                 ES_AUTO                                         1
 556 #define                 GS_AUTO                                         2
 557 #define                 ES_AND_GS_AUTO                                  3
 558 #define VGT_ESGS_RING_SIZE                              0x88C8
 559 #define VGT_GSVS_RING_SIZE                              0x88CC
 560
 561 #define VGT_GS_VERTEX_REUSE                             0x88D4
 562
 563 #define VGT_PRIMITIVE_TYPE                              0x8958
 564 #define VGT_INDEX_TYPE                                  0x895C
 565
 566 #define VGT_NUM_INDICES                                 0x8970
 567 #define VGT_NUM_INSTANCES                               0x8974
 568
 569 #define VGT_TF_RING_SIZE                                0x8988
 570
 571 #define VGT_HS_OFFCHIP_PARAM                            0x89B0
 572
 573 #define VGT_TF_MEMORY_BASE                              0x89B8
 574
 575 #define CC_GC_SHADER_ARRAY_CONFIG                       0x89bc
 576 #define         INACTIVE_CUS_MASK                       0xFFFF0000
 577 #define         INACTIVE_CUS_SHIFT                      16
 578 #define GC_USER_SHADER_ARRAY_CONFIG                     0x89c0
 579
 580 #define PA_CL_ENHANCE                                   0x8A14
 581 #define         CLIP_VTX_REORDER_ENA                            (1 << 0)
 582 #define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
 583
 584 #define PA_SU_LINE_STIPPLE_VALUE                        0x8A60
 585
 586 #define PA_SC_LINE_STIPPLE_STATE                        0x8B10
 587
 588 #define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
 589 #define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
 590 #define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
 591
 592 #define PA_SC_FIFO_SIZE                                 0x8BCC
 593 #define         SC_FRONTEND_PRIM_FIFO_SIZE(x)                   ((x) << 0)
 594 #define         SC_BACKEND_PRIM_FIFO_SIZE(x)                    ((x) << 6)
 595 #define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 15)
 596 #define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 23)
 597
 598 #define PA_SC_ENHANCE                                   0x8BF0
 599
 600 #define SQ_CONFIG                                       0x8C00
 601
 602 #define SQC_CACHES                                      0x8C08
 603
 604 #define SX_DEBUG_1                                      0x9060
 605
 606 #define SPI_STATIC_THREAD_MGMT_1                        0x90E0
 607 #define SPI_STATIC_THREAD_MGMT_2                        0x90E4
 608 #define SPI_STATIC_THREAD_MGMT_3                        0x90E8
 609 #define SPI_PS_MAX_WAVE_ID                              0x90EC
 610
 611 #define SPI_CONFIG_CNTL                                 0x9100
 612
 613 #define SPI_CONFIG_CNTL_1                               0x913C
 614 #define         VTX_DONE_DELAY(x)                               ((x) << 0)
 615 #define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
 616
 617 #define CGTS_TCC_DISABLE                                0x9148
 618 #define CGTS_USER_TCC_DISABLE                           0x914C
 619 #define         TCC_DISABLE_MASK                                0xFFFF0000
 620 #define         TCC_DISABLE_SHIFT                               16
 621
 622 #define TA_CNTL_AUX                                     0x9508
 623
 624 #define CC_RB_BACKEND_DISABLE                           0x98F4
 625 #define         BACKEND_DISABLE(x)                      ((x) << 16)
 626 #define GB_ADDR_CONFIG                                  0x98F8
 627 #define         NUM_PIPES(x)                            ((x) << 0)
 628 #define         NUM_PIPES_MASK                          0x00000007
 629 #define         NUM_PIPES_SHIFT                         0
 630 #define         PIPE_INTERLEAVE_SIZE(x)                 ((x) << 4)
 631 #define         PIPE_INTERLEAVE_SIZE_MASK               0x00000070
 632 #define         PIPE_INTERLEAVE_SIZE_SHIFT              4
 633 #define         NUM_SHADER_ENGINES(x)                   ((x) << 12)
 634 #define         NUM_SHADER_ENGINES_MASK                 0x00003000
 635 #define         NUM_SHADER_ENGINES_SHIFT                12
 636 #define         SHADER_ENGINE_TILE_SIZE(x)              ((x) << 16)
 637 #define         SHADER_ENGINE_TILE_SIZE_MASK            0x00070000
 638 #define         SHADER_ENGINE_TILE_SIZE_SHIFT           16
 639 #define         NUM_GPUS(x)                             ((x) << 20)
 640 #define         NUM_GPUS_MASK                           0x00700000
 641 #define         NUM_GPUS_SHIFT                          20
 642 #define         MULTI_GPU_TILE_SIZE(x)                  ((x) << 24)
 643 #define         MULTI_GPU_TILE_SIZE_MASK                0x03000000
 644 #define         MULTI_GPU_TILE_SIZE_SHIFT               24
 645 #define         ROW_SIZE(x)                             ((x) << 28)
 646 #define         ROW_SIZE_MASK                           0x30000000
 647 #define         ROW_SIZE_SHIFT                          28
 648
 649 #define GB_TILE_MODE0                                   0x9910
 650 #       define MICRO_TILE_MODE(x)                               ((x) << 0)
 651 #              define   ADDR_SURF_DISPLAY_MICRO_TILING          0
 652 #              define   ADDR_SURF_THIN_MICRO_TILING             1
 653 #              define   ADDR_SURF_DEPTH_MICRO_TILING            2
 654 #       define ARRAY_MODE(x)                                    ((x) << 2)
 655 #              define   ARRAY_LINEAR_GENERAL                    0
 656 #              define   ARRAY_LINEAR_ALIGNED                    1
 657 #              define   ARRAY_1D_TILED_THIN1                    2
 658 #              define   ARRAY_2D_TILED_THIN1                    4
 659 #       define PIPE_CONFIG(x)                                   ((x) << 6)
 660 #              define   ADDR_SURF_P2                            0
 661 #              define   ADDR_SURF_P4_8x16                       4
 662 #              define   ADDR_SURF_P4_16x16                      5
 663 #              define   ADDR_SURF_P4_16x32                      6
 664 #              define   ADDR_SURF_P4_32x32                      7
 665 #              define   ADDR_SURF_P8_16x16_8x16                 8
 666 #              define   ADDR_SURF_P8_16x32_8x16                 9
 667 #              define   ADDR_SURF_P8_32x32_8x16                 10
 668 #              define   ADDR_SURF_P8_16x32_16x16                11
 669 #              define   ADDR_SURF_P8_32x32_16x16                12
 670 #              define   ADDR_SURF_P8_32x32_16x32                13
 671 #              define   ADDR_SURF_P8_32x64_32x32                14
 672 #       define TILE_SPLIT(x)                                    ((x) << 11)
 673 #              define   ADDR_SURF_TILE_SPLIT_64B                0
 674 #              define   ADDR_SURF_TILE_SPLIT_128B               1
 675 #              define   ADDR_SURF_TILE_SPLIT_256B               2
 676 #              define   ADDR_SURF_TILE_SPLIT_512B               3
 677 #              define   ADDR_SURF_TILE_SPLIT_1KB                4
 678 #              define   ADDR_SURF_TILE_SPLIT_2KB                5
 679 #              define   ADDR_SURF_TILE_SPLIT_4KB                6
 680 #       define BANK_WIDTH(x)                                    ((x) << 14)
 681 #              define   ADDR_SURF_BANK_WIDTH_1                  0
 682 #              define   ADDR_SURF_BANK_WIDTH_2                  1
 683 #              define   ADDR_SURF_BANK_WIDTH_4                  2
 684 #              define   ADDR_SURF_BANK_WIDTH_8                  3
 685 #       define BANK_HEIGHT(x)                                   ((x) << 16)
 686 #              define   ADDR_SURF_BANK_HEIGHT_1                 0
 687 #              define   ADDR_SURF_BANK_HEIGHT_2                 1
 688 #              define   ADDR_SURF_BANK_HEIGHT_4                 2
 689 #              define   ADDR_SURF_BANK_HEIGHT_8                 3
 690 #       define MACRO_TILE_ASPECT(x)                             ((x) << 18)
 691 #              define   ADDR_SURF_MACRO_ASPECT_1                0
 692 #              define   ADDR_SURF_MACRO_ASPECT_2                1
 693 #              define   ADDR_SURF_MACRO_ASPECT_4                2
 694 #              define   ADDR_SURF_MACRO_ASPECT_8                3
 695 #       define NUM_BANKS(x)                                     ((x) << 20)
 696 #              define   ADDR_SURF_2_BANK                        0
 697 #              define   ADDR_SURF_4_BANK                        1
 698 #              define   ADDR_SURF_8_BANK                        2
 699 #              define   ADDR_SURF_16_BANK                       3
 700
 701 #define CB_PERFCOUNTER0_SELECT0                         0x9a20
 702 #define CB_PERFCOUNTER0_SELECT1                         0x9a24
 703 #define CB_PERFCOUNTER1_SELECT0                         0x9a28
 704 #define CB_PERFCOUNTER1_SELECT1                         0x9a2c
 705 #define CB_PERFCOUNTER2_SELECT0                         0x9a30
 706 #define CB_PERFCOUNTER2_SELECT1                         0x9a34
 707 #define CB_PERFCOUNTER3_SELECT0                         0x9a38
 708 #define CB_PERFCOUNTER3_SELECT1                         0x9a3c
 709
 710 #define GC_USER_RB_BACKEND_DISABLE                      0x9B7C
 711 #define         BACKEND_DISABLE_MASK                    0x00FF0000
 712 #define         BACKEND_DISABLE_SHIFT                   16
 713
 714 #define TCP_CHAN_STEER_LO                               0xac0c
 715 #define TCP_CHAN_STEER_HI                               0xac10
 716
 717 #define CP_RB0_BASE                                     0xC100
 718 #define CP_RB0_CNTL                                     0xC104
 719 #define         RB_BUFSZ(x)                                     ((x) << 0)
 720 #define         RB_BLKSZ(x)                                     ((x) << 8)
 721 #define         BUF_SWAP_32BIT                                  (2 << 16)
 722 #define         RB_NO_UPDATE                                    (1 << 27)
 723 #define         RB_RPTR_WR_ENA                                  (1 << 31)
 724
 725 #define CP_RB0_RPTR_ADDR                                0xC10C
 726 #define CP_RB0_RPTR_ADDR_HI                             0xC110
 727 #define CP_RB0_WPTR                                     0xC114
 728
 729 #define CP_PFP_UCODE_ADDR                               0xC150
 730 #define CP_PFP_UCODE_DATA                               0xC154
 731 #define CP_ME_RAM_RADDR                                 0xC158
 732 #define CP_ME_RAM_WADDR                                 0xC15C
 733 #define CP_ME_RAM_DATA                                  0xC160
 734
 735 #define CP_CE_UCODE_ADDR                                0xC168
 736 #define CP_CE_UCODE_DATA                                0xC16C
 737
 738 #define CP_RB1_BASE                                     0xC180
 739 #define CP_RB1_CNTL                                     0xC184
 740 #define CP_RB1_RPTR_ADDR                                0xC188
 741 #define CP_RB1_RPTR_ADDR_HI                             0xC18C
 742 #define CP_RB1_WPTR                                     0xC190
 743 #define CP_RB2_BASE                                     0xC194
 744 #define CP_RB2_CNTL                                     0xC198
 745 #define CP_RB2_RPTR_ADDR                                0xC19C
 746 #define CP_RB2_RPTR_ADDR_HI                             0xC1A0
 747 #define CP_RB2_WPTR                                     0xC1A4
 748 #define CP_INT_CNTL_RING0                               0xC1A8
 749 #define CP_INT_CNTL_RING1                               0xC1AC
 750 #define CP_INT_CNTL_RING2                               0xC1B0
 751 #       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
 752 #       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
 753 #       define WAIT_MEM_SEM_INT_ENABLE                  (1 << 21)
 754 #       define TIME_STAMP_INT_ENABLE                    (1 << 26)
 755 #       define CP_RINGID2_INT_ENABLE                    (1 << 29)
 756 #       define CP_RINGID1_INT_ENABLE                    (1 << 30)
 757 #       define CP_RINGID0_INT_ENABLE                    (1 << 31)
 758 #define CP_INT_STATUS_RING0                             0xC1B4
 759 #define CP_INT_STATUS_RING1                             0xC1B8
 760 #define CP_INT_STATUS_RING2                             0xC1BC
 761 #       define WAIT_MEM_SEM_INT_STAT                    (1 << 21)
 762 #       define TIME_STAMP_INT_STAT                      (1 << 26)
 763 #       define CP_RINGID2_INT_STAT                      (1 << 29)
 764 #       define CP_RINGID1_INT_STAT                      (1 << 30)
 765 #       define CP_RINGID0_INT_STAT                      (1 << 31)
 766
 767 #define CP_DEBUG                                        0xC1FC
 768
 769 #define RLC_CNTL                                          0xC300
 770 #       define RLC_ENABLE                                 (1 << 0)
 771 #define RLC_RL_BASE                                       0xC304
 772 #define RLC_RL_SIZE                                       0xC308
 773 #define RLC_LB_CNTL                                       0xC30C
 774 #define RLC_SAVE_AND_RESTORE_BASE                         0xC310
 775 #define RLC_LB_CNTR_MAX                                   0xC314
 776 #define RLC_LB_CNTR_INIT                                  0xC318
 777
 778 #define RLC_CLEAR_STATE_RESTORE_BASE                      0xC320
 779
 780 #define RLC_UCODE_ADDR                                    0xC32C
 781 #define RLC_UCODE_DATA                                    0xC330
 782
 783 #define RLC_GPU_CLOCK_COUNT_LSB                           0xC338
 784 #define RLC_GPU_CLOCK_COUNT_MSB                           0xC33C
 785 #define RLC_CAPTURE_GPU_CLOCK_COUNT                       0xC340
 786 #define RLC_MC_CNTL                                       0xC344
 787 #define RLC_UCODE_CNTL                                    0xC348
 788
 789 #define PA_SC_RASTER_CONFIG                             0x28350
 790 #       define RASTER_CONFIG_RB_MAP_0                   0
 791 #       define RASTER_CONFIG_RB_MAP_1                   1
 792 #       define RASTER_CONFIG_RB_MAP_2                   2
 793 #       define RASTER_CONFIG_RB_MAP_3                   3
 794
 795 #define VGT_EVENT_INITIATOR                             0x28a90
 796 #       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
 797 #       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)
 798 #       define SAMPLE_STREAMOUTSTATS3                   (3 << 0)
 799 #       define CACHE_FLUSH_TS                           (4 << 0)
 800 #       define CACHE_FLUSH                              (6 << 0)
 801 #       define CS_PARTIAL_FLUSH                         (7 << 0)
 802 #       define VGT_STREAMOUT_RESET                      (10 << 0)
 803 #       define END_OF_PIPE_INCR_DE                      (11 << 0)
 804 #       define END_OF_PIPE_IB_END                       (12 << 0)
 805 #       define RST_PIX_CNT                              (13 << 0)
 806 #       define VS_PARTIAL_FLUSH                         (15 << 0)
 807 #       define PS_PARTIAL_FLUSH                         (16 << 0)
 808 #       define CACHE_FLUSH_AND_INV_TS_EVENT             (20 << 0)
 809 #       define ZPASS_DONE                               (21 << 0)
 810 #       define CACHE_FLUSH_AND_INV_EVENT                (22 << 0)
 811 #       define PERFCOUNTER_START                        (23 << 0)
 812 #       define PERFCOUNTER_STOP                         (24 << 0)
 813 #       define PIPELINESTAT_START                       (25 << 0)
 814 #       define PIPELINESTAT_STOP                        (26 << 0)
 815 #       define PERFCOUNTER_SAMPLE                       (27 << 0)
 816 #       define SAMPLE_PIPELINESTAT                      (30 << 0)
 817 #       define SAMPLE_STREAMOUTSTATS                    (32 << 0)
 818 #       define RESET_VTX_CNT                            (33 << 0)
 819 #       define VGT_FLUSH                                (36 << 0)
 820 #       define BOTTOM_OF_PIPE_TS                        (40 << 0)
 821 #       define DB_CACHE_FLUSH_AND_INV                   (42 << 0)
 822 #       define FLUSH_AND_INV_DB_DATA_TS                 (43 << 0)
 823 #       define FLUSH_AND_INV_DB_META                    (44 << 0)
 824 #       define FLUSH_AND_INV_CB_DATA_TS                 (45 << 0)
 825 #       define FLUSH_AND_INV_CB_META                    (46 << 0)
 826 #       define CS_DONE                                  (47 << 0)
 827 #       define PS_DONE                                  (48 << 0)
 828 #       define FLUSH_AND_INV_CB_PIXEL_DATA              (49 << 0)
 829 #       define THREAD_TRACE_START                       (51 << 0)
 830 #       define THREAD_TRACE_STOP                        (52 << 0)
 831 #       define THREAD_TRACE_FLUSH                       (54 << 0)
 832 #       define THREAD_TRACE_FINISH                      (55 << 0)
 833
 834 /*
 835  * UVD
 836  */
 837 #define UVD_UDEC_ADDR_CONFIG                            0xEF4C
 838 #define UVD_UDEC_DB_ADDR_CONFIG                         0xEF50
 839 #define UVD_UDEC_DBW_ADDR_CONFIG                        0xEF54
 840 #define UVD_RBC_RB_RPTR                                 0xF690
 841 #define UVD_RBC_RB_WPTR                                 0xF694
 842
 843 /*
 844  * PM4
 845  */
 846 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) |                  \
 847                          (((reg) >> 2) & 0xFFFF) |                      \
 848                          ((n) & 0x3FFF) << 16)
 849 #define CP_PACKET2                      0x80000000
 850 #define         PACKET2_PAD_SHIFT               0
 851 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
 852
 853 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
 854
 855 #define PACKET3(op, n)  ((RADEON_PACKET_TYPE3 << 30) |                  \
 856                          (((op) & 0xFF) << 8) |                         \
 857                          ((n) & 0x3FFF) << 16)
 858
 859 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
 860
 861 /* Packet 3 types */
 862 #define PACKET3_NOP                                     0x10
 863 #define PACKET3_SET_BASE                                0x11
 864 #define         PACKET3_BASE_INDEX(x)                  ((x) << 0)
 865 #define                 GDS_PARTITION_BASE              2
 866 #define                 CE_PARTITION_BASE               3
 867 #define PACKET3_CLEAR_STATE                             0x12
 868 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
 869 #define PACKET3_DISPATCH_DIRECT                         0x15
 870 #define PACKET3_DISPATCH_INDIRECT                       0x16
 871 #define PACKET3_ALLOC_GDS                               0x1B
 872 #define PACKET3_WRITE_GDS_RAM                           0x1C
 873 #define PACKET3_ATOMIC_GDS                              0x1D
 874 #define PACKET3_ATOMIC                                  0x1E
 875 #define PACKET3_OCCLUSION_QUERY                         0x1F
 876 #define PACKET3_SET_PREDICATION                         0x20
 877 #define PACKET3_REG_RMW                                 0x21
 878 #define PACKET3_COND_EXEC                               0x22
 879 #define PACKET3_PRED_EXEC                               0x23
 880 #define PACKET3_DRAW_INDIRECT                           0x24
 881 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
 882 #define PACKET3_INDEX_BASE                              0x26
 883 #define PACKET3_DRAW_INDEX_2                            0x27
 884 #define PACKET3_CONTEXT_CONTROL                         0x28
 885 #define PACKET3_INDEX_TYPE                              0x2A
 886 #define PACKET3_DRAW_INDIRECT_MULTI                     0x2C
 887 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
 888 #define PACKET3_DRAW_INDEX_IMMD                         0x2E
 889 #define PACKET3_NUM_INSTANCES                           0x2F
 890 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
 891 #define PACKET3_INDIRECT_BUFFER_CONST                   0x31
 892 #define PACKET3_INDIRECT_BUFFER                         0x32
 893 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
 894 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
 895 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT                0x36
 896 #define PACKET3_WRITE_DATA                              0x37
 897 #define         WRITE_DATA_DST_SEL(x)                   ((x) << 8)
 898                 /* 0 - register
 899                  * 1 - memory (sync - via GRBM)
 900                  * 2 - tc/l2
 901                  * 3 - gds
 902                  * 4 - reserved
 903                  * 5 - memory (async - direct)
 904                  */
 905 #define         WR_ONE_ADDR                             (1 << 16)
 906 #define         WR_CONFIRM                              (1 << 20)
 907 #define         WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
 908                 /* 0 - me
 909                  * 1 - pfp
 910                  * 2 - ce
 911                  */
 912 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI               0x38
 913 #define PACKET3_MEM_SEMAPHORE                           0x39
 914 #define PACKET3_MPEG_INDEX                              0x3A
 915 #define PACKET3_COPY_DW                                 0x3B
 916 #define PACKET3_WAIT_REG_MEM                            0x3C
 917 #define PACKET3_MEM_WRITE                               0x3D
 918 #define PACKET3_COPY_DATA                               0x40
 919 #define PACKET3_CP_DMA                                  0x41
 920 /* 1. header
 921  * 2. SRC_ADDR_LO or DATA [31:0]
 922  * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
 923  *    SRC_ADDR_HI [7:0]
 924  * 4. DST_ADDR_LO [31:0]
 925  * 5. DST_ADDR_HI [7:0]
 926  * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
 927  */
 928 #              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)
 929                 /* 0 - SRC_ADDR
 930                  * 1 - GDS
 931                  */
 932 #              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)
 933                 /* 0 - ME
 934                  * 1 - PFP
 935                  */
 936 #              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)
 937                 /* 0 - SRC_ADDR
 938                  * 1 - GDS
 939                  * 2 - DATA
 940                  */
 941 #              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)
 942 /* COMMAND */
 943 #              define PACKET3_CP_DMA_DIS_WC        (1 << 21)
 944 #              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
 945                 /* 0 - none
 946                  * 1 - 8 in 16
 947                  * 2 - 8 in 32
 948                  * 3 - 8 in 64
 949                  */
 950 #              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
 951                 /* 0 - none
 952                  * 1 - 8 in 16
 953                  * 2 - 8 in 32
 954                  * 3 - 8 in 64
 955                  */
 956 #              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)
 957                 /* 0 - memory
 958                  * 1 - register
 959                  */
 960 #              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)
 961                 /* 0 - memory
 962                  * 1 - register
 963                  */
 964 #              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
 965 #              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
 966 #              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 << 30)
 967 #define PACKET3_PFP_SYNC_ME                             0x42
 968 #define PACKET3_SURFACE_SYNC                            0x43
 969 #              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
 970 #              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
 971 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
 972 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
 973 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
 974 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
 975 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
 976 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
 977 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
 978 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
 979 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
 980 #              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
 981 #              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
 982 #              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
 983 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
 984 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
 985 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
 986 #              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
 987 #              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
 988 #define PACKET3_ME_INITIALIZE                           0x44
 989 #define         PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
 990 #define PACKET3_COND_WRITE                              0x45
 991 #define PACKET3_EVENT_WRITE                             0x46
 992 #define         EVENT_TYPE(x)                           ((x) << 0)
 993 #define         EVENT_INDEX(x)                          ((x) << 8)
 994                 /* 0 - any non-TS event
 995                  * 1 - ZPASS_DONE
 996                  * 2 - SAMPLE_PIPELINESTAT
 997                  * 3 - SAMPLE_STREAMOUTSTAT*
 998                  * 4 - *S_PARTIAL_FLUSH
 999                  * 5 - EOP events
1000                  * 6 - EOS events
1001                  * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
1002                  */
1003 #define         INV_L2                                  (1 << 20)
1004                 /* INV TC L2 cache when EVENT_INDEX = 7 */
1005 #define PACKET3_EVENT_WRITE_EOP                         0x47
1006 #define         DATA_SEL(x)                             ((x) << 29)
1007                 /* 0 - discard
1008                  * 1 - send low 32bit data
1009                  * 2 - send 64bit data
1010                  * 3 - send 64bit counter value
1011                  */
1012 #define         INT_SEL(x)                              ((x) << 24)
1013                 /* 0 - none
1014                  * 1 - interrupt only (DATA_SEL = 0)
1015                  * 2 - interrupt when data write is confirmed
1016                  */
1017 #define PACKET3_EVENT_WRITE_EOS                         0x48
1018 #define PACKET3_PREAMBLE_CNTL                           0x4A
1019 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
1020 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
1021 #define PACKET3_ONE_REG_WRITE                           0x57
1022 #define PACKET3_LOAD_CONFIG_REG                         0x5F
1023 #define PACKET3_LOAD_CONTEXT_REG                        0x60
1024 #define PACKET3_LOAD_SH_REG                             0x61
1025 #define PACKET3_SET_CONFIG_REG                          0x68
1026 #define         PACKET3_SET_CONFIG_REG_START                    0x00008000
1027 #define         PACKET3_SET_CONFIG_REG_END                      0x0000b000
1028 #define PACKET3_SET_CONTEXT_REG                         0x69
1029 #define         PACKET3_SET_CONTEXT_REG_START                   0x00028000
1030 #define         PACKET3_SET_CONTEXT_REG_END                     0x00029000
1031 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
1032 #define PACKET3_SET_RESOURCE_INDIRECT                   0x74
1033 #define PACKET3_SET_SH_REG                              0x76
1034 #define         PACKET3_SET_SH_REG_START                        0x0000b000
1035 #define         PACKET3_SET_SH_REG_END                          0x0000c000
1036 #define PACKET3_SET_SH_REG_OFFSET                       0x77
1037 #define PACKET3_ME_WRITE                                0x7A
1038 #define PACKET3_SCRATCH_RAM_WRITE                       0x7D
1039 #define PACKET3_SCRATCH_RAM_READ                        0x7E
1040 #define PACKET3_CE_WRITE                                0x7F
1041 #define PACKET3_LOAD_CONST_RAM                          0x80
1042 #define PACKET3_WRITE_CONST_RAM                         0x81
1043 #define PACKET3_WRITE_CONST_RAM_OFFSET                  0x82
1044 #define PACKET3_DUMP_CONST_RAM                          0x83
1045 #define PACKET3_INCREMENT_CE_COUNTER                    0x84
1046 #define PACKET3_INCREMENT_DE_COUNTER                    0x85
1047 #define PACKET3_WAIT_ON_CE_COUNTER                      0x86
1048 #define PACKET3_WAIT_ON_DE_COUNTER                      0x87
1049 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF                 0x88
1050 #define PACKET3_SET_CE_DE_COUNTERS                      0x89
1051 #define PACKET3_WAIT_ON_AVAIL_BUFFER                    0x8A
1052 #define PACKET3_SWITCH_BUFFER                           0x8B
1053
1054 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1055 #define DMA0_REGISTER_OFFSET                              0x0 /* not a register */
1056 #define DMA1_REGISTER_OFFSET                              0x800 /* not a register */
1057
1058 #define DMA_RB_CNTL                                       0xd000
1059 #       define DMA_RB_ENABLE                              (1 << 0)
1060 #       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
1061 #       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
1062 #       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
1063 #       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
1064 #       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
1065 #define DMA_RB_BASE                                       0xd004
1066 #define DMA_RB_RPTR                                       0xd008
1067 #define DMA_RB_WPTR                                       0xd00c
1068
1069 #define DMA_RB_RPTR_ADDR_HI                               0xd01c
1070 #define DMA_RB_RPTR_ADDR_LO                               0xd020
1071
1072 #define DMA_IB_CNTL                                       0xd024
1073 #       define DMA_IB_ENABLE                              (1 << 0)
1074 #       define DMA_IB_SWAP_ENABLE                         (1 << 4)
1075 #define DMA_IB_RPTR                                       0xd028
1076 #define DMA_CNTL                                          0xd02c
1077 #       define TRAP_ENABLE                                (1 << 0)
1078 #       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
1079 #       define SEM_WAIT_INT_ENABLE                        (1 << 2)
1080 #       define DATA_SWAP_ENABLE                           (1 << 3)
1081 #       define FENCE_SWAP_ENABLE                          (1 << 4)
1082 #       define CTXEMPTY_INT_ENABLE                        (1 << 28)
1083 #define DMA_STATUS_REG                                    0xd034
1084 #       define DMA_IDLE                                   (1 << 0)
1085 #define DMA_TILING_CONFIG                                 0xd0b8
1086
1087 #define DMA_PACKET(cmd, b, t, s, n)     ((((cmd) & 0xF) << 28) |        \
1088                                          (((b) & 0x1) << 26) |          \
1089                                          (((t) & 0x1) << 23) |          \
1090                                          (((s) & 0x1) << 22) |          \
1091                                          (((n) & 0xFFFFF) << 0))
1092
1093 #define DMA_IB_PACKET(cmd, vmid, n)     ((((cmd) & 0xF) << 28) |        \
1094                                          (((vmid) & 0xF) << 20) |       \
1095                                          (((n) & 0xFFFFF) << 0))
1096
1097 #define DMA_PTE_PDE_PACKET(n)           ((2 << 28) |                    \
1098                                          (1 << 26) |                    \
1099                                          (1 << 21) |                    \
1100                                          (((n) & 0xFFFFF) << 0))
1101
1102 /* async DMA Packet types */
1103 #define DMA_PACKET_WRITE                                  0x2
1104 #define DMA_PACKET_COPY                                   0x3
1105 #define DMA_PACKET_INDIRECT_BUFFER                        0x4
1106 #define DMA_PACKET_SEMAPHORE                              0x5
1107 #define DMA_PACKET_FENCE                                  0x6
1108 #define DMA_PACKET_TRAP                                   0x7
1109 #define DMA_PACKET_SRBM_WRITE                             0x9
1110 #define DMA_PACKET_CONSTANT_FILL                          0xd
1111 #define DMA_PACKET_NOP                                    0xf
1112
1113 #endif