1 /* mach64_state.c -- State support for mach64 (Rage Pro) driver -*- linux-c -*-
2 * Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com
5 * Copyright 2000 Gareth Hughes
6 * Copyright 2002-2003 Leif Delgass
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
24 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
25 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
29 * Leif Delgass <ldelgass@retinalburn.net>
30 * José Fonseca <j_r_fonseca@yahoo.co.uk>
33 #include "dev/drm/drmP.h"
34 #include "dev/drm/drm.h"
35 #include "dev/drm/mach64_drm.h"
36 #include "dev/drm/mach64_drv.h"
40 * 1.0 - Initial mach64 DRM
43 struct drm_ioctl_desc mach64_ioctls[] = {
44 DRM_IOCTL_DEF(DRM_MACH64_INIT, mach64_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
45 DRM_IOCTL_DEF(DRM_MACH64_CLEAR, mach64_dma_clear, DRM_AUTH),
46 DRM_IOCTL_DEF(DRM_MACH64_SWAP, mach64_dma_swap, DRM_AUTH),
47 DRM_IOCTL_DEF(DRM_MACH64_IDLE, mach64_dma_idle, DRM_AUTH),
48 DRM_IOCTL_DEF(DRM_MACH64_RESET, mach64_engine_reset, DRM_AUTH),
49 DRM_IOCTL_DEF(DRM_MACH64_VERTEX, mach64_dma_vertex, DRM_AUTH),
50 DRM_IOCTL_DEF(DRM_MACH64_BLIT, mach64_dma_blit, DRM_AUTH),
51 DRM_IOCTL_DEF(DRM_MACH64_FLUSH, mach64_dma_flush, DRM_AUTH),
52 DRM_IOCTL_DEF(DRM_MACH64_GETPARAM, mach64_get_param, DRM_AUTH),
55 int mach64_max_ioctl = DRM_ARRAY_SIZE(mach64_ioctls);
57 /* ================================================================
58 * DMA hardware state programming functions
61 static void mach64_print_dirty(const char *msg, unsigned int flags)
63 DRM_DEBUG("%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n",
66 (flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " :
68 (flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "",
69 (flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " :
70 "", (flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "",
71 (flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " :
73 (flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "",
74 (flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "",
75 (flags & MACH64_UPLOAD_MISC) ? "misc, " : "",
76 (flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "",
77 (flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "",
78 (flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "",
79 (flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : "");
82 /* Mach64 doesn't have hardware cliprects, just one hardware scissor,
83 * so the GL scissor is intersected with each cliprect here
85 /* This function returns 0 on success, 1 for no intersection, and
86 * negative for an error
88 static int mach64_emit_cliprect(struct drm_file *file_priv,
89 drm_mach64_private_t * dev_priv,
90 struct drm_clip_rect * box)
92 u32 sc_left_right, sc_top_bottom;
93 struct drm_clip_rect scissor;
94 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
95 drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
98 DRM_DEBUG("box=%p\n", box);
101 /* FIXME: store scissor in SAREA as a cliprect instead of in
102 * hardware format, or do intersection client-side
104 scissor.x1 = regs->sc_left_right & 0xffff;
105 scissor.x2 = (regs->sc_left_right & 0xffff0000) >> 16;
106 scissor.y1 = regs->sc_top_bottom & 0xffff;
107 scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16;
109 /* Intersect GL scissor with cliprect */
110 if (box->x1 > scissor.x1)
111 scissor.x1 = box->x1;
112 if (box->y1 > scissor.y1)
113 scissor.y1 = box->y1;
114 if (box->x2 < scissor.x2)
115 scissor.x2 = box->x2;
116 if (box->y2 < scissor.y2)
117 scissor.y2 = box->y2;
118 /* positive return means skip */
119 if (scissor.x1 >= scissor.x2)
121 if (scissor.y1 >= scissor.y2)
124 DMAGETPTR(file_priv, dev_priv, 2); /* returns on failure to get buffer */
126 sc_left_right = ((scissor.x1 << 0) | (scissor.x2 << 16));
127 sc_top_bottom = ((scissor.y1 << 0) | (scissor.y2 << 16));
129 DMAOUTREG(MACH64_SC_LEFT_RIGHT, sc_left_right);
130 DMAOUTREG(MACH64_SC_TOP_BOTTOM, sc_top_bottom);
132 DMAADVANCE(dev_priv, 1);
137 static __inline__ int mach64_emit_state(struct drm_file *file_priv,
138 drm_mach64_private_t * dev_priv)
140 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
141 drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
142 unsigned int dirty = sarea_priv->dirty;
143 u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2);
146 if (MACH64_VERBOSE) {
147 mach64_print_dirty(__FUNCTION__, dirty);
149 DRM_DEBUG("dirty=0x%08x\n", dirty);
152 DMAGETPTR(file_priv, dev_priv, 17); /* returns on failure to get buffer */
154 if (dirty & MACH64_UPLOAD_MISC) {
155 DMAOUTREG(MACH64_DP_MIX, regs->dp_mix);
156 DMAOUTREG(MACH64_DP_SRC, regs->dp_src);
157 DMAOUTREG(MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl);
158 DMAOUTREG(MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl);
159 sarea_priv->dirty &= ~MACH64_UPLOAD_MISC;
162 if (dirty & MACH64_UPLOAD_DST_OFF_PITCH) {
163 DMAOUTREG(MACH64_DST_OFF_PITCH, regs->dst_off_pitch);
164 sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH;
166 if (dirty & MACH64_UPLOAD_Z_OFF_PITCH) {
167 DMAOUTREG(MACH64_Z_OFF_PITCH, regs->z_off_pitch);
168 sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH;
170 if (dirty & MACH64_UPLOAD_Z_ALPHA_CNTL) {
171 DMAOUTREG(MACH64_Z_CNTL, regs->z_cntl);
172 DMAOUTREG(MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl);
173 sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL;
175 if (dirty & MACH64_UPLOAD_SCALE_3D_CNTL) {
176 DMAOUTREG(MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl);
177 sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL;
179 if (dirty & MACH64_UPLOAD_DP_FOG_CLR) {
180 DMAOUTREG(MACH64_DP_FOG_CLR, regs->dp_fog_clr);
181 sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR;
183 if (dirty & MACH64_UPLOAD_DP_WRITE_MASK) {
184 DMAOUTREG(MACH64_DP_WRITE_MASK, regs->dp_write_mask);
185 sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK;
187 if (dirty & MACH64_UPLOAD_DP_PIX_WIDTH) {
188 DMAOUTREG(MACH64_DP_PIX_WIDTH, regs->dp_pix_width);
189 sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH;
191 if (dirty & MACH64_UPLOAD_SETUP_CNTL) {
192 DMAOUTREG(MACH64_SETUP_CNTL, regs->setup_cntl);
193 sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL;
196 if (dirty & MACH64_UPLOAD_TEXTURE) {
197 DMAOUTREG(MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch);
198 DMAOUTREG(MACH64_TEX_CNTL, regs->tex_cntl);
199 DMAOUTREG(MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off);
200 DMAOUTREG(MACH64_TEX_0_OFF + offset, regs->tex_offset);
201 sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE;
204 DMAADVANCE(dev_priv, 1);
206 sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS;
212 /* ================================================================
213 * DMA command dispatch functions
216 static int mach64_dma_dispatch_clear(struct drm_device * dev,
217 struct drm_file *file_priv,
219 int cx, int cy, int cw, int ch,
220 unsigned int clear_color,
221 unsigned int clear_depth)
223 drm_mach64_private_t *dev_priv = dev->dev_private;
224 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
225 drm_mach64_context_regs_t *ctx = &sarea_priv->context_state;
226 int nbox = sarea_priv->nbox;
227 struct drm_clip_rect *pbox = sarea_priv->boxes;
228 u32 fb_bpp, depth_bpp;
234 switch (dev_priv->fb_bpp) {
236 fb_bpp = MACH64_DATATYPE_RGB565;
239 fb_bpp = MACH64_DATATYPE_ARGB8888;
244 switch (dev_priv->depth_bpp) {
246 depth_bpp = MACH64_DATATYPE_RGB565;
250 depth_bpp = MACH64_DATATYPE_ARGB8888;
259 DMAGETPTR(file_priv, dev_priv, nbox * 31); /* returns on failure to get buffer */
261 for (i = 0; i < nbox; i++) {
264 int w = pbox[i].x2 - x;
265 int h = pbox[i].y2 - y;
267 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
268 pbox[i].x1, pbox[i].y1,
269 pbox[i].x2, pbox[i].y2, flags);
271 if (flags & (MACH64_FRONT | MACH64_BACK)) {
272 /* Setup for color buffer clears
275 DMAOUTREG(MACH64_Z_CNTL, 0);
276 DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
278 DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right);
279 DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom);
281 DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
282 DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
283 (MACH64_DST_X_LEFT_TO_RIGHT |
284 MACH64_DST_Y_TOP_TO_BOTTOM));
286 DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
292 DMAOUTREG(MACH64_DP_FRGD_CLR, clear_color);
293 DMAOUTREG(MACH64_DP_WRITE_MASK, ctx->dp_write_mask);
294 DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
296 DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
297 MACH64_FRGD_SRC_FRGD_CLR |
298 MACH64_MONO_SRC_ONE));
302 if (flags & MACH64_FRONT) {
304 DMAOUTREG(MACH64_DST_OFF_PITCH,
305 dev_priv->front_offset_pitch);
306 DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
307 DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
311 if (flags & MACH64_BACK) {
313 DMAOUTREG(MACH64_DST_OFF_PITCH,
314 dev_priv->back_offset_pitch);
315 DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
316 DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
320 if (flags & MACH64_DEPTH) {
321 /* Setup for depth buffer clear
323 DMAOUTREG(MACH64_Z_CNTL, 0);
324 DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
326 DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right);
327 DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom);
329 DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
330 DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
331 (MACH64_DST_X_LEFT_TO_RIGHT |
332 MACH64_DST_Y_TOP_TO_BOTTOM));
334 DMAOUTREG(MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) |
340 DMAOUTREG(MACH64_DP_FRGD_CLR, clear_depth);
341 DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);
342 DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
344 DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
345 MACH64_FRGD_SRC_FRGD_CLR |
346 MACH64_MONO_SRC_ONE));
348 DMAOUTREG(MACH64_DST_OFF_PITCH,
349 dev_priv->depth_offset_pitch);
350 DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
351 DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
355 DMAADVANCE(dev_priv, 1);
360 static int mach64_dma_dispatch_swap(struct drm_device * dev,
361 struct drm_file *file_priv)
363 drm_mach64_private_t *dev_priv = dev->dev_private;
364 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
365 int nbox = sarea_priv->nbox;
366 struct drm_clip_rect *pbox = sarea_priv->boxes;
373 switch (dev_priv->fb_bpp) {
375 fb_bpp = MACH64_DATATYPE_RGB565;
379 fb_bpp = MACH64_DATATYPE_ARGB8888;
386 DMAGETPTR(file_priv, dev_priv, 13 + nbox * 4); /* returns on failure to get buffer */
388 DMAOUTREG(MACH64_Z_CNTL, 0);
389 DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
391 DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16)); /* no scissor */
392 DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16));
394 DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
395 DMAOUTREG(MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT |
396 MACH64_DST_Y_TOP_TO_BOTTOM));
398 DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
401 (fb_bpp << 16) | (fb_bpp << 28)));
403 DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);
404 DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S));
405 DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR |
406 MACH64_FRGD_SRC_BLIT | MACH64_MONO_SRC_ONE));
408 DMAOUTREG(MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch);
409 DMAOUTREG(MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch);
411 for (i = 0; i < nbox; i++) {
414 int w = pbox[i].x2 - x;
415 int h = pbox[i].y2 - y;
417 DRM_DEBUG("dispatch swap %d,%d-%d,%d\n",
418 pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2);
420 DMAOUTREG(MACH64_SRC_WIDTH1, w);
421 DMAOUTREG(MACH64_SRC_Y_X, (x << 16) | y);
422 DMAOUTREG(MACH64_DST_Y_X, (x << 16) | y);
423 DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
427 DMAADVANCE(dev_priv, 1);
429 if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) {
430 for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) {
431 dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i + 1];
433 dev_priv->frame_ofs[i] = GETRINGOFFSET();
435 dev_priv->sarea_priv->frames_queued++;
441 static int mach64_do_get_frames_queued(drm_mach64_private_t * dev_priv)
443 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
444 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
450 if (sarea_priv->frames_queued == 0)
454 mach64_ring_tick(dev_priv, ring);
457 start = (MACH64_MAX_QUEUED_FRAMES -
458 DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued));
461 sarea_priv->frames_queued = 0;
462 for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
463 dev_priv->frame_ofs[i] = ~0;
468 for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
469 ofs = dev_priv->frame_ofs[i];
470 DRM_DEBUG("frame_ofs[%d] ofs: %d\n", i, ofs);
472 (head < tail && (ofs < head || ofs >= tail)) ||
473 (head > tail && (ofs < head && ofs >= tail))) {
474 sarea_priv->frames_queued =
475 (MACH64_MAX_QUEUED_FRAMES - 1) - i;
476 dev_priv->frame_ofs[i] = ~0;
480 return sarea_priv->frames_queued;
483 /* Copy and verify a client submited buffer.
484 * FIXME: Make an assembly optimized version
486 static __inline__ int copy_from_user_vertex(u32 *to,
487 const u32 __user *ufrom,
490 unsigned long n = bytes; /* dwords remaining in buffer */
491 u32 *from, *orig_from;
493 from = drm_alloc(bytes, DRM_MEM_DRIVER);
497 if (DRM_COPY_FROM_USER(from, ufrom, bytes)) {
498 drm_free(from, bytes, DRM_MEM_DRIVER);
501 orig_from = from; /* we'll be modifying the "from" ptr, so save it */
506 u32 data, reg, count;
512 reg = le32_to_cpu(data);
513 count = (reg >> 16) + 1;
518 /* This is an exact match of Mach64's Setup Engine registers,
519 * excluding SETUP_CNTL (1_C1).
521 if ((reg >= 0x0190 && reg < 0x01c1) ||
522 (reg >= 0x01ca && reg <= 0x01cf)) {
524 memcpy(to, from, count << 2);
528 DRM_ERROR("Got bad command: 0x%04x\n", reg);
529 drm_free(orig_from, bytes, DRM_MEM_DRIVER);
534 ("Got bad command count(=%u) dwords remaining=%lu\n",
536 drm_free(orig_from, bytes, DRM_MEM_DRIVER);
541 drm_free(orig_from, bytes, DRM_MEM_DRIVER);
545 DRM_ERROR("Bad buf->used(=%lu)\n", bytes);
550 static int mach64_dma_dispatch_vertex(struct drm_device * dev,
551 struct drm_file *file_priv,
552 drm_mach64_vertex_t * vertex)
554 drm_mach64_private_t *dev_priv = dev->dev_private;
555 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
556 struct drm_buf *copy_buf;
557 void *buf = vertex->buf;
558 unsigned long used = vertex->used;
565 DRM_DEBUG("buf=%p used=%lu nbox=%d\n",
566 buf, used, sarea_priv->nbox);
571 copy_buf = mach64_freelist_get(dev_priv);
572 if (copy_buf == NULL) {
573 DRM_ERROR("couldn't get buffer\n");
577 /* Mach64's vertex data is actually register writes. To avoid security
578 * compromises these register writes have to be verified and copied from
579 * user space into a private DMA buffer.
581 verify_ret = copy_from_user_vertex(GETBUFPTR(copy_buf), buf, used);
583 if (verify_ret != 0) {
584 mach64_freelist_put(dev_priv, copy_buf);
588 copy_buf->used = used;
592 if (sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS) {
593 ret = mach64_emit_state(file_priv, dev_priv);
599 /* Emit the next cliprect */
600 if (i < sarea_priv->nbox) {
601 ret = mach64_emit_cliprect(file_priv, dev_priv,
602 &sarea_priv->boxes[i]);
604 /* failed to get buffer */
606 } else if (ret != 0) {
607 /* null intersection with scissor */
611 if ((i >= sarea_priv->nbox - 1))
614 /* Add the buffer to the DMA queue */
615 DMAADVANCE(dev_priv, done);
617 } while (++i < sarea_priv->nbox);
620 if (copy_buf->pending) {
623 /* This buffer wasn't used (no cliprects), so place it
624 * back on the free list
626 mach64_freelist_put(dev_priv, copy_buf);
631 sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS;
632 sarea_priv->nbox = 0;
637 static __inline__ int copy_from_user_blit(u32 *to,
638 const u32 __user *ufrom,
641 to = (u32 *)((char *)to + MACH64_HOSTDATA_BLIT_OFFSET);
643 if (DRM_COPY_FROM_USER(to, ufrom, bytes)) {
650 static int mach64_dma_dispatch_blit(struct drm_device * dev,
651 struct drm_file *file_priv,
652 drm_mach64_blit_t * blit)
654 drm_mach64_private_t *dev_priv = dev->dev_private;
655 int dword_shift, dwords;
657 struct drm_buf *copy_buf;
661 /* The compiler won't optimize away a division by a variable,
662 * even if the only legal values are powers of two. Thus, we'll
663 * use a shift instead.
665 switch (blit->format) {
666 case MACH64_DATATYPE_ARGB8888:
669 case MACH64_DATATYPE_ARGB1555:
670 case MACH64_DATATYPE_RGB565:
671 case MACH64_DATATYPE_VYUY422:
672 case MACH64_DATATYPE_YVYU422:
673 case MACH64_DATATYPE_ARGB4444:
676 case MACH64_DATATYPE_CI8:
677 case MACH64_DATATYPE_RGB8:
681 DRM_ERROR("invalid blit format %d\n", blit->format);
685 /* Set buf->used to the bytes of blit data based on the blit dimensions
686 * and verify the size. When the setup is emitted to the buffer with
687 * the DMA* macros below, buf->used is incremented to include the bytes
688 * used for setup as well as the blit data.
690 dwords = (blit->width * blit->height) >> dword_shift;
693 used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET) {
694 DRM_ERROR("Invalid blit size: %lu bytes\n", used);
698 copy_buf = mach64_freelist_get(dev_priv);
699 if (copy_buf == NULL) {
700 DRM_ERROR("couldn't get buffer\n");
704 /* Copy the blit data from userspace.
706 * XXX: This is overkill. The most efficient solution would be having
707 * two sets of buffers (one set private for vertex data, the other set
708 * client-writable for blits). However that would bring more complexity
709 * and would break backward compatability. The solution currently
710 * implemented is keeping all buffers private, allowing to secure the
711 * driver, without increasing complexity at the expense of some speed
714 verify_ret = copy_from_user_blit(GETBUFPTR(copy_buf), blit->buf, used);
716 if (verify_ret != 0) {
717 mach64_freelist_put(dev_priv, copy_buf);
721 copy_buf->used = used;
723 /* FIXME: Use a last buffer flag and reduce the state emitted for subsequent,
724 * continuation buffers?
727 /* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require
728 * a register command every 16 dwords. State setup is added at the start of the
729 * buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET
733 DMAOUTREG(MACH64_Z_CNTL, 0);
734 DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
736 DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16)); /* no scissor */
737 DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16));
739 DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); /* disable */
740 DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
741 MACH64_DST_X_LEFT_TO_RIGHT | MACH64_DST_Y_TOP_TO_BOTTOM);
743 DMAOUTREG(MACH64_DP_PIX_WIDTH, (blit->format << 0) /* dst pix width */
744 |(blit->format << 4) /* composite pix width */
745 |(blit->format << 8) /* src pix width */
746 |(blit->format << 16) /* host data pix width */
747 |(blit->format << 28) /* scaler/3D pix width */
750 DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff); /* enable all planes */
751 DMAOUTREG(MACH64_DP_MIX, MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S);
752 DMAOUTREG(MACH64_DP_SRC,
753 MACH64_BKGD_SRC_BKGD_CLR
754 | MACH64_FRGD_SRC_HOST | MACH64_MONO_SRC_ONE);
756 DMAOUTREG(MACH64_DST_OFF_PITCH,
757 (blit->pitch << 22) | (blit->offset >> 3));
758 DMAOUTREG(MACH64_DST_X_Y, (blit->y << 16) | blit->x);
759 DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width);
761 DRM_DEBUG("%lu bytes\n", used);
763 /* Add the buffer to the queue */
764 DMAADVANCEHOSTDATA(dev_priv);
770 /* ================================================================
774 int mach64_dma_clear(struct drm_device *dev, void *data,
775 struct drm_file *file_priv)
777 drm_mach64_private_t *dev_priv = dev->dev_private;
778 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
779 drm_mach64_clear_t *clear = data;
782 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
784 LOCK_TEST_WITH_RETURN(dev, file_priv);
786 if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
787 sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
789 ret = mach64_dma_dispatch_clear(dev, file_priv, clear->flags,
790 clear->x, clear->y, clear->w, clear->h,
794 /* Make sure we restore the 3D state next time.
796 sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC);
800 int mach64_dma_swap(struct drm_device *dev, void *data,
801 struct drm_file *file_priv)
803 drm_mach64_private_t *dev_priv = dev->dev_private;
804 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
807 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
809 LOCK_TEST_WITH_RETURN(dev, file_priv);
811 if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
812 sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
814 ret = mach64_dma_dispatch_swap(dev, file_priv);
816 /* Make sure we restore the 3D state next time.
818 sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC);
822 int mach64_dma_vertex(struct drm_device *dev, void *data,
823 struct drm_file *file_priv)
825 drm_mach64_private_t *dev_priv = dev->dev_private;
826 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
827 drm_mach64_vertex_t *vertex = data;
829 LOCK_TEST_WITH_RETURN(dev, file_priv);
832 DRM_ERROR("called with no initialization\n");
836 DRM_DEBUG("pid=%d buf=%p used=%lu discard=%d\n",
838 vertex->buf, vertex->used, vertex->discard);
840 if (vertex->prim < 0 || vertex->prim > MACH64_PRIM_POLYGON) {
841 DRM_ERROR("buffer prim %d\n", vertex->prim);
845 if (vertex->used > MACH64_BUFFER_SIZE || (vertex->used & 3) != 0) {
846 DRM_ERROR("Invalid vertex buffer size: %lu bytes\n",
851 if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
852 sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
854 return mach64_dma_dispatch_vertex(dev, file_priv, vertex);
857 int mach64_dma_blit(struct drm_device *dev, void *data,
858 struct drm_file *file_priv)
860 drm_mach64_private_t *dev_priv = dev->dev_private;
861 drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
862 drm_mach64_blit_t *blit = data;
865 LOCK_TEST_WITH_RETURN(dev, file_priv);
867 ret = mach64_dma_dispatch_blit(dev, file_priv, blit);
869 /* Make sure we restore the 3D state next time.
871 sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
872 MACH64_UPLOAD_MISC | MACH64_UPLOAD_CLIPRECTS);
877 int mach64_get_param(struct drm_device *dev, void *data,
878 struct drm_file *file_priv)
880 drm_mach64_private_t *dev_priv = dev->dev_private;
881 drm_mach64_getparam_t *param = data;
887 DRM_ERROR("called with no initialization\n");
891 switch (param->param) {
892 case MACH64_PARAM_FRAMES_QUEUED:
893 /* Needs lock since it calls mach64_ring_tick() */
894 LOCK_TEST_WITH_RETURN(dev, file_priv);
895 value = mach64_do_get_frames_queued(dev_priv);
897 case MACH64_PARAM_IRQ_NR:
904 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
905 DRM_ERROR("copy_to_user\n");