1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
31 #include <drm/i915_drm.h>
33 #include "intel_drv.h"
34 #include "intel_ringbuffer.h"
36 static struct drm_i915_private *i915_mch_dev;
38 * Lock protecting IPS related data structures
40 * - dev_priv->max_delay
41 * - dev_priv->min_delay
43 * - dev_priv->gpu_busy
45 static struct lock mchdev_lock;
46 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE);
48 static void i915_pineview_get_mem_freq(struct drm_device *dev);
49 static void i915_ironlake_get_mem_freq(struct drm_device *dev);
50 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
52 static void i915_write_hws_pga(struct drm_device *dev)
54 drm_i915_private_t *dev_priv = dev->dev_private;
57 addr = dev_priv->status_page_dmah->busaddr;
58 if (INTEL_INFO(dev)->gen >= 4)
59 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
60 I915_WRITE(HWS_PGA, addr);
64 * Sets up the hardware status page for devices that need a physical address
67 static int i915_init_phys_hws(struct drm_device *dev)
69 drm_i915_private_t *dev_priv = dev->dev_private;
70 struct intel_ring_buffer *ring = LP_RING(dev_priv);
73 * Program Hardware Status Page
74 * XXXKIB Keep 4GB limit for allocation for now. This method
75 * of allocation is used on <= 965 hardware, that has several
76 * erratas regarding the use of physical memory > 4 GB.
79 dev_priv->status_page_dmah =
80 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
82 if (!dev_priv->status_page_dmah) {
83 DRM_ERROR("Can not allocate hardware status page\n");
86 ring->status_page.page_addr = dev_priv->hw_status_page =
87 dev_priv->status_page_dmah->vaddr;
88 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
90 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
92 i915_write_hws_pga(dev);
93 DRM_DEBUG("Enabled hardware status page, phys %jx\n",
94 (uintmax_t)dev_priv->dma_status_page);
99 * Frees the hardware status page, whether it's a physical address or a virtual
100 * address set up by the X Server.
102 static void i915_free_hws(struct drm_device *dev)
104 drm_i915_private_t *dev_priv = dev->dev_private;
105 struct intel_ring_buffer *ring = LP_RING(dev_priv);
107 if (dev_priv->status_page_dmah) {
108 drm_pci_free(dev, dev_priv->status_page_dmah);
109 dev_priv->status_page_dmah = NULL;
112 if (dev_priv->status_gfx_addr) {
113 dev_priv->status_gfx_addr = 0;
114 ring->status_page.gfx_addr = 0;
115 drm_core_ioremapfree(&dev_priv->hws_map, dev);
118 /* Need to rewrite hardware status page */
119 I915_WRITE(HWS_PGA, 0x1ffff000);
122 void i915_kernel_lost_context(struct drm_device * dev)
124 drm_i915_private_t *dev_priv = dev->dev_private;
125 struct intel_ring_buffer *ring = LP_RING(dev_priv);
128 * We should never lose context on the ring with modesetting
129 * as we don't expose it to userspace
131 if (drm_core_check_feature(dev, DRIVER_MODESET))
134 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
135 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
136 ring->space = ring->head - (ring->tail + 8);
138 ring->space += ring->size;
143 if (!dev->primary->master)
147 if (ring->head == ring->tail && dev_priv->sarea_priv)
148 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
151 static int i915_dma_cleanup(struct drm_device * dev)
153 drm_i915_private_t *dev_priv = dev->dev_private;
157 /* Make sure interrupts are disabled here because the uninstall ioctl
158 * may not have been called from userspace and after dev_private
159 * is freed, it's too late.
161 if (dev->irq_enabled)
162 drm_irq_uninstall(dev);
164 for (i = 0; i < I915_NUM_RINGS; i++)
165 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
167 /* Clear the HWS virtual address at teardown */
168 if (I915_NEED_GFX_HWS(dev))
174 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
176 drm_i915_private_t *dev_priv = dev->dev_private;
179 dev_priv->sarea = drm_getsarea(dev);
180 if (!dev_priv->sarea) {
181 DRM_ERROR("can not find sarea!\n");
182 i915_dma_cleanup(dev);
186 dev_priv->sarea_priv = (drm_i915_sarea_t *)
187 ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
189 if (init->ring_size != 0) {
190 if (LP_RING(dev_priv)->obj != NULL) {
191 i915_dma_cleanup(dev);
192 DRM_ERROR("Client tried to initialize ringbuffer in "
197 ret = intel_render_ring_init_dri(dev,
201 i915_dma_cleanup(dev);
206 dev_priv->cpp = init->cpp;
207 dev_priv->back_offset = init->back_offset;
208 dev_priv->front_offset = init->front_offset;
209 dev_priv->current_page = 0;
210 dev_priv->sarea_priv->pf_current_page = 0;
212 /* Allow hardware batchbuffers unless told otherwise.
214 dev_priv->allow_batchbuffer = 1;
219 static int i915_dma_resume(struct drm_device * dev)
221 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
222 struct intel_ring_buffer *ring = LP_RING(dev_priv);
226 if (ring->map.handle == NULL) {
227 DRM_ERROR("can not ioremap virtual address for"
232 /* Program Hardware Status Page */
233 if (!ring->status_page.page_addr) {
234 DRM_ERROR("Can not find hardware status page\n");
237 DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
238 if (ring->status_page.gfx_addr != 0)
239 intel_ring_setup_status_page(ring);
241 i915_write_hws_pga(dev);
243 DRM_DEBUG("Enabled hardware status page\n");
248 static int i915_dma_init(struct drm_device *dev, void *data,
249 struct drm_file *file_priv)
251 drm_i915_init_t *init = data;
254 switch (init->func) {
256 retcode = i915_initialize(dev, init);
258 case I915_CLEANUP_DMA:
259 retcode = i915_dma_cleanup(dev);
261 case I915_RESUME_DMA:
262 retcode = i915_dma_resume(dev);
272 /* Implement basically the same security restrictions as hardware does
273 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
275 * Most of the calculations below involve calculating the size of a
276 * particular instruction. It's important to get the size right as
277 * that tells us where the next instruction to check is. Any illegal
278 * instruction detected will be given a size of zero, which is a
279 * signal to abort the rest of the buffer.
281 static int do_validate_cmd(int cmd)
283 switch (((cmd >> 29) & 0x7)) {
285 switch ((cmd >> 23) & 0x3f) {
287 return 1; /* MI_NOOP */
289 return 1; /* MI_FLUSH */
291 return 0; /* disallow everything else */
295 return 0; /* reserved */
297 return (cmd & 0xff) + 2; /* 2d commands */
299 if (((cmd >> 24) & 0x1f) <= 0x18)
302 switch ((cmd >> 24) & 0x1f) {
306 switch ((cmd >> 16) & 0xff) {
308 return (cmd & 0x1f) + 2;
310 return (cmd & 0xf) + 2;
312 return (cmd & 0xffff) + 2;
316 return (cmd & 0xffff) + 1;
320 if ((cmd & (1 << 23)) == 0) /* inline vertices */
321 return (cmd & 0x1ffff) + 2;
322 else if (cmd & (1 << 17)) /* indirect random */
323 if ((cmd & 0xffff) == 0)
324 return 0; /* unknown length, too hard */
326 return (((cmd & 0xffff) + 1) / 2) + 1;
328 return 2; /* indirect sequential */
339 static int validate_cmd(int cmd)
341 int ret = do_validate_cmd(cmd);
343 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
348 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
351 drm_i915_private_t *dev_priv = dev->dev_private;
354 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
357 BEGIN_LP_RING((dwords+1)&~1);
359 for (i = 0; i < dwords;) {
362 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
365 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
371 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
387 int i915_emit_box(struct drm_device * dev,
388 struct drm_clip_rect *boxes,
389 int i, int DR1, int DR4)
391 struct drm_clip_rect box;
393 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
397 return (i915_emit_box_p(dev, &box, DR1, DR4));
401 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
404 drm_i915_private_t *dev_priv = dev->dev_private;
407 if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
409 DRM_ERROR("Bad box %d,%d..%d,%d\n",
410 box->x1, box->y1, box->x2, box->y2);
414 if (INTEL_INFO(dev)->gen >= 4) {
415 ret = BEGIN_LP_RING(4);
419 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
420 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
421 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
424 ret = BEGIN_LP_RING(6);
428 OUT_RING(GFX_OP_DRAWRECT_INFO);
430 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
431 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
440 /* XXX: Emitting the counter should really be moved to part of the IRQ
441 * emit. For now, do it in both places:
444 static void i915_emit_breadcrumb(struct drm_device *dev)
446 drm_i915_private_t *dev_priv = dev->dev_private;
448 if (++dev_priv->counter > 0x7FFFFFFFUL)
449 dev_priv->counter = 0;
450 if (dev_priv->sarea_priv)
451 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
453 if (BEGIN_LP_RING(4) == 0) {
454 OUT_RING(MI_STORE_DWORD_INDEX);
455 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
456 OUT_RING(dev_priv->counter);
462 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
463 drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
465 int nbox = cmd->num_cliprects;
466 int i = 0, count, ret;
469 DRM_ERROR("alignment\n");
473 i915_kernel_lost_context(dev);
475 count = nbox ? nbox : 1;
477 for (i = 0; i < count; i++) {
479 ret = i915_emit_box_p(dev, &cmd->cliprects[i],
485 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
490 i915_emit_breadcrumb(dev);
495 i915_dispatch_batchbuffer(struct drm_device * dev,
496 drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
498 drm_i915_private_t *dev_priv = dev->dev_private;
499 int nbox = batch->num_cliprects;
502 if ((batch->start | batch->used) & 0x7) {
503 DRM_ERROR("alignment\n");
507 i915_kernel_lost_context(dev);
509 count = nbox ? nbox : 1;
511 for (i = 0; i < count; i++) {
513 int ret = i915_emit_box_p(dev, &cliprects[i],
514 batch->DR1, batch->DR4);
519 if (!IS_I830(dev) && !IS_845G(dev)) {
520 ret = BEGIN_LP_RING(2);
524 if (INTEL_INFO(dev)->gen >= 4) {
525 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
526 MI_BATCH_NON_SECURE_I965);
527 OUT_RING(batch->start);
529 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
530 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
533 ret = BEGIN_LP_RING(4);
537 OUT_RING(MI_BATCH_BUFFER);
538 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
539 OUT_RING(batch->start + batch->used - 4);
545 i915_emit_breadcrumb(dev);
550 static int i915_dispatch_flip(struct drm_device * dev)
552 drm_i915_private_t *dev_priv = dev->dev_private;
555 if (!dev_priv->sarea_priv)
558 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
560 dev_priv->current_page,
561 dev_priv->sarea_priv->pf_current_page);
563 i915_kernel_lost_context(dev);
565 ret = BEGIN_LP_RING(10);
568 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
571 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
573 if (dev_priv->current_page == 0) {
574 OUT_RING(dev_priv->back_offset);
575 dev_priv->current_page = 1;
577 OUT_RING(dev_priv->front_offset);
578 dev_priv->current_page = 0;
582 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
587 if (++dev_priv->counter > 0x7FFFFFFFUL)
588 dev_priv->counter = 0;
589 if (dev_priv->sarea_priv)
590 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
592 if (BEGIN_LP_RING(4) == 0) {
593 OUT_RING(MI_STORE_DWORD_INDEX);
594 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
595 OUT_RING(dev_priv->counter);
600 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
605 i915_quiescent(struct drm_device *dev)
607 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
609 i915_kernel_lost_context(dev);
610 return (intel_wait_ring_idle(ring));
614 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
618 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
621 ret = i915_quiescent(dev);
627 static int i915_batchbuffer(struct drm_device *dev, void *data,
628 struct drm_file *file_priv)
630 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
631 drm_i915_sarea_t *sarea_priv;
632 drm_i915_batchbuffer_t *batch = data;
633 struct drm_clip_rect *cliprects;
637 if (!dev_priv->allow_batchbuffer) {
638 DRM_ERROR("Batchbuffer ioctl disabled\n");
643 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
644 batch->start, batch->used, batch->num_cliprects);
646 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
647 if (batch->num_cliprects < 0)
649 if (batch->num_cliprects != 0) {
650 cliprects = kmalloc(batch->num_cliprects *
651 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
654 ret = -copyin(batch->cliprects, cliprects,
655 batch->num_cliprects * sizeof(struct drm_clip_rect));
664 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
665 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
667 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
669 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
672 drm_free(cliprects, DRM_MEM_DMA);
676 static int i915_cmdbuffer(struct drm_device *dev, void *data,
677 struct drm_file *file_priv)
679 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
680 drm_i915_sarea_t *sarea_priv;
681 drm_i915_cmdbuffer_t *cmdbuf = data;
682 struct drm_clip_rect *cliprects = NULL;
686 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
687 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
689 if (cmdbuf->num_cliprects < 0)
694 batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
696 ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
699 goto fail_batch_free;
702 if (cmdbuf->num_cliprects) {
703 cliprects = kmalloc(cmdbuf->num_cliprects *
704 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
706 ret = -copyin(cmdbuf->cliprects, cliprects,
707 cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
715 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
716 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
718 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
722 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
724 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
727 drm_free(cliprects, DRM_MEM_DMA);
729 drm_free(batch_data, DRM_MEM_DMA);
733 static int i915_flip_bufs(struct drm_device *dev, void *data,
734 struct drm_file *file_priv)
738 DRM_DEBUG("%s\n", __func__);
740 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
742 ret = i915_dispatch_flip(dev);
747 static int i915_getparam(struct drm_device *dev, void *data,
748 struct drm_file *file_priv)
750 drm_i915_private_t *dev_priv = dev->dev_private;
751 drm_i915_getparam_t *param = data;
755 DRM_ERROR("called with no initialization\n");
759 switch (param->param) {
760 case I915_PARAM_IRQ_ACTIVE:
761 value = dev->irq_enabled ? 1 : 0;
763 case I915_PARAM_ALLOW_BATCHBUFFER:
764 value = dev_priv->allow_batchbuffer ? 1 : 0;
766 case I915_PARAM_LAST_DISPATCH:
767 value = READ_BREADCRUMB(dev_priv);
769 case I915_PARAM_CHIPSET_ID:
770 value = dev->pci_device;
772 case I915_PARAM_HAS_GEM:
775 case I915_PARAM_NUM_FENCES_AVAIL:
776 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
778 case I915_PARAM_HAS_OVERLAY:
779 value = dev_priv->overlay ? 1 : 0;
781 case I915_PARAM_HAS_PAGEFLIPPING:
784 case I915_PARAM_HAS_EXECBUF2:
787 case I915_PARAM_HAS_BSD:
788 value = HAS_BSD(dev);
790 case I915_PARAM_HAS_BLT:
791 value = HAS_BLT(dev);
793 case I915_PARAM_HAS_RELAXED_FENCING:
796 case I915_PARAM_HAS_COHERENT_RINGS:
799 case I915_PARAM_HAS_EXEC_CONSTANTS:
800 value = INTEL_INFO(dev)->gen >= 4;
802 case I915_PARAM_HAS_RELAXED_DELTA:
805 case I915_PARAM_HAS_GEN7_SOL_RESET:
808 case I915_PARAM_HAS_LLC:
809 value = HAS_LLC(dev);
812 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
817 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
818 DRM_ERROR("DRM_COPY_TO_USER failed\n");
825 static int i915_setparam(struct drm_device *dev, void *data,
826 struct drm_file *file_priv)
828 drm_i915_private_t *dev_priv = dev->dev_private;
829 drm_i915_setparam_t *param = data;
832 DRM_ERROR("called with no initialization\n");
836 switch (param->param) {
837 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
839 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
840 dev_priv->tex_lru_log_granularity = param->value;
842 case I915_SETPARAM_ALLOW_BATCHBUFFER:
843 dev_priv->allow_batchbuffer = param->value;
845 case I915_SETPARAM_NUM_USED_FENCES:
846 if (param->value > dev_priv->num_fence_regs ||
849 /* Userspace can use first N regs */
850 dev_priv->fence_reg_start = param->value;
853 DRM_DEBUG("unknown parameter %d\n", param->param);
860 static int i915_set_status_page(struct drm_device *dev, void *data,
861 struct drm_file *file_priv)
863 drm_i915_private_t *dev_priv = dev->dev_private;
864 drm_i915_hws_addr_t *hws = data;
865 struct intel_ring_buffer *ring = LP_RING(dev_priv);
867 if (!I915_NEED_GFX_HWS(dev))
871 DRM_ERROR("called with no initialization\n");
875 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
876 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
877 DRM_ERROR("tried to set status page when mode setting active\n");
881 ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
882 hws->addr & (0x1ffff<<12);
884 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
885 dev_priv->hws_map.size = 4*1024;
886 dev_priv->hws_map.type = 0;
887 dev_priv->hws_map.flags = 0;
888 dev_priv->hws_map.mtrr = 0;
890 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
891 if (dev_priv->hws_map.virtual == NULL) {
892 i915_dma_cleanup(dev);
893 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
894 DRM_ERROR("can not ioremap virtual address for"
895 " G33 hw status page\n");
898 ring->status_page.page_addr = dev_priv->hw_status_page =
899 dev_priv->hws_map.virtual;
901 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
902 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
903 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
904 dev_priv->status_gfx_addr);
905 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
910 intel_enable_ppgtt(struct drm_device *dev)
912 if (i915_enable_ppgtt >= 0)
913 return i915_enable_ppgtt;
915 /* Disable ppgtt on SNB if VT-d is on. */
916 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
923 i915_load_gem_init(struct drm_device *dev)
925 struct drm_i915_private *dev_priv = dev->dev_private;
926 unsigned long prealloc_size, gtt_size, mappable_size;
929 prealloc_size = dev_priv->mm.gtt->stolen_size;
930 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
931 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
933 /* Basic memrange allocator for stolen space */
934 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
937 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
938 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
939 * aperture accordingly when using aliasing ppgtt. */
940 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
941 /* For paranoia keep the guard page in between. */
942 gtt_size -= PAGE_SIZE;
944 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
946 ret = i915_gem_init_aliasing_ppgtt(dev);
952 /* Let GEM Manage all of the aperture.
954 * However, leave one page at the end still bound to the scratch
955 * page. There are a number of places where the hardware
956 * apparently prefetches past the end of the object, and we've
957 * seen multiple hangs with the GPU head pointer stuck in a
958 * batchbuffer bound at the last page of the aperture. One page
959 * should be enough to keep any prefetching inside of the
962 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
965 ret = i915_gem_init_hw(dev);
968 i915_gem_cleanup_aliasing_ppgtt(dev);
973 /* Try to set up FBC with a reasonable compressed buffer size */
974 if (I915_HAS_FBC(dev) && i915_powersave) {
977 /* Leave 1M for line length buffer & misc. */
979 /* Try to get a 32M buffer... */
980 if (prealloc_size > (36*1024*1024))
981 cfb_size = 32*1024*1024;
982 else /* fall back to 7/8 of the stolen space */
983 cfb_size = prealloc_size * 7 / 8;
984 i915_setup_compression(dev, cfb_size);
988 /* Allow hardware batchbuffers unless told otherwise. */
989 dev_priv->allow_batchbuffer = 1;
994 i915_load_modeset_init(struct drm_device *dev)
996 struct drm_i915_private *dev_priv = dev->dev_private;
999 ret = intel_parse_bios(dev);
1001 DRM_INFO("failed to find VBIOS tables\n");
1004 intel_register_dsm_handler();
1007 /* IIR "flip pending" bit means done if this bit is set */
1008 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1009 dev_priv->flip_pending_is_done = true;
1011 intel_modeset_init(dev);
1013 ret = i915_load_gem_init(dev);
1017 intel_modeset_gem_init(dev);
1019 ret = drm_irq_install(dev);
1023 dev->vblank_disable_allowed = 1;
1025 ret = intel_fbdev_init(dev);
1029 drm_kms_helper_poll_init(dev);
1031 /* We're off and running w/KMS */
1032 dev_priv->mm.suspended = 0;
1038 i915_gem_cleanup_ringbuffer(dev);
1040 i915_gem_cleanup_aliasing_ppgtt(dev);
1045 i915_get_bridge_dev(struct drm_device *dev)
1047 struct drm_i915_private *dev_priv;
1049 dev_priv = dev->dev_private;
1051 dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1052 if (dev_priv->bridge_dev == NULL) {
1053 DRM_ERROR("bridge device not found\n");
1059 #define MCHBAR_I915 0x44
1060 #define MCHBAR_I965 0x48
1061 #define MCHBAR_SIZE (4*4096)
1063 #define DEVEN_REG 0x54
1064 #define DEVEN_MCHBAR_EN (1 << 28)
1066 /* Allocate space for the MCH regs if needed, return nonzero on error */
1068 intel_alloc_mchbar_resource(struct drm_device *dev)
1070 drm_i915_private_t *dev_priv;
1073 u32 temp_lo, temp_hi;
1074 u64 mchbar_addr, temp;
1076 dev_priv = dev->dev_private;
1077 reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1079 if (INTEL_INFO(dev)->gen >= 4)
1080 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1083 temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1084 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1086 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1087 #ifdef XXX_CONFIG_PNP
1089 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1093 /* Get some space for it */
1094 vga = device_get_parent(dev->dev);
1095 dev_priv->mch_res_rid = 0x100;
1096 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1097 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1098 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1099 if (dev_priv->mch_res == NULL) {
1100 DRM_ERROR("failed mchbar resource alloc\n");
1104 if (INTEL_INFO(dev)->gen >= 4) {
1105 temp = rman_get_start(dev_priv->mch_res);
1107 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1109 pci_write_config(dev_priv->bridge_dev, reg,
1110 rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1115 intel_setup_mchbar(struct drm_device *dev)
1117 drm_i915_private_t *dev_priv;
1122 dev_priv = dev->dev_private;
1123 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1125 dev_priv->mchbar_need_disable = false;
1127 if (IS_I915G(dev) || IS_I915GM(dev)) {
1128 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1129 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1131 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1135 /* If it's already enabled, don't have to do anything */
1137 DRM_DEBUG("mchbar already enabled\n");
1141 if (intel_alloc_mchbar_resource(dev))
1144 dev_priv->mchbar_need_disable = true;
1146 /* Space is allocated or reserved, so enable it. */
1147 if (IS_I915G(dev) || IS_I915GM(dev)) {
1148 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1149 temp | DEVEN_MCHBAR_EN, 4);
1151 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1152 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1157 intel_teardown_mchbar(struct drm_device *dev)
1159 drm_i915_private_t *dev_priv;
1164 dev_priv = dev->dev_private;
1165 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1167 if (dev_priv->mchbar_need_disable) {
1168 if (IS_I915G(dev) || IS_I915GM(dev)) {
1169 temp = pci_read_config(dev_priv->bridge_dev,
1171 temp &= ~DEVEN_MCHBAR_EN;
1172 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1175 temp = pci_read_config(dev_priv->bridge_dev,
1178 pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1183 if (dev_priv->mch_res != NULL) {
1184 vga = device_get_parent(dev->dev);
1185 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1186 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1187 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1188 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1189 dev_priv->mch_res = NULL;
1194 i915_driver_load(struct drm_device *dev, unsigned long flags)
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197 unsigned long base, size;
1202 /* i915 has 4 more counters */
1204 dev->types[6] = _DRM_STAT_IRQ;
1205 dev->types[7] = _DRM_STAT_PRIMARY;
1206 dev->types[8] = _DRM_STAT_SECONDARY;
1207 dev->types[9] = _DRM_STAT_DMA;
1209 dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1211 if (dev_priv == NULL)
1214 dev->dev_private = (void *)dev_priv;
1215 dev_priv->dev = dev;
1216 dev_priv->info = i915_get_device_id(dev->pci_device);
1218 if (i915_get_bridge_dev(dev)) {
1219 drm_free(dev_priv, DRM_MEM_DRIVER);
1222 dev_priv->mm.gtt = intel_gtt_get();
1224 /* Add register map (needed for suspend/resume) */
1225 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1226 base = drm_get_resource_start(dev, mmio_bar);
1227 size = drm_get_resource_len(dev, mmio_bar);
1229 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1230 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1232 dev_priv->tq = taskqueue_create("915", M_WAITOK,
1233 taskqueue_thread_enqueue, &dev_priv->tq);
1234 taskqueue_start_threads(&dev_priv->tq, 1, 0, -1, "i915 taskq");
1235 lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE);
1236 lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1237 lockinit(&dev_priv->error_completion_lock, "915cmp", 0, LK_CANRECURSE);
1238 lockinit(&dev_priv->rps_lock, "915rps", 0, LK_CANRECURSE);
1240 dev_priv->has_gem = 1;
1241 intel_irq_init(dev);
1243 intel_setup_mchbar(dev);
1244 intel_setup_gmbus(dev);
1245 intel_opregion_setup(dev);
1247 intel_setup_bios(dev);
1252 if (!I915_NEED_GFX_HWS(dev)) {
1253 ret = i915_init_phys_hws(dev);
1255 drm_rmmap(dev, dev_priv->mmio_map);
1256 drm_free(dev_priv, DRM_MEM_DRIVER);
1261 if (IS_PINEVIEW(dev))
1262 i915_pineview_get_mem_freq(dev);
1263 else if (IS_GEN5(dev))
1264 i915_ironlake_get_mem_freq(dev);
1266 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1268 if (IS_IVYBRIDGE(dev))
1269 dev_priv->num_pipe = 3;
1270 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1271 dev_priv->num_pipe = 2;
1273 dev_priv->num_pipe = 1;
1275 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1277 goto out_gem_unload;
1279 /* Start out suspended */
1280 dev_priv->mm.suspended = 1;
1282 intel_detect_pch(dev);
1284 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1286 ret = i915_load_modeset_init(dev);
1289 DRM_ERROR("failed to init modeset\n");
1290 goto out_gem_unload;
1294 intel_opregion_init(dev);
1296 callout_init_mp(&dev_priv->hangcheck_timer);
1297 callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1298 i915_hangcheck_elapsed, dev);
1301 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1302 i915_mch_dev = dev_priv;
1303 dev_priv->mchdev_lock = &mchdev_lock;
1304 lockmgr(&mchdev_lock, LK_RELEASE);
1311 (void) i915_driver_unload_int(dev, true);
1316 i915_driver_unload_int(struct drm_device *dev, bool locked)
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1323 ret = i915_gpu_idle(dev, true);
1325 DRM_ERROR("failed to idle hardware: %d\n", ret);
1331 intel_teardown_mchbar(dev);
1335 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1336 intel_fbdev_fini(dev);
1337 intel_modeset_cleanup(dev);
1340 /* Free error state after interrupts are fully disabled. */
1341 callout_stop(&dev_priv->hangcheck_timer);
1343 i915_destroy_error_state(dev);
1345 intel_opregion_fini(dev);
1350 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1353 i915_gem_free_all_phys_object(dev);
1354 i915_gem_cleanup_ringbuffer(dev);
1357 i915_gem_cleanup_aliasing_ppgtt(dev);
1361 if (I915_HAS_FBC(dev) && i915_powersave)
1362 i915_cleanup_compression(dev);
1364 drm_mm_takedown(&dev_priv->mm.stolen);
1366 intel_cleanup_overlay(dev);
1368 if (!I915_NEED_GFX_HWS(dev))
1372 i915_gem_unload(dev);
1374 lockuninit(&dev_priv->irq_lock);
1376 if (dev_priv->tq != NULL)
1377 taskqueue_free(dev_priv->tq);
1379 bus_generic_detach(dev->dev);
1380 drm_rmmap(dev, dev_priv->mmio_map);
1381 intel_teardown_gmbus(dev);
1383 lockuninit(&dev_priv->error_lock);
1384 lockuninit(&dev_priv->error_completion_lock);
1385 lockuninit(&dev_priv->rps_lock);
1386 drm_free(dev->dev_private, DRM_MEM_DRIVER);
1392 i915_driver_unload(struct drm_device *dev)
1395 return (i915_driver_unload_int(dev, true));
1399 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1401 struct drm_i915_file_private *i915_file_priv;
1403 i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1406 spin_init(&i915_file_priv->mm.lock);
1407 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1408 file_priv->driver_priv = i915_file_priv;
1414 i915_driver_lastclose(struct drm_device * dev)
1416 drm_i915_private_t *dev_priv = dev->dev_private;
1418 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1422 drm_fb_helper_restore();
1423 vga_switcheroo_process_delayed_switch();
1427 i915_gem_lastclose(dev);
1428 i915_dma_cleanup(dev);
1431 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1434 i915_gem_release(dev, file_priv);
1437 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1439 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1441 spin_uninit(&i915_file_priv->mm.lock);
1442 drm_free(i915_file_priv, DRM_MEM_FILES);
1445 struct drm_ioctl_desc i915_ioctls[] = {
1446 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1447 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1448 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1449 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1450 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1451 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1452 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1453 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1454 DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1455 DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1456 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1457 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1458 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1459 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1460 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1461 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1462 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1463 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1464 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1465 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1466 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1467 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1468 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1469 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1470 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1471 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1472 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1473 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1474 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1475 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1476 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1477 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1478 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1479 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1480 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1481 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1482 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1483 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1484 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1485 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1486 DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1487 DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1490 struct drm_driver i915_driver_info = {
1491 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1492 DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1493 DRIVER_GEM /*| DRIVER_MODESET*/,
1495 .buf_priv_size = sizeof(drm_i915_private_t),
1496 .load = i915_driver_load,
1497 .open = i915_driver_open,
1498 .unload = i915_driver_unload,
1499 .preclose = i915_driver_preclose,
1500 .lastclose = i915_driver_lastclose,
1501 .postclose = i915_driver_postclose,
1502 .device_is_agp = i915_driver_device_is_agp,
1503 .gem_init_object = i915_gem_init_object,
1504 .gem_free_object = i915_gem_free_object,
1505 .gem_pager_ops = &i915_gem_pager_ops,
1506 .dumb_create = i915_gem_dumb_create,
1507 .dumb_map_offset = i915_gem_mmap_gtt,
1508 .dumb_destroy = i915_gem_dumb_destroy,
1509 .sysctl_init = i915_sysctl_init,
1510 .sysctl_cleanup = i915_sysctl_cleanup,
1512 .ioctls = i915_ioctls,
1513 .max_ioctl = DRM_ARRAY_SIZE(i915_ioctls),
1515 .name = DRIVER_NAME,
1516 .desc = DRIVER_DESC,
1517 .date = DRIVER_DATE,
1518 .major = DRIVER_MAJOR,
1519 .minor = DRIVER_MINOR,
1520 .patchlevel = DRIVER_PATCHLEVEL,
1524 * Determine if the device really is AGP or not.
1526 * All Intel graphics chipsets are treated as AGP, even if they are really
1529 * \param dev The device to be tested.
1532 * A value of 1 is always retured to indictate every i9x5 is AGP.
1534 int i915_driver_device_is_agp(struct drm_device * dev)
1539 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1541 drm_i915_private_t *dev_priv = dev->dev_private;
1544 tmp = I915_READ(CLKCFG);
1546 switch (tmp & CLKCFG_FSB_MASK) {
1547 case CLKCFG_FSB_533:
1548 dev_priv->fsb_freq = 533; /* 133*4 */
1550 case CLKCFG_FSB_800:
1551 dev_priv->fsb_freq = 800; /* 200*4 */
1553 case CLKCFG_FSB_667:
1554 dev_priv->fsb_freq = 667; /* 167*4 */
1556 case CLKCFG_FSB_400:
1557 dev_priv->fsb_freq = 400; /* 100*4 */
1561 switch (tmp & CLKCFG_MEM_MASK) {
1562 case CLKCFG_MEM_533:
1563 dev_priv->mem_freq = 533;
1565 case CLKCFG_MEM_667:
1566 dev_priv->mem_freq = 667;
1568 case CLKCFG_MEM_800:
1569 dev_priv->mem_freq = 800;
1573 /* detect pineview DDR3 setting */
1574 tmp = I915_READ(CSHRDDR3CTL);
1575 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1578 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1580 drm_i915_private_t *dev_priv = dev->dev_private;
1583 ddrpll = I915_READ16(DDRMPLL1);
1584 csipll = I915_READ16(CSIPLL0);
1586 switch (ddrpll & 0xff) {
1588 dev_priv->mem_freq = 800;
1591 dev_priv->mem_freq = 1066;
1594 dev_priv->mem_freq = 1333;
1597 dev_priv->mem_freq = 1600;
1600 DRM_DEBUG("unknown memory frequency 0x%02x\n",
1602 dev_priv->mem_freq = 0;
1606 dev_priv->r_t = dev_priv->mem_freq;
1608 switch (csipll & 0x3ff) {
1610 dev_priv->fsb_freq = 3200;
1613 dev_priv->fsb_freq = 3733;
1616 dev_priv->fsb_freq = 4266;
1619 dev_priv->fsb_freq = 4800;
1622 dev_priv->fsb_freq = 5333;
1625 dev_priv->fsb_freq = 5866;
1628 dev_priv->fsb_freq = 6400;
1631 DRM_DEBUG("unknown fsb frequency 0x%04x\n",
1633 dev_priv->fsb_freq = 0;
1637 if (dev_priv->fsb_freq == 3200) {
1639 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1646 static const struct cparams {
1652 { 1, 1333, 301, 28664 },
1653 { 1, 1066, 294, 24460 },
1654 { 1, 800, 294, 25192 },
1655 { 0, 1333, 276, 27605 },
1656 { 0, 1066, 276, 27605 },
1657 { 0, 800, 231, 23784 },
1660 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1662 u64 total_count, diff, ret;
1663 u32 count1, count2, count3, m = 0, c = 0;
1664 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1667 diff1 = now - dev_priv->last_time1;
1669 * sysctl(8) reads the value of sysctl twice in rapid
1670 * succession. There is high chance that it happens in the
1671 * same timer tick. Use the cached value to not divide by
1672 * zero and give the hw a chance to gather more samples.
1675 return (dev_priv->chipset_power);
1677 count1 = I915_READ(DMIEC);
1678 count2 = I915_READ(DDREC);
1679 count3 = I915_READ(CSIEC);
1681 total_count = count1 + count2 + count3;
1683 /* FIXME: handle per-counter overflow */
1684 if (total_count < dev_priv->last_count1) {
1685 diff = ~0UL - dev_priv->last_count1;
1686 diff += total_count;
1688 diff = total_count - dev_priv->last_count1;
1691 for (i = 0; i < DRM_ARRAY_SIZE(cparams); i++) {
1692 if (cparams[i].i == dev_priv->c_m &&
1693 cparams[i].t == dev_priv->r_t) {
1700 diff = diff / diff1;
1701 ret = ((m * diff) + c);
1704 dev_priv->last_count1 = total_count;
1705 dev_priv->last_time1 = now;
1707 dev_priv->chipset_power = ret;
1711 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1713 unsigned long m, x, b;
1716 tsfs = I915_READ(TSFS);
1718 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1719 x = I915_READ8(I915_TR1);
1721 b = tsfs & TSFS_INTR_MASK;
1723 return ((m * x) / 127) - b;
1726 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1728 static const struct v_table {
1729 u16 vd; /* in .1 mil */
1730 u16 vm; /* in .1 mil */
1861 if (dev_priv->info->is_mobile)
1862 return v_table[pxvid].vm;
1864 return v_table[pxvid].vd;
1867 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1869 struct timespec now, diff1;
1871 unsigned long diffms;
1874 if (dev_priv->info->gen != 5)
1879 timespecsub(&diff1, &dev_priv->last_time2);
1881 /* Don't divide by 0 */
1882 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1886 count = I915_READ(GFXEC);
1888 if (count < dev_priv->last_count2) {
1889 diff = ~0UL - dev_priv->last_count2;
1892 diff = count - dev_priv->last_count2;
1895 dev_priv->last_count2 = count;
1896 dev_priv->last_time2 = now;
1898 /* More magic constants... */
1900 diff = diff / (diffms * 10);
1901 dev_priv->gfx_power = diff;
1904 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1906 unsigned long t, corr, state1, corr2, state2;
1909 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1910 pxvid = (pxvid >> 24) & 0x7f;
1911 ext_v = pvid_to_extvid(dev_priv, pxvid);
1915 t = i915_mch_val(dev_priv);
1917 /* Revel in the empirically derived constants */
1919 /* Correction factor in 1/100000 units */
1921 corr = ((t * 2349) + 135940);
1923 corr = ((t * 964) + 29317);
1925 corr = ((t * 301) + 1004);
1927 corr = corr * ((150142 * state1) / 10000 - 78642);
1929 corr2 = (corr * dev_priv->corr);
1931 state2 = (corr2 * state1) / 10000;
1932 state2 /= 100; /* convert to mW */
1934 i915_update_gfx_val(dev_priv);
1936 return dev_priv->gfx_power + state2;
1940 * i915_read_mch_val - return value for IPS use
1942 * Calculate and return a value for the IPS driver to use when deciding whether
1943 * we have thermal and power headroom to increase CPU or GPU power budget.
1945 unsigned long i915_read_mch_val(void)
1947 struct drm_i915_private *dev_priv;
1948 unsigned long chipset_val, graphics_val, ret = 0;
1950 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1953 dev_priv = i915_mch_dev;
1955 chipset_val = i915_chipset_val(dev_priv);
1956 graphics_val = i915_gfx_val(dev_priv);
1958 ret = chipset_val + graphics_val;
1961 lockmgr(&mchdev_lock, LK_RELEASE);
1967 * i915_gpu_raise - raise GPU frequency limit
1969 * Raise the limit; IPS indicates we have thermal headroom.
1971 bool i915_gpu_raise(void)
1973 struct drm_i915_private *dev_priv;
1976 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1977 if (!i915_mch_dev) {
1981 dev_priv = i915_mch_dev;
1983 if (dev_priv->max_delay > dev_priv->fmax)
1984 dev_priv->max_delay--;
1987 lockmgr(&mchdev_lock, LK_RELEASE);
1993 * i915_gpu_lower - lower GPU frequency limit
1995 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1996 * frequency maximum.
1998 bool i915_gpu_lower(void)
2000 struct drm_i915_private *dev_priv;
2003 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2004 if (!i915_mch_dev) {
2008 dev_priv = i915_mch_dev;
2010 if (dev_priv->max_delay < dev_priv->min_delay)
2011 dev_priv->max_delay++;
2014 lockmgr(&mchdev_lock, LK_RELEASE);
2020 * i915_gpu_busy - indicate GPU business to IPS
2022 * Tell the IPS driver whether or not the GPU is busy.
2024 bool i915_gpu_busy(void)
2026 struct drm_i915_private *dev_priv;
2029 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2032 dev_priv = i915_mch_dev;
2034 ret = dev_priv->busy;
2037 lockmgr(&mchdev_lock, LK_RELEASE);
2043 * i915_gpu_turbo_disable - disable graphics turbo
2045 * Disable graphics turbo by resetting the max frequency and setting the
2046 * current frequency to the default.
2048 bool i915_gpu_turbo_disable(void)
2050 struct drm_i915_private *dev_priv;
2053 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2054 if (!i915_mch_dev) {
2058 dev_priv = i915_mch_dev;
2060 dev_priv->max_delay = dev_priv->fstart;
2062 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2066 lockmgr(&mchdev_lock, LK_RELEASE);