2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
34 * $DragonFly: src/sys/cpu/i386/include/cpufunc.h,v 1.21 2007/04/27 23:23:59 dillon Exp $
38 * Functions to provide access to special i386 instructions.
41 #ifndef _CPU_CPUFUNC_H_
42 #define _CPU_CPUFUNC_H_
45 #include <sys/types.h>
48 #include <sys/cdefs.h>
52 #define readb(va) (*(volatile u_int8_t *) (va))
53 #define readw(va) (*(volatile u_int16_t *) (va))
54 #define readl(va) (*(volatile u_int32_t *) (va))
56 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
57 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
58 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
63 #include <machine/lock.h> /* XXX */
66 #ifdef SWTCH_OPTIM_STATS
67 extern int tlb_flush_count; /* XXX */
73 __asm __volatile("int $3");
79 __asm __volatile("pause");
83 * Find the first 1 in mask, starting with bit 0 and return the
84 * bit number. If mask is 0 the result is undefined.
91 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
96 * Find the last 1 in mask, starting with bit 31 and return the
97 * bit number. If mask is 0 the result is undefined.
104 __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
109 * Test and set the specified bit (1 << bit) in the integer. The
110 * previous value of the bit is returned (0 or 1).
113 btsl(u_int *mask, int bit)
117 __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
118 "=r"(result), "=m"(*mask) : "r" (bit));
123 * Test and clear the specified bit (1 << bit) in the integer. The
124 * previous value of the bit is returned (0 or 1).
127 btrl(u_int *mask, int bit)
131 __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
132 "=r"(result), "=m"(*mask) : "r" (bit));
137 do_cpuid(u_int ax, u_int *p)
139 __asm __volatile("cpuid"
140 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
145 cpuid_count(u_int ax, u_int cx, u_int *p)
147 __asm __volatile("cpuid"
148 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
149 : "0" (ax), "c" (cx));
152 #ifndef _CPU_DISABLE_INTR_DEFINED
155 cpu_disable_intr(void)
157 __asm __volatile("cli" : : : "memory");
162 #ifndef _CPU_ENABLE_INTR_DEFINED
165 cpu_enable_intr(void)
167 __asm __volatile("sti");
173 * Cpu and compiler memory ordering fence. mfence ensures strong read and
176 * A serializing or fence instruction is required here. A locked bus
177 * cycle on data for which we already own cache mastership is the most
185 __asm __volatile("mfence" : : : "memory");
187 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
190 __asm __volatile("" : : : "memory");
195 * cpu_lfence() ensures strong read ordering for reads issued prior
196 * to the instruction verses reads issued afterwords.
198 * A serializing or fence instruction is required here. A locked bus
199 * cycle on data for which we already own cache mastership is the most
207 __asm __volatile("lfence" : : : "memory");
209 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
212 __asm __volatile("" : : : "memory");
217 * cpu_sfence() ensures strong write ordering for writes issued prior
218 * to the instruction verses writes issued afterwords. Writes are
219 * ordered on intel cpus so we do not actually have to do anything.
226 * Don't use 'sfence' here, as it will create a lot of
227 * unnecessary stalls.
229 __asm __volatile("" : : : "memory");
233 * cpu_ccfence() prevents the compiler from reordering instructions, in
234 * particular stores, relative to the current cpu. Use cpu_sfence() if
235 * you need to guarentee ordering by both the compiler and by the cpu.
237 * This also prevents the compiler from caching memory loads into local
238 * variables across the routine.
243 __asm __volatile("" : : : "memory");
248 #define HAVE_INLINE_FFS
254 * Note that gcc-2's builtin ffs would be used if we didn't declare
255 * this inline or turn off the builtin. The builtin is faster but
256 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
259 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
262 #define HAVE_INLINE_FLS
267 return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
273 * The following complications are to get around gcc not having a
274 * constraint letter for the range 0..255. We still put "d" in the
275 * constraint because "i" isn't a valid constraint when the port
276 * isn't constant. This only matters for -O0 because otherwise
277 * the non-working version gets optimized away.
279 * Use an expression-statement instead of a conditional expression
280 * because gcc-2.6.0 would promote the operands of the conditional
281 * and produce poor code for "if ((inb(var) & const1) == const2)".
283 * The unnecessary test `(port) < 0x10000' is to generate a warning if
284 * the `port' has type u_short or smaller. Such types are pessimal.
285 * This actually only works for signed types. The range check is
286 * careful to avoid generating warnings.
288 #define inb(port) __extension__ ({ \
290 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
291 && (port) < 0x10000) \
292 _data = inbc(port); \
294 _data = inbv(port); \
297 #define outb(port, data) ( \
298 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
299 && (port) < 0x10000 \
300 ? outbc(port, data) : outbv(port, data))
302 static __inline u_char
307 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
312 outbc(u_int port, u_char data)
314 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
317 static __inline u_char
322 * We use %%dx and not %1 here because i/o is done at %dx and not at
323 * %edx, while gcc generates inferior code (movw instead of movl)
324 * if we tell it to load (u_short) port.
326 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
330 static __inline u_int
335 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
340 insb(u_int port, void *addr, size_t cnt)
342 __asm __volatile("cld; rep; insb"
343 : "=D" (addr), "=c" (cnt)
344 : "0" (addr), "1" (cnt), "d" (port)
349 insw(u_int port, void *addr, size_t cnt)
351 __asm __volatile("cld; rep; insw"
352 : "=D" (addr), "=c" (cnt)
353 : "0" (addr), "1" (cnt), "d" (port)
358 insl(u_int port, void *addr, size_t cnt)
360 __asm __volatile("cld; rep; insl"
361 : "=D" (addr), "=c" (cnt)
362 : "0" (addr), "1" (cnt), "d" (port)
369 __asm __volatile("invd");
375 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
376 * will cause the invl*() functions to be equivalent to the cpu_invl*()
380 void smp_invltlb(void);
381 void smp_invltlb_intr(void);
383 #define smp_invltlb()
386 #ifndef _CPU_INVLPG_DEFINED
389 * Invalidate a patricular VA on this cpu only
392 cpu_invlpg(void *addr)
394 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
399 #ifndef _CPU_INVLTLB_DEFINED
402 * Invalidate the TLB on this cpu only
409 * This should be implemented as load_cr3(rcr3()) when load_cr3()
412 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
414 #if defined(SWTCH_OPTIM_STATS)
424 __asm __volatile("rep; nop");
429 static __inline u_short
434 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
438 static __inline u_int
439 loadandclear(volatile u_int *addr)
443 __asm __volatile("xorl %0,%0; xchgl %1,%0"
444 : "=&r" (result) : "m" (*addr));
449 outbv(u_int port, u_char data)
453 * Use an unnecessary assignment to help gcc's register allocator.
454 * This make a large difference for gcc-1.40 and a tiny difference
455 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
456 * best results. gcc-2.6.0 can't handle this.
459 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
463 outl(u_int port, u_int data)
466 * outl() and outw() aren't used much so we haven't looked at
467 * possible micro-optimizations such as the unnecessary
468 * assignment for them.
470 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
474 outsb(u_int port, const void *addr, size_t cnt)
476 __asm __volatile("cld; rep; outsb"
477 : "=S" (addr), "=c" (cnt)
478 : "0" (addr), "1" (cnt), "d" (port));
482 outsw(u_int port, const void *addr, size_t cnt)
484 __asm __volatile("cld; rep; outsw"
485 : "=S" (addr), "=c" (cnt)
486 : "0" (addr), "1" (cnt), "d" (port));
490 outsl(u_int port, const void *addr, size_t cnt)
492 __asm __volatile("cld; rep; outsl"
493 : "=S" (addr), "=c" (cnt)
494 : "0" (addr), "1" (cnt), "d" (port));
498 outw(u_int port, u_short data)
500 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
503 static __inline u_int
508 __asm __volatile("movl %%cr2,%0" : "=r" (data));
512 static __inline u_int
517 __asm __volatile("pushfl; popl %0" : "=r" (ef));
521 static __inline u_int64_t
526 __asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
530 static __inline u_int64_t
535 __asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
539 #define _RDTSC_SUPPORTED_
541 static __inline u_int64_t
546 __asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
553 __asm __volatile("wbinvd");
557 write_eflags(u_int ef)
559 __asm __volatile("pushl %0; popfl" : : "r" (ef));
563 wrmsr(u_int msr, u_int64_t newval)
565 __asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
568 static __inline u_int
572 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
576 static __inline u_int
580 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
587 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
593 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
596 static __inline u_int
600 __asm __volatile("movl %%dr0,%0" : "=r" (data));
607 __asm __volatile("movl %0,%%dr0" : : "r" (sel));
610 static __inline u_int
614 __asm __volatile("movl %%dr1,%0" : "=r" (data));
621 __asm __volatile("movl %0,%%dr1" : : "r" (sel));
624 static __inline u_int
628 __asm __volatile("movl %%dr2,%0" : "=r" (data));
635 __asm __volatile("movl %0,%%dr2" : : "r" (sel));
638 static __inline u_int
642 __asm __volatile("movl %%dr3,%0" : "=r" (data));
649 __asm __volatile("movl %0,%%dr3" : : "r" (sel));
652 static __inline u_int
656 __asm __volatile("movl %%dr4,%0" : "=r" (data));
663 __asm __volatile("movl %0,%%dr4" : : "r" (sel));
666 static __inline u_int
670 __asm __volatile("movl %%dr5,%0" : "=r" (data));
677 __asm __volatile("movl %0,%%dr5" : : "r" (sel));
680 static __inline u_int
684 __asm __volatile("movl %%dr6,%0" : "=r" (data));
691 __asm __volatile("movl %0,%%dr6" : : "r" (sel));
694 static __inline u_int
698 __asm __volatile("movl %%dr7,%0" : "=r" (data));
705 __asm __volatile("movl %0,%%dr7" : : "r" (sel));
708 #else /* !__GNUC__ */
710 int breakpoint (void);
711 void cpu_pause (void);
712 u_int bsfl (u_int mask);
713 u_int bsrl (u_int mask);
714 void cpu_disable_intr (void);
715 void do_cpuid (u_int ax, u_int *p);
716 void cpu_enable_intr (void);
717 u_char inb (u_int port);
718 u_int inl (u_int port);
719 void insb (u_int port, void *addr, size_t cnt);
720 void insl (u_int port, void *addr, size_t cnt);
721 void insw (u_int port, void *addr, size_t cnt);
723 u_short inw (u_int port);
724 u_int loadandclear (u_int *addr);
725 void outb (u_int port, u_char data);
726 void outl (u_int port, u_int data);
727 void outsb (u_int port, void *addr, size_t cnt);
728 void outsl (u_int port, void *addr, size_t cnt);
729 void outsw (u_int port, void *addr, size_t cnt);
730 void outw (u_int port, u_short data);
732 u_int64_t rdmsr (u_int msr);
733 u_int64_t rdpmc (u_int pmc);
734 u_int64_t rdtsc (void);
735 u_int read_eflags (void);
737 void write_eflags (u_int ef);
738 void wrmsr (u_int msr, u_int64_t newval);
741 void load_fs (u_int sel);
742 void load_gs (u_int sel);
744 #endif /* __GNUC__ */
746 void load_cr0 (u_int cr0);
747 void load_cr3 (u_int cr3);
748 void load_cr4 (u_int cr4);
749 void ltr (u_short sel);
753 int rdmsr_safe (u_int msr, uint64_t *val);
754 void reset_dbregs (void);
757 #endif /* !_CPU_CPUFUNC_H_ */