2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
31 * that this driver still in its early stage, and possible of rewrite are
32 * pretty much guaranteed. There are supposedly several distinct parent/child
33 * busses to make this "perfect", but as for now and for the sake of
34 * simplicity, everything is gobble up within single source.
37 * 1) HDA Controller support
38 * 2) HDA Codecs support, which may include
41 * 3) Widget parser - the real magic of why this driver works on so
42 * many hardwares with minimal vendor specific quirk. The original
43 * parser was written using Ruby and can be found at
44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
45 * ruby parser take the verbose dmesg dump as its input. Refer to
46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
47 * interesting documents, especially UAA (Universal Audio Architecture).
48 * 4) Possible vendor specific support.
49 * (snd_hda_intel, snd_hda_ati, etc..)
51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
52 * Compaq V3000 with Conexant HDA.
54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
56 * * This driver is a collaborative effort made by: *
58 * * Stephane E. Potvin <sepotvin@videotron.ca> *
59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
60 * * Wesley Morgan <morganw@chemikals.org> *
61 * * Daniel Eischen <deischen@FreeBSD.org> *
62 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
63 * * Ariff Abdullah <ariff@FreeBSD.org> *
64 * * Alexander Motin <mav@FreeBSD.org> *
66 * * ....and various people from freebsd-multimedia@FreeBSD.org *
68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
71 #ifdef HAVE_KERNEL_OPTION_HEADERS
75 #include <dev/sound/pcm/sound.h>
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
79 #include <sys/ctype.h>
80 #include <sys/taskqueue.h>
82 #include <dev/sound/pci/hda/hdac_private.h>
83 #include <dev/sound/pci/hda/hdac_reg.h>
84 #include <dev/sound/pci/hda/hda_reg.h>
85 #include <dev/sound/pci/hda/hdac.h>
89 #define HDA_DRV_TEST_REV "20100226_0142"
91 SND_DECLARE_FILE("$FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.135 2011/06/15 19:53:08 joel Exp $");
93 #define HDA_BOOTVERBOSE(stmt) do { \
94 if (bootverbose != 0 || snd_verbose > 3) { \
99 #define HDA_BOOTHVERBOSE(stmt) do { \
100 if (snd_verbose > 3) { \
106 #undef HDAC_INTR_EXTRA
107 #define HDAC_INTR_EXTRA 1
110 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
111 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
112 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
113 #define hdac_lockowned(sc) mtx_owned((sc)->lock)
115 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
116 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
117 (fl) == 0xffffffff || \
118 (((fl) & 0xffff0000) == 0xffff0000 && \
119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
120 (((fl) & 0x0000ffff) == 0x0000ffff && \
121 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
122 #define HDA_MATCH_ALL 0xffffffff
123 #define HDAC_INVALID 0xffffffff
125 /* Default controller / jack sense poll: 250ms */
126 #define HDAC_POLL_INTERVAL max(hz >> 2, 1)
129 * Make room for possible 4096 playback/record channels, in 100 years to come.
131 #define HDAC_TRIGGER_NONE 0x00000000
132 #define HDAC_TRIGGER_PLAY 0x00000fff
133 #define HDAC_TRIGGER_REC 0x00fff000
134 #define HDAC_TRIGGER_UNSOL 0x80000000
136 #define HDA_MODEL_CONSTRUCT(vendor, model) \
137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
139 /* Controller models */
142 #define INTEL_VENDORID 0x8086
143 #define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20)
144 #define HDA_INTEL_PATSBURG HDA_MODEL_CONSTRUCT(INTEL, 0x1d20)
145 #define HDA_INTEL_PPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x1e20)
146 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
147 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
148 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
149 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
150 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
151 #define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e)
152 #define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e)
153 #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56)
154 #define HDA_INTEL_PCH2 HDA_MODEL_CONSTRUCT(INTEL, 0x3b57)
155 #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b)
156 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
159 #define NVIDIA_VENDORID 0x10de
160 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
161 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
162 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
163 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
164 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
165 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
166 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)
167 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)
168 #define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774)
169 #define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775)
170 #define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776)
171 #define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777)
172 #define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc)
173 #define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd)
174 #define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0)
175 #define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1)
176 #define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2)
177 #define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3)
178 #define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94)
179 #define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95)
180 #define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96)
181 #define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97)
182 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
185 #define ATI_VENDORID 0x1002
186 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
187 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
188 #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b)
189 #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919)
190 #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f)
191 #define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00)
192 #define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08)
193 #define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10)
194 #define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18)
195 #define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20)
196 #define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28)
197 #define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30)
198 #define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38)
199 #define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40)
200 #define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48)
201 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
204 #define RDC_VENDORID 0x17f3
205 #define HDA_RDC_M3010 HDA_MODEL_CONSTRUCT(RDC, 0x3010)
208 #define VIA_VENDORID 0x1106
209 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
210 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
213 #define SIS_VENDORID 0x1039
214 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
215 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
218 #define ULI_VENDORID 0x10b9
219 #define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461)
220 #define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff)
225 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
228 #define HP_VENDORID 0x103c
229 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
230 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
231 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
232 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
233 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
234 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
235 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
236 #define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801)
237 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802)
238 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
239 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
240 #define HP_NX6325_SUBVENDORX 0x103c30b0
243 #define DELL_VENDORID 0x1028
244 #define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9)
245 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
246 #define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227)
247 #define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228)
248 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
249 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
250 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
251 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
254 #define CLEVO_VENDORID 0x1558
255 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
256 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
259 #define ACER_VENDORID 0x1025
260 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
261 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127)
262 #define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f)
263 #define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133)
264 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
265 #define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b)
266 #define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f)
267 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
270 #define ASUS_VENDORID 0x1043
271 #define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
272 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
273 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
274 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
275 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
276 #define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339)
277 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
278 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
279 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
280 #define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f)
281 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
282 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
283 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
284 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
285 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
286 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
287 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
290 #define IBM_VENDORID 0x1014
291 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
292 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
295 #define LENOVO_VENDORID 0x17aa
296 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
297 #define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e)
298 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)
299 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
302 #define SAMSUNG_VENDORID 0x144d
303 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
304 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
307 #define MEDION_VENDORID 0x161f
308 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
309 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
311 /* Apple Computer Inc. */
312 #define APPLE_VENDORID 0x106b
313 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)
316 #define SONY_VENDORID 0x104d
317 #define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc)
318 #define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff)
321 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
322 * instead of their own, which is beyond my comprehension
323 * (see HDA_CODEC_STAC9221 below).
325 #define APPLE_INTEL_MAC 0x76808384
326 #define APPLE_MACBOOKPRO55 0xcb7910de
329 #define LG_VENDORID 0x1854
330 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
331 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
333 /* Fujitsu Siemens */
334 #define FS_VENDORID 0x1734
335 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
336 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd)
337 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
339 /* Fujitsu Limited */
340 #define FL_VENDORID 0x10cf
341 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326)
342 #define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d)
343 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff)
346 #define TOSHIBA_VENDORID 0x1179
347 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
348 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)
349 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
351 /* Micro-Star International (MSI) */
352 #define MSI_VENDORID 0x1462
353 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
354 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a)
355 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
357 /* Giga-Byte Technology */
358 #define GB_VENDORID 0x1458
359 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022)
360 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff)
363 #define UNIWILL_VENDORID 0x1584
364 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
365 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
368 /* Misc constants.. */
369 #define HDA_AMP_VOL_DEFAULT (-1)
370 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
371 #define HDA_AMP_MUTE_NONE (0)
372 #define HDA_AMP_MUTE_LEFT (1 << 0)
373 #define HDA_AMP_MUTE_RIGHT (1 << 1)
374 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
376 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
377 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
379 #define HDA_ADC_MONITOR (1 << 0)
381 #define HDA_CTL_OUT 1
384 #define HDA_GPIO_MAX 8
385 /* 0 - 7 = GPIO , 8 = Flush */
386 #define HDA_QUIRK_GPIO0 (1 << 0)
387 #define HDA_QUIRK_GPIO1 (1 << 1)
388 #define HDA_QUIRK_GPIO2 (1 << 2)
389 #define HDA_QUIRK_GPIO3 (1 << 3)
390 #define HDA_QUIRK_GPIO4 (1 << 4)
391 #define HDA_QUIRK_GPIO5 (1 << 5)
392 #define HDA_QUIRK_GPIO6 (1 << 6)
393 #define HDA_QUIRK_GPIO7 (1 << 7)
394 #define HDA_QUIRK_GPIOFLUSH (1 << 8)
396 /* 9 - 25 = anything else */
397 #define HDA_QUIRK_SOFTPCMVOL (1 << 9)
398 #define HDA_QUIRK_FIXEDRATE (1 << 10)
399 #define HDA_QUIRK_FORCESTEREO (1 << 11)
400 #define HDA_QUIRK_EAPDINV (1 << 12)
401 #define HDA_QUIRK_DMAPOS (1 << 13)
402 #define HDA_QUIRK_SENSEINV (1 << 14)
404 /* 26 - 31 = vrefs */
405 #define HDA_QUIRK_IVREF50 (1 << 26)
406 #define HDA_QUIRK_IVREF80 (1 << 27)
407 #define HDA_QUIRK_IVREF100 (1 << 28)
408 #define HDA_QUIRK_OVREF50 (1 << 29)
409 #define HDA_QUIRK_OVREF80 (1 << 30)
410 #define HDA_QUIRK_OVREF100 (1 << 31)
412 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
414 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
416 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
418 #if __FreeBSD_version < 600000
419 #define taskqueue_drain(...)
422 static const struct {
425 } hdac_quirks_tab[] = {
426 { "gpio0", HDA_QUIRK_GPIO0 },
427 { "gpio1", HDA_QUIRK_GPIO1 },
428 { "gpio2", HDA_QUIRK_GPIO2 },
429 { "gpio3", HDA_QUIRK_GPIO3 },
430 { "gpio4", HDA_QUIRK_GPIO4 },
431 { "gpio5", HDA_QUIRK_GPIO5 },
432 { "gpio6", HDA_QUIRK_GPIO6 },
433 { "gpio7", HDA_QUIRK_GPIO7 },
434 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
435 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
436 { "fixedrate", HDA_QUIRK_FIXEDRATE },
437 { "forcestereo", HDA_QUIRK_FORCESTEREO },
438 { "eapdinv", HDA_QUIRK_EAPDINV },
439 { "dmapos", HDA_QUIRK_DMAPOS },
440 { "senseinv", HDA_QUIRK_SENSEINV },
441 { "ivref50", HDA_QUIRK_IVREF50 },
442 { "ivref80", HDA_QUIRK_IVREF80 },
443 { "ivref100", HDA_QUIRK_IVREF100 },
444 { "ovref50", HDA_QUIRK_OVREF50 },
445 { "ovref80", HDA_QUIRK_OVREF80 },
446 { "ovref100", HDA_QUIRK_OVREF100 },
447 { "ivref", HDA_QUIRK_IVREF },
448 { "ovref", HDA_QUIRK_OVREF },
449 { "vref", HDA_QUIRK_VREF },
451 #define HDAC_QUIRKS_TAB_LEN \
452 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
454 #define HDA_BDL_MIN 2
455 #define HDA_BDL_MAX 256
456 #define HDA_BDL_DEFAULT HDA_BDL_MIN
458 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
459 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
461 #define HDA_BUFSZ_MIN 4096
462 #define HDA_BUFSZ_MAX 65536
463 #define HDA_BUFSZ_DEFAULT 16384
465 #define HDA_PARSE_MAXDEPTH 10
467 #define HDAC_UNSOLTAG_EVENT_HP 0x00
469 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
471 const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red",
472 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D",
475 const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD",
476 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in",
477 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"};
479 const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"};
482 static uint32_t hdac_fmt[] = {
483 SND_FORMAT(AFMT_S16_LE, 2, 0),
487 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
489 #define HDAC_NO_MSI 1
490 #define HDAC_NO_64BIT 2
492 static const struct {
497 { HDA_INTEL_CPT, "Intel Cougar Point", 0 },
498 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0 },
499 { HDA_INTEL_PPT1, "Intel Panther Point", 0 },
500 { HDA_INTEL_82801F, "Intel 82801F", 0 },
501 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 },
502 { HDA_INTEL_82801G, "Intel 82801G", 0 },
503 { HDA_INTEL_82801H, "Intel 82801H", 0 },
504 { HDA_INTEL_82801I, "Intel 82801I", 0 },
505 { HDA_INTEL_82801JI, "Intel 82801JI", 0 },
506 { HDA_INTEL_82801JD, "Intel 82801JD", 0 },
507 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0 },
508 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0 },
509 { HDA_INTEL_SCH, "Intel SCH", 0 },
510 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI },
511 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI },
512 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 },
513 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 },
514 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 },
515 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 },
516 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 },
517 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 },
518 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 },
519 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 },
520 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT },
521 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT },
522 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT },
523 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT },
524 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 },
525 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 },
526 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 },
527 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 },
528 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 },
529 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 },
530 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 },
531 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 },
532 { HDA_ATI_SB450, "ATI SB450", 0 },
533 { HDA_ATI_SB600, "ATI SB600", 0 },
534 { HDA_ATI_RS600, "ATI RS600", 0 },
535 { HDA_ATI_RS690, "ATI RS690", 0 },
536 { HDA_ATI_RS780, "ATI RS780", 0 },
537 { HDA_ATI_R600, "ATI R600", 0 },
538 { HDA_ATI_RV610, "ATI RV610", 0 },
539 { HDA_ATI_RV620, "ATI RV620", 0 },
540 { HDA_ATI_RV630, "ATI RV630", 0 },
541 { HDA_ATI_RV635, "ATI RV635", 0 },
542 { HDA_ATI_RV710, "ATI RV710", 0 },
543 { HDA_ATI_RV730, "ATI RV730", 0 },
544 { HDA_ATI_RV740, "ATI RV740", 0 },
545 { HDA_ATI_RV770, "ATI RV770", 0 },
546 { HDA_RDC_M3010, "RDC M3010", 0 },
547 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 },
548 { HDA_SIS_966, "SiS 966", 0 },
549 { HDA_ULI_M5461, "ULI M5461", 0 },
551 { HDA_INTEL_ALL, "Intel (Unknown)" },
552 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
553 { HDA_ATI_ALL, "ATI (Unknown)" },
554 { HDA_VIA_ALL, "VIA (Unknown)" },
555 { HDA_SIS_ALL, "SiS (Unknown)" },
556 { HDA_ULI_ALL, "ULI (Unknown)" },
558 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
560 static const struct {
565 } hdac_pcie_snoop[] = {
566 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
567 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
568 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
570 #define HDAC_PCIESNOOP_LEN \
571 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
573 static const struct {
580 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
581 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
582 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
583 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
584 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
585 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
586 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
587 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
588 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
589 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
590 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
591 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
592 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
593 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
594 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
595 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
596 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
597 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
598 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
599 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
600 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
601 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
602 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
603 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
604 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
605 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
606 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
607 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
608 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
609 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
610 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
611 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
612 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
613 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
614 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
616 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
618 /* All codecs you can eat... */
619 #define HDA_CODEC_CONSTRUCT(vendor, id) \
620 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
623 #define CIRRUSLOGIC_VENDORID 0x1013
624 #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206)
625 #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207)
626 #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff)
629 #define REALTEK_VENDORID 0x10ec
630 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
631 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
632 #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267)
633 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
634 #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269)
635 #define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270)
636 #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272)
637 #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273)
638 #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275)
639 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
640 #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662)
641 #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663)
642 #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665)
643 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
644 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
645 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
646 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
647 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
648 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
649 #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887)
650 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
651 #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889)
652 #define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892)
653 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
656 #define ANALOGDEVICES_VENDORID 0x11d4
657 #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a)
658 #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882)
659 #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883)
660 #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884)
661 #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a)
662 #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b)
663 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
664 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
665 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984)
666 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
667 #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987)
668 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
669 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
670 #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a)
671 #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b)
672 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
675 #define CMEDIA_VENDORID 0x434d
676 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
677 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
680 #define SIGMATEL_VENDORID 0x8384
681 #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612)
682 #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613)
683 #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614)
684 #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615)
685 #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616)
686 #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617)
687 #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
688 #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619)
689 #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620)
690 #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621)
691 #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622)
692 #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623)
693 #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624)
694 #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625)
695 #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626)
696 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
697 #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628)
698 #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629)
699 #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634)
700 #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636)
701 #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638)
702 #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639)
703 #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645)
704 #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646)
705 #define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661)
706 #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662)
707 #define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664)
708 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
709 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
710 #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682)
711 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
712 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
713 #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691)
714 #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698)
715 #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699)
716 #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0)
717 #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1)
718 #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2)
719 #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3)
720 #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880)
721 #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882)
722 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
725 #define IDT_VENDORID 0x111d
726 #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603)
727 #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604)
728 #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605)
729 #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608)
730 #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674)
731 #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675)
732 #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676)
733 #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0)
734 #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2)
735 #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6)
736 #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4)
737 #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5)
738 #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff)
741 #define SII_VENDORID 0x1095
742 #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390)
743 #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392)
744 #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff)
747 #define AGERE_VENDORID 0x11c1
748 #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff)
751 #define CONEXANT_VENDORID 0x14f1
752 #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
753 #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
754 #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051)
755 #define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066)
756 #define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067)
757 #define HDA_CODEC_CX20584 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5068)
758 #define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069)
759 #define HDA_CODEC_CX20590 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506e)
760 #define HDA_CODEC_CX20631 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5097)
761 #define HDA_CODEC_CX20632 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5098)
762 #define HDA_CODEC_CX20641 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a1)
763 #define HDA_CODEC_CX20642 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a2)
764 #define HDA_CODEC_CX20651 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ab)
765 #define HDA_CODEC_CX20652 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ac)
766 #define HDA_CODEC_CX20664 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b8)
767 #define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9)
768 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
771 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
772 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
773 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
774 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
775 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
776 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
777 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
778 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
779 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
780 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
781 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
782 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
783 #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720)
784 #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721)
785 #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722)
786 #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723)
787 #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724)
788 #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725)
789 #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726)
790 #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727)
791 #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397)
792 #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397)
793 #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397)
794 #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397)
795 #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397)
796 #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397)
797 #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397)
798 #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397)
799 #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398)
800 #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398)
801 #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398)
802 #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398)
803 #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398)
804 #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398)
805 #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398)
806 #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398)
807 #define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433)
808 #define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721)
809 #define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428)
810 #define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428)
811 #define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448)
812 #define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440)
813 #define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441)
814 #define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438)
815 #define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438)
816 #define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441)
817 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
820 #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c)
821 #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919)
822 #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a)
823 #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01)
824 #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff)
827 #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002)
828 #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006)
829 #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007)
830 #define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a)
831 #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b)
832 #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c)
833 #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d)
834 #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067)
835 #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001)
836 #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff)
839 #define HDA_CODEC_INTELIP HDA_CODEC_CONSTRUCT(INTEL, 0x0054)
840 #define HDA_CODEC_INTELBL HDA_CODEC_CONSTRUCT(INTEL, 0x2801)
841 #define HDA_CODEC_INTELCA HDA_CODEC_CONSTRUCT(INTEL, 0x2802)
842 #define HDA_CODEC_INTELEL HDA_CODEC_CONSTRUCT(INTEL, 0x2803)
843 #define HDA_CODEC_INTELIP2 HDA_CODEC_CONSTRUCT(INTEL, 0x2804)
844 #define HDA_CODEC_INTELCPT HDA_CODEC_CONSTRUCT(INTEL, 0x2805)
845 #define HDA_CODEC_INTELCL HDA_CODEC_CONSTRUCT(INTEL, 0x29fb)
846 #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff)
849 static const struct {
853 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" },
854 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" },
855 { HDA_CODEC_ALC260, "Realtek ALC260" },
856 { HDA_CODEC_ALC262, "Realtek ALC262" },
857 { HDA_CODEC_ALC267, "Realtek ALC267" },
858 { HDA_CODEC_ALC268, "Realtek ALC268" },
859 { HDA_CODEC_ALC269, "Realtek ALC269" },
860 { HDA_CODEC_ALC270, "Realtek ALC270" },
861 { HDA_CODEC_ALC272, "Realtek ALC272" },
862 { HDA_CODEC_ALC273, "Realtek ALC273" },
863 { HDA_CODEC_ALC275, "Realtek ALC275" },
864 { HDA_CODEC_ALC660, "Realtek ALC660" },
865 { HDA_CODEC_ALC662, "Realtek ALC662" },
866 { HDA_CODEC_ALC663, "Realtek ALC663" },
867 { HDA_CODEC_ALC665, "Realtek ALC665" },
868 { HDA_CODEC_ALC861, "Realtek ALC861" },
869 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
870 { HDA_CODEC_ALC880, "Realtek ALC880" },
871 { HDA_CODEC_ALC882, "Realtek ALC882" },
872 { HDA_CODEC_ALC883, "Realtek ALC883" },
873 { HDA_CODEC_ALC885, "Realtek ALC885" },
874 { HDA_CODEC_ALC887, "Realtek ALC887" },
875 { HDA_CODEC_ALC888, "Realtek ALC888" },
876 { HDA_CODEC_ALC889, "Realtek ALC889" },
877 { HDA_CODEC_ALC892, "Realtek ALC892" },
878 { HDA_CODEC_AD1882, "Analog Devices AD1882" },
879 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" },
880 { HDA_CODEC_AD1883, "Analog Devices AD1883" },
881 { HDA_CODEC_AD1884, "Analog Devices AD1884" },
882 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" },
883 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
884 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
885 { HDA_CODEC_AD1984, "Analog Devices AD1984" },
886 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" },
887 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" },
888 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
889 { HDA_CODEC_AD1987, "Analog Devices AD1987" },
890 { HDA_CODEC_AD1988, "Analog Devices AD1988A" },
891 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
892 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" },
893 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
894 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" },
895 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" },
896 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" },
897 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" },
898 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" },
899 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" },
900 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" },
901 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
902 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" },
903 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" },
904 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
905 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" },
906 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
907 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
908 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" },
909 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" },
910 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" },
911 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" },
912 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" },
913 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" },
914 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" },
915 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" },
916 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" },
917 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" },
918 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" },
919 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
920 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" },
921 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" },
922 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" },
923 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" },
924 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" },
925 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" },
926 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" },
927 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" },
928 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" },
929 { HDA_CODEC_IDT92HD005, "IDT 92HD005" },
930 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" },
931 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" },
932 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" },
933 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" },
934 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" },
935 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" },
936 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" },
937 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" },
938 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" },
939 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" },
940 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" },
941 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" },
942 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" },
943 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" },
944 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" },
945 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" },
946 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" },
947 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" },
948 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" },
949 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" },
950 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" },
951 { HDA_CODEC_CX20583, "Conexant CX20583 (Pebble HSF)" },
952 { HDA_CODEC_CX20584, "Conexant CX20584" },
953 { HDA_CODEC_CX20585, "Conexant CX20585" },
954 { HDA_CODEC_CX20590, "Conexant CX20590" },
955 { HDA_CODEC_CX20631, "Conexant CX20631" },
956 { HDA_CODEC_CX20632, "Conexant CX20632" },
957 { HDA_CODEC_CX20641, "Conexant CX20641" },
958 { HDA_CODEC_CX20642, "Conexant CX20642" },
959 { HDA_CODEC_CX20651, "Conexant CX20651" },
960 { HDA_CODEC_CX20652, "Conexant CX20652" },
961 { HDA_CODEC_CX20664, "Conexant CX20664" },
962 { HDA_CODEC_CX20665, "Conexant CX20665" },
963 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
964 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
965 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
966 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
967 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
968 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
969 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
970 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
971 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
972 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
973 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
974 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
975 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" },
976 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" },
977 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" },
978 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" },
979 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" },
980 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" },
981 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" },
982 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" },
983 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" },
984 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" },
985 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" },
986 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" },
987 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" },
988 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" },
989 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" },
990 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" },
991 { HDA_CODEC_VT1702_0, "VIA VT1702_0" },
992 { HDA_CODEC_VT1702_1, "VIA VT1702_1" },
993 { HDA_CODEC_VT1702_2, "VIA VT1702_2" },
994 { HDA_CODEC_VT1702_3, "VIA VT1702_3" },
995 { HDA_CODEC_VT1702_4, "VIA VT1702_4" },
996 { HDA_CODEC_VT1702_5, "VIA VT1702_5" },
997 { HDA_CODEC_VT1702_6, "VIA VT1702_6" },
998 { HDA_CODEC_VT1702_7, "VIA VT1702_7" },
999 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" },
1000 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" },
1001 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" },
1002 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" },
1003 { HDA_CODEC_VT1812, "VIA VT1812" },
1004 { HDA_CODEC_VT1818S, "VIA VT1818S" },
1005 { HDA_CODEC_VT1828S, "VIA VT1828S" },
1006 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" },
1007 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" },
1008 { HDA_CODEC_VT2020, "VIA VT2020" },
1009 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" },
1010 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" },
1011 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" },
1012 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" },
1013 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" },
1014 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" },
1015 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" },
1016 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" },
1017 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" },
1018 { HDA_CODEC_NVIDIAGT220, "NVidia GT220 HDMI" },
1019 { HDA_CODEC_NVIDIAGT21X, "NVidia GT21x HDMI" },
1020 { HDA_CODEC_NVIDIAMCP89, "NVidia MCP89 HDMI" },
1021 { HDA_CODEC_NVIDIAGT240, "NVidia GT240 HDMI" },
1022 { HDA_CODEC_INTELIP, "Intel Ibex Peak HDMI" },
1023 { HDA_CODEC_INTELBL, "Intel Bearlake HDMI" },
1024 { HDA_CODEC_INTELCA, "Intel Cantiga HDMI" },
1025 { HDA_CODEC_INTELEL, "Intel Eaglelake HDMI" },
1026 { HDA_CODEC_INTELIP2, "Intel Ibex Peak HDMI" },
1027 { HDA_CODEC_INTELCPT, "Intel Cougar Point HDMI" },
1028 { HDA_CODEC_INTELCL, "Intel Crestline HDMI" },
1029 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" },
1030 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" },
1032 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
1033 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
1034 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" },
1035 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
1036 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
1037 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" },
1038 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" },
1039 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
1040 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
1041 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" },
1042 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" },
1043 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" },
1044 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" },
1046 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
1049 /****************************************************************************
1050 * Function prototypes
1051 ****************************************************************************/
1052 static void hdac_intr_handler(void *);
1053 static int hdac_reset(struct hdac_softc *, int);
1054 static int hdac_get_capabilities(struct hdac_softc *);
1055 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
1056 static int hdac_dma_alloc(struct hdac_softc *,
1057 struct hdac_dma *, bus_size_t);
1058 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
1059 static int hdac_mem_alloc(struct hdac_softc *);
1060 static void hdac_mem_free(struct hdac_softc *);
1061 static int hdac_irq_alloc(struct hdac_softc *);
1062 static void hdac_irq_free(struct hdac_softc *);
1063 static void hdac_corb_init(struct hdac_softc *);
1064 static void hdac_rirb_init(struct hdac_softc *);
1065 static void hdac_corb_start(struct hdac_softc *);
1066 static void hdac_rirb_start(struct hdac_softc *);
1067 static void hdac_scan_codecs(struct hdac_softc *);
1068 static void hdac_probe_codec(struct hdac_codec *);
1069 static void hdac_probe_function(struct hdac_codec *, nid_t);
1070 static int hdac_pcmchannel_setup(struct hdac_chan *);
1072 static void hdac_attach2(void *);
1074 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
1076 static void hdac_command_send_internal(struct hdac_softc *,
1077 struct hdac_command_list *, int);
1079 static int hdac_probe(device_t);
1080 static int hdac_attach(device_t);
1081 static int hdac_detach(device_t);
1082 static int hdac_suspend(device_t);
1083 static int hdac_resume(device_t);
1084 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
1085 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
1086 uint32_t, int, int);
1087 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
1088 nid_t, int, int, int);
1089 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
1090 nid_t, nid_t, int, int, int, int, int, int);
1091 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
1093 static int hdac_rirb_flush(struct hdac_softc *sc);
1094 static int hdac_unsolq_flush(struct hdac_softc *sc);
1096 static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf);
1098 #define hdac_command(a1, a2, a3) \
1099 hdac_command_sendone_internal(a1, a2, a3)
1101 #define hdac_codec_id(c) \
1102 ((uint32_t)((c == NULL) ? 0x00000000 : \
1103 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \
1104 ((uint32_t)(c)->device_id & 0x0000ffff))))
1107 hdac_codec_name(struct hdac_codec *codec)
1112 id = hdac_codec_id(codec);
1114 for (i = 0; i < HDAC_CODECS_LEN; i++) {
1115 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
1116 return (hdac_codecs[i].name);
1119 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
1123 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
1125 static char *ossname[] = SOUND_DEVICE_NAMES;
1129 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1130 if (mask & (1 << i)) {
1132 strlcat(buf, ", ", len);
1133 strlcat(buf, ossname[i], len);
1140 static struct hdac_audio_ctl *
1141 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
1143 if (devinfo == NULL ||
1144 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
1145 index == NULL || devinfo->function.audio.ctl == NULL ||
1146 devinfo->function.audio.ctlcnt < 1 ||
1147 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
1149 return (&devinfo->function.audio.ctl[(*index)++]);
1152 static struct hdac_audio_ctl *
1153 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir,
1156 struct hdac_audio_ctl *ctl;
1159 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
1163 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
1164 if (ctl->enable == 0)
1166 if (ctl->widget->nid != nid)
1168 if (dir && ctl->ndir != dir)
1170 if (index >= 0 && ctl->ndir == HDA_CTL_IN &&
1171 ctl->dir == ctl->ndir && ctl->index != index)
1174 if (found == cnt || cnt <= 0)
1182 * Jack detection (Speaker/HP redirection) event handler.
1185 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
1187 struct hdac_audio_as *as;
1188 struct hdac_softc *sc;
1189 struct hdac_widget *w;
1190 struct hdac_audio_ctl *ctl;
1195 if (devinfo == NULL || devinfo->codec == NULL ||
1196 devinfo->codec->sc == NULL)
1199 sc = devinfo->codec->sc;
1200 cad = devinfo->codec->cad;
1201 as = devinfo->function.audio.as;
1202 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
1203 if (as[i].hpredir < 0)
1206 w = hdac_widget_get(devinfo, as[i].pins[15]);
1207 if (w == NULL || w->enable == 0 || w->type !=
1208 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1211 res = hdac_command(sc,
1212 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad);
1215 device_printf(sc->dev,
1216 "Pin sense: nid=%d res=0x%08x\n",
1217 as[i].pins[15], res);
1220 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
1221 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV)
1224 /* (Un)Mute headphone pin. */
1225 ctl = hdac_audio_ctl_amp_get(devinfo,
1226 as[i].pins[15], HDA_CTL_IN, -1, 1);
1227 if (ctl != NULL && ctl->mute) {
1228 /* If pin has muter - use it. */
1229 val = (res != 0) ? 0 : 1;
1230 if (val != ctl->forcemute) {
1231 ctl->forcemute = val;
1232 hdac_audio_ctl_amp_set(ctl,
1233 HDA_AMP_MUTE_DEFAULT,
1234 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
1237 /* If there is no muter - disable pin output. */
1238 w = hdac_widget_get(devinfo, as[i].pins[15]);
1239 if (w != NULL && w->type ==
1240 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1242 val = w->wclass.pin.ctrl |
1243 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1245 val = w->wclass.pin.ctrl &
1246 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1247 if (val != w->wclass.pin.ctrl) {
1248 w->wclass.pin.ctrl = val;
1250 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1251 w->nid, w->wclass.pin.ctrl), cad);
1255 /* (Un)Mute other pins. */
1256 for (j = 0; j < 15; j++) {
1257 if (as[i].pins[j] <= 0)
1259 ctl = hdac_audio_ctl_amp_get(devinfo,
1260 as[i].pins[j], HDA_CTL_IN, -1, 1);
1261 if (ctl != NULL && ctl->mute) {
1262 /* If pin has muter - use it. */
1263 val = (res != 0) ? 1 : 0;
1264 if (val == ctl->forcemute)
1266 ctl->forcemute = val;
1267 hdac_audio_ctl_amp_set(ctl,
1268 HDA_AMP_MUTE_DEFAULT,
1269 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
1272 /* If there is no muter - disable pin output. */
1273 w = hdac_widget_get(devinfo, as[i].pins[j]);
1274 if (w != NULL && w->type ==
1275 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1277 val = w->wclass.pin.ctrl &
1278 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1280 val = w->wclass.pin.ctrl |
1281 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1282 if (val != w->wclass.pin.ctrl) {
1283 w->wclass.pin.ctrl = val;
1285 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1286 w->nid, w->wclass.pin.ctrl), cad);
1294 * Callback for poll based jack detection.
1297 hdac_jack_poll_callback(void *arg)
1299 struct hdac_devinfo *devinfo = arg;
1300 struct hdac_softc *sc;
1302 if (devinfo == NULL || devinfo->codec == NULL ||
1303 devinfo->codec->sc == NULL)
1305 sc = devinfo->codec->sc;
1307 if (sc->poll_ival == 0) {
1311 hdac_hp_switch_handler(devinfo);
1312 callout_reset(&sc->poll_jack, sc->poll_ival,
1313 hdac_jack_poll_callback, devinfo);
1318 * Jack detection initializer.
1321 hdac_hp_switch_init(struct hdac_devinfo *devinfo)
1323 struct hdac_softc *sc = devinfo->codec->sc;
1324 struct hdac_audio_as *as = devinfo->function.audio.as;
1325 struct hdac_widget *w;
1327 int i, enable = 0, poll = 0;
1330 id = hdac_codec_id(devinfo->codec);
1331 cad = devinfo->codec->cad;
1332 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
1333 if (as[i].hpredir < 0)
1336 w = hdac_widget_get(devinfo, as[i].pins[15]);
1337 if (w == NULL || w->enable == 0 || w->type !=
1338 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1340 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 ||
1341 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) {
1342 device_printf(sc->dev,
1343 "No jack detection support at pin %d\n",
1348 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) {
1350 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
1351 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
1352 HDAC_UNSOLTAG_EVENT_HP), cad);
1356 device_printf(sc->dev,
1357 "Enabling headphone/speaker "
1358 "audio routing switching:\n");
1359 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n",
1360 i, w->nid, (poll != 0) ? "POLL" : "UNSOL");
1364 hdac_hp_switch_handler(devinfo);
1366 callout_reset(&sc->poll_jack, 1,
1367 hdac_jack_poll_callback, devinfo);
1373 * Unsolicited messages handler.
1376 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1378 struct hdac_softc *sc;
1379 struct hdac_devinfo *devinfo = NULL;
1382 if (codec == NULL || codec->sc == NULL)
1388 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag);
1391 for (i = 0; i < codec->num_fgs; i++) {
1392 if (codec->fgs[i].node_type ==
1393 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
1394 devinfo = &codec->fgs[i];
1399 if (devinfo == NULL)
1403 case HDAC_UNSOLTAG_EVENT_HP:
1404 hdac_hp_switch_handler(devinfo);
1407 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag);
1413 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1415 /* XXX to be removed */
1416 #ifdef HDAC_INTR_EXTRA
1420 if (!(ch->flags & HDAC_CHN_RUNNING))
1423 /* XXX to be removed */
1424 #ifdef HDAC_INTR_EXTRA
1425 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1428 /* XXX to be removed */
1429 #ifdef HDAC_INTR_EXTRA
1431 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1432 device_printf(ch->pdevinfo->dev,
1433 "PCMDIR_%s intr triggered beyond stream boundary:"
1435 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1439 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1440 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1442 /* XXX to be removed */
1443 #ifdef HDAC_INTR_EXTRA
1444 if (res & HDAC_SDSTS_BCIS) {
1447 /* XXX to be removed */
1448 #ifdef HDAC_INTR_EXTRA
1455 /****************************************************************************
1456 * void hdac_intr_handler(void *)
1458 * Interrupt handler. Processes interrupts received from the hdac.
1459 ****************************************************************************/
1461 hdac_intr_handler(void *context)
1463 struct hdac_softc *sc;
1466 struct hdac_rirb *rirb_base;
1470 sc = (struct hdac_softc *)context;
1473 if (sc->polling != 0) {
1478 /* Do we have anything to do? */
1479 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1480 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1487 /* Was this a controller interrupt? */
1488 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1489 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1490 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1491 /* Get as many responses that we can */
1492 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1493 HDAC_WRITE_1(&sc->mem,
1494 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1495 if (hdac_rirb_flush(sc) != 0)
1496 trigger |= HDAC_TRIGGER_UNSOL;
1497 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1499 /* XXX to be removed */
1500 /* Clear interrupt and exit */
1501 #ifdef HDAC_INTR_EXTRA
1502 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1506 if (intsts & HDAC_INTSTS_SIS_MASK) {
1507 for (i = 0; i < sc->num_chans; i++) {
1508 if ((intsts & (1 << (sc->chans[i].off >> 5))) &&
1509 hdac_stream_intr(sc, &sc->chans[i]) != 0)
1510 trigger |= (1 << i);
1512 /* XXX to be removed */
1513 #ifdef HDAC_INTR_EXTRA
1514 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1515 HDAC_INTSTS_SIS_MASK);
1521 for (i = 0; i < sc->num_chans; i++) {
1522 if (trigger & (1 << i))
1523 chn_intr(sc->chans[i].c);
1525 if (trigger & HDAC_TRIGGER_UNSOL)
1526 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1529 /****************************************************************************
1530 * int hdac_reset(hdac_softc *, int)
1532 * Reset the hdac to a quiescent and known state.
1533 ****************************************************************************/
1535 hdac_reset(struct hdac_softc *sc, int wakeup)
1541 * Stop all Streams DMA engine
1543 for (i = 0; i < sc->num_iss; i++)
1544 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1545 for (i = 0; i < sc->num_oss; i++)
1546 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1547 for (i = 0; i < sc->num_bss; i++)
1548 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1551 * Stop Control DMA engines.
1553 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1554 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1557 * Reset DMA position buffer.
1559 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1560 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1563 * Reset the controller. The reset must remain asserted for
1564 * a minimum of 100us.
1566 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1567 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1570 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1571 if (!(gctl & HDAC_GCTL_CRST))
1575 if (gctl & HDAC_GCTL_CRST) {
1576 device_printf(sc->dev, "Unable to put hdac in reset\n");
1580 /* If wakeup is not requested - leave the controller in reset state. */
1585 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1586 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1589 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1590 if (gctl & HDAC_GCTL_CRST)
1594 if (!(gctl & HDAC_GCTL_CRST)) {
1595 device_printf(sc->dev, "Device stuck in reset\n");
1600 * Wait for codecs to finish their own reset sequence. The delay here
1601 * should be of 250us but for some reasons, on it's not enough on my
1602 * computer. Let's use twice as much as necessary to make sure that
1603 * it's reset properly.
1611 /****************************************************************************
1612 * int hdac_get_capabilities(struct hdac_softc *);
1614 * Retreive the general capabilities of the hdac;
1615 * Number of Input Streams
1616 * Number of Output Streams
1617 * Number of bidirectional Streams
1619 * CORB and RIRB sizes
1620 ****************************************************************************/
1622 hdac_get_capabilities(struct hdac_softc *sc)
1625 uint8_t corbsize, rirbsize;
1627 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1628 sc->num_iss = HDAC_GCAP_ISS(gcap);
1629 sc->num_oss = HDAC_GCAP_OSS(gcap);
1630 sc->num_bss = HDAC_GCAP_BSS(gcap);
1631 sc->num_sdo = HDAC_GCAP_NSDO(gcap);
1632 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1634 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1635 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1636 HDAC_CORBSIZE_CORBSZCAP_256)
1637 sc->corb_size = 256;
1638 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1639 HDAC_CORBSIZE_CORBSZCAP_16)
1641 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1642 HDAC_CORBSIZE_CORBSZCAP_2)
1645 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1646 __func__, corbsize);
1650 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1651 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1652 HDAC_RIRBSIZE_RIRBSZCAP_256)
1653 sc->rirb_size = 256;
1654 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1655 HDAC_RIRBSIZE_RIRBSZCAP_16)
1657 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1658 HDAC_RIRBSIZE_RIRBSZCAP_2)
1661 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1662 __func__, rirbsize);
1667 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
1668 "NSDO %d%s, CORB %d, RIRB %d\n",
1669 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
1670 sc->support_64bit ? ", 64bit" : "",
1671 sc->corb_size, sc->rirb_size);
1678 /****************************************************************************
1681 * This function is called by bus_dmamap_load when the mapping has been
1682 * established. We just record the physical address of the mapping into
1683 * the struct hdac_dma passed in.
1684 ****************************************************************************/
1686 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1688 struct hdac_dma *dma;
1691 dma = (struct hdac_dma *)callback_arg;
1692 dma->dma_paddr = segs[0].ds_addr;
1697 /****************************************************************************
1698 * int hdac_dma_alloc
1700 * This function allocate and setup a dma region (struct hdac_dma).
1701 * It must be freed by a corresponding hdac_dma_free.
1702 ****************************************************************************/
1704 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1709 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1710 bzero(dma, sizeof(*dma));
1715 result = bus_dma_tag_create(
1716 bus_get_dma_tag(sc->dev), /* parent */
1717 HDAC_DMA_ALIGNMENT, /* alignment */
1719 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1720 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1721 BUS_SPACE_MAXADDR, /* highaddr */
1722 NULL, /* filtfunc */
1723 NULL, /* fistfuncarg */
1724 roundsz, /* maxsize */
1726 roundsz, /* maxsegsz */
1728 NULL, /* lockfunc */
1729 NULL, /* lockfuncarg */
1730 &dma->dma_tag); /* dmat */
1732 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1734 goto hdac_dma_alloc_fail;
1738 * Allocate DMA memory
1740 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1741 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1742 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1745 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1747 goto hdac_dma_alloc_fail;
1750 dma->dma_size = roundsz;
1755 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1756 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1757 if (result != 0 || dma->dma_paddr == 0) {
1760 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1762 goto hdac_dma_alloc_fail;
1766 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1767 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1772 hdac_dma_alloc_fail:
1773 hdac_dma_free(sc, dma);
1779 /****************************************************************************
1780 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1782 * Free a struct dhac_dma that has been previously allocated via the
1783 * hdac_dma_alloc function.
1784 ****************************************************************************/
1786 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1788 if (dma->dma_map != NULL) {
1791 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1792 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1794 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1796 if (dma->dma_vaddr != NULL) {
1797 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1798 dma->dma_vaddr = NULL;
1800 dma->dma_map = NULL;
1801 if (dma->dma_tag != NULL) {
1802 bus_dma_tag_destroy(dma->dma_tag);
1803 dma->dma_tag = NULL;
1808 /****************************************************************************
1809 * int hdac_mem_alloc(struct hdac_softc *)
1811 * Allocate all the bus resources necessary to speak with the physical
1813 ****************************************************************************/
1815 hdac_mem_alloc(struct hdac_softc *sc)
1817 struct hdac_mem *mem;
1820 mem->mem_rid = PCIR_BAR(0);
1821 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1822 &mem->mem_rid, RF_ACTIVE);
1823 if (mem->mem_res == NULL) {
1824 device_printf(sc->dev,
1825 "%s: Unable to allocate memory resource\n", __func__);
1828 mem->mem_tag = rman_get_bustag(mem->mem_res);
1829 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1834 /****************************************************************************
1835 * void hdac_mem_free(struct hdac_softc *)
1837 * Free up resources previously allocated by hdac_mem_alloc.
1838 ****************************************************************************/
1840 hdac_mem_free(struct hdac_softc *sc)
1842 struct hdac_mem *mem;
1845 if (mem->mem_res != NULL)
1846 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1848 mem->mem_res = NULL;
1851 /****************************************************************************
1852 * int hdac_irq_alloc(struct hdac_softc *)
1854 * Allocate and setup the resources necessary for interrupt handling.
1855 ****************************************************************************/
1857 hdac_irq_alloc(struct hdac_softc *sc)
1859 struct hdac_irq *irq;
1865 if ((sc->flags & HDAC_F_MSI) &&
1866 (result = pci_msi_count(sc->dev)) == 1 &&
1867 pci_alloc_msi(sc->dev, &result) == 0)
1870 sc->flags &= ~HDAC_F_MSI;
1872 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1873 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1874 if (irq->irq_res == NULL) {
1875 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1877 goto hdac_irq_alloc_fail;
1879 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
1880 NULL, hdac_intr_handler, sc, &irq->irq_handle);
1882 device_printf(sc->dev,
1883 "%s: Unable to setup interrupt handler (%x)\n",
1885 goto hdac_irq_alloc_fail;
1890 hdac_irq_alloc_fail:
1896 /****************************************************************************
1897 * void hdac_irq_free(struct hdac_softc *)
1899 * Free up resources previously allocated by hdac_irq_alloc.
1900 ****************************************************************************/
1902 hdac_irq_free(struct hdac_softc *sc)
1904 struct hdac_irq *irq;
1907 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1908 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1909 if (irq->irq_res != NULL)
1910 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1912 if (irq->irq_rid == 0x1)
1913 pci_release_msi(sc->dev);
1914 irq->irq_handle = NULL;
1915 irq->irq_res = NULL;
1919 /****************************************************************************
1920 * void hdac_corb_init(struct hdac_softc *)
1922 * Initialize the corb registers for operations but do not start it up yet.
1923 * The CORB engine must not be running when this function is called.
1924 ****************************************************************************/
1926 hdac_corb_init(struct hdac_softc *sc)
1931 /* Setup the CORB size. */
1932 switch (sc->corb_size) {
1934 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1937 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1940 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1943 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1945 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1947 /* Setup the CORB Address in the hdac */
1948 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1949 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1950 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1952 /* Set the WP and RP */
1954 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1955 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1957 * The HDA specification indicates that the CORBRPRST bit will always
1958 * read as zero. Unfortunately, it seems that at least the 82801G
1959 * doesn't reset the bit to zero, which stalls the corb engine.
1960 * manually reset the bit to zero before continuing.
1962 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1964 /* Enable CORB error reporting */
1966 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1970 /****************************************************************************
1971 * void hdac_rirb_init(struct hdac_softc *)
1973 * Initialize the rirb registers for operations but do not start it up yet.
1974 * The RIRB engine must not be running when this function is called.
1975 ****************************************************************************/
1977 hdac_rirb_init(struct hdac_softc *sc)
1982 /* Setup the RIRB size. */
1983 switch (sc->rirb_size) {
1985 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1988 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1991 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1994 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1996 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1998 /* Setup the RIRB Address in the hdac */
1999 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
2000 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
2001 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
2003 /* Setup the WP and RP */
2005 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
2007 /* Setup the interrupt threshold */
2008 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
2010 /* Enable Overrun and response received reporting */
2012 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
2013 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
2015 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
2020 * Make sure that the Host CPU cache doesn't contain any dirty
2021 * cache lines that falls in the rirb. If I understood correctly, it
2022 * should be sufficient to do this only once as the rirb is purely
2023 * read-only from now on.
2025 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2026 BUS_DMASYNC_PREREAD);
2030 /****************************************************************************
2031 * void hdac_corb_start(hdac_softc *)
2033 * Startup the corb DMA engine
2034 ****************************************************************************/
2036 hdac_corb_start(struct hdac_softc *sc)
2040 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
2041 corbctl |= HDAC_CORBCTL_CORBRUN;
2042 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
2045 /****************************************************************************
2046 * void hdac_rirb_start(hdac_softc *)
2048 * Startup the rirb DMA engine
2049 ****************************************************************************/
2051 hdac_rirb_start(struct hdac_softc *sc)
2055 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
2056 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
2057 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
2061 /****************************************************************************
2062 * void hdac_scan_codecs(struct hdac_softc *, int)
2064 * Scan the bus for available codecs, starting with num.
2065 ****************************************************************************/
2067 hdac_scan_codecs(struct hdac_softc *sc)
2069 struct hdac_codec *codec;
2073 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
2074 for (i = 0; i < HDAC_CODEC_MAX; i++) {
2075 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
2076 /* We have found a codec. */
2077 codec = (struct hdac_codec *)malloc(sizeof(*codec),
2078 M_HDAC, M_ZERO | M_NOWAIT);
2079 if (codec == NULL) {
2080 device_printf(sc->dev,
2081 "Unable to allocate memory for codec\n");
2084 codec->commands = NULL;
2085 codec->responses_received = 0;
2086 codec->verbs_sent = 0;
2089 sc->codecs[i] = codec;
2090 hdac_probe_codec(codec);
2093 /* All codecs have been probed, now try to attach drivers to them */
2094 /* bus_generic_attach(sc->dev); */
2097 /****************************************************************************
2098 * void hdac_probe_codec(struct hdac_softc *, int)
2100 * Probe a the given codec_id for available function groups.
2101 ****************************************************************************/
2103 hdac_probe_codec(struct hdac_codec *codec)
2105 struct hdac_softc *sc = codec->sc;
2106 uint32_t vendorid, revisionid, subnode;
2110 nid_t cad = codec->cad;
2113 device_printf(sc->dev, "Probing codec #%d...\n", cad);
2115 vendorid = hdac_command(sc,
2116 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
2118 revisionid = hdac_command(sc,
2119 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
2121 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
2122 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
2123 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
2124 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
2126 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) {
2127 device_printf(sc->dev, "Codec #%d is not responding!"
2128 " Probing aborted.\n", cad);
2132 device_printf(sc->dev, "HDA Codec #%d: %s\n",
2133 cad, hdac_codec_name(codec));
2135 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n",
2136 hdac_codec_id(codec));
2137 device_printf(sc->dev, " Vendor: 0x%04x\n",
2139 device_printf(sc->dev, " Device: 0x%04x\n",
2141 device_printf(sc->dev, " Revision: 0x%02x\n",
2142 codec->revision_id);
2143 device_printf(sc->dev, " Stepping: 0x%02x\n",
2144 codec->stepping_id);
2145 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
2148 subnode = hdac_command(sc,
2149 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
2151 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
2152 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
2155 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n",
2156 startnode, endnode);
2159 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) *
2160 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO);
2161 if (codec->fgs == NULL) {
2162 device_printf(sc->dev, "%s: Unable to allocate function groups\n",
2167 for (i = startnode; i < endnode; i++)
2168 hdac_probe_function(codec, i);
2173 * Probe codec function and add it to the list.
2176 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
2178 struct hdac_softc *sc = codec->sc;
2179 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs];
2180 uint32_t fctgrptype;
2182 nid_t cad = codec->cad;
2184 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
2185 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
2188 devinfo->node_type = fctgrptype;
2189 devinfo->codec = codec;
2191 res = hdac_command(sc,
2192 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
2194 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
2195 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
2196 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
2199 device_printf(sc->dev,
2200 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n",
2201 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio":
2202 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem":
2203 "unknown", nid, devinfo->startnode, devinfo->endnode,
2207 if (devinfo->nodecnt > 0)
2208 devinfo->widget = (struct hdac_widget *)malloc(
2209 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
2212 devinfo->widget = NULL;
2214 if (devinfo->widget == NULL) {
2215 device_printf(sc->dev, "unable to allocate widgets!\n");
2216 devinfo->endnode = devinfo->startnode;
2217 devinfo->nodecnt = 0;
2225 hdac_widget_connection_parse(struct hdac_widget *w)
2227 struct hdac_softc *sc = w->devinfo->codec->sc;
2229 int i, j, max, ents, entnum;
2230 nid_t cad = w->devinfo->codec->cad;
2232 nid_t cnid, addcnid, prevcnid;
2236 res = hdac_command(sc,
2237 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
2239 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
2244 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
2245 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
2248 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
2249 #define CONN_NMASK(e) (CONN_RMASK(e) - 1)
2250 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
2251 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
2252 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
2254 for (i = 0; i < ents; i += entnum) {
2255 res = hdac_command(sc,
2256 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
2257 for (j = 0; j < entnum; j++) {
2258 cnid = CONN_CNID(res, entnum, j);
2260 if (w->nconns < ents)
2261 device_printf(sc->dev,
2262 "%s: nid=%d WARNING: zero cnid "
2263 "entnum=%d j=%d index=%d "
2264 "entries=%d found=%d res=0x%08x\n",
2265 __func__, nid, entnum, j, i,
2266 ents, w->nconns, res);
2270 if (cnid < w->devinfo->startnode ||
2271 cnid >= w->devinfo->endnode) {
2273 device_printf(sc->dev,
2274 "GHOST: nid=%d j=%d "
2275 "entnum=%d index=%d res=0x%08x\n",
2276 nid, j, entnum, i, res);
2279 if (CONN_RANGE(res, entnum, j) == 0)
2281 else if (prevcnid == 0 || prevcnid >= cnid) {
2282 device_printf(sc->dev,
2283 "%s: WARNING: Invalid child range "
2284 "nid=%d index=%d j=%d entnum=%d "
2285 "prevcnid=%d cnid=%d res=0x%08x\n",
2286 __func__, nid, i, j, entnum, prevcnid,
2290 addcnid = prevcnid + 1;
2291 while (addcnid <= cnid) {
2292 if (w->nconns > max) {
2293 device_printf(sc->dev,
2294 "Adding %d (nid=%d): "
2295 "Max connection reached! max=%d\n",
2296 addcnid, nid, max + 1);
2299 w->connsenable[w->nconns] = 1;
2300 w->conns[w->nconns++] = addcnid++;
2311 hdac_widget_pin_patch(uint32_t config, const char *str)
2314 char *key, *value, *rest, *bad;
2317 strlcpy(buf, str, sizeof(buf));
2319 while ((key = strsep(&rest, "=")) != NULL) {
2320 value = strsep(&rest, " \t");
2323 ival = strtol(value, &bad, 10);
2324 if (strcmp(key, "seq") == 0) {
2325 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK;
2326 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) &
2327 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK);
2328 } else if (strcmp(key, "as") == 0) {
2329 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK;
2330 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) &
2331 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK);
2332 } else if (strcmp(key, "misc") == 0) {
2333 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK;
2334 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) &
2335 HDA_CONFIG_DEFAULTCONF_MISC_MASK);
2336 } else if (strcmp(key, "color") == 0) {
2337 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK;
2339 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) &
2340 HDA_CONFIG_DEFAULTCONF_COLOR_MASK);
2342 for (i = 0; i < 16; i++) {
2343 if (strcasecmp(HDA_COLORS[i], value) == 0) {
2344 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT);
2348 } else if (strcmp(key, "ctype") == 0) {
2349 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK;
2350 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) &
2351 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK);
2352 } else if (strcmp(key, "device") == 0) {
2353 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2355 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) &
2356 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK);
2359 for (i = 0; i < 16; i++) {
2360 if (strcasecmp(HDA_DEVS[i], value) == 0) {
2361 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT);
2365 } else if (strcmp(key, "loc") == 0) {
2366 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK;
2367 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) &
2368 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK);
2369 } else if (strcmp(key, "conn") == 0) {
2370 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2372 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) &
2373 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2376 for (i = 0; i < 4; i++) {
2377 if (strcasecmp(HDA_CONNS[i], value) == 0) {
2378 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT);
2388 hdac_widget_pin_getconfig(struct hdac_widget *w)
2390 struct hdac_softc *sc;
2391 uint32_t config, orig, id;
2394 const char *res = NULL, *patch = NULL;
2396 sc = w->devinfo->codec->sc;
2397 cad = w->devinfo->codec->cad;
2399 id = hdac_codec_id(w->devinfo->codec);
2401 config = hdac_command(sc,
2402 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
2407 hdac_dump_pin_config(w, orig);
2410 /* XXX: Old patches require complete review.
2411 * Now they may create more problem then solve due to
2412 * incorrect associations.
2414 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
2417 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2418 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2421 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2422 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
2427 } else if (id == HDA_CODEC_ALC880 &&
2428 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
2429 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
2435 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2436 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2438 case 25: /* XXX MIC2 */
2439 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2440 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2442 case 26: /* LINE1 */
2443 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2444 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2446 case 27: /* XXX LINE2 */
2447 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2448 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2451 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2452 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2455 } else if (id == HDA_CODEC_ALC883 &&
2456 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR ||
2457 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) {
2460 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2461 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2462 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2463 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2466 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2467 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2468 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2469 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2472 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor ==
2473 HP_V3000_SUBVENDOR) {
2476 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2477 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2480 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2481 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2482 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2483 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2486 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2487 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2488 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2489 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2492 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor ==
2493 HP_DV5000_SUBVENDOR) {
2497 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2498 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2501 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2502 ASUS_W6F_SUBVENDOR) {
2505 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2506 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2507 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2508 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2515 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2516 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2517 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2518 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2521 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2522 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2523 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2524 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2527 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2528 UNIWILL_9075_SUBVENDOR) {
2531 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2532 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2533 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2534 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2540 if (id == HDA_CODEC_AD1986A &&
2541 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2542 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR ||
2543 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) {
2545 case 26: /* Headphones with redirection */
2546 patch = "as=1 seq=15";
2548 case 28: /* 5.1 out => 2.0 out + 1 input */
2549 patch = "device=Line-in as=8 seq=1";
2551 case 29: /* Can't use this as input, as the only available mic
2552 * preamplifier is busy by front panel mic (nid 31).
2553 * If you want to use this rear connector as mic input,
2554 * you have to disable the front panel one. */
2557 case 31: /* Lot of inputs configured with as=15 and unusable */
2558 patch = "as=8 seq=3";
2561 patch = "as=8 seq=4";
2564 patch = "as=8 seq=5";
2567 patch = "as=8 seq=6";
2570 } else if (id == HDA_CODEC_ALC260 &&
2571 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) {
2574 patch = "seq=15 device=Headphones";
2577 } else if (id == HDA_CODEC_ALC268) {
2578 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) {
2580 case 20: /* Headphones Jack */
2581 patch = "as=1 seq=15";
2588 config = hdac_widget_pin_patch(config, patch);
2590 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid);
2591 if (resource_string_value(device_get_name(sc->dev),
2592 device_get_unit(sc->dev), buf, &res) == 0) {
2593 if (strncmp(res, "0x", 2) == 0) {
2594 config = strtol(res + 2, NULL, 16);
2596 config = hdac_widget_pin_patch(config, res);
2602 device_printf(sc->dev,
2603 "Patching pin config nid=%u 0x%08x -> 0x%08x\n",
2611 hdac_widget_pin_getcaps(struct hdac_widget *w)
2613 struct hdac_softc *sc;
2614 uint32_t caps, orig, id;
2617 sc = w->devinfo->codec->sc;
2618 cad = w->devinfo->codec->cad;
2620 id = hdac_codec_id(w->devinfo->codec);
2622 caps = hdac_command(sc,
2623 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2628 device_printf(sc->dev,
2629 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n",
2637 hdac_widget_pin_parse(struct hdac_widget *w)
2639 struct hdac_softc *sc = w->devinfo->codec->sc;
2640 uint32_t config, pincap;
2642 nid_t cad = w->devinfo->codec->cad;
2646 config = hdac_widget_pin_getconfig(w);
2647 w->wclass.pin.config = config;
2649 pincap = hdac_widget_pin_getcaps(w);
2650 w->wclass.pin.cap = pincap;
2652 w->wclass.pin.ctrl = hdac_command(sc,
2653 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad);
2655 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2656 w->param.eapdbtl = hdac_command(sc,
2657 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2658 w->param.eapdbtl &= 0x7;
2659 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2661 w->param.eapdbtl = HDAC_INVALID;
2663 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >>
2664 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT];
2666 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >>
2667 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT;
2668 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >>
2669 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT;
2671 strlcat(w->name, ": ", sizeof(w->name));
2672 strlcat(w->name, devstr, sizeof(w->name));
2673 strlcat(w->name, " (", sizeof(w->name));
2674 if (conn == 0 && color != 0 && color != 15) {
2675 strlcat(w->name, HDA_COLORS[color], sizeof(w->name));
2676 strlcat(w->name, " ", sizeof(w->name));
2678 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name));
2679 strlcat(w->name, ")", sizeof(w->name));
2683 hdac_widget_getcaps(struct hdac_widget *w, int *waspin)
2685 struct hdac_softc *sc;
2686 uint32_t caps, orig, id;
2687 nid_t cad, nid, beeper = -1;
2689 sc = w->devinfo->codec->sc;
2690 cad = w->devinfo->codec->cad;
2692 id = hdac_codec_id(w->devinfo->codec);
2694 caps = hdac_command(sc,
2695 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2699 /* On some codecs beeper is an input pin, but it is not recordable
2700 alone. Also most of BIOSes does not declare beeper pin.
2701 Change beeper pin node type to beeper to help parser. */
2704 case HDA_CODEC_AD1882:
2705 case HDA_CODEC_AD1883:
2706 case HDA_CODEC_AD1984:
2707 case HDA_CODEC_AD1984A:
2708 case HDA_CODEC_AD1984B:
2709 case HDA_CODEC_AD1987:
2710 case HDA_CODEC_AD1988:
2711 case HDA_CODEC_AD1988B:
2712 case HDA_CODEC_AD1989B:
2715 case HDA_CODEC_ALC260:
2718 case HDA_CODEC_ALC262:
2719 case HDA_CODEC_ALC268:
2720 case HDA_CODEC_ALC880:
2721 case HDA_CODEC_ALC882:
2722 case HDA_CODEC_ALC883:
2723 case HDA_CODEC_ALC885:
2724 case HDA_CODEC_ALC888:
2725 case HDA_CODEC_ALC889:
2729 if (nid == beeper) {
2730 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
2731 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
2732 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
2738 device_printf(sc->dev,
2739 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n",
2748 hdac_widget_parse(struct hdac_widget *w)
2750 struct hdac_softc *sc = w->devinfo->codec->sc;
2753 nid_t cad = w->devinfo->codec->cad;
2756 wcap = hdac_widget_getcaps(w, &w->waspin);
2758 w->param.widget_cap = wcap;
2759 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2762 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2763 typestr = "audio output";
2765 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2766 typestr = "audio input";
2768 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2769 typestr = "audio mixer";
2771 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2772 typestr = "audio selector";
2774 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2777 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2778 typestr = "power widget";
2780 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2781 typestr = "volume widget";
2783 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2784 typestr = "beep widget";
2786 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2787 typestr = "vendor widget";
2790 typestr = "unknown type";
2794 strlcpy(w->name, typestr, sizeof(w->name));
2796 hdac_widget_connection_parse(w);
2798 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2799 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2800 w->param.outamp_cap =
2802 HDA_CMD_GET_PARAMETER(cad, nid,
2803 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2805 w->param.outamp_cap =
2806 w->devinfo->function.audio.outamp_cap;
2808 w->param.outamp_cap = 0;
2810 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2811 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2812 w->param.inamp_cap =
2814 HDA_CMD_GET_PARAMETER(cad, nid,
2815 HDA_PARAM_INPUT_AMP_CAP), cad);
2817 w->param.inamp_cap =
2818 w->devinfo->function.audio.inamp_cap;
2820 w->param.inamp_cap = 0;
2822 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2823 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2824 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2825 cap = hdac_command(sc,
2826 HDA_CMD_GET_PARAMETER(cad, nid,
2827 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2828 w->param.supp_stream_formats = (cap != 0) ? cap :
2829 w->devinfo->function.audio.supp_stream_formats;
2830 cap = hdac_command(sc,
2831 HDA_CMD_GET_PARAMETER(cad, nid,
2832 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2833 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2834 w->devinfo->function.audio.supp_pcm_size_rate;
2836 w->param.supp_stream_formats =
2837 w->devinfo->function.audio.supp_stream_formats;
2838 w->param.supp_pcm_size_rate =
2839 w->devinfo->function.audio.supp_pcm_size_rate;
2842 w->param.supp_stream_formats = 0;
2843 w->param.supp_pcm_size_rate = 0;
2846 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2847 hdac_widget_pin_parse(w);
2850 static struct hdac_widget *
2851 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2853 if (devinfo == NULL || devinfo->widget == NULL ||
2854 nid < devinfo->startnode || nid >= devinfo->endnode)
2856 return (&devinfo->widget[nid - devinfo->startnode]);
2860 hda_poll_channel(struct hdac_chan *ch)
2863 volatile uint32_t ptr;
2865 if (!(ch->flags & HDAC_CHN_RUNNING))
2868 sz = ch->blksz * ch->blkcnt;
2869 if (ch->dmapos != NULL)
2870 ptr = *(ch->dmapos);
2872 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2873 ch->off + HDAC_SDLPIB);
2876 ptr &= ~(ch->blksz - 1);
2877 delta = (sz + ptr - ch->prevptr) % sz;
2879 if (delta < ch->blksz)
2888 hda_poll_callback(void *arg)
2890 struct hdac_softc *sc = arg;
2898 if (sc->polling == 0) {
2904 for (i = 0; i < sc->num_chans; i++) {
2905 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0)
2908 if (hda_poll_channel(&sc->chans[i]))
2909 trigger |= (1 << i);
2914 callout_reset(&sc->poll_hda, sc->poll_ticks,
2915 hda_poll_callback, sc);
2919 for (i = 0; i < sc->num_chans; i++) {
2920 if (trigger & (1 << i))
2921 chn_intr(sc->chans[i].c);
2926 hdac_rirb_flush(struct hdac_softc *sc)
2928 struct hdac_rirb *rirb_base, *rirb;
2929 struct hdac_codec *codec;
2930 struct hdac_command_list *commands;
2936 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2937 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2939 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2940 BUS_DMASYNC_POSTREAD);
2945 while (sc->rirb_rp != rirbwp) {
2947 sc->rirb_rp %= sc->rirb_size;
2948 rirb = &rirb_base[sc->rirb_rp];
2949 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2950 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2951 sc->codecs[cad] == NULL)
2953 resp = rirb->response;
2954 codec = sc->codecs[cad];
2955 commands = codec->commands;
2956 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2957 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2958 ((resp >> 26) & 0xffff);
2959 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2960 } else if (commands != NULL && commands->num_commands > 0 &&
2961 codec->responses_received < commands->num_commands)
2962 commands->responses[codec->responses_received++] =
2971 hdac_unsolq_flush(struct hdac_softc *sc)
2977 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2978 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2979 while (sc->unsolq_rp != sc->unsolq_wp) {
2980 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2981 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2982 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2983 hdac_unsolicited_handler(sc->codecs[cad], tag);
2986 sc->unsolq_st = HDAC_UNSOLQ_READY;
2993 hdac_poll_callback(void *arg)
2995 struct hdac_softc *sc = arg;
3000 if (sc->polling == 0 || sc->poll_ival == 0) {
3004 if (hdac_rirb_flush(sc) != 0)
3005 hdac_unsolq_flush(sc);
3006 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
3011 hdac_poll_reinit(struct hdac_softc *sc)
3013 int i, pollticks, min = 1000000;
3014 struct hdac_chan *ch;
3016 for (i = 0; i < sc->num_chans; i++) {
3017 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0)
3020 pollticks = ((uint64_t)hz * ch->blksz) /
3021 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b));
3025 if (pollticks < 1) {
3027 device_printf(sc->dev,
3028 "%s: pollticks=%d < 1 !\n",
3029 __func__, pollticks);
3033 if (min > pollticks)
3037 device_printf(sc->dev,
3038 "%s: pollticks %d -> %d\n",
3039 __func__, sc->poll_ticks, min);
3041 sc->poll_ticks = min;
3043 callout_stop(&sc->poll_hda);
3045 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc);
3049 hdac_stream_stop(struct hdac_chan *ch)
3051 struct hdac_softc *sc = ch->devinfo->codec->sc;
3054 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3055 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
3057 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3059 ch->flags &= ~HDAC_CHN_RUNNING;
3061 if (sc->polling != 0)
3062 hdac_poll_reinit(sc);
3064 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
3065 ctl &= ~(1 << (ch->off >> 5));
3066 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
3070 hdac_stream_start(struct hdac_chan *ch)
3072 struct hdac_softc *sc = ch->devinfo->codec->sc;
3075 ch->flags |= HDAC_CHN_RUNNING;
3077 if (sc->polling != 0)
3078 hdac_poll_reinit(sc);
3080 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
3081 ctl |= 1 << (ch->off >> 5);
3082 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
3084 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3085 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
3087 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3091 hdac_stream_reset(struct hdac_chan *ch)
3093 struct hdac_softc *sc = ch->devinfo->codec->sc;
3098 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3099 ctl |= HDAC_SDCTL_SRST;
3100 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3102 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3103 if (ctl & HDAC_SDCTL_SRST)
3107 if (!(ctl & HDAC_SDCTL_SRST)) {
3108 device_printf(sc->dev, "timeout in reset\n");
3110 ctl &= ~HDAC_SDCTL_SRST;
3111 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3114 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3115 if (!(ctl & HDAC_SDCTL_SRST))
3119 if (ctl & HDAC_SDCTL_SRST)
3120 device_printf(sc->dev, "can't reset!\n");
3124 hdac_stream_setid(struct hdac_chan *ch)
3126 struct hdac_softc *sc = ch->devinfo->codec->sc;
3129 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
3130 ctl &= ~HDAC_SDCTL2_STRM_MASK;
3131 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
3132 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
3136 hdac_bdl_setup(struct hdac_chan *ch)
3138 struct hdac_softc *sc = ch->devinfo->codec->sc;
3139 struct hdac_bdle *bdle;
3141 uint32_t blksz, blkcnt;
3144 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
3145 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
3148 blkcnt = ch->blkcnt;
3150 for (i = 0; i < blkcnt; i++, bdle++) {
3151 bdle->addrl = (uint32_t)addr;
3152 bdle->addrh = (uint32_t)(addr >> 32);
3158 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
3159 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
3160 addr = ch->bdl_dma.dma_paddr;
3161 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
3162 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
3163 if (ch->dmapos != NULL &&
3164 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
3165 addr = sc->pos_dma.dma_paddr;
3166 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
3167 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
3168 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
3173 hdac_bdl_alloc(struct hdac_chan *ch)
3175 struct hdac_softc *sc = ch->devinfo->codec->sc;
3178 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
3179 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
3181 device_printf(sc->dev, "can't alloc bdl\n");
3189 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
3190 int index, int lmute, int rmute,
3191 int left, int right, int dir)
3198 if (left != right || lmute != rmute) {
3199 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
3200 (lmute << 7) | left;
3202 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
3203 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
3204 (rmute << 7) | right;
3206 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
3207 (lmute << 7) | left;
3210 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
3214 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
3215 int left, int right)
3217 struct hdac_softc *sc;
3221 sc = ctl->widget->devinfo->codec->sc;
3222 cad = ctl->widget->devinfo->codec->cad;
3223 nid = ctl->widget->nid;
3225 /* Save new values if valid. */
3226 if (mute != HDA_AMP_MUTE_DEFAULT)
3228 if (left != HDA_AMP_VOL_DEFAULT)
3230 if (right != HDA_AMP_VOL_DEFAULT)
3232 /* Prepare effective values */
3233 if (ctl->forcemute) {
3239 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
3240 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
3244 /* Apply effective values */
3245 if (ctl->dir & HDA_CTL_OUT)
3246 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
3247 lmute, rmute, left, right, 0);
3248 if (ctl->dir & HDA_CTL_IN)
3249 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
3250 lmute, rmute, left, right, 1);
3254 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
3256 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
3258 hdac_command(w->devinfo->codec->sc,
3259 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
3260 w->nid, index), w->devinfo->codec->cad);
3265 /****************************************************************************
3266 * uint32_t hdac_command_sendone_internal
3268 * Wrapper function that sends only one command to a given codec
3269 ****************************************************************************/
3271 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
3273 struct hdac_command_list cl;
3274 uint32_t response = HDAC_INVALID;
3276 if (!hdac_lockowned(sc))
3277 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
3278 cl.num_commands = 1;
3280 cl.responses = &response;
3282 hdac_command_send_internal(sc, &cl, cad);
3287 /****************************************************************************
3288 * hdac_command_send_internal
3290 * Send a command list to the codec via the corb. We queue as much verbs as
3291 * we can and msleep on the codec. When the interrupt get the responses
3292 * back from the rirb, it will wake us up so we can queue the remaining verbs
3294 ****************************************************************************/
3296 hdac_command_send_internal(struct hdac_softc *sc,
3297 struct hdac_command_list *commands, nid_t cad)
3299 struct hdac_codec *codec;
3304 struct hdac_rirb *rirb_base;
3306 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
3307 commands->num_commands < 1)
3310 codec = sc->codecs[cad];
3311 codec->commands = commands;
3312 codec->responses_received = 0;
3313 codec->verbs_sent = 0;
3314 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
3315 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
3318 if (codec->verbs_sent != commands->num_commands) {
3319 /* Queue as many verbs as possible */
3320 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
3322 bus_dmamap_sync(sc->corb_dma.dma_tag,
3323 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
3325 while (codec->verbs_sent != commands->num_commands &&
3326 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
3328 sc->corb_wp %= sc->corb_size;
3330 commands->verbs[codec->verbs_sent++];
3333 /* Send the verbs to the codecs */
3335 bus_dmamap_sync(sc->corb_dma.dma_tag,
3336 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
3338 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
3342 while (hdac_rirb_flush(sc) == 0 && --timeout)
3344 } while ((codec->verbs_sent != commands->num_commands ||
3345 codec->responses_received != commands->num_commands) && --retry);
3348 device_printf(sc->dev,
3349 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
3350 __func__, commands->num_commands, codec->verbs_sent,
3351 codec->responses_received);
3353 codec->commands = NULL;
3354 codec->responses_received = 0;
3355 codec->verbs_sent = 0;
3357 hdac_unsolq_flush(sc);
3361 /****************************************************************************
3363 ****************************************************************************/
3365 /****************************************************************************
3366 * int hdac_probe(device_t)
3368 * Probe for the presence of an hdac. If none is found, check for a generic
3369 * match using the subclass of the device.
3370 ****************************************************************************/
3372 hdac_probe(device_t dev)
3376 uint16_t class, subclass;
3379 model = (uint32_t)pci_get_device(dev) << 16;
3380 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
3381 class = pci_get_class(dev);
3382 subclass = pci_get_subclass(dev);
3384 bzero(desc, sizeof(desc));
3386 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
3387 if (hdac_devices[i].model == model) {
3388 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3389 result = BUS_PROBE_DEFAULT;
3392 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
3393 class == PCIC_MULTIMEDIA &&
3394 subclass == PCIS_MULTIMEDIA_HDA) {
3395 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3396 result = BUS_PROBE_GENERIC;
3400 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
3401 subclass == PCIS_MULTIMEDIA_HDA) {
3402 strlcpy(desc, "Generic", sizeof(desc));
3403 result = BUS_PROBE_GENERIC;
3405 if (result != ENXIO) {
3406 strlcat(desc, " High Definition Audio Controller",
3408 device_set_desc_copy(dev, desc);
3415 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
3416 struct pcm_channel *c, int dir)
3418 struct hdac_pcm_devinfo *pdevinfo = data;
3419 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3420 struct hdac_softc *sc = devinfo->codec->sc;
3421 struct hdac_chan *ch;
3422 int i, ord = 0, chid;
3426 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec;
3427 ch = &sc->chans[chid];
3428 for (i = 0; i < sc->num_chans && i < chid; i++) {
3429 if (ch->dir == sc->chans[i].dir)
3432 if (dir == PCMDIR_PLAY) {
3433 ch->off = (sc->num_iss + ord) << 5;
3438 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
3439 ch->caps.minspeed = ch->caps.maxspeed = 48000;
3440 ch->pcmrates[0] = 48000;
3441 ch->pcmrates[1] = 0;
3443 if (sc->pos_dma.dma_vaddr != NULL)
3444 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
3445 (sc->streamcnt * 8));
3448 ch->sid = ++sc->streamcnt;
3452 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt;
3453 ch->blkcnt = pdevinfo->chan_blkcnt;
3456 if (hdac_bdl_alloc(ch) != 0) {
3461 if (sndbuf_alloc(ch->b, sc->chan_dmat,
3462 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0,
3463 pdevinfo->chan_size) != 0)
3470 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3472 struct hdac_chan *ch = data;
3475 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3476 if (format == ch->caps.fmtlist[i]) {
3486 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3488 struct hdac_chan *ch = data;
3489 uint32_t spd = 0, threshold;
3492 for (i = 0; ch->pcmrates[i] != 0; i++) {
3493 spd = ch->pcmrates[i];
3494 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3495 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3496 if (speed < threshold)
3500 if (spd == 0) /* impossible */
3509 hdac_stream_setup(struct hdac_chan *ch)
3511 struct hdac_softc *sc = ch->devinfo->codec->sc;
3512 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as];
3513 struct hdac_widget *w;
3514 int i, chn, totalchn, c;
3515 nid_t cad = ch->devinfo->codec->cad;
3517 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */
3518 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */
3521 totalchn = AFMT_CHANNEL(ch->fmt);
3523 device_printf(ch->pdevinfo->dev,
3524 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n",
3525 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3529 if (ch->fmt & AFMT_S16_LE)
3530 fmt |= ch->bit16 << 4;
3531 else if (ch->fmt & AFMT_S32_LE)
3532 fmt |= ch->bit32 << 4;
3535 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3536 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3537 fmt |= hda_rate_tab[i].base;
3538 fmt |= hda_rate_tab[i].mul;
3539 fmt |= hda_rate_tab[i].div;
3543 fmt |= (totalchn - 1);
3545 /* Set channel mapping for known speaker setups. */
3546 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */
3548 else if (as->pinset == 0x0017) /* Standard 7.1 */
3551 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3553 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN;
3554 if (ch->fmt & AFMT_AC3)
3555 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO;
3558 for (i = 0; ch->io[i] != -1; i++) {
3559 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3563 /* If HP redirection is enabled, but failed to use same
3564 DAC, make last DAC to duplicate first one. */
3565 if (as->fakeredir && i == (as->pincnt - 1)) {
3568 if (map >= 0) /* Map known speaker setups. */
3569 chn = (((chmap[map][totalchn / 2] >> i * 4) &
3571 if (chn < 0 || chn >= totalchn) {
3574 c = (ch->sid << 4) | chn;
3578 device_printf(ch->pdevinfo->dev,
3579 "PCMDIR_%s: Stream setup nid=%d: "
3580 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n",
3581 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3582 ch->io[i], fmt, dfmt, c);
3585 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3586 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
3588 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt),
3592 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad);
3595 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad);
3597 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad);
3599 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad);
3601 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1;
3606 * Greatest Common Divisor.
3609 gcd(unsigned a, unsigned b)
3622 * Least Common Multiple.
3625 lcm(unsigned a, unsigned b)
3628 return ((a * b) / gcd(a, b));
3632 hdac_channel_setfragments(kobj_t obj, void *data,
3633 uint32_t blksz, uint32_t blkcnt)
3635 struct hdac_chan *ch = data;
3636 struct hdac_softc *sc = ch->devinfo->codec->sc;
3638 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b));
3640 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3641 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3642 if (blksz < HDA_BLK_MIN)
3643 blksz = HDA_BLK_MIN;
3644 if (blkcnt > HDA_BDL_MAX)
3645 blkcnt = HDA_BDL_MAX;
3646 if (blkcnt < HDA_BDL_MIN)
3647 blkcnt = HDA_BDL_MIN;
3649 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3650 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3652 else if ((blksz >> 1) >= HDA_BLK_MIN)
3658 if ((sndbuf_getblksz(ch->b) != blksz ||
3659 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3660 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3661 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3662 __func__, blksz, blkcnt);
3664 ch->blksz = sndbuf_getblksz(ch->b);
3665 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3671 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3673 struct hdac_chan *ch = data;
3675 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt);
3681 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3683 struct hdac_devinfo *devinfo = ch->devinfo;
3684 struct hdac_widget *w;
3685 nid_t cad = devinfo->codec->cad;
3688 hdac_stream_stop(ch);
3690 for (i = 0; ch->io[i] != -1; i++) {
3691 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3694 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
3696 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0),
3700 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3706 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3710 hdac_stream_stop(ch);
3711 hdac_stream_reset(ch);
3713 hdac_stream_setid(ch);
3714 hdac_stream_setup(ch);
3715 hdac_stream_start(ch);
3719 hdac_channel_trigger(kobj_t obj, void *data, int go)
3721 struct hdac_chan *ch = data;
3722 struct hdac_softc *sc = ch->devinfo->codec->sc;
3724 if (!PCMTRIG_COMMON(go))
3730 hdac_channel_start(sc, ch);
3734 hdac_channel_stop(sc, ch);
3745 hdac_channel_getptr(kobj_t obj, void *data)
3747 struct hdac_chan *ch = data;
3748 struct hdac_softc *sc = ch->devinfo->codec->sc;
3752 if (sc->polling != 0)
3754 else if (ch->dmapos != NULL)
3755 ptr = *(ch->dmapos);
3757 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3761 * Round to available space and force 128 bytes aligment.
3763 ptr %= ch->blksz * ch->blkcnt;
3764 ptr &= HDA_BLK_ALIGN;
3769 static struct pcmchan_caps *
3770 hdac_channel_getcaps(kobj_t obj, void *data)
3772 return (&((struct hdac_chan *)data)->caps);
3775 static kobj_method_t hdac_channel_methods[] = {
3776 KOBJMETHOD(channel_init, hdac_channel_init),
3777 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3778 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3779 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3780 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments),
3781 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3782 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3783 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3786 CHANNEL_DECLARE(hdac_channel);
3789 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3791 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
3792 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3793 struct hdac_softc *sc = devinfo->codec->sc;
3794 struct hdac_widget *w, *cw;
3795 struct hdac_audio_ctl *ctl;
3796 uint32_t mask, recmask, id;
3797 int i, j, softpcmvol;
3801 /* Make sure that in case of soft volume it won't stay muted. */
3802 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3803 pdevinfo->left[i] = 100;
3804 pdevinfo->right[i] = 100;
3809 id = hdac_codec_id(devinfo->codec);
3811 /* Declate EAPD as ogain control. */
3812 if (pdevinfo->play >= 0) {
3813 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3814 w = hdac_widget_get(devinfo, i);
3815 if (w == NULL || w->enable == 0)
3817 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3818 w->param.eapdbtl == HDAC_INVALID ||
3819 w->bindas != sc->chans[pdevinfo->play].as)
3821 mask |= SOUND_MASK_OGAIN;
3826 /* Declare volume controls assigned to this association. */
3829 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3830 if (ctl->enable == 0)
3832 if ((pdevinfo->play >= 0 &&
3833 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
3834 (pdevinfo->rec >= 0 &&
3835 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
3836 (ctl->widget->bindas == -2 && pdevinfo->index == 0))
3837 mask |= ctl->ossmask;
3840 /* Declare record sources available to this association. */
3841 if (pdevinfo->rec >= 0) {
3842 struct hdac_chan *ch = &sc->chans[pdevinfo->rec];
3843 for (i = 0; ch->io[i] != -1; i++) {
3844 w = hdac_widget_get(devinfo, ch->io[i]);
3845 if (w == NULL || w->enable == 0)
3847 for (j = 0; j < w->nconns; j++) {
3848 if (w->connsenable[j] == 0)
3850 cw = hdac_widget_get(devinfo, w->conns[j]);
3851 if (cw == NULL || cw->enable == 0)
3853 if (cw->bindas != sc->chans[pdevinfo->rec].as &&
3856 recmask |= cw->ossmask;
3861 /* Declare soft PCM volume if needed. */
3862 if (pdevinfo->play >= 0) {
3864 if ((mask & SOUND_MASK_PCM) == 0 ||
3865 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) {
3867 mask |= SOUND_MASK_PCM;
3871 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3872 if (ctl->enable == 0)
3874 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as &&
3875 (ctl->widget->bindas != -2 || pdevinfo->index != 0))
3877 if (!(ctl->ossmask & SOUND_MASK_PCM))
3884 if (softpcmvol == 1 || ctl == NULL) {
3885 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL);
3887 device_printf(pdevinfo->dev,
3888 "%s Soft PCM volume\n",
3889 (softpcmvol == 1) ? "Forcing" : "Enabling");
3894 /* Declare master volume if needed. */
3895 if (pdevinfo->play >= 0) {
3896 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) ==
3898 mask |= SOUND_MASK_VOLUME;
3899 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3901 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3904 device_printf(pdevinfo->dev,
3905 "Forcing master volume with PCM\n");
3910 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3911 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3913 mix_setrecdevs(m, recmask);
3914 mix_setdevs(m, mask);
3922 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3923 unsigned left, unsigned right)
3925 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
3926 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3927 struct hdac_softc *sc = devinfo->codec->sc;
3928 struct hdac_widget *w;
3929 struct hdac_audio_ctl *ctl;
3935 /* Save new values. */
3936 pdevinfo->left[dev] = left;
3937 pdevinfo->right[dev] = right;
3939 /* 'ogain' is the special case implemented with EAPD. */
3940 if (dev == SOUND_MIXER_OGAIN) {
3943 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3944 w = hdac_widget_get(devinfo, i);
3945 if (w == NULL || w->enable == 0)
3947 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3948 w->param.eapdbtl == HDAC_INVALID)
3952 if (i >= devinfo->endnode) {
3956 orig = w->param.eapdbtl;
3958 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3960 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3961 if (orig != w->param.eapdbtl) {
3964 val = w->param.eapdbtl;
3965 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3966 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3968 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3969 w->nid, val), devinfo->codec->cad);
3972 return (left | (left << 8));
3975 /* Recalculate all controls related to this OSS device. */
3977 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3978 if (ctl->enable == 0 ||
3979 !(ctl->ossmask & (1 << dev)))
3981 if (!((pdevinfo->play >= 0 &&
3982 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
3983 (pdevinfo->rec >= 0 &&
3984 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
3985 ctl->widget->bindas == -2))
3990 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) {
3991 if (ctl->ossmask & (1 << j)) {
3992 lvol = lvol * pdevinfo->left[j] / 100;
3993 rvol = rvol * pdevinfo->right[j] / 100;
3996 mute = (lvol == 0) ? HDA_AMP_MUTE_LEFT : 0;
3997 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 0;
3998 lvol = (lvol * ctl->step + 50) / 100;
3999 rvol = (rvol * ctl->step + 50) / 100;
4000 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
4004 return (left | (right << 8));
4008 * Commutate specified record source.
4011 hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth)
4013 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
4014 struct hdac_widget *w, *cw;
4015 struct hdac_audio_ctl *ctl;
4020 if (depth > HDA_PARSE_MAXDEPTH)
4023 w = hdac_widget_get(devinfo, nid);
4024 if (w == NULL || w->enable == 0)
4027 for (i = 0; i < w->nconns; i++) {
4028 if (w->connsenable[i] == 0)
4030 cw = hdac_widget_get(devinfo, w->conns[i]);
4031 if (cw == NULL || cw->enable == 0 || cw->bindas == -1)
4033 /* Call recursively to trace signal to it's source if needed. */
4034 if ((src & cw->ossmask) != 0) {
4035 if (cw->ossdev < 0) {
4036 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src,
4037 w->conns[i], depth + 1);
4042 /* We have two special cases: mixers and others (selectors). */
4043 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
4044 ctl = hdac_audio_ctl_amp_get(devinfo,
4045 w->nid, HDA_CTL_IN, i, 1);
4048 /* If we have input control on this node mute them
4049 * according to requested sources. */
4050 muted = (src & cw->ossmask) ? 0 : 1;
4051 if (muted != ctl->forcemute) {
4052 ctl->forcemute = muted;
4053 hdac_audio_ctl_amp_set(ctl,
4054 HDA_AMP_MUTE_DEFAULT,
4055 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
4058 device_printf(pdevinfo->dev,
4059 "Recsel (%s): nid %d source %d %s\n",
4060 hdac_audio_ctl_ossmixer_mask2allname(
4061 src, buf, sizeof(buf)),
4062 nid, i, muted?"mute":"unmute");
4067 if ((src & cw->ossmask) == 0)
4069 /* If we found requested source - select it and exit. */
4070 hdac_widget_connection_select(w, i);
4072 device_printf(pdevinfo->dev,
4073 "Recsel (%s): nid %d source %d select\n",
4074 hdac_audio_ctl_ossmixer_mask2allname(
4075 src, buf, sizeof(buf)),
4085 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
4087 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
4088 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
4089 struct hdac_widget *w;
4090 struct hdac_softc *sc = devinfo->codec->sc;
4091 struct hdac_chan *ch;
4093 uint32_t ret = 0xffffffff;
4097 /* Commutate requested recsrc for each ADC. */
4098 ch = &sc->chans[pdevinfo->rec];
4099 for (i = 0; ch->io[i] != -1; i++) {
4100 w = hdac_widget_get(devinfo, ch->io[i]);
4101 if (w == NULL || w->enable == 0)
4103 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0);
4108 return ((ret == 0xffffffff)? 0 : ret);
4111 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
4112 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
4113 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
4114 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
4117 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
4120 hdac_unsolq_task(void *context, int pending)
4122 struct hdac_softc *sc;
4124 sc = (struct hdac_softc *)context;
4127 hdac_unsolq_flush(sc);
4131 /****************************************************************************
4132 * int hdac_attach(device_t)
4134 * Attach the device into the kernel. Interrupts usually won't be enabled
4135 * when this function is called. Setup everything that doesn't require
4136 * interrupts and defer probing of codecs until interrupts are enabled.
4137 ****************************************************************************/
4139 hdac_attach(device_t dev)
4141 struct hdac_softc *sc;
4145 uint16_t class, subclass;
4150 device_printf(dev, "HDA Driver Revision: %s\n",
4154 model = (uint32_t)pci_get_device(dev) << 16;
4155 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
4156 class = pci_get_class(dev);
4157 subclass = pci_get_subclass(dev);
4159 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
4160 if (hdac_devices[i].model == model) {
4164 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
4165 class == PCIC_MULTIMEDIA &&
4166 subclass == PCIS_MULTIMEDIA_HDA) {
4172 sc = device_get_softc(dev);
4173 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
4175 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
4176 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
4177 vendor = pci_get_vendor(dev);
4179 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
4180 /* Screw nx6325 - subdevice/subvendor swapped */
4181 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
4184 callout_init(&sc->poll_hda, CALLOUT_MPSAFE);
4185 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE);
4186 callout_init(&sc->poll_jack, CALLOUT_MPSAFE);
4188 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
4190 sc->poll_ticks = 1000000;
4191 sc->poll_ival = HDAC_POLL_INTERVAL;
4192 if (resource_int_value(device_get_name(dev),
4193 device_get_unit(dev), "polling", &i) == 0 && i != 0)
4199 for (i = 0; i < HDAC_CODEC_MAX; i++)
4200 sc->codecs[i] = NULL;
4202 pci_enable_busmaster(dev);
4204 if (vendor == INTEL_VENDORID) {
4206 v = pci_read_config(dev, 0x44, 1);
4207 pci_write_config(dev, 0x44, v & 0xf8, 1);
4209 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
4210 pci_read_config(dev, 0x44, 1));
4214 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI))
4215 sc->flags &= ~HDAC_F_MSI;
4217 sc->flags |= HDAC_F_MSI;
4218 if (resource_int_value(device_get_name(dev),
4219 device_get_unit(dev), "msi", &i) == 0) {
4221 sc->flags &= ~HDAC_F_MSI;
4223 sc->flags |= HDAC_F_MSI;
4226 #if defined(__i386__) || defined(__amd64__)
4227 sc->flags |= HDAC_F_DMA_NOCACHE;
4229 if (resource_int_value(device_get_name(dev),
4230 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
4232 sc->flags &= ~HDAC_F_DMA_NOCACHE;
4235 * Try to enable PCIe snoop to avoid messing around with
4236 * uncacheable DMA attribute. Since PCIe snoop register
4237 * config is pretty much vendor specific, there are no
4238 * general solutions on how to enable it, forcing us (even
4239 * Microsoft) to enable uncacheable or write combined DMA
4242 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
4244 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
4245 if (hdac_pcie_snoop[i].vendor != vendor)
4247 sc->flags &= ~HDAC_F_DMA_NOCACHE;
4248 if (hdac_pcie_snoop[i].reg == 0x00)
4250 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
4251 if ((v & hdac_pcie_snoop[i].enable) ==
4252 hdac_pcie_snoop[i].enable)
4254 v &= hdac_pcie_snoop[i].mask;
4255 v |= hdac_pcie_snoop[i].enable;
4256 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
4257 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
4258 if ((v & hdac_pcie_snoop[i].enable) !=
4259 hdac_pcie_snoop[i].enable) {
4262 "WARNING: Failed to enable PCIe "
4265 #if defined(__i386__) || defined(__amd64__)
4266 sc->flags |= HDAC_F_DMA_NOCACHE;
4271 #if defined(__i386__) || defined(__amd64__)
4276 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
4277 (sc->flags & HDAC_F_DMA_NOCACHE) ?
4278 "Uncacheable" : "PCIe snoop", vendor);
4281 /* Allocate resources */
4282 result = hdac_mem_alloc(sc);
4284 goto hdac_attach_fail;
4285 result = hdac_irq_alloc(sc);
4287 goto hdac_attach_fail;
4289 /* Get Capabilities */
4290 result = hdac_get_capabilities(sc);
4292 goto hdac_attach_fail;
4294 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT))
4295 sc->support_64bit = 0;
4297 /* Allocate CORB and RIRB dma memory */
4298 result = hdac_dma_alloc(sc, &sc->corb_dma,
4299 sc->corb_size * sizeof(uint32_t));
4301 goto hdac_attach_fail;
4302 result = hdac_dma_alloc(sc, &sc->rirb_dma,
4303 sc->rirb_size * sizeof(struct hdac_rirb));
4305 goto hdac_attach_fail;
4307 result = bus_dma_tag_create(
4308 bus_get_dma_tag(sc->dev), /* parent */
4309 HDAC_DMA_ALIGNMENT, /* alignment */
4311 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
4312 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
4313 BUS_SPACE_MAXADDR, /* highaddr */
4314 NULL, /* filtfunc */
4315 NULL, /* fistfuncarg */
4316 HDA_BUFSZ_MAX, /* maxsize */
4318 HDA_BUFSZ_MAX, /* maxsegsz */
4320 NULL, /* lockfunc */
4321 NULL, /* lockfuncarg */
4322 &sc->chan_dmat); /* dmat */
4324 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
4326 goto hdac_attach_fail;
4329 /* Quiesce everything */
4331 device_printf(dev, "Reset controller...\n");
4335 /* Initialize the CORB and RIRB */
4339 /* Defer remaining of initialization until interrupts are enabled */
4340 sc->intrhook.ich_func = hdac_attach2;
4341 sc->intrhook.ich_arg = (void *)sc;
4342 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
4343 sc->intrhook.ich_func = NULL;
4344 hdac_attach2((void *)sc);
4351 hdac_dma_free(sc, &sc->rirb_dma);
4352 hdac_dma_free(sc, &sc->corb_dma);
4354 snd_mtxfree(sc->lock);
4360 hdac_audio_parse(struct hdac_devinfo *devinfo)
4362 struct hdac_codec *codec = devinfo->codec;
4363 struct hdac_softc *sc = codec->sc;
4364 struct hdac_widget *w;
4369 cad = devinfo->codec->cad;
4372 res = hdac_command(sc,
4373 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
4374 devinfo->function.audio.gpio = res;
4377 device_printf(sc->dev, "GPIO: 0x%08x "
4378 "NumGPIO=%d NumGPO=%d "
4379 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
4380 devinfo->function.audio.gpio,
4381 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
4382 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
4383 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
4384 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
4385 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
4388 res = hdac_command(sc,
4389 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
4391 devinfo->function.audio.supp_stream_formats = res;
4393 res = hdac_command(sc,
4394 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
4396 devinfo->function.audio.supp_pcm_size_rate = res;
4398 res = hdac_command(sc,
4399 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
4401 devinfo->function.audio.outamp_cap = res;
4403 res = hdac_command(sc,
4404 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
4406 devinfo->function.audio.inamp_cap = res;
4408 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4409 w = hdac_widget_get(devinfo, i);
4411 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
4413 w->devinfo = devinfo;
4420 w->param.eapdbtl = HDAC_INVALID;
4421 hdac_widget_parse(w);
4427 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
4429 struct hdac_softc *sc = devinfo->codec->sc;
4430 struct hdac_audio_ctl *ctls;
4431 struct hdac_widget *w, *cw;
4432 int i, j, cnt, max, ocap, icap;
4433 int mute, offset, step, size;
4435 /* XXX This is redundant */
4437 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4438 w = hdac_widget_get(devinfo, i);
4439 if (w == NULL || w->enable == 0)
4441 if (w->param.outamp_cap != 0)
4443 if (w->param.inamp_cap != 0) {
4445 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4446 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4447 for (j = 0; j < w->nconns; j++) {
4448 cw = hdac_widget_get(devinfo,
4450 if (cw == NULL || cw->enable == 0)
4462 devinfo->function.audio.ctlcnt = max;
4467 ctls = (struct hdac_audio_ctl *)malloc(
4468 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
4472 device_printf(sc->dev, "unable to allocate ctls!\n");
4473 devinfo->function.audio.ctlcnt = 0;
4478 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
4480 device_printf(sc->dev, "%s: Ctl overflow!\n",
4484 w = hdac_widget_get(devinfo, i);
4485 if (w == NULL || w->enable == 0)
4487 ocap = w->param.outamp_cap;
4488 icap = w->param.inamp_cap;
4490 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
4491 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
4492 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
4493 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
4494 /*if (offset > step) {
4496 device_printf(sc->dev,
4497 "BUGGY outamp: nid=%d "
4498 "[offset=%d > step=%d]\n",
4499 w->nid, offset, step);
4503 ctls[cnt].enable = 1;
4504 ctls[cnt].widget = w;
4505 ctls[cnt].mute = mute;
4506 ctls[cnt].step = step;
4507 ctls[cnt].size = size;
4508 ctls[cnt].offset = offset;
4509 ctls[cnt].left = offset;
4510 ctls[cnt].right = offset;
4511 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
4513 ctls[cnt].ndir = HDA_CTL_IN;
4515 ctls[cnt].ndir = HDA_CTL_OUT;
4516 ctls[cnt++].dir = HDA_CTL_OUT;
4520 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4521 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4522 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4523 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4524 /*if (offset > step) {
4526 device_printf(sc->dev,
4527 "BUGGY inamp: nid=%d "
4528 "[offset=%d > step=%d]\n",
4529 w->nid, offset, step);
4534 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4535 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4536 for (j = 0; j < w->nconns; j++) {
4538 device_printf(sc->dev,
4539 "%s: Ctl overflow!\n",
4543 cw = hdac_widget_get(devinfo,
4545 if (cw == NULL || cw->enable == 0)
4547 ctls[cnt].enable = 1;
4548 ctls[cnt].widget = w;
4549 ctls[cnt].childwidget = cw;
4550 ctls[cnt].index = j;
4551 ctls[cnt].mute = mute;
4552 ctls[cnt].step = step;
4553 ctls[cnt].size = size;
4554 ctls[cnt].offset = offset;
4555 ctls[cnt].left = offset;
4556 ctls[cnt].right = offset;
4557 ctls[cnt].ndir = HDA_CTL_IN;
4558 ctls[cnt++].dir = HDA_CTL_IN;
4563 device_printf(sc->dev,
4564 "%s: Ctl overflow!\n",
4568 ctls[cnt].enable = 1;
4569 ctls[cnt].widget = w;
4570 ctls[cnt].mute = mute;
4571 ctls[cnt].step = step;
4572 ctls[cnt].size = size;
4573 ctls[cnt].offset = offset;
4574 ctls[cnt].left = offset;
4575 ctls[cnt].right = offset;
4577 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4578 ctls[cnt].ndir = HDA_CTL_OUT;
4580 ctls[cnt].ndir = HDA_CTL_IN;
4581 ctls[cnt++].dir = HDA_CTL_IN;
4587 devinfo->function.audio.ctl = ctls;
4591 hdac_audio_as_parse(struct hdac_devinfo *devinfo)
4593 struct hdac_softc *sc = devinfo->codec->sc;
4594 struct hdac_audio_as *as;
4595 struct hdac_widget *w;
4596 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir;
4598 /* Count present associations */
4600 for (j = 1; j < 16; j++) {
4601 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4602 w = hdac_widget_get(devinfo, i);
4603 if (w == NULL || w->enable == 0)
4605 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4607 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config)
4611 if (j != 15) /* There could be many 1-pin assocs #15 */
4616 devinfo->function.audio.ascnt = max;
4621 as = (struct hdac_audio_as *)malloc(
4622 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT);
4626 device_printf(sc->dev, "unable to allocate assocs!\n");
4627 devinfo->function.audio.ascnt = 0;
4631 for (i = 0; i < max; i++) {
4637 /* Scan associations skipping as=0. */
4639 for (j = 1; j < 16; j++) {
4642 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4643 w = hdac_widget_get(devinfo, i);
4644 if (w == NULL || w->enable == 0)
4646 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4648 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config);
4649 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config);
4654 ("%s: Associations owerflow (%d of %d)",
4655 __func__, cnt, max));
4656 type = w->wclass.pin.config &
4657 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4658 /* Get pin direction. */
4659 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT ||
4660 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4661 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4662 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT ||
4663 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT)
4667 /* If this is a first pin - create new association. */
4668 if (as[cnt].pincnt == 0) {
4675 /* Check association correctness. */
4676 if (as[cnt].pins[seq] != 0) {
4677 device_printf(sc->dev, "%s: Duplicate pin %d (%d) "
4678 "in association %d! Disabling association.\n",
4679 __func__, seq, w->nid, j);
4682 if (dir != as[cnt].dir) {
4683 device_printf(sc->dev, "%s: Pin %d has wrong "
4684 "direction for association %d! Disabling "
4686 __func__, w->nid, j);
4689 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
4690 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap))
4691 as[cnt].digital = 3;
4692 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap))
4693 as[cnt].digital = 2;
4695 as[cnt].digital = 1;
4697 /* Headphones with seq=15 may mean redirection. */
4698 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT &&
4701 as[cnt].pins[seq] = w->nid;
4703 /* Association 15 is a multiple unassociated pins. */
4707 if (j != 15 && as[cnt].pincnt > 0) {
4708 if (hpredir && as[cnt].pincnt > 1)
4709 as[cnt].hpredir = first;
4714 device_printf(sc->dev,
4715 "%d associations found:\n", max);
4716 for (i = 0; i < max; i++) {
4717 device_printf(sc->dev,
4718 "Association %d (%d) %s%s:\n",
4719 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out",
4720 as[i].enable?"":" (disabled)");
4721 for (j = 0; j < 16; j++) {
4722 if (as[i].pins[j] == 0)
4724 device_printf(sc->dev,
4725 " Pin nid=%d seq=%d\n",
4731 devinfo->function.audio.as = as;
4734 static const struct {
4737 uint32_t set, unset;
4740 * XXX Force stereo quirk. Monoural recording / playback
4741 * on few codecs (especially ALC880) seems broken or
4742 * perhaps unsupported.
4744 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4745 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4746 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4747 HDA_QUIRK_GPIO0, 0 },
4748 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660,
4749 HDA_QUIRK_GPIO0, 0 },
4750 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4751 HDA_QUIRK_GPIO0, 0 },
4752 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4753 HDA_QUIRK_GPIO0, 0 },
4754 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4755 HDA_QUIRK_GPIO0, 0 },
4756 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4757 HDA_QUIRK_GPIO0, 0 },
4758 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4759 HDA_QUIRK_EAPDINV, 0 },
4760 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A,
4761 HDA_QUIRK_EAPDINV, 0 },
4762 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4763 HDA_QUIRK_OVREF, 0 },
4764 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4765 HDA_QUIRK_OVREF, 0 },
4766 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4767 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4768 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4769 HDA_QUIRK_GPIO1, 0 },
4770 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4771 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 },
4772 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4773 HDA_QUIRK_EAPDINV, 0 },
4774 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885,
4775 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0},
4776 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4777 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4778 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206,
4779 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 },
4780 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X,
4781 HDA_QUIRK_GPIO0, 0 },
4782 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X,
4783 HDA_QUIRK_GPIO2, 0 },
4784 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X,
4785 HDA_QUIRK_GPIO0, 0 },
4786 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4787 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4788 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4789 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4790 { HDA_MATCH_ALL, HDA_CODEC_CX20549,
4791 0, HDA_QUIRK_FORCESTEREO }
4793 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4796 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4798 struct hdac_widget *w;
4799 uint32_t id, subvendor;
4802 id = hdac_codec_id(devinfo->codec);
4803 subvendor = devinfo->codec->sc->pci_subvendor;
4808 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4809 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4810 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4812 if (hdac_quirks[i].set != 0)
4813 devinfo->function.audio.quirks |=
4815 if (hdac_quirks[i].unset != 0)
4816 devinfo->function.audio.quirks &=
4817 ~(hdac_quirks[i].unset);
4821 case HDA_CODEC_AD1983:
4823 * This codec has several possible usages, but none
4824 * fit the parser best. Help parser to choose better.
4826 /* Disable direct unmixed playback to get pcm volume. */
4827 w = hdac_widget_get(devinfo, 5);
4829 w->connsenable[0] = 0;
4830 w = hdac_widget_get(devinfo, 6);
4832 w->connsenable[0] = 0;
4833 w = hdac_widget_get(devinfo, 11);
4835 w->connsenable[0] = 0;
4836 /* Disable mic and line selectors. */
4837 w = hdac_widget_get(devinfo, 12);
4839 w->connsenable[1] = 0;
4840 w = hdac_widget_get(devinfo, 13);
4842 w->connsenable[1] = 0;
4843 /* Disable recording from mono playback mix. */
4844 w = hdac_widget_get(devinfo, 20);
4846 w->connsenable[3] = 0;
4848 case HDA_CODEC_AD1986A:
4850 * This codec has overcomplicated input mixing.
4851 * Make some cleaning there.
4853 /* Disable input mono mixer. Not needed and not supported. */
4854 w = hdac_widget_get(devinfo, 43);
4857 /* Disable any with any input mixing mesh. Use separately. */
4858 w = hdac_widget_get(devinfo, 39);
4861 w = hdac_widget_get(devinfo, 40);
4864 w = hdac_widget_get(devinfo, 41);
4867 w = hdac_widget_get(devinfo, 42);
4870 /* Disable duplicate mixer node connector. */
4871 w = hdac_widget_get(devinfo, 15);
4873 w->connsenable[3] = 0;
4874 /* There is only one mic preamplifier, use it effectively. */
4875 w = hdac_widget_get(devinfo, 31);
4877 if ((w->wclass.pin.config &
4878 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
4879 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) {
4880 w = hdac_widget_get(devinfo, 16);
4882 w->connsenable[2] = 0;
4884 w = hdac_widget_get(devinfo, 15);
4886 w->connsenable[0] = 0;
4889 w = hdac_widget_get(devinfo, 32);
4891 if ((w->wclass.pin.config &
4892 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
4893 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) {
4894 w = hdac_widget_get(devinfo, 16);
4896 w->connsenable[0] = 0;
4898 w = hdac_widget_get(devinfo, 15);
4900 w->connsenable[1] = 0;
4904 if (subvendor == ASUS_A8X_SUBVENDOR) {
4906 * This is just plain ridiculous.. There
4907 * are several A8 series that share the same
4908 * pci id but works differently (EAPD).
4910 w = hdac_widget_get(devinfo, 26);
4911 if (w != NULL && w->type ==
4912 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4913 (w->wclass.pin.config &
4914 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) !=
4915 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
4916 devinfo->function.audio.quirks &=
4920 case HDA_CODEC_AD1981HD:
4922 * This codec has very unusual design with several
4923 * points inappropriate for the present parser.
4925 /* Disable recording from mono playback mix. */
4926 w = hdac_widget_get(devinfo, 21);
4928 w->connsenable[3] = 0;
4929 /* Disable rear to front mic mixer, use separately. */
4930 w = hdac_widget_get(devinfo, 31);
4933 /* Disable direct playback, use mixer. */
4934 w = hdac_widget_get(devinfo, 5);
4936 w->connsenable[0] = 0;
4937 w = hdac_widget_get(devinfo, 6);
4939 w->connsenable[0] = 0;
4940 w = hdac_widget_get(devinfo, 9);
4942 w->connsenable[0] = 0;
4943 w = hdac_widget_get(devinfo, 24);
4945 w->connsenable[0] = 0;
4947 case HDA_CODEC_CX20582:
4948 case HDA_CODEC_CX20583:
4949 case HDA_CODEC_CX20584:
4950 case HDA_CODEC_CX20585:
4951 case HDA_CODEC_CX20590:
4953 * These codecs have extra connectivity on record side
4954 * too reach for the present parser.
4956 w = hdac_widget_get(devinfo, 20);
4958 w->connsenable[1] = 0;
4959 w = hdac_widget_get(devinfo, 21);
4961 w->connsenable[1] = 0;
4962 w = hdac_widget_get(devinfo, 22);
4964 w->connsenable[0] = 0;
4970 * Trace path from DAC to pin.
4973 hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid,
4974 int dupseq, int min, int only, int depth)
4976 struct hdac_widget *w;
4980 if (depth > HDA_PARSE_MAXDEPTH)
4982 w = hdac_widget_get(devinfo, nid);
4983 if (w == NULL || w->enable == 0)
4987 device_printf(devinfo->codec->sc->dev,
4988 " %*stracing via nid %d\n",
4989 depth + 1, "", w->nid);
4992 /* Use only unused widgets */
4993 if (w->bindas >= 0 && w->bindas != as) {
4996 device_printf(devinfo->codec->sc->dev,
4997 " %*snid %d busy by association %d\n",
4998 depth + 1, "", w->nid, w->bindas);
5004 if (w->bindseqmask != 0) {
5007 device_printf(devinfo->codec->sc->dev,
5008 " %*snid %d busy by seqmask %x\n",
5009 depth + 1, "", w->nid, w->bindseqmask);
5015 /* If this is headphones - allow duplicate first pin. */
5016 if (w->bindseqmask != 0 &&
5017 (w->bindseqmask & (1 << dupseq)) == 0) {
5019 device_printf(devinfo->codec->sc->dev,
5020 " %*snid %d busy by seqmask %x\n",
5021 depth + 1, "", w->nid, w->bindseqmask);
5028 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
5029 /* Do not traverse input. AD1988 has digital monitor
5030 for which we are not ready. */
5032 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
5033 /* If we are tracing HP take only dac of first pin. */
5034 if ((only == 0 || only == w->nid) &&
5035 (w->nid >= min) && (dupseq < 0 || w->nid ==
5036 devinfo->function.audio.as[as].dacs[dupseq]))
5039 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
5044 /* Find reachable DACs with smallest nid respecting constraints. */
5045 for (i = 0; i < w->nconns; i++) {
5046 if (w->connsenable[i] == 0)
5048 if (w->selconn != -1 && w->selconn != i)
5050 if ((ret = hdac_audio_trace_dac(devinfo, as, seq,
5051 w->conns[i], dupseq, min, only, depth + 1)) != 0) {
5052 if (m == 0 || ret < m) {
5056 if (only || dupseq >= 0)
5060 if (m && only && ((w->nconns > 1 &&
5061 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
5062 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
5068 w->bindseqmask |= (1 << seq);
5072 device_printf(devinfo->codec->sc->dev,
5073 " %*snid %d returned %d\n",
5074 depth + 1, "", w->nid, m);
5081 * Trace path from widget to ADC.
5084 hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid,
5085 int only, int depth)
5087 struct hdac_widget *w, *wc;
5091 if (depth > HDA_PARSE_MAXDEPTH)
5093 w = hdac_widget_get(devinfo, nid);
5094 if (w == NULL || w->enable == 0)
5097 device_printf(devinfo->codec->sc->dev,
5098 " %*stracing via nid %d\n",
5099 depth + 1, "", w->nid);
5101 /* Use only unused widgets */
5102 if (w->bindas >= 0 && w->bindas != as) {
5104 device_printf(devinfo->codec->sc->dev,
5105 " %*snid %d busy by association %d\n",
5106 depth + 1, "", w->nid, w->bindas);
5112 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
5113 /* If we are tracing HP take only dac of first pin. */
5117 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
5122 /* Try to find reachable ADCs with specified nid. */
5123 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5124 wc = hdac_widget_get(devinfo, j);
5125 if (wc == NULL || wc->enable == 0)
5127 for (i = 0; i < wc->nconns; i++) {
5128 if (wc->connsenable[i] == 0)
5130 if (wc->conns[i] != nid)
5132 if (hdac_audio_trace_adc(devinfo, as, seq,
5133 j, only, depth + 1) != 0) {
5135 if (((wc->nconns > 1 &&
5136 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
5137 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) &&
5147 w->bindseqmask |= (1 << seq);
5150 device_printf(devinfo->codec->sc->dev,
5151 " %*snid %d returned %d\n",
5152 depth + 1, "", w->nid, res);
5158 * Erase trace path of the specified association.
5161 hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq)
5163 struct hdac_widget *w;
5166 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5167 w = hdac_widget_get(devinfo, i);
5168 if (w == NULL || w->enable == 0)
5170 if (w->bindas == as) {
5172 w->bindseqmask &= ~(1 << seq);
5173 if (w->bindseqmask == 0) {
5187 * Trace association path from DAC to output
5190 hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq)
5192 struct hdac_audio_as *ases = devinfo->function.audio.as;
5197 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++)
5199 /* Check if there is no any left. If so - we succeeded. */
5203 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1;
5208 device_printf(devinfo->codec->sc->dev,
5209 " Tracing pin %d with min nid %d",
5210 ases[as].pins[i], min);
5212 printf(" and hpredir %d", hpredir);
5215 /* Trace this pin taking min nid into account. */
5216 res = hdac_audio_trace_dac(devinfo, as, i,
5217 ases[as].pins[i], hpredir, min, 0, 0);
5219 /* If we failed - return to previous and redo it. */
5221 device_printf(devinfo->codec->sc->dev,
5222 " Unable to trace pin %d seq %d with min "
5224 ases[as].pins[i], i, min);
5226 printf(" and hpredir %d", hpredir);
5232 device_printf(devinfo->codec->sc->dev,
5233 " Pin %d traced to DAC %d",
5234 ases[as].pins[i], res);
5236 printf(" and hpredir %d", hpredir);
5237 if (ases[as].fakeredir)
5238 printf(" with fake redirection");
5241 /* Trace again to mark the path */
5242 hdac_audio_trace_dac(devinfo, as, i,
5243 ases[as].pins[i], hpredir, min, res, 0);
5244 ases[as].dacs[i] = res;
5245 /* We succeeded, so call next. */
5246 if (hdac_audio_trace_as_out(devinfo, as, i + 1))
5248 /* If next failed, we should retry with next min */
5249 hdac_audio_undo_trace(devinfo, as, i);
5250 ases[as].dacs[i] = 0;
5256 * Trace association path from input to ADC
5259 hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as)
5261 struct hdac_audio_as *ases = devinfo->function.audio.as;
5262 struct hdac_widget *w;
5265 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5266 w = hdac_widget_get(devinfo, j);
5267 if (w == NULL || w->enable == 0)
5269 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
5271 if (w->bindas >= 0 && w->bindas != as)
5275 for (i = 0; i < 16; i++) {
5276 if (ases[as].pins[i] == 0)
5280 device_printf(devinfo->codec->sc->dev,
5281 " Tracing pin %d to ADC %d\n",
5282 ases[as].pins[i], j);
5284 /* Trace this pin taking goal into account. */
5285 if (hdac_audio_trace_adc(devinfo, as, i,
5286 ases[as].pins[i], j, 0) == 0) {
5287 /* If we failed - return to previous and redo it. */
5289 device_printf(devinfo->codec->sc->dev,
5290 " Unable to trace pin %d to ADC %d, undo traces\n",
5291 ases[as].pins[i], j);
5293 hdac_audio_undo_trace(devinfo, as, -1);
5294 for (k = 0; k < 16; k++)
5295 ases[as].dacs[k] = 0;
5299 device_printf(devinfo->codec->sc->dev,
5300 " Pin %d traced to ADC %d\n",
5301 ases[as].pins[i], j);
5303 ases[as].dacs[i] = j;
5312 * Trace input monitor path from mixer to output association.
5315 hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5317 struct hdac_audio_as *ases = devinfo->function.audio.as;
5318 struct hdac_widget *w, *wc;
5322 if (depth > HDA_PARSE_MAXDEPTH)
5324 w = hdac_widget_get(devinfo, nid);
5325 if (w == NULL || w->enable == 0)
5328 device_printf(devinfo->codec->sc->dev,
5329 " %*stracing via nid %d\n",
5330 depth + 1, "", w->nid);
5332 /* Use only unused widgets */
5333 if (depth > 0 && w->bindas != -1) {
5334 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) {
5336 device_printf(devinfo->codec->sc->dev,
5337 " %*snid %d found output association %d\n",
5338 depth + 1, "", w->nid, w->bindas);
5341 w->pflags |= HDA_ADC_MONITOR;
5345 device_printf(devinfo->codec->sc->dev,
5346 " %*snid %d busy by input association %d\n",
5347 depth + 1, "", w->nid, w->bindas);
5354 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
5355 /* Do not traverse input. AD1988 has digital monitor
5356 for which we are not ready. */
5358 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
5363 /* Try to find reachable ADCs with specified nid. */
5364 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5365 wc = hdac_widget_get(devinfo, j);
5366 if (wc == NULL || wc->enable == 0)
5368 for (i = 0; i < wc->nconns; i++) {
5369 if (wc->connsenable[i] == 0)
5371 if (wc->conns[i] != nid)
5373 if (hdac_audio_trace_to_out(devinfo,
5374 j, depth + 1) != 0) {
5376 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5384 if (res && w->bindas == -1)
5388 device_printf(devinfo->codec->sc->dev,
5389 " %*snid %d returned %d\n",
5390 depth + 1, "", w->nid, res);
5396 * Trace extra associations (beeper, monitor)
5399 hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo)
5401 struct hdac_audio_as *as = devinfo->function.audio.as;
5402 struct hdac_widget *w;
5406 /* Find mixer associated with input, but supplying signal
5407 for output associations. Hope it will be input monitor. */
5409 device_printf(devinfo->codec->sc->dev,
5410 "Tracing input monitor\n");
5412 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5413 w = hdac_widget_get(devinfo, j);
5414 if (w == NULL || w->enable == 0)
5416 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5418 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN)
5421 device_printf(devinfo->codec->sc->dev,
5422 " Tracing nid %d to out\n",
5425 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) {
5427 device_printf(devinfo->codec->sc->dev,
5428 " nid %d is input monitor\n",
5431 w->ossdev = SOUND_MIXER_IMIX;
5435 /* Other inputs monitor */
5436 /* Find input pins supplying signal for output associations.
5437 Hope it will be input monitoring. */
5439 device_printf(devinfo->codec->sc->dev,
5440 "Tracing other input monitors\n");
5442 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5443 w = hdac_widget_get(devinfo, j);
5444 if (w == NULL || w->enable == 0)
5446 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5448 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN)
5451 device_printf(devinfo->codec->sc->dev,
5452 " Tracing nid %d to out\n",
5455 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) {
5457 device_printf(devinfo->codec->sc->dev,
5458 " nid %d is input monitor\n",
5466 device_printf(devinfo->codec->sc->dev,
5467 "Tracing beeper\n");
5469 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5470 w = hdac_widget_get(devinfo, j);
5471 if (w == NULL || w->enable == 0)
5473 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET)
5476 device_printf(devinfo->codec->sc->dev,
5477 " Tracing nid %d to out\n",
5480 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) {
5482 device_printf(devinfo->codec->sc->dev,
5483 " nid %d traced to out\n",
5492 * Bind assotiations to PCM channels
5495 hdac_audio_bind_as(struct hdac_devinfo *devinfo)
5497 struct hdac_softc *sc = devinfo->codec->sc;
5498 struct hdac_audio_as *as = devinfo->function.audio.as;
5499 int j, cnt = 0, free;
5501 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
5505 if (sc->num_chans == 0) {
5506 sc->chans = (struct hdac_chan *)malloc(
5507 sizeof(struct hdac_chan) * cnt,
5508 M_HDAC, M_ZERO | M_NOWAIT);
5509 if (sc->chans == NULL) {
5510 device_printf(sc->dev,
5511 "Channels memory allocation failed!\n");
5515 sc->chans = (struct hdac_chan *)realloc(sc->chans,
5516 sizeof(struct hdac_chan) * (sc->num_chans + cnt),
5517 M_HDAC, M_ZERO | M_NOWAIT);
5518 if (sc->chans == NULL) {
5520 device_printf(sc->dev,
5521 "Channels memory allocation failed!\n");
5524 /* Fixup relative pointers after realloc */
5525 for (j = 0; j < sc->num_chans; j++)
5526 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist;
5528 free = sc->num_chans;
5529 sc->num_chans += cnt;
5531 for (j = free; j < free + cnt; j++) {
5532 sc->chans[j].devinfo = devinfo;
5533 sc->chans[j].as = -1;
5536 /* Assign associations in order of their numbers, */
5537 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
5538 if (as[j].enable == 0)
5542 sc->chans[free].as = j;
5543 sc->chans[free].dir =
5544 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY;
5545 hdac_pcmchannel_setup(&sc->chans[free]);
5551 hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo)
5553 struct hdac_widget *w;
5556 /* Disable power and volume widgets. */
5557 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5558 w = hdac_widget_get(devinfo, i);
5559 if (w == NULL || w->enable == 0)
5561 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET ||
5562 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) {
5565 device_printf(devinfo->codec->sc->dev,
5566 " Disabling nid %d due to it's"
5567 " non-audio type.\n",
5575 hdac_audio_disable_useless(struct hdac_devinfo *devinfo)
5577 struct hdac_widget *w, *cw;
5578 struct hdac_audio_ctl *ctl;
5579 int done, found, i, j, k;
5581 /* Disable useless pins. */
5582 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5583 w = hdac_widget_get(devinfo, i);
5584 if (w == NULL || w->enable == 0)
5586 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5587 if ((w->wclass.pin.config &
5588 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
5589 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) {
5592 device_printf(devinfo->codec->sc->dev,
5593 " Disabling pin nid %d due"
5594 " to None connectivity.\n",
5597 } else if ((w->wclass.pin.config &
5598 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) {
5601 device_printf(devinfo->codec->sc->dev,
5602 " Disabling unassociated"
5611 /* Disable and mute controls for disabled widgets. */
5613 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5614 if (ctl->enable == 0)
5616 if (ctl->widget->enable == 0 ||
5617 (ctl->childwidget != NULL &&
5618 ctl->childwidget->enable == 0)) {
5620 ctl->muted = HDA_AMP_MUTE_ALL;
5624 if (ctl->ndir == HDA_CTL_IN)
5625 ctl->widget->connsenable[ctl->index] = 0;
5628 device_printf(devinfo->codec->sc->dev,
5629 " Disabling ctl %d nid %d cnid %d due"
5630 " to disabled widget.\n", i,
5632 (ctl->childwidget != NULL)?
5633 ctl->childwidget->nid:-1);
5637 /* Disable useless widgets. */
5638 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5639 w = hdac_widget_get(devinfo, i);
5640 if (w == NULL || w->enable == 0)
5642 /* Disable inputs with disabled child widgets. */
5643 for (j = 0; j < w->nconns; j++) {
5644 if (w->connsenable[j]) {
5645 cw = hdac_widget_get(devinfo, w->conns[j]);
5646 if (cw == NULL || cw->enable == 0) {
5647 w->connsenable[j] = 0;
5649 device_printf(devinfo->codec->sc->dev,
5650 " Disabling nid %d connection %d due"
5651 " to disabled child widget.\n",
5657 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5658 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5660 /* Disable mixers and selectors without inputs. */
5662 for (j = 0; j < w->nconns; j++) {
5663 if (w->connsenable[j]) {
5672 device_printf(devinfo->codec->sc->dev,
5673 " Disabling nid %d due to all it's"
5674 " inputs disabled.\n", w->nid);
5677 /* Disable nodes without consumers. */
5678 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5679 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5682 for (k = devinfo->startnode; k < devinfo->endnode; k++) {
5683 cw = hdac_widget_get(devinfo, k);
5684 if (cw == NULL || cw->enable == 0)
5686 for (j = 0; j < cw->nconns; j++) {
5687 if (cw->connsenable[j] && cw->conns[j] == i) {
5697 device_printf(devinfo->codec->sc->dev,
5698 " Disabling nid %d due to all it's"
5699 " consumers disabled.\n", w->nid);
5703 } while (done == 0);
5708 hdac_audio_disable_unas(struct hdac_devinfo *devinfo)
5710 struct hdac_audio_as *as = devinfo->function.audio.as;
5711 struct hdac_widget *w, *cw;
5712 struct hdac_audio_ctl *ctl;
5715 /* Disable unassosiated widgets. */
5716 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5717 w = hdac_widget_get(devinfo, i);
5718 if (w == NULL || w->enable == 0)
5720 if (w->bindas == -1) {
5723 device_printf(devinfo->codec->sc->dev,
5724 " Disabling unassociated nid %d.\n",
5729 /* Disable input connections on input pin and
5730 * output on output. */
5731 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5732 w = hdac_widget_get(devinfo, i);
5733 if (w == NULL || w->enable == 0)
5735 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5739 if (as[w->bindas].dir == HDA_CTL_IN) {
5740 for (j = 0; j < w->nconns; j++) {
5741 if (w->connsenable[j] == 0)
5743 w->connsenable[j] = 0;
5745 device_printf(devinfo->codec->sc->dev,
5746 " Disabling connection to input pin "
5747 "nid %d conn %d.\n",
5751 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
5753 if (ctl && ctl->enable) {
5755 ctl->muted = HDA_AMP_MUTE_ALL;
5761 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
5762 HDA_CTL_OUT, -1, 1);
5763 if (ctl && ctl->enable) {
5765 ctl->muted = HDA_AMP_MUTE_ALL;
5770 for (k = devinfo->startnode; k < devinfo->endnode; k++) {
5771 cw = hdac_widget_get(devinfo, k);
5772 if (cw == NULL || cw->enable == 0)
5774 for (j = 0; j < cw->nconns; j++) {
5775 if (cw->connsenable[j] && cw->conns[j] == i) {
5776 cw->connsenable[j] = 0;
5778 device_printf(devinfo->codec->sc->dev,
5779 " Disabling connection from output pin "
5780 "nid %d conn %d cnid %d.\n",
5783 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
5786 ctl = hdac_audio_ctl_amp_get(devinfo, k,
5788 if (ctl && ctl->enable) {
5790 ctl->muted = HDA_AMP_MUTE_ALL;
5803 hdac_audio_disable_notselected(struct hdac_devinfo *devinfo)
5805 struct hdac_audio_as *as = devinfo->function.audio.as;
5806 struct hdac_widget *w;
5809 /* On playback path we can safely disable all unseleted inputs. */
5810 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5811 w = hdac_widget_get(devinfo, i);
5812 if (w == NULL || w->enable == 0)
5816 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5818 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN)
5820 for (j = 0; j < w->nconns; j++) {
5821 if (w->connsenable[j] == 0)
5823 if (w->selconn < 0 || w->selconn == j)
5825 w->connsenable[j] = 0;
5827 device_printf(devinfo->codec->sc->dev,
5828 " Disabling unselected connection "
5829 "nid %d conn %d.\n",
5837 hdac_audio_disable_crossas(struct hdac_devinfo *devinfo)
5839 struct hdac_audio_as *ases = devinfo->function.audio.as;
5840 struct hdac_widget *w, *cw;
5841 struct hdac_audio_ctl *ctl;
5844 /* Disable crossassociatement and unwanted crosschannel connections. */
5845 /* ... using selectors */
5846 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5847 w = hdac_widget_get(devinfo, i);
5848 if (w == NULL || w->enable == 0)
5852 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5854 if (w->bindas == -2)
5856 for (j = 0; j < w->nconns; j++) {
5857 if (w->connsenable[j] == 0)
5859 cw = hdac_widget_get(devinfo, w->conns[j]);
5860 if (cw == NULL || w->enable == 0)
5862 if (cw->bindas == -2 ||
5863 ((w->pflags & HDA_ADC_MONITOR) &&
5865 ases[cw->bindas].dir == HDA_CTL_IN))
5867 if (w->bindas == cw->bindas &&
5868 (w->bindseqmask & cw->bindseqmask) != 0)
5870 w->connsenable[j] = 0;
5872 device_printf(devinfo->codec->sc->dev,
5873 " Disabling crossassociatement connection "
5874 "nid %d conn %d cnid %d.\n",
5879 /* ... using controls */
5881 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5882 if (ctl->enable == 0 || ctl->childwidget == NULL)
5884 if (ctl->widget->bindas == -2)
5886 if (ctl->childwidget->bindas == -2 ||
5887 ((ctl->widget->pflags & HDA_ADC_MONITOR) &&
5888 ctl->childwidget->bindas >= 0 &&
5889 ases[ctl->childwidget->bindas].dir == HDA_CTL_IN))
5891 if (ctl->widget->bindas != ctl->childwidget->bindas ||
5892 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) {
5894 ctl->muted = HDA_AMP_MUTE_ALL;
5898 if (ctl->ndir == HDA_CTL_IN)
5899 ctl->widget->connsenable[ctl->index] = 0;
5901 device_printf(devinfo->codec->sc->dev,
5902 " Disabling crossassociatement connection "
5903 "ctl %d nid %d cnid %d.\n", i,
5905 ctl->childwidget->nid);
5912 #define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0)
5915 * Find controls to control amplification for source.
5918 hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index,
5919 int ossdev, int ctlable, int depth, int need)
5921 struct hdac_widget *w, *wc;
5922 struct hdac_audio_ctl *ctl;
5923 int i, j, conns = 0, rneed;
5925 if (depth > HDA_PARSE_MAXDEPTH)
5928 w = hdac_widget_get(devinfo, nid);
5929 if (w == NULL || w->enable == 0)
5932 /* Count number of active inputs. */
5934 for (j = 0; j < w->nconns; j++) {
5935 if (w->connsenable[j])
5940 /* If this is not a first step - use input mixer.
5941 Pins have common input ctl so care must be taken. */
5942 if (depth > 0 && ctlable && (conns == 1 ||
5943 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) {
5944 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN,
5947 if (HDA_CTL_GIVE(ctl) & need)
5948 ctl->ossmask |= (1 << ossdev);
5950 ctl->possmask |= (1 << ossdev);
5951 need &= ~HDA_CTL_GIVE(ctl);
5955 /* If widget has own ossdev - not traverse it.
5956 It will be traversed on it's own. */
5957 if (w->ossdev >= 0 && depth > 0)
5960 /* We must not traverse pin */
5961 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
5962 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5966 /* record that this widget exports such signal, */
5967 w->ossmask |= (1 << ossdev);
5969 /* If signals mixed, we can't assign controls farther.
5970 * Ignore this on depth zero. Caller must knows why.
5971 * Ignore this for static selectors if this input selected.
5977 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1);
5979 if (HDA_CTL_GIVE(ctl) & need)
5980 ctl->ossmask |= (1 << ossdev);
5982 ctl->possmask |= (1 << ossdev);
5983 need &= ~HDA_CTL_GIVE(ctl);
5988 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5989 wc = hdac_widget_get(devinfo, i);
5990 if (wc == NULL || wc->enable == 0)
5992 for (j = 0; j < wc->nconns; j++) {
5993 if (wc->connsenable[j] && wc->conns[j] == nid) {
5994 rneed |= hdac_audio_ctl_source_amp(devinfo,
5995 wc->nid, j, ossdev, ctlable, depth + 1, need);
6005 * Find controls to control amplification for destination.
6008 hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, int index,
6009 int ossdev, int depth, int need)
6011 struct hdac_audio_as *as = devinfo->function.audio.as;
6012 struct hdac_widget *w, *wc;
6013 struct hdac_audio_ctl *ctl;
6014 int i, j, consumers;
6016 if (depth > HDA_PARSE_MAXDEPTH)
6019 w = hdac_widget_get(devinfo, nid);
6020 if (w == NULL || w->enable == 0)
6024 /* If this node produce output for several consumers,
6025 we can't touch it. */
6027 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6028 wc = hdac_widget_get(devinfo, i);
6029 if (wc == NULL || wc->enable == 0)
6031 for (j = 0; j < wc->nconns; j++) {
6032 if (wc->connsenable[j] && wc->conns[j] == nid)
6036 /* The only exception is if real HP redirection is configured
6037 and this is a duplication point.
6038 XXX: Actually exception is not completely correct.
6039 XXX: Duplication point check is not perfect. */
6040 if ((consumers == 2 && (w->bindas < 0 ||
6041 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir ||
6042 (w->bindseqmask & (1 << 15)) == 0)) ||
6046 /* Else use it's output mixer. */
6047 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
6048 HDA_CTL_OUT, -1, 1);
6050 if (HDA_CTL_GIVE(ctl) & need)
6051 ctl->ossmask |= (1 << ossdev);
6053 ctl->possmask |= (1 << ossdev);
6054 need &= ~HDA_CTL_GIVE(ctl);
6058 /* We must not traverse pin */
6059 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6063 for (i = 0; i < w->nconns; i++) {
6065 if (w->connsenable[i] == 0)
6067 if (index >= 0 && i != index)
6069 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
6072 if (HDA_CTL_GIVE(ctl) & tneed)
6073 ctl->ossmask |= (1 << ossdev);
6075 ctl->possmask |= (1 << ossdev);
6076 tneed &= ~HDA_CTL_GIVE(ctl);
6078 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], -1, ossdev,
6084 * Assign OSS names to sound sources
6087 hdac_audio_assign_names(struct hdac_devinfo *devinfo)
6089 struct hdac_audio_as *as = devinfo->function.audio.as;
6090 struct hdac_widget *w;
6092 int type = -1, use, used = 0;
6093 static const int types[7][13] = {
6094 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2,
6095 SOUND_MIXER_LINE3, -1 }, /* line */
6096 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */
6097 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */
6098 { SOUND_MIXER_CD, -1 }, /* cd */
6099 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */
6100 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3,
6102 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2,
6103 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT,
6104 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1,
6105 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR,
6109 /* Surely known names */
6110 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6111 w = hdac_widget_get(devinfo, i);
6112 if (w == NULL || w->enable == 0)
6114 if (w->bindas == -1)
6118 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
6119 if (as[w->bindas].dir == HDA_CTL_OUT)
6122 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
6123 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
6126 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
6127 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK)
6128 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
6132 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
6135 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
6138 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
6139 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
6146 while (types[type][j] >= 0 &&
6147 (used & (1 << types[type][j])) != 0) {
6150 if (types[type][j] >= 0)
6151 use = types[type][j];
6153 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
6154 use = SOUND_MIXER_PCM;
6156 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
6157 use = SOUND_MIXER_SPEAKER;
6167 /* Semi-known names */
6168 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6169 w = hdac_widget_get(devinfo, i);
6170 if (w == NULL || w->enable == 0)
6174 if (w->bindas == -1)
6176 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6178 if (as[w->bindas].dir == HDA_CTL_OUT)
6181 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
6182 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
6183 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
6184 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
6185 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
6188 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
6191 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
6192 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
6199 while (types[type][j] >= 0 &&
6200 (used & (1 << types[type][j])) != 0) {
6203 if (types[type][j] >= 0) {
6204 w->ossdev = types[type][j];
6205 used |= (1 << types[type][j]);
6209 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6210 w = hdac_widget_get(devinfo, i);
6211 if (w == NULL || w->enable == 0)
6215 if (w->bindas == -1)
6217 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6219 if (as[w->bindas].dir == HDA_CTL_OUT)
6222 while (types[6][j] >= 0 &&
6223 (used & (1 << types[6][j])) != 0) {
6226 if (types[6][j] >= 0) {
6227 w->ossdev = types[6][j];
6228 used |= (1 << types[6][j]);
6234 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
6236 struct hdac_audio_as *as = devinfo->function.audio.as;
6239 /* Trace all associations in order of their numbers, */
6240 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
6241 if (as[j].enable == 0)
6244 device_printf(devinfo->codec->sc->dev,
6245 "Tracing association %d (%d)\n", j, as[j].index);
6247 if (as[j].dir == HDA_CTL_OUT) {
6249 res = hdac_audio_trace_as_out(devinfo, j, 0);
6250 if (res == 0 && as[j].hpredir >= 0 &&
6251 as[j].fakeredir == 0) {
6252 /* If codec can't do analog HP redirection
6253 try to make it using one more DAC. */
6254 as[j].fakeredir = 1;
6258 res = hdac_audio_trace_as_in(devinfo, j);
6262 device_printf(devinfo->codec->sc->dev,
6263 "Association %d (%d) trace succeeded\n",
6268 device_printf(devinfo->codec->sc->dev,
6269 "Association %d (%d) trace failed\n",
6276 /* Trace mixer and beeper pseudo associations. */
6277 hdac_audio_trace_as_extra(devinfo);
6281 hdac_audio_assign_mixers(struct hdac_devinfo *devinfo)
6283 struct hdac_audio_as *as = devinfo->function.audio.as;
6284 struct hdac_audio_ctl *ctl;
6285 struct hdac_widget *w, *cw;
6288 /* Assign mixers to the tree. */
6289 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6290 w = hdac_widget_get(devinfo, i);
6291 if (w == NULL || w->enable == 0)
6293 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
6294 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET ||
6295 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6296 as[w->bindas].dir == HDA_CTL_IN)) {
6299 hdac_audio_ctl_source_amp(devinfo, w->nid, -1,
6300 w->ossdev, 1, 0, 1);
6301 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
6302 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1,
6303 SOUND_MIXER_RECLEV, 0, 1);
6304 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6305 as[w->bindas].dir == HDA_CTL_OUT) {
6306 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1,
6307 SOUND_MIXER_VOLUME, 0, 1);
6309 if (w->ossdev == SOUND_MIXER_IMIX) {
6310 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1,
6311 w->ossdev, 1, 0, 1)) {
6312 /* If we are unable to control input monitor
6313 as source - try to control it as destination. */
6314 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1,
6318 if (w->pflags & HDA_ADC_MONITOR) {
6319 for (j = 0; j < w->nconns; j++) {
6320 if (!w->connsenable[j])
6322 cw = hdac_widget_get(devinfo, w->conns[j]);
6323 if (cw == NULL || cw->enable == 0)
6325 if (cw->bindas == -1)
6327 if (cw->bindas >= 0 &&
6328 as[cw->bindas].dir != HDA_CTL_IN)
6330 hdac_audio_ctl_dest_amp(devinfo,
6331 w->nid, j, SOUND_MIXER_IGAIN, 0, 1);
6335 /* Treat unrequired as possible. */
6337 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6338 if (ctl->ossmask == 0)
6339 ctl->ossmask = ctl->possmask;
6344 hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo)
6346 struct hdac_audio_as *as = devinfo->function.audio.as;
6347 struct hdac_widget *w;
6351 for (i = 0; i < devinfo->nodecnt; i++) {
6352 w = &devinfo->widget[i];
6355 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6358 pincap = w->wclass.pin.cap;
6360 /* Disable everything. */
6361 w->wclass.pin.ctrl &= ~(
6362 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
6363 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
6364 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
6365 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
6367 if (w->enable == 0 ||
6368 w->bindas < 0 || as[w->bindas].enable == 0) {
6369 /* Pin is unused so left it disabled. */
6371 } else if (as[w->bindas].dir == HDA_CTL_IN) {
6372 /* Input pin, configure for input. */
6373 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
6374 w->wclass.pin.ctrl |=
6375 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
6377 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
6378 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6379 w->wclass.pin.ctrl |=
6380 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6381 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
6382 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
6383 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6384 w->wclass.pin.ctrl |=
6385 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6386 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
6387 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
6388 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6389 w->wclass.pin.ctrl |=
6390 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6391 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
6393 /* Output pin, configure for output. */
6394 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
6395 w->wclass.pin.ctrl |=
6396 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
6398 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) &&
6399 (w->wclass.pin.config &
6400 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
6401 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
6402 w->wclass.pin.ctrl |=
6403 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
6405 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
6406 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6407 w->wclass.pin.ctrl |=
6408 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6409 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
6410 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
6411 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6412 w->wclass.pin.ctrl |=
6413 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6414 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
6415 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
6416 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6417 w->wclass.pin.ctrl |=
6418 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6419 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
6425 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
6427 struct hdac_audio_ctl *ctl;
6431 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6432 if (ctl->enable == 0 || ctl->ossmask != 0) {
6433 /* Mute disabled and mixer controllable controls.
6434 * Last will be initialized by mixer_init().
6435 * This expected to reduce click on startup. */
6436 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0);
6439 /* Init fixed controls to 0dB amplification. */
6443 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z);
6448 hdac_audio_commit(struct hdac_devinfo *devinfo)
6450 struct hdac_softc *sc = devinfo->codec->sc;
6451 struct hdac_widget *w;
6453 uint32_t gdata, gmask, gdir;
6454 int commitgpio, numgpio;
6457 cad = devinfo->codec->cad;
6459 if (sc->pci_subvendor == APPLE_INTEL_MAC)
6460 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
6463 /* Commit controls. */
6464 hdac_audio_ctl_commit(devinfo);
6466 /* Commit selectors, pins and EAPD. */
6467 for (i = 0; i < devinfo->nodecnt; i++) {
6468 w = &devinfo->widget[i];
6471 if (w->selconn == -1)
6474 hdac_widget_connection_select(w, w->selconn);
6475 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
6477 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
6478 w->wclass.pin.ctrl), cad);
6480 if (w->param.eapdbtl != HDAC_INVALID) {
6483 val = w->param.eapdbtl;
6484 if (devinfo->function.audio.quirks &
6486 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
6488 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
6498 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
6499 devinfo->function.audio.gpio);
6501 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
6502 commitgpio = (numgpio > 0) ? 1 : 0;
6504 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
6505 if (!(devinfo->function.audio.quirks &
6508 if (commitgpio == 0) {
6511 gdata = hdac_command(sc,
6512 HDA_CMD_GET_GPIO_DATA(cad,
6513 devinfo->nid), cad);
6514 gmask = hdac_command(sc,
6515 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
6516 devinfo->nid), cad);
6517 gdir = hdac_command(sc,
6518 HDA_CMD_GET_GPIO_DIRECTION(cad,
6519 devinfo->nid), cad);
6520 device_printf(sc->dev,
6521 "GPIO init: data=0x%08x "
6522 "mask=0x%08x dir=0x%08x\n",
6523 gdata, gmask, gdir);
6535 if (commitgpio != 0) {
6537 device_printf(sc->dev,
6538 "GPIO commit: data=0x%08x mask=0x%08x "
6540 gdata, gmask, gdir);
6543 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
6546 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
6549 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
6555 hdac_powerup(struct hdac_devinfo *devinfo)
6557 struct hdac_softc *sc = devinfo->codec->sc;
6558 nid_t cad = devinfo->codec->cad;
6562 HDA_CMD_SET_POWER_STATE(cad,
6563 devinfo->nid, HDA_CMD_POWER_STATE_D0),
6567 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6569 HDA_CMD_SET_POWER_STATE(cad,
6570 i, HDA_CMD_POWER_STATE_D0),
6577 hdac_pcmchannel_setup(struct hdac_chan *ch)
6579 struct hdac_devinfo *devinfo = ch->devinfo;
6580 struct hdac_audio_as *as = devinfo->function.audio.as;
6581 struct hdac_widget *w;
6582 uint32_t cap, fmtcap, pcmcap;
6583 int i, j, ret, channels, onlystereo;
6586 ch->caps = hdac_caps;
6587 ch->caps.fmtlist = ch->fmtlist;
6590 ch->pcmrates[0] = 48000;
6591 ch->pcmrates[1] = 0;
6597 fmtcap = devinfo->function.audio.supp_stream_formats;
6598 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
6600 for (i = 0; i < 16; i++) {
6601 /* Check as is correct */
6604 /* Cound only present DACs */
6605 if (as[ch->as].dacs[i] <= 0)
6607 /* Ignore duplicates */
6608 for (j = 0; j < ret; j++) {
6609 if (ch->io[j] == as[ch->as].dacs[i])
6615 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]);
6616 if (w == NULL || w->enable == 0)
6618 cap = w->param.supp_stream_formats;
6619 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) &&
6620 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
6622 /* Many CODECs does not declare AC3 support on SPDIF.
6623 I don't beleave that they doesn't support it! */
6624 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6625 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK;
6628 pcmcap = w->param.supp_pcm_size_rate;
6631 pcmcap &= w->param.supp_pcm_size_rate;
6633 ch->io[ret++] = as[ch->as].dacs[i];
6634 /* Do not count redirection pin/dac channels. */
6635 if (i == 15 && as[ch->as].hpredir >= 0)
6637 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1;
6638 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1)
6644 if (as[ch->as].fakeredir)
6646 /* Standard speaks only about stereo pins and playback, ... */
6647 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT)
6649 /* ..., but there it gives us info about speakers layout. */
6650 as[ch->as].pinset = pinset;
6652 ch->supp_stream_formats = fmtcap;
6653 ch->supp_pcm_size_rate = pcmcap;
6664 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) {
6665 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap))
6667 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap))
6669 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap))
6671 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap))
6673 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap))
6675 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) {
6676 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0);
6678 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0);
6680 if (channels >= 2) {
6681 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0);
6683 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0);
6685 if (channels == 4 || /* Any 4-channel */
6686 pinset == 0x0007 || /* 5.1 */
6687 pinset == 0x0013 || /* 5.1 */
6688 pinset == 0x0017) { /* 7.1 */
6689 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0);
6691 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0);
6693 if (channels == 6 || /* Any 6-channel */
6694 pinset == 0x0017) { /* 7.1 */
6695 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1);
6697 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1);
6699 if (channels == 8) { /* Any 8-channel */
6700 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1);
6702 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1);
6705 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) {
6706 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0);
6710 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap))
6711 ch->pcmrates[i++] = 8000;
6712 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap))
6713 ch->pcmrates[i++] = 11025;
6714 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap))
6715 ch->pcmrates[i++] = 16000;
6716 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap))
6717 ch->pcmrates[i++] = 22050;
6718 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap))
6719 ch->pcmrates[i++] = 32000;
6720 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap))
6721 ch->pcmrates[i++] = 44100;
6722 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */
6723 ch->pcmrates[i++] = 48000;
6724 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap))
6725 ch->pcmrates[i++] = 88200;
6726 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap))
6727 ch->pcmrates[i++] = 96000;
6728 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap))
6729 ch->pcmrates[i++] = 176400;
6730 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap))
6731 ch->pcmrates[i++] = 192000;
6732 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */
6733 ch->pcmrates[i] = 0;
6735 ch->caps.minspeed = ch->pcmrates[0];
6736 ch->caps.maxspeed = ch->pcmrates[i - 1];
6744 hdac_create_pcms(struct hdac_devinfo *devinfo)
6746 struct hdac_softc *sc = devinfo->codec->sc;
6747 struct hdac_audio_as *as = devinfo->function.audio.as;
6748 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0;
6750 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
6751 if (as[i].enable == 0)
6753 if (as[i].dir == HDA_CTL_IN) {
6765 devinfo->function.audio.num_devs =
6766 max(ardev, apdev) + max(drdev, dpdev);
6767 devinfo->function.audio.devs =
6768 (struct hdac_pcm_devinfo *)malloc(
6769 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo),
6770 M_HDAC, M_ZERO | M_NOWAIT);
6771 if (devinfo->function.audio.devs == NULL) {
6772 device_printf(sc->dev,
6773 "Unable to allocate memory for devices\n");
6776 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
6777 devinfo->function.audio.devs[i].index = i;
6778 devinfo->function.audio.devs[i].devinfo = devinfo;
6779 devinfo->function.audio.devs[i].play = -1;
6780 devinfo->function.audio.devs[i].rec = -1;
6781 devinfo->function.audio.devs[i].digital = 255;
6783 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
6784 if (as[i].enable == 0)
6786 for (j = 0; j < devinfo->function.audio.num_devs; j++) {
6787 if (devinfo->function.audio.devs[j].digital != 255 &&
6788 (!devinfo->function.audio.devs[j].digital) !=
6791 if (as[i].dir == HDA_CTL_IN) {
6792 if (devinfo->function.audio.devs[j].rec >= 0)
6794 devinfo->function.audio.devs[j].rec
6797 if (devinfo->function.audio.devs[j].play >= 0)
6799 devinfo->function.audio.devs[j].play
6802 sc->chans[as[i].chan].pdevinfo =
6803 &devinfo->function.audio.devs[j];
6804 devinfo->function.audio.devs[j].digital =
6809 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
6810 struct hdac_pcm_devinfo *pdevinfo =
6811 &devinfo->function.audio.devs[i];
6813 device_add_child(sc->dev, "pcm", -1);
6814 device_set_ivars(pdevinfo->dev,
6820 hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag)
6822 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
6823 struct hdac_audio_ctl *ctl;
6824 struct hdac_softc *sc = devinfo->codec->sc;
6829 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM |
6830 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
6831 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IGAIN |
6832 SOUND_MASK_OGAIN | SOUND_MASK_IMIX | SOUND_MASK_MONITOR);
6835 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) {
6836 if ((flag & (1 << j)) == 0)
6840 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6841 if (ctl->enable == 0 ||
6842 ctl->widget->enable == 0)
6844 if (!((pdevinfo->play >= 0 &&
6845 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
6846 (pdevinfo->rec >= 0 &&
6847 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
6848 (ctl->widget->bindas == -2 && pdevinfo->index == 0)))
6850 if ((ctl->ossmask & (1 << j)) == 0)
6854 device_printf(pdevinfo->dev, "\n");
6855 if (banner != NULL) {
6856 device_printf(pdevinfo->dev, "%s", banner);
6858 device_printf(pdevinfo->dev, "Unknown Ctl");
6860 printf(" (OSS: %s)\n",
6861 hdac_audio_ctl_ossmixer_mask2allname(1 << j,
6863 device_printf(pdevinfo->dev, " |\n");
6866 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i,
6868 (ctl->ndir == HDA_CTL_IN)?"in ":"out");
6869 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir)
6870 printf(" %2d): ", ctl->index);
6873 if (ctl->step > 0) {
6874 printf("%+d/%+ddB (%d steps)%s\n",
6875 (0 - ctl->offset) * (ctl->size + 1) / 4,
6876 (ctl->step - ctl->offset) * (ctl->size + 1) / 4,
6878 ctl->mute?" + mute":"");
6880 printf("%s\n", ctl->mute?"mute":"");
6886 hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap)
6892 device_printf(dev, " Stream cap: 0x%08x\n", cap);
6893 device_printf(dev, " ");
6894 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
6896 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
6898 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
6904 device_printf(dev, " PCM cap: 0x%08x\n", cap);
6905 device_printf(dev, " ");
6906 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
6908 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
6910 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
6912 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
6914 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
6917 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
6919 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
6921 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
6923 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
6925 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
6927 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
6930 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
6932 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
6934 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
6936 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
6943 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
6947 pincap = w->wclass.pin.cap;
6949 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
6950 device_printf(sc->dev, " ");
6951 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
6953 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
6955 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
6957 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
6959 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
6961 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
6963 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
6965 if (HDA_PARAM_PIN_CAP_HDMI(pincap))
6967 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
6969 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6971 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6973 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6975 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
6977 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
6981 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
6983 if (HDA_PARAM_PIN_CAP_DP(pincap))
6985 if (HDA_PARAM_PIN_CAP_HBR(pincap))
6988 device_printf(sc->dev, " Pin config: 0x%08x\n",
6989 w->wclass.pin.config);
6990 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
6991 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
6993 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
6995 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
6997 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK)
7003 hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf)
7005 struct hdac_softc *sc = w->devinfo->codec->sc;
7007 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s "
7008 "jack %2d loc %2d color %7s misc %d%s\n",
7010 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf),
7011 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf),
7012 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)],
7013 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)],
7014 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf),
7015 HDA_CONFIG_DEFAULTCONF_LOCATION(conf),
7016 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)],
7017 HDA_CONFIG_DEFAULTCONF_MISC(conf),
7018 (w->enable == 0)?" [DISABLED]":"");
7022 hdac_dump_pin_configs(struct hdac_devinfo *devinfo)
7024 struct hdac_widget *w;
7027 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7028 w = hdac_widget_get(devinfo, i);
7031 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
7033 hdac_dump_pin_config(w, w->wclass.pin.config);
7038 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
7040 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
7041 device_printf(sc->dev, " "
7042 "mute=%d step=%d size=%d offset=%d\n",
7043 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
7044 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
7045 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
7046 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
7050 hdac_dump_nodes(struct hdac_devinfo *devinfo)
7052 struct hdac_softc *sc = devinfo->codec->sc;
7053 static char *ossname[] = SOUND_DEVICE_NAMES;
7054 struct hdac_widget *w, *cw;
7058 device_printf(sc->dev, "\n");
7059 device_printf(sc->dev, "Default Parameter\n");
7060 device_printf(sc->dev, "-----------------\n");
7061 hdac_dump_audio_formats(sc->dev,
7062 devinfo->function.audio.supp_stream_formats,
7063 devinfo->function.audio.supp_pcm_size_rate);
7064 device_printf(sc->dev, " IN amp: 0x%08x\n",
7065 devinfo->function.audio.inamp_cap);
7066 device_printf(sc->dev, " OUT amp: 0x%08x\n",
7067 devinfo->function.audio.outamp_cap);
7068 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7069 w = hdac_widget_get(devinfo, i);
7071 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
7074 device_printf(sc->dev, "\n");
7075 device_printf(sc->dev, " nid: %d%s\n", w->nid,
7076 (w->enable == 0) ? " [DISABLED]" : "");
7077 device_printf(sc->dev, " Name: %s\n", w->name);
7078 device_printf(sc->dev, " Widget cap: 0x%08x\n",
7079 w->param.widget_cap);
7080 if (w->param.widget_cap & 0x0ee1) {
7081 device_printf(sc->dev, " ");
7082 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap))
7084 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap))
7086 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
7088 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
7090 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap))
7092 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap))
7094 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap);
7098 printf(" %dCH", j + 1);
7101 if (w->bindas != -1) {
7102 device_printf(sc->dev, " Association: %d (0x%08x)\n",
7103 w->bindas, w->bindseqmask);
7105 if (w->ossmask != 0 || w->ossdev >= 0) {
7106 device_printf(sc->dev, " OSS: %s",
7107 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf)));
7109 printf(" (%s)", ossname[w->ossdev]);
7112 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
7113 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
7114 hdac_dump_audio_formats(sc->dev,
7115 w->param.supp_stream_formats,
7116 w->param.supp_pcm_size_rate);
7117 } else if (w->type ==
7118 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
7119 hdac_dump_pin(sc, w);
7120 if (w->param.eapdbtl != HDAC_INVALID)
7121 device_printf(sc->dev, " EAPD: 0x%08x\n",
7123 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
7124 w->param.outamp_cap != 0)
7125 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
7126 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
7127 w->param.inamp_cap != 0)
7128 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
7129 if (w->nconns > 0) {
7130 device_printf(sc->dev, " connections: %d\n", w->nconns);
7131 device_printf(sc->dev, " |\n");
7133 for (j = 0; j < w->nconns; j++) {
7134 cw = hdac_widget_get(devinfo, w->conns[j]);
7135 device_printf(sc->dev, " + %s<- nid=%d [%s]",
7136 (w->connsenable[j] == 0)?"[DISABLED] ":"",
7137 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
7139 printf(" [UNKNOWN]");
7140 else if (cw->enable == 0)
7141 printf(" [DISABLED]");
7142 if (w->nconns > 1 && w->selconn == j && w->type !=
7143 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
7144 printf(" (selected)");
7152 hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth)
7154 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7155 struct hdac_widget *w, *cw;
7159 if (depth > HDA_PARSE_MAXDEPTH)
7162 w = hdac_widget_get(devinfo, nid);
7163 if (w == NULL || w->enable == 0)
7167 device_printf(pdevinfo->dev, "%*s", 4, "");
7169 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, "");
7170 printf("nid=%d [%s]", w->nid, w->name);
7173 if (w->ossmask == 0) {
7177 printf(" [src: %s]",
7178 hdac_audio_ctl_ossmixer_mask2allname(
7179 w->ossmask, buf, sizeof(buf)));
7180 if (w->ossdev >= 0) {
7187 for (i = 0; i < w->nconns; i++) {
7188 if (w->connsenable[i] == 0)
7190 cw = hdac_widget_get(devinfo, w->conns[i]);
7191 if (cw == NULL || cw->enable == 0 || cw->bindas == -1)
7194 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, "");
7197 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1);
7203 hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo)
7205 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7206 struct hdac_softc *sc = devinfo->codec->sc;
7207 struct hdac_audio_as *as;
7208 struct hdac_widget *w;
7211 if (pdevinfo->play < 0)
7214 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as];
7215 for (i = 0; i < 16; i++) {
7216 if (as->pins[i] <= 0)
7218 w = hdac_widget_get(devinfo, as->pins[i]);
7219 if (w == NULL || w->enable == 0)
7223 device_printf(pdevinfo->dev, "\n");
7224 device_printf(pdevinfo->dev, "Playback:\n");
7226 device_printf(pdevinfo->dev, "\n");
7227 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0);
7232 hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo)
7234 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7235 struct hdac_softc *sc = devinfo->codec->sc;
7236 struct hdac_widget *w;
7240 if (pdevinfo->rec < 0)
7243 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7244 w = hdac_widget_get(devinfo, i);
7245 if (w == NULL || w->enable == 0)
7247 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
7249 if (w->bindas != sc->chans[pdevinfo->rec].as)
7253 device_printf(pdevinfo->dev, "\n");
7254 device_printf(pdevinfo->dev, "Record:\n");
7256 device_printf(pdevinfo->dev, "\n");
7257 hdac_dump_dst_nid(pdevinfo, i, 0);
7262 hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo)
7264 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7265 struct hdac_widget *w;
7269 if (pdevinfo->index != 0)
7272 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7273 w = hdac_widget_get(devinfo, i);
7274 if (w == NULL || w->enable == 0)
7276 if (w->ossdev != SOUND_MIXER_IMIX)
7280 device_printf(pdevinfo->dev, "\n");
7281 device_printf(pdevinfo->dev, "Input Mix:\n");
7283 device_printf(pdevinfo->dev, "\n");
7284 hdac_dump_dst_nid(pdevinfo, i, 0);
7289 hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo)
7291 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc;
7295 if (pdevinfo->play >= 0) {
7297 device_printf(pdevinfo->dev, "\n");
7298 device_printf(pdevinfo->dev, "Playback:\n");
7299 device_printf(pdevinfo->dev, "\n");
7300 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats,
7301 sc->chans[i].supp_pcm_size_rate);
7302 device_printf(pdevinfo->dev, " DAC:");
7303 for (nids = sc->chans[i].io; *nids != -1; nids++)
7304 printf(" %d", *nids);
7307 if (pdevinfo->rec >= 0) {
7309 device_printf(pdevinfo->dev, "\n");
7310 device_printf(pdevinfo->dev, "Record:\n");
7311 device_printf(pdevinfo->dev, "\n");
7312 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats,
7313 sc->chans[i].supp_pcm_size_rate);
7314 device_printf(pdevinfo->dev, " ADC:");
7315 for (nids = sc->chans[i].io; *nids != -1; nids++)
7316 printf(" %d", *nids);
7322 hdac_release_resources(struct hdac_softc *sc)
7332 callout_stop(&sc->poll_hda);
7333 callout_stop(&sc->poll_hdac);
7334 callout_stop(&sc->poll_jack);
7337 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7338 callout_drain(&sc->poll_hda);
7339 callout_drain(&sc->poll_hdac);
7340 callout_drain(&sc->poll_jack);
7344 for (i = 0; i < HDAC_CODEC_MAX; i++) {
7345 if (sc->codecs[i] == NULL)
7347 for (j = 0; j < sc->codecs[i]->num_fgs; j++) {
7348 free(sc->codecs[i]->fgs[j].widget, M_HDAC);
7349 if (sc->codecs[i]->fgs[j].node_type ==
7350 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
7351 free(sc->codecs[i]->fgs[j].function.audio.ctl,
7353 free(sc->codecs[i]->fgs[j].function.audio.as,
7355 free(sc->codecs[i]->fgs[j].function.audio.devs,
7359 free(sc->codecs[i]->fgs, M_HDAC);
7360 free(sc->codecs[i], M_HDAC);
7361 sc->codecs[i] = NULL;
7364 hdac_dma_free(sc, &sc->pos_dma);
7365 hdac_dma_free(sc, &sc->rirb_dma);
7366 hdac_dma_free(sc, &sc->corb_dma);
7367 for (i = 0; i < sc->num_chans; i++) {
7368 if (sc->chans[i].blkcnt > 0)
7369 hdac_dma_free(sc, &sc->chans[i].bdl_dma);
7371 free(sc->chans, M_HDAC);
7372 if (sc->chan_dmat != NULL) {
7373 bus_dma_tag_destroy(sc->chan_dmat);
7374 sc->chan_dmat = NULL;
7377 snd_mtxfree(sc->lock);
7380 /* This function surely going to make its way into upper level someday. */
7382 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
7384 const char *res = NULL;
7385 int i = 0, j, k, len, inv;
7393 if (resource_string_value(device_get_name(sc->dev),
7394 device_get_unit(sc->dev), "config", &res) != 0)
7396 if (!(res != NULL && strlen(res) > 0))
7399 device_printf(sc->dev, "HDA Config:");
7402 while (res[i] != '\0' &&
7403 (res[i] == ',' || isspace(res[i]) != 0))
7405 if (res[i] == '\0') {
7412 while (res[j] != '\0' &&
7413 !(res[j] == ',' || isspace(res[j]) != 0))
7416 if (len > 2 && strncmp(res + i, "no", 2) == 0)
7420 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
7421 if (strncmp(res + i + inv,
7422 hdac_quirks_tab[k].key, len - inv) != 0)
7424 if (len - inv != strlen(hdac_quirks_tab[k].key))
7427 printf(" %s%s", (inv != 0) ? "no" : "",
7428 hdac_quirks_tab[k].key);
7430 if (inv == 0 && on != NULL)
7431 *on |= hdac_quirks_tab[k].value;
7432 else if (inv != 0 && off != NULL)
7433 *off |= hdac_quirks_tab[k].value;
7441 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
7443 struct hdac_softc *sc;
7448 dev = oidp->oid_arg1;
7449 sc = device_get_softc(dev);
7455 err = sysctl_handle_int(oidp, &val, 0, req);
7457 if (err != 0 || req->newptr == NULL)
7459 if (val < 0 || val > 1)
7463 if (val != sc->polling) {
7465 callout_stop(&sc->poll_hda);
7466 callout_stop(&sc->poll_hdac);
7468 callout_drain(&sc->poll_hda);
7469 callout_drain(&sc->poll_hdac);
7472 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
7473 ctl |= HDAC_INTCTL_GIE;
7474 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
7476 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
7477 ctl &= ~HDAC_INTCTL_GIE;
7478 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
7480 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7483 hdac_poll_reinit(sc);
7484 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
7493 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
7495 struct hdac_softc *sc;
7499 dev = oidp->oid_arg1;
7500 sc = device_get_softc(dev);
7504 val = ((uint64_t)sc->poll_ival * 1000) / hz;
7506 err = sysctl_handle_int(oidp, &val, 0, req);
7508 if (err != 0 || req->newptr == NULL)
7515 val = ((uint64_t)val * hz) / 1000;
7522 sc->poll_ival = val;
7529 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
7531 struct hdac_softc *sc;
7532 struct hdac_codec *codec;
7533 struct hdac_devinfo *devinfo;
7534 struct hdac_widget *w;
7536 uint32_t res, pincap, delay;
7537 int codec_index, fg_index;
7541 dev = oidp->oid_arg1;
7542 sc = device_get_softc(dev);
7546 err = sysctl_handle_int(oidp, &val, 0, req);
7547 if (err != 0 || req->newptr == NULL || val == 0)
7550 /* XXX: Temporary. For debugging. */
7554 } else if (val == 101) {
7560 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7561 codec = sc->codecs[codec_index];
7565 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7566 devinfo = &codec->fgs[fg_index];
7567 if (devinfo->node_type !=
7568 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
7571 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n",
7572 codec_index, devinfo->nid);
7573 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7574 w = hdac_widget_get(devinfo, i);
7575 if (w == NULL || w->type !=
7576 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
7578 hdac_dump_pin_config(w, w->wclass.pin.config);
7579 pincap = w->wclass.pin.cap;
7580 device_printf(dev, " Caps: %2s %3s %2s %4s %4s",
7581 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"",
7582 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"",
7583 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"",
7584 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"",
7585 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":"");
7586 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) ||
7587 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) {
7588 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) {
7591 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad);
7593 res = hdac_command(sc,
7594 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
7595 if (res != 0x7fffffff && res != 0xffffffff)
7598 } while (++delay < 10000);
7601 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad,
7604 printf(" Sense: 0x%08x", res);
7606 printf(" delay %dus", delay * 10);
7611 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
7612 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
7613 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
7614 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
7615 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
7616 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
7617 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
7618 device_printf(dev, " GPI:");
7619 res = hdac_command(sc,
7620 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
7621 printf(" data=0x%08x", res);
7622 res = hdac_command(sc,
7623 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
7625 printf(" wake=0x%08x", res);
7626 res = hdac_command(sc,
7627 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
7629 printf(" unsol=0x%08x", res);
7630 res = hdac_command(sc,
7631 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
7632 printf(" sticky=0x%08x\n", res);
7634 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
7635 device_printf(dev, " GPO:");
7636 res = hdac_command(sc,
7637 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
7638 printf(" data=0x%08x\n", res);
7640 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
7641 device_printf(dev, "GPIO:");
7642 res = hdac_command(sc,
7643 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
7644 printf(" data=0x%08x", res);
7645 res = hdac_command(sc,
7646 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
7647 printf(" enable=0x%08x", res);
7648 res = hdac_command(sc,
7649 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
7650 printf(" direction=0x%08x\n", res);
7651 res = hdac_command(sc,
7652 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
7653 device_printf(dev, " wake=0x%08x", res);
7654 res = hdac_command(sc,
7655 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
7657 printf(" unsol=0x%08x", res);
7658 res = hdac_command(sc,
7659 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
7660 printf(" sticky=0x%08x\n", res);
7669 hdac_attach2(void *arg)
7671 struct hdac_codec *codec;
7672 struct hdac_softc *sc;
7673 struct hdac_audio_ctl *ctl;
7674 uint32_t quirks_on, quirks_off;
7675 int codec_index, fg_index;
7676 int i, dmaalloc = 0;
7677 struct hdac_devinfo *devinfo;
7679 sc = (struct hdac_softc *)arg;
7681 hdac_config_fetch(sc, &quirks_on, &quirks_off);
7684 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n",
7685 quirks_on, quirks_off);
7690 /* Remove ourselves from the config hooks */
7691 if (sc->intrhook.ich_func != NULL) {
7692 config_intrhook_disestablish(&sc->intrhook);
7693 sc->intrhook.ich_func = NULL;
7696 /* Start the corb and rirb engines */
7698 device_printf(sc->dev, "Starting CORB Engine...\n");
7700 hdac_corb_start(sc);
7702 device_printf(sc->dev, "Starting RIRB Engine...\n");
7704 hdac_rirb_start(sc);
7707 device_printf(sc->dev,
7708 "Enabling controller interrupt...\n");
7710 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
7712 if (sc->polling == 0) {
7713 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
7714 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
7716 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
7721 device_printf(sc->dev,
7722 "Scanning HDA codecs ...\n");
7724 hdac_scan_codecs(sc);
7726 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7727 codec = sc->codecs[codec_index];
7730 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7731 devinfo = &codec->fgs[fg_index];
7733 device_printf(sc->dev, "\n");
7734 device_printf(sc->dev,
7735 "Processing %s FG cad=%d nid=%d...\n",
7736 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio":
7737 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem":
7739 devinfo->codec->cad, devinfo->nid);
7741 if (devinfo->node_type !=
7742 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
7744 device_printf(sc->dev,
7745 "Powering down...\n");
7748 HDA_CMD_SET_POWER_STATE(codec->cad,
7749 devinfo->nid, HDA_CMD_POWER_STATE_D3),
7755 device_printf(sc->dev, "Powering up...\n");
7757 hdac_powerup(devinfo);
7759 device_printf(sc->dev, "Parsing audio FG...\n");
7761 hdac_audio_parse(devinfo);
7763 device_printf(sc->dev, "Parsing Ctls...\n");
7765 hdac_audio_ctl_parse(devinfo);
7767 device_printf(sc->dev, "Parsing vendor patch...\n");
7769 hdac_vendor_patch_parse(devinfo);
7770 devinfo->function.audio.quirks |= quirks_on;
7771 devinfo->function.audio.quirks &= ~quirks_off;
7774 device_printf(sc->dev, "Disabling nonaudio...\n");
7776 hdac_audio_disable_nonaudio(devinfo);
7778 device_printf(sc->dev, "Disabling useless...\n");
7780 hdac_audio_disable_useless(devinfo);
7782 device_printf(sc->dev, "Patched pins configuration:\n");
7783 hdac_dump_pin_configs(devinfo);
7786 device_printf(sc->dev, "Parsing pin associations...\n");
7788 hdac_audio_as_parse(devinfo);
7790 device_printf(sc->dev, "Building AFG tree...\n");
7792 hdac_audio_build_tree(devinfo);
7794 device_printf(sc->dev, "Disabling unassociated "
7797 hdac_audio_disable_unas(devinfo);
7799 device_printf(sc->dev, "Disabling nonselected "
7802 hdac_audio_disable_notselected(devinfo);
7804 device_printf(sc->dev, "Disabling useless...\n");
7806 hdac_audio_disable_useless(devinfo);
7808 device_printf(sc->dev, "Disabling "
7809 "crossassociatement connections...\n");
7811 hdac_audio_disable_crossas(devinfo);
7813 device_printf(sc->dev, "Disabling useless...\n");
7815 hdac_audio_disable_useless(devinfo);
7817 device_printf(sc->dev, "Binding associations to channels...\n");
7819 hdac_audio_bind_as(devinfo);
7821 device_printf(sc->dev, "Assigning names to signal sources...\n");
7823 hdac_audio_assign_names(devinfo);
7825 device_printf(sc->dev, "Assigning mixers to the tree...\n");
7827 hdac_audio_assign_mixers(devinfo);
7829 device_printf(sc->dev, "Preparing pin controls...\n");
7831 hdac_audio_prepare_pin_ctrl(devinfo);
7833 device_printf(sc->dev, "AFG commit...\n");
7835 hdac_audio_commit(devinfo);
7837 device_printf(sc->dev, "HP switch init...\n");
7839 hdac_hp_switch_init(devinfo);
7841 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
7843 if (hdac_dma_alloc(sc, &sc->pos_dma,
7844 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
7846 device_printf(sc->dev, "Failed to "
7847 "allocate DMA pos buffer "
7855 device_printf(sc->dev, "Creating PCM devices...\n");
7857 hdac_create_pcms(devinfo);
7860 if (devinfo->function.audio.quirks != 0) {
7861 device_printf(sc->dev, "FG config/quirks:");
7862 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
7863 if ((devinfo->function.audio.quirks &
7864 hdac_quirks_tab[i].value) ==
7865 hdac_quirks_tab[i].value)
7866 printf(" %s", hdac_quirks_tab[i].key);
7871 device_printf(sc->dev, "\n");
7872 device_printf(sc->dev, "+-------------------+\n");
7873 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
7874 device_printf(sc->dev, "+-------------------+\n");
7875 hdac_dump_nodes(devinfo);
7879 device_printf(sc->dev, "\n");
7880 device_printf(sc->dev, "+------------------------+\n");
7881 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
7882 device_printf(sc->dev, "+------------------------+\n");
7883 device_printf(sc->dev, "\n");
7885 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
7886 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i,
7887 (ctl->widget != NULL) ? ctl->widget->nid : -1,
7888 (ctl->ndir == HDA_CTL_IN)?"in ":"out",
7889 (ctl->dir == HDA_CTL_IN)?"in ":"out",
7891 if (ctl->childwidget != NULL)
7892 printf(" cnid %3d", ctl->childwidget->nid);
7895 printf(" ossmask=0x%08x\n",
7897 device_printf(sc->dev,
7898 " mute: %d step: %3d size: %3d off: %3d%s\n",
7899 ctl->mute, ctl->step, ctl->size, ctl->offset,
7900 (ctl->enable == 0) ? " [DISABLED]" :
7901 ((ctl->ossmask == 0) ? " [UNUSED]" : ""));
7909 device_printf(sc->dev, "\n");
7912 bus_generic_attach(sc->dev);
7914 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7915 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7916 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
7917 sysctl_hdac_polling, "I", "Enable polling mode");
7918 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7919 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7920 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
7921 sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
7922 "Controller/Jack Sense polling interval (1-1000 ms)");
7923 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7924 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7925 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
7926 sysctl_hdac_pindump, "I", "Dump pin states/data");
7929 /****************************************************************************
7930 * int hdac_suspend(device_t)
7932 * Suspend and power down HDA bus and codecs.
7933 ****************************************************************************/
7935 hdac_suspend(device_t dev)
7937 struct hdac_softc *sc;
7938 struct hdac_codec *codec;
7939 struct hdac_devinfo *devinfo;
7940 int codec_index, fg_index, i;
7943 device_printf(dev, "Suspend...\n");
7946 sc = device_get_softc(dev);
7950 device_printf(dev, "Stop streams...\n");
7952 for (i = 0; i < sc->num_chans; i++) {
7953 if (sc->chans[i].flags & HDAC_CHN_RUNNING) {
7954 sc->chans[i].flags |= HDAC_CHN_SUSPEND;
7955 hdac_channel_stop(sc, &sc->chans[i]);
7959 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7960 codec = sc->codecs[codec_index];
7963 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7964 devinfo = &codec->fgs[fg_index];
7968 " cad=%d nid=%d to the D3 state...\n",
7969 codec->cad, devinfo->nid);
7972 HDA_CMD_SET_POWER_STATE(codec->cad,
7973 devinfo->nid, HDA_CMD_POWER_STATE_D3),
7979 device_printf(dev, "Reset controller...\n");
7981 callout_stop(&sc->poll_hda);
7982 callout_stop(&sc->poll_hdac);
7983 callout_stop(&sc->poll_jack);
7986 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7987 callout_drain(&sc->poll_hda);
7988 callout_drain(&sc->poll_hdac);
7989 callout_drain(&sc->poll_jack);
7992 device_printf(dev, "Suspend done\n");
7998 /****************************************************************************
7999 * int hdac_resume(device_t)
8001 * Powerup and restore HDA bus and codecs state.
8002 ****************************************************************************/
8004 hdac_resume(device_t dev)
8006 struct hdac_softc *sc;
8007 struct hdac_codec *codec;
8008 struct hdac_devinfo *devinfo;
8009 int codec_index, fg_index, i;
8012 device_printf(dev, "Resume...\n");
8015 sc = device_get_softc(dev);
8018 /* Quiesce everything */
8020 device_printf(dev, "Reset controller...\n");
8024 /* Initialize the CORB and RIRB */
8028 /* Start the corb and rirb engines */
8030 device_printf(dev, "Starting CORB Engine...\n");
8032 hdac_corb_start(sc);
8034 device_printf(dev, "Starting RIRB Engine...\n");
8036 hdac_rirb_start(sc);
8040 "Enabling controller interrupt...\n");
8042 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
8044 if (sc->polling == 0) {
8045 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
8046 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
8048 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
8052 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
8053 codec = sc->codecs[codec_index];
8056 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
8057 devinfo = &codec->fgs[fg_index];
8058 if (devinfo->node_type !=
8059 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
8062 "Power down unsupported non-audio FG"
8063 " cad=%d nid=%d to the D3 state...\n",
8064 codec->cad, devinfo->nid);
8067 HDA_CMD_SET_POWER_STATE(codec->cad,
8068 devinfo->nid, HDA_CMD_POWER_STATE_D3),
8075 "Power up audio FG cad=%d nid=%d...\n",
8076 devinfo->codec->cad, devinfo->nid);
8078 hdac_powerup(devinfo);
8080 device_printf(dev, "AFG commit...\n");
8082 hdac_audio_commit(devinfo);
8084 device_printf(dev, "HP switch init...\n");
8086 hdac_hp_switch_init(devinfo);
8089 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
8090 struct hdac_pcm_devinfo *pdevinfo =
8091 &devinfo->function.audio.devs[i];
8093 device_printf(pdevinfo->dev,
8094 "OSS mixer reinitialization...\n");
8096 if (mixer_reinit(pdevinfo->dev) == -1)
8097 device_printf(pdevinfo->dev,
8098 "unable to reinitialize the mixer\n");
8105 device_printf(dev, "Start streams...\n");
8107 for (i = 0; i < sc->num_chans; i++) {
8108 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) {
8109 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND;
8110 hdac_channel_start(sc, &sc->chans[i]);
8117 device_printf(dev, "Resume done\n");
8122 /****************************************************************************
8123 * int hdac_detach(device_t)
8125 * Detach and free up resources utilized by the hdac device.
8126 ****************************************************************************/
8128 hdac_detach(device_t dev)
8130 struct hdac_softc *sc;
8132 int i, devcount, error;
8134 if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
8136 for (i = 0; i < devcount; i++) {
8137 if ((error = device_delete_child(dev, devlist[i])) != 0) {
8138 free(devlist, M_TEMP);
8142 free(devlist, M_TEMP);
8144 sc = device_get_softc(dev);
8145 hdac_release_resources(sc);
8151 hdac_print_child(device_t dev, device_t child)
8153 struct hdac_pcm_devinfo *pdevinfo =
8154 (struct hdac_pcm_devinfo *)device_get_ivars(child);
8157 retval = bus_print_child_header(dev, child);
8158 retval += printf(" at cad %d nid %d",
8159 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid);
8160 retval += bus_print_child_footer(dev, child);
8165 static device_method_t hdac_methods[] = {
8166 /* device interface */
8167 DEVMETHOD(device_probe, hdac_probe),
8168 DEVMETHOD(device_attach, hdac_attach),
8169 DEVMETHOD(device_detach, hdac_detach),
8170 DEVMETHOD(device_suspend, hdac_suspend),
8171 DEVMETHOD(device_resume, hdac_resume),
8173 DEVMETHOD(bus_print_child, hdac_print_child),
8177 static driver_t hdac_driver = {
8180 sizeof(struct hdac_softc),
8183 static devclass_t hdac_devclass;
8185 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0);
8186 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
8187 MODULE_VERSION(snd_hda, 1);
8190 hdac_pcm_probe(device_t dev)
8192 struct hdac_pcm_devinfo *pdevinfo =
8193 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
8196 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s",
8197 hdac_codec_name(pdevinfo->devinfo->codec),
8199 (pdevinfo->digital == 3)?"DisplayPort":
8200 ((pdevinfo->digital == 2)?"HDMI":
8201 ((pdevinfo->digital)?"Digital":"Analog")));
8202 device_set_desc_copy(dev, buf);
8207 hdac_pcm_attach(device_t dev)
8209 struct hdac_pcm_devinfo *pdevinfo =
8210 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
8211 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc;
8212 char status[SND_STATUSLEN];
8215 pdevinfo->chan_size = pcm_getbuffersize(dev,
8216 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
8219 device_printf(dev, "+--------------------------------------+\n");
8220 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n");
8221 device_printf(dev, "+--------------------------------------+\n");
8222 hdac_dump_pcmchannels(pdevinfo);
8223 device_printf(dev, "\n");
8224 device_printf(dev, "+-------------------------------+\n");
8225 device_printf(dev, "| DUMPING Playback/Record Paths |\n");
8226 device_printf(dev, "+-------------------------------+\n");
8227 hdac_dump_dac(pdevinfo);
8228 hdac_dump_adc(pdevinfo);
8229 hdac_dump_mix(pdevinfo);
8230 device_printf(dev, "\n");
8231 device_printf(dev, "+-------------------------+\n");
8232 device_printf(dev, "| DUMPING Volume Controls |\n");
8233 device_printf(dev, "+-------------------------+\n");
8234 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME);
8235 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM);
8236 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD);
8237 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC);
8238 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR);
8239 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE);
8240 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER);
8241 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV);
8242 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX);
8243 hdac_dump_ctls(pdevinfo, "Input Monitoring Level", SOUND_MASK_IGAIN);
8244 hdac_dump_ctls(pdevinfo, NULL, 0);
8245 device_printf(dev, "\n");
8248 if (resource_int_value(device_get_name(dev),
8249 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
8251 if (i < HDA_BLK_MIN)
8253 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i;
8255 while (pdevinfo->chan_blkcnt >> i)
8257 pdevinfo->chan_blkcnt = 1 << (i - 1);
8258 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN)
8259 pdevinfo->chan_blkcnt = HDA_BDL_MIN;
8260 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX)
8261 pdevinfo->chan_blkcnt = HDA_BDL_MAX;
8263 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT;
8266 * We don't register interrupt handler with snd_setup_intr
8267 * in pcm device. Mark pcm device as MPSAFE manually.
8269 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
8272 device_printf(dev, "OSS mixer initialization...\n");
8274 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0)
8275 device_printf(dev, "Can't register mixer\n");
8278 device_printf(dev, "Registering PCM channels...\n");
8280 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0,
8281 (pdevinfo->rec >= 0)?1:0) != 0)
8282 device_printf(dev, "Can't register PCM\n");
8284 pdevinfo->registered++;
8286 if (pdevinfo->play >= 0)
8287 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo);
8288 if (pdevinfo->rec >= 0)
8289 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo);
8291 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s",
8292 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid,
8293 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda));
8294 pcm_setstatus(dev, status);
8300 hdac_pcm_detach(device_t dev)
8302 struct hdac_pcm_devinfo *pdevinfo =
8303 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
8306 if (pdevinfo->registered > 0) {
8307 err = pcm_unregister(dev);
8315 static device_method_t hdac_pcm_methods[] = {
8316 /* device interface */
8317 DEVMETHOD(device_probe, hdac_pcm_probe),
8318 DEVMETHOD(device_attach, hdac_pcm_attach),
8319 DEVMETHOD(device_detach, hdac_pcm_detach),
8323 static driver_t hdac_pcm_driver = {
8329 DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0);
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