2 * Copyright (c) 2002 Myson Technology Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $
29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.28 2007/03/11 03:46:48 swildner Exp $
31 * Myson fast ethernet PCI NIC driver
33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
44 #include <sys/module.h>
45 #include <sys/serialize.h>
49 #include <sys/thread2.h>
52 #include <net/ifq_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_media.h>
56 #include <net/if_dl.h>
59 #include <vm/vm.h> /* for vtophys */
60 #include <vm/pmap.h> /* for vtophys */
61 #include <machine/clock.h> /* for DELAY */
63 #include <bus/pci/pcireg.h>
64 #include <bus/pci/pcivar.h>
67 * #define MY_USEIOSPACE
70 static int MY_USEIOSPACE = 1;
73 #define MY_RES SYS_RES_IOPORT
74 #define MY_RID MY_PCI_LOIO
76 #define MY_RES SYS_RES_MEMORY
77 #define MY_RID MY_PCI_LOMEM
84 * Various supported device vendors/types and their names.
86 static struct my_type my_devs[] = {
87 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
88 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
89 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
94 * Various supported PHY vendors/types and their names. Note that this driver
95 * will work with pretty much any MII-compliant PHY, so failure to positively
96 * identify the chip is not a fatal error.
98 static struct my_type my_phys[] = {
99 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
100 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
101 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
102 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
103 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
104 {0, 0, "<MII-compliant physical interface>"}
107 static int my_probe(device_t);
108 static int my_attach(device_t);
109 static int my_detach(device_t);
110 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
111 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
112 static void my_rxeof(struct my_softc *);
113 static void my_txeof(struct my_softc *);
114 static void my_txeoc(struct my_softc *);
115 static void my_intr(void *);
116 static void my_start(struct ifnet *);
117 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
118 static void my_init(void *);
119 static void my_stop(struct my_softc *);
120 static void my_watchdog(struct ifnet *);
121 static void my_shutdown(device_t);
122 static int my_ifmedia_upd(struct ifnet *);
123 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
124 static u_int16_t my_phy_readreg(struct my_softc *, int);
125 static void my_phy_writereg(struct my_softc *, int, int);
126 static void my_autoneg_xmit(struct my_softc *);
127 static void my_autoneg_mii(struct my_softc *, int, int);
128 static void my_setmode_mii(struct my_softc *, int);
129 static void my_getmode_mii(struct my_softc *);
130 static void my_setcfg(struct my_softc *, int);
131 static u_int8_t my_calchash(caddr_t);
132 static void my_setmulti(struct my_softc *);
133 static void my_reset(struct my_softc *);
134 static int my_list_rx_init(struct my_softc *);
135 static int my_list_tx_init(struct my_softc *);
136 static long my_send_cmd_to_phy(struct my_softc *, int, int);
138 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
139 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
141 static device_method_t my_methods[] = {
142 /* Device interface */
143 DEVMETHOD(device_probe, my_probe),
144 DEVMETHOD(device_attach, my_attach),
145 DEVMETHOD(device_detach, my_detach),
146 DEVMETHOD(device_shutdown, my_shutdown),
151 static driver_t my_driver = {
154 sizeof(struct my_softc)
157 static devclass_t my_devclass;
159 DECLARE_DUMMY_MODULE(if_my);
160 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
163 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
169 /* enable MII output */
170 miir = CSR_READ_4(sc, MY_MANAGEMENT);
173 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
175 /* send 32 1's preamble */
176 for (i = 0; i < 32; i++) {
177 /* low MDC; MDO is already high (miir) */
178 miir &= ~MY_MASK_MIIR_MII_MDC;
179 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
182 miir |= MY_MASK_MIIR_MII_MDC;
183 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
186 /* calculate ST+OP+PHYAD+REGAD+TA */
187 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
192 /* low MDC, prepare MDO */
193 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
195 miir |= MY_MASK_MIIR_MII_MDO;
197 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
199 miir |= MY_MASK_MIIR_MII_MDC;
200 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
205 if (mask == 0x2 && opcode == MY_OP_READ)
206 miir &= ~MY_MASK_MIIR_MII_WRITE;
214 my_phy_readreg(struct my_softc * sc, int reg)
219 if (sc->my_info->my_did == MTD803ID)
220 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
222 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
229 miir &= ~MY_MASK_MIIR_MII_MDC;
230 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
233 miir = CSR_READ_4(sc, MY_MANAGEMENT);
234 if (miir & MY_MASK_MIIR_MII_MDI)
237 /* high MDC, and wait */
238 miir |= MY_MASK_MIIR_MII_MDC;
239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
247 miir &= ~MY_MASK_MIIR_MII_MDC;
248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
251 return (u_int16_t) data;
256 my_phy_writereg(struct my_softc * sc, int reg, int data)
261 if (sc->my_info->my_did == MTD803ID)
262 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
264 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
269 /* low MDC, prepare MDO */
270 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
272 miir |= MY_MASK_MIIR_MII_MDO;
273 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
277 miir |= MY_MASK_MIIR_MII_MDC;
278 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
286 miir &= ~MY_MASK_MIIR_MII_MDC;
287 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
292 my_calchash(caddr_t addr)
294 u_int32_t crc, carry;
298 /* Compute CRC for the address value. */
299 crc = 0xFFFFFFFF; /* initial value */
301 for (i = 0; i < 6; i++) {
303 for (j = 0; j < 8; j++) {
304 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
308 crc = (crc ^ 0x04c11db6) | carry;
313 * return the filter bit position Note: I arrived at the following
314 * nonsense through experimentation. It's not the usual way to
315 * generate the bit position but it's the only thing I could come up
318 return (~(crc >> 26) & 0x0000003F);
323 * Program the 64-bit multicast hash filter.
326 my_setmulti(struct my_softc * sc)
328 struct ifnet *ifp = &sc->arpcom.ac_if;
330 u_int32_t hashes[2] = {0, 0};
331 struct ifmultiaddr *ifma;
335 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
337 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
339 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
340 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
341 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
345 /* first, zot all the existing hash bits */
346 CSR_WRITE_4(sc, MY_MAR0, 0);
347 CSR_WRITE_4(sc, MY_MAR1, 0);
349 /* now program new ones */
350 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
351 if (ifma->ifma_addr->sa_family != AF_LINK)
353 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
355 hashes[0] |= (1 << h);
357 hashes[1] |= (1 << (h - 32));
365 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
366 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
367 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
371 * Initiate an autonegotiation session.
374 my_autoneg_xmit(struct my_softc * sc)
376 u_int16_t phy_sts = 0;
378 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
380 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
382 phy_sts = my_phy_readreg(sc, PHY_BMCR);
383 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
384 my_phy_writereg(sc, PHY_BMCR, phy_sts);
389 * Invoke autonegotiation on a PHY.
392 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
394 u_int16_t phy_sts = 0, media, advert, ability;
395 u_int16_t ability2 = 0;
396 struct ifnet *ifp = &sc->arpcom.ac_if;
397 struct ifmedia *ifm = &sc->ifmedia;
399 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
401 #ifndef FORCE_AUTONEG_TFOUR
403 * First, see if autoneg is supported. If not, there's no point in
406 phy_sts = my_phy_readreg(sc, PHY_BMSR);
407 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
409 kprintf("my%d: autonegotiation not supported\n",
411 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
416 case MY_FLAG_FORCEDELAY:
418 * XXX Never use this option anywhere but in the probe
419 * routine: making the kernel stop dead in its tracks for
420 * three whole seconds after we've gone multi-user is really
426 case MY_FLAG_SCHEDDELAY:
428 * Wait for the transmitter to go idle before starting an
429 * autoneg session, otherwise my_start() may clobber our
430 * timeout, and we don't want to allow transmission during an
431 * autoneg session since that can screw it up.
433 if (sc->my_cdata.my_tx_head != NULL) {
434 sc->my_want_auto = 1;
440 sc->my_want_auto = 0;
442 case MY_FLAG_DELAYTIMEO:
447 kprintf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
451 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
453 kprintf("my%d: autoneg complete, ", sc->my_unit);
454 phy_sts = my_phy_readreg(sc, PHY_BMSR);
457 kprintf("my%d: autoneg not complete, ", sc->my_unit);
460 media = my_phy_readreg(sc, PHY_BMCR);
462 /* Link is good. Report modes and set duplex mode. */
463 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
465 kprintf("my%d: link status good. ", sc->my_unit);
466 advert = my_phy_readreg(sc, PHY_ANAR);
467 ability = my_phy_readreg(sc, PHY_LPAR);
468 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
469 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
470 ability2 = my_phy_readreg(sc, PHY_1000SR);
471 if (ability2 & PHY_1000SR_1000BTXFULL) {
475 * this version did not support 1000M,
477 * IFM_ETHER | IFM_1000_T | IFM_FDX;
480 IFM_ETHER | IFM_100_TX | IFM_FDX;
481 media &= ~PHY_BMCR_SPEEDSEL;
482 media |= PHY_BMCR_1000;
483 media |= PHY_BMCR_DUPLEX;
484 kprintf("(full-duplex, 1000Mbps)\n");
485 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
489 * this version did not support 1000M,
490 * ifm->ifm_media = IFM_ETHER | IFM_1000_T;
492 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
493 media &= ~PHY_BMCR_SPEEDSEL;
494 media &= ~PHY_BMCR_DUPLEX;
495 media |= PHY_BMCR_1000;
496 kprintf("(half-duplex, 1000Mbps)\n");
499 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
500 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
501 media |= PHY_BMCR_SPEEDSEL;
502 media &= ~PHY_BMCR_DUPLEX;
503 kprintf("(100baseT4)\n");
504 } else if (advert & PHY_ANAR_100BTXFULL &&
505 ability & PHY_ANAR_100BTXFULL) {
506 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
507 media |= PHY_BMCR_SPEEDSEL;
508 media |= PHY_BMCR_DUPLEX;
509 kprintf("(full-duplex, 100Mbps)\n");
510 } else if (advert & PHY_ANAR_100BTXHALF &&
511 ability & PHY_ANAR_100BTXHALF) {
512 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
513 media |= PHY_BMCR_SPEEDSEL;
514 media &= ~PHY_BMCR_DUPLEX;
515 kprintf("(half-duplex, 100Mbps)\n");
516 } else if (advert & PHY_ANAR_10BTFULL &&
517 ability & PHY_ANAR_10BTFULL) {
518 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
519 media &= ~PHY_BMCR_SPEEDSEL;
520 media |= PHY_BMCR_DUPLEX;
521 kprintf("(full-duplex, 10Mbps)\n");
523 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
524 media &= ~PHY_BMCR_SPEEDSEL;
525 media &= ~PHY_BMCR_DUPLEX;
526 kprintf("(half-duplex, 10Mbps)\n");
528 media &= ~PHY_BMCR_AUTONEGENBL;
530 /* Set ASIC's duplex mode to match the PHY. */
531 my_phy_writereg(sc, PHY_BMCR, media);
532 my_setcfg(sc, media);
535 kprintf("my%d: no carrier\n", sc->my_unit);
539 if (sc->my_tx_pend) {
547 * To get PHY ability.
550 my_getmode_mii(struct my_softc * sc)
552 struct ifnet *ifp = &sc->arpcom.ac_if;
555 bmsr = my_phy_readreg(sc, PHY_BMSR);
557 kprintf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
560 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
562 if (bmsr & PHY_BMSR_10BTHALF) {
564 kprintf("my%d: 10Mbps half-duplex mode supported\n",
566 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
568 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
570 if (bmsr & PHY_BMSR_10BTFULL) {
572 kprintf("my%d: 10Mbps full-duplex mode supported\n",
575 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
577 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
579 if (bmsr & PHY_BMSR_100BTXHALF) {
581 kprintf("my%d: 100Mbps half-duplex mode supported\n",
583 ifp->if_baudrate = 100000000;
584 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
585 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
587 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
589 if (bmsr & PHY_BMSR_100BTXFULL) {
591 kprintf("my%d: 100Mbps full-duplex mode supported\n",
593 ifp->if_baudrate = 100000000;
594 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
596 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
598 /* Some also support 100BaseT4. */
599 if (bmsr & PHY_BMSR_100BT4) {
601 kprintf("my%d: 100baseT4 mode supported\n", sc->my_unit);
602 ifp->if_baudrate = 100000000;
603 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
604 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
605 #ifdef FORCE_AUTONEG_TFOUR
607 kprintf("my%d: forcing on autoneg support for BT4\n",
609 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
610 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
613 #if 0 /* this version did not support 1000M, */
614 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
616 kprintf("my%d: 1000Mbps half-duplex mode supported\n",
619 ifp->if_baudrate = 1000000000;
620 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
621 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
624 kprintf("my%d: 1000Mbps full-duplex mode supported\n",
626 ifp->if_baudrate = 1000000000;
627 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
629 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
632 if (bmsr & PHY_BMSR_CANAUTONEG) {
634 kprintf("my%d: autoneg supported\n", sc->my_unit);
635 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
636 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
641 * Set speed and duplex mode.
644 my_setmode_mii(struct my_softc * sc, int media)
646 struct ifnet *ifp = &sc->arpcom.ac_if;
650 * If an autoneg session is in progress, stop it.
652 if (sc->my_autoneg) {
653 kprintf("my%d: canceling autoneg session\n", sc->my_unit);
654 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
655 bmcr = my_phy_readreg(sc, PHY_BMCR);
656 bmcr &= ~PHY_BMCR_AUTONEGENBL;
657 my_phy_writereg(sc, PHY_BMCR, bmcr);
659 kprintf("my%d: selecting MII, ", sc->my_unit);
660 bmcr = my_phy_readreg(sc, PHY_BMCR);
661 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
662 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
664 #if 0 /* this version did not support 1000M, */
665 if (IFM_SUBTYPE(media) == IFM_1000_T) {
666 kprintf("1000Mbps/T4, half-duplex\n");
667 bmcr &= ~PHY_BMCR_SPEEDSEL;
668 bmcr &= ~PHY_BMCR_DUPLEX;
669 bmcr |= PHY_BMCR_1000;
672 if (IFM_SUBTYPE(media) == IFM_100_T4) {
673 kprintf("100Mbps/T4, half-duplex\n");
674 bmcr |= PHY_BMCR_SPEEDSEL;
675 bmcr &= ~PHY_BMCR_DUPLEX;
677 if (IFM_SUBTYPE(media) == IFM_100_TX) {
678 kprintf("100Mbps, ");
679 bmcr |= PHY_BMCR_SPEEDSEL;
681 if (IFM_SUBTYPE(media) == IFM_10_T) {
683 bmcr &= ~PHY_BMCR_SPEEDSEL;
685 if ((media & IFM_GMASK) == IFM_FDX) {
686 kprintf("full duplex\n");
687 bmcr |= PHY_BMCR_DUPLEX;
689 kprintf("half duplex\n");
690 bmcr &= ~PHY_BMCR_DUPLEX;
692 my_phy_writereg(sc, PHY_BMCR, bmcr);
697 * The Myson manual states that in order to fiddle with the 'full-duplex' and
698 * '100Mbps' bits in the netconfig register, we first have to put the
699 * transmit and/or receive logic in the idle state.
702 my_setcfg(struct my_softc * sc, int bmcr)
706 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
708 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
709 for (i = 0; i < MY_TIMEOUT; i++) {
711 if (!(CSR_READ_4(sc, MY_TCRRCR) &
712 (MY_TXRUN | MY_RXRUN)))
716 kprintf("my%d: failed to force tx and rx to idle \n",
719 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
720 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
721 if (bmcr & PHY_BMCR_1000)
722 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
723 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
724 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
725 if (bmcr & PHY_BMCR_DUPLEX)
726 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
728 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
730 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
734 my_reset(struct my_softc * sc)
738 MY_SETBIT(sc, MY_BCR, MY_SWR);
739 for (i = 0; i < MY_TIMEOUT; i++) {
741 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
745 kprintf("m0x%d: reset never completed!\n", sc->my_unit);
747 /* Wait a little while for the chip to get its brains in order. */
752 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
753 * list and return a device name if we find a match.
756 my_probe(device_t dev)
759 uint16_t vendor, product;
761 vendor = pci_get_vendor(dev);
762 product = pci_get_device(dev);
764 for (t = my_devs; t->my_name != NULL; t++) {
765 if (vendor == t->my_vid && product == t->my_did) {
766 device_set_desc(dev, t->my_name);
775 * Attach the interface. Allocate softc structures, do ifmedia setup and
776 * ethernet/BPF attach.
779 my_attach(device_t dev)
782 u_char eaddr[ETHER_ADDR_LEN];
783 u_int32_t command, iobase;
786 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
790 u_int16_t phy_vid, phy_did, phy_sts = 0;
791 int rid, unit, error = 0;
793 uint16_t vendor, product;
795 vendor = pci_get_vendor(dev);
796 product = pci_get_device(dev);
798 for (t = my_devs; t->my_name != NULL; t++) {
799 if (vendor == t->my_vid && product == t->my_did)
803 if (t->my_name == NULL)
806 sc = device_get_softc(dev);
807 unit = device_get_unit(dev);
810 * Map control/status registers.
812 command = pci_read_config(dev, PCIR_COMMAND, 4);
813 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
814 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
815 command = pci_read_config(dev, PCIR_COMMAND, 4);
817 if (t->my_did == MTD800ID) {
818 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
823 if (!(command & PCIM_CMD_PORTEN)) {
824 kprintf("my%d: failed to enable I/O ports!\n", unit);
829 if (!(command & PCIM_CMD_MEMEN)) {
830 kprintf("my%d: failed to enable memory mapping!\n",
838 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
840 if (sc->my_res == NULL) {
841 kprintf("my%d: couldn't map ports/memory\n", unit);
845 sc->my_btag = rman_get_bustag(sc->my_res);
846 sc->my_bhandle = rman_get_bushandle(sc->my_res);
849 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
850 RF_SHAREABLE | RF_ACTIVE);
852 if (sc->my_irq == NULL) {
853 kprintf("my%d: couldn't map interrupt\n", unit);
860 /* Reset the adapter. */
864 * Get station address
866 for (i = 0; i < ETHER_ADDR_LEN; ++i)
867 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
871 sc->my_ldata_ptr = kmalloc(sizeof(struct my_list_data) + 8,
873 if (sc->my_ldata_ptr == NULL) {
874 kprintf("my%d: no memory for list buffers!\n", unit);
878 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
879 round = (unsigned int)sc->my_ldata_ptr & 0xF;
880 roundptr = sc->my_ldata_ptr;
881 for (i = 0; i < 8; i++) {
888 sc->my_ldata = (struct my_list_data *) roundptr;
889 bzero(sc->my_ldata, sizeof(struct my_list_data));
891 ifp = &sc->arpcom.ac_if;
893 if_initname(ifp, "my", unit);
894 ifp->if_mtu = ETHERMTU;
895 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
896 ifp->if_ioctl = my_ioctl;
897 ifp->if_start = my_start;
898 ifp->if_watchdog = my_watchdog;
899 ifp->if_init = my_init;
900 ifp->if_baudrate = 10000000;
901 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
902 ifq_set_ready(&ifp->if_snd);
904 if (sc->my_info->my_did == MTD803ID)
905 sc->my_pinfo = my_phys;
908 kprintf("my%d: probing for a PHY\n", sc->my_unit);
909 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
911 kprintf("my%d: checking address: %d\n",
914 phy_sts = my_phy_readreg(sc, PHY_BMSR);
915 if ((phy_sts != 0) && (phy_sts != 0xffff))
921 phy_vid = my_phy_readreg(sc, PHY_VENID);
922 phy_did = my_phy_readreg(sc, PHY_DEVID);
924 kprintf("my%d: found PHY at address %d, ",
925 sc->my_unit, sc->my_phy_addr);
926 kprintf("vendor id: %x device id: %x\n",
931 if (phy_vid == p->my_vid) {
937 if (sc->my_pinfo == NULL)
938 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
940 kprintf("my%d: PHY type: %s\n",
941 sc->my_unit, sc->my_pinfo->my_name);
943 kprintf("my%d: MII without any phy!\n", sc->my_unit);
949 /* Do ifmedia setup. */
950 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
952 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
953 media = sc->ifmedia.ifm_media;
955 ifmedia_set(&sc->ifmedia, media);
957 ether_ifattach(ifp, eaddr, NULL);
959 error = bus_setup_intr(dev, sc->my_irq, INTR_NETSAFE,
960 my_intr, sc, &sc->my_intrhand,
964 kprintf("my%d: couldn't set up irq\n", unit);
976 my_detach(device_t dev)
978 struct my_softc *sc = device_get_softc(dev);
979 struct ifnet *ifp = &sc->arpcom.ac_if;
981 if (device_is_attached(dev)) {
982 lwkt_serialize_enter(ifp->if_serializer);
984 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
985 lwkt_serialize_exit(ifp->if_serializer);
991 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
993 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1000 * Initialize the transmit descriptors.
1003 my_list_tx_init(struct my_softc * sc)
1005 struct my_chain_data *cd;
1006 struct my_list_data *ld;
1011 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1012 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1013 if (i == (MY_TX_LIST_CNT - 1))
1014 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1016 cd->my_tx_chain[i].my_nextdesc =
1017 &cd->my_tx_chain[i + 1];
1019 cd->my_tx_free = &cd->my_tx_chain[0];
1020 cd->my_tx_tail = cd->my_tx_head = NULL;
1025 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1026 * arrange the descriptors in a closed ring, so that the last descriptor
1027 * points back to the first.
1030 my_list_rx_init(struct my_softc * sc)
1032 struct my_chain_data *cd;
1033 struct my_list_data *ld;
1038 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1039 cd->my_rx_chain[i].my_ptr =
1040 (struct my_desc *) & ld->my_rx_list[i];
1041 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS)
1043 if (i == (MY_RX_LIST_CNT - 1)) {
1044 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1045 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1047 cd->my_rx_chain[i].my_nextdesc =
1048 &cd->my_rx_chain[i + 1];
1049 ld->my_rx_list[i].my_next =
1050 vtophys(&ld->my_rx_list[i + 1]);
1053 cd->my_rx_head = &cd->my_rx_chain[0];
1058 * Initialize an RX descriptor and attach an MBUF cluster.
1061 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1063 struct mbuf *m_new = NULL;
1065 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1066 if (m_new == NULL) {
1067 kprintf("my%d: no memory for rx list -- packet dropped!\n",
1071 MCLGET(m_new, MB_DONTWAIT);
1072 if (!(m_new->m_flags & M_EXT)) {
1073 kprintf("my%d: no memory for rx list -- packet dropped!\n",
1079 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1080 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1081 c->my_ptr->my_status = MY_OWNByNIC;
1086 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1090 my_rxeof(struct my_softc * sc)
1093 struct ifnet *ifp = &sc->arpcom.ac_if;
1094 struct my_chain_onefrag *cur_rx;
1098 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1100 cur_rx = sc->my_cdata.my_rx_head;
1101 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1103 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1105 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1108 /* No errors; receive the packet. */
1109 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1110 total_len -= ETHER_CRC_LEN;
1112 if (total_len < MINCLSIZE) {
1113 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1114 total_len, 0, ifp, NULL);
1115 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1121 m = cur_rx->my_mbuf;
1123 * Try to conjure up a new mbuf cluster. If that
1124 * fails, it means we have an out of memory condition
1125 * and should leave the buffer in place and continue.
1126 * This will result in a lost packet, but there's
1127 * little else we can do in this situation.
1129 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1131 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1134 m->m_pkthdr.rcvif = ifp;
1135 m->m_pkthdr.len = m->m_len = total_len;
1138 ifp->if_input(ifp, m);
1144 * A frame was downloaded to the chip. It's safe for us to clean up the list
1148 my_txeof(struct my_softc * sc)
1150 struct ifnet *ifp = &sc->arpcom.ac_if;
1151 struct my_chain *cur_tx;
1153 /* Clear the timeout timer. */
1155 if (sc->my_cdata.my_tx_head == NULL)
1158 * Go through our tx list and free mbufs for those frames that have
1161 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1164 cur_tx = sc->my_cdata.my_tx_head;
1165 txstat = MY_TXSTATUS(cur_tx);
1166 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1168 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1169 if (txstat & MY_TXERR) {
1171 if (txstat & MY_EC) /* excessive collision */
1172 ifp->if_collisions++;
1173 if (txstat & MY_LC) /* late collision */
1174 ifp->if_collisions++;
1176 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1180 m_freem(cur_tx->my_mbuf);
1181 cur_tx->my_mbuf = NULL;
1182 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1183 sc->my_cdata.my_tx_head = NULL;
1184 sc->my_cdata.my_tx_tail = NULL;
1187 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1189 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1190 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1195 * TX 'end of channel' interrupt handler.
1198 my_txeoc(struct my_softc * sc)
1200 struct ifnet *ifp = &sc->arpcom.ac_if;
1203 if (sc->my_cdata.my_tx_head == NULL) {
1204 ifp->if_flags &= ~IFF_OACTIVE;
1205 sc->my_cdata.my_tx_tail = NULL;
1206 if (sc->my_want_auto)
1207 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1209 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1210 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1212 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1220 struct my_softc *sc = arg;
1221 struct ifnet *ifp = &sc->arpcom.ac_if;
1224 if (!(ifp->if_flags & IFF_UP))
1227 /* Disable interrupts. */
1228 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1231 status = CSR_READ_4(sc, MY_ISR);
1234 CSR_WRITE_4(sc, MY_ISR, status);
1238 if (status & MY_RI) /* receive interrupt */
1241 if ((status & MY_RBU) || (status & MY_RxErr)) {
1242 /* rx buffer unavailable or rx error */
1250 if (status & MY_TI) /* tx interrupt */
1252 if (status & MY_ETI) /* tx early interrupt */
1254 if (status & MY_TBU) /* tx buffer unavailable */
1257 #if 0 /* 90/1/18 delete */
1258 if (status & MY_FBE) {
1266 /* Re-enable interrupts. */
1267 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1268 if (!ifq_is_empty(&ifp->if_snd))
1273 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1274 * pointers to the fragment pointers.
1277 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1279 struct my_desc *f = NULL;
1281 struct mbuf *m, *m_new = NULL;
1283 /* calculate the total tx pkt length */
1285 for (m = m_head; m != NULL; m = m->m_next)
1286 total_len += m->m_len;
1288 * Start packing the mbufs in this chain into the fragment pointers.
1289 * Stop when we run out of fragments or hit the end of the mbuf
1293 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1294 if (m_new == NULL) {
1295 kprintf("my%d: no memory for tx list", sc->my_unit);
1298 if (m_head->m_pkthdr.len > MHLEN) {
1299 MCLGET(m_new, MB_DONTWAIT);
1300 if (!(m_new->m_flags & M_EXT)) {
1302 kprintf("my%d: no memory for tx list", sc->my_unit);
1306 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1307 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1310 f = &c->my_ptr->my_frag[0];
1312 f->my_data = vtophys(mtod(m_new, caddr_t));
1313 total_len = m_new->m_len;
1314 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1315 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1316 f->my_ctl |= total_len; /* buffer size */
1317 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1318 if (sc->my_info->my_did == MTD891ID)
1319 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1320 c->my_mbuf = m_head;
1322 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1327 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1328 * to the mbuf data regions directly in the transmit lists. We also save a
1329 * copy of the pointers since the transmit list fragment pointers are
1330 * physical addresses.
1333 my_start(struct ifnet * ifp)
1335 struct my_softc *sc = ifp->if_softc;
1336 struct mbuf *m_head = NULL;
1337 struct my_chain *cur_tx = NULL, *start_tx;
1341 if (sc->my_autoneg) {
1347 * Check for an available queue slot. If there are none, punt.
1349 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1350 ifp->if_flags |= IFF_OACTIVE;
1355 start_tx = sc->my_cdata.my_tx_free;
1356 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1357 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1361 /* Pick a descriptor off the free list. */
1362 cur_tx = sc->my_cdata.my_tx_free;
1363 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1365 /* Pack the data into the descriptor. */
1366 my_encap(sc, cur_tx, m_head);
1368 if (cur_tx != start_tx)
1369 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1370 BPF_MTAP(ifp, cur_tx->my_mbuf);
1373 * If there are no packets queued, bail.
1375 if (cur_tx == NULL) {
1380 * Place the request for the upload interrupt in the last descriptor
1381 * in the chain. This way, if we're chaining several packets at once,
1382 * we'll only get an interupt once for the whole chain rather than
1383 * once for each packet.
1385 MY_TXCTL(cur_tx) |= MY_TXIC;
1386 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1387 sc->my_cdata.my_tx_tail = cur_tx;
1388 if (sc->my_cdata.my_tx_head == NULL)
1389 sc->my_cdata.my_tx_head = start_tx;
1390 MY_TXOWN(start_tx) = MY_OWNByNIC;
1391 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1394 * Set a timeout in case the chip goes out to lunch.
1404 struct my_softc *sc = xsc;
1405 struct ifnet *ifp = &sc->arpcom.ac_if;
1406 u_int16_t phy_bmcr = 0;
1409 if (sc->my_autoneg) {
1413 if (sc->my_pinfo != NULL)
1414 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1416 * Cancel pending I/O and free all RX/TX buffers.
1422 * Set cache alignment and burst length.
1424 #if 0 /* 89/9/1 modify, */
1425 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1426 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1428 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1429 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1431 * 89/12/29 add, for mtd891,
1433 if (sc->my_info->my_did == MTD891ID) {
1434 MY_SETBIT(sc, MY_BCR, MY_PROG);
1435 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1437 my_setcfg(sc, phy_bmcr);
1438 /* Init circular RX list. */
1439 if (my_list_rx_init(sc) == ENOBUFS) {
1440 kprintf("my%d: init failed: no memory for rx buffers\n",
1446 /* Init TX descriptors. */
1447 my_list_tx_init(sc);
1449 /* If we want promiscuous mode, set the allframes bit. */
1450 if (ifp->if_flags & IFF_PROMISC)
1451 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1453 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1456 * Set capture broadcast bit to capture broadcast frames.
1458 if (ifp->if_flags & IFF_BROADCAST)
1459 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1461 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1464 * Program the multicast filter, if necessary.
1469 * Load the address of the RX list.
1471 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1472 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1475 * Enable interrupts.
1477 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1478 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1480 /* Enable receiver and transmitter. */
1481 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1482 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1483 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1484 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1486 /* Restore state of BMCR */
1487 if (sc->my_pinfo != NULL)
1488 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1489 ifp->if_flags |= IFF_RUNNING;
1490 ifp->if_flags &= ~IFF_OACTIVE;
1495 * Set media options.
1499 my_ifmedia_upd(struct ifnet * ifp)
1501 struct my_softc *sc = ifp->if_softc;
1502 struct ifmedia *ifm = &sc->ifmedia;
1504 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1509 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1510 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1512 my_setmode_mii(sc, ifm->ifm_media);
1520 * Report current media status.
1524 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1526 struct my_softc *sc = ifp->if_softc;
1527 u_int16_t advert = 0, ability = 0;
1531 ifmr->ifm_active = IFM_ETHER;
1532 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1533 #if 0 /* this version did not support 1000M, */
1534 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1535 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1537 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1538 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1540 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1541 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1542 ifmr->ifm_active |= IFM_FDX;
1544 ifmr->ifm_active |= IFM_HDX;
1550 ability = my_phy_readreg(sc, PHY_LPAR);
1551 advert = my_phy_readreg(sc, PHY_ANAR);
1553 #if 0 /* this version did not support 1000M, */
1554 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1555 ability2 = my_phy_readreg(sc, PHY_1000SR);
1556 if (ability2 & PHY_1000SR_1000BTXFULL) {
1559 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX;
1560 } else if (ability & PHY_1000SR_1000BTXHALF) {
1563 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX;
1567 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1568 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1569 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1570 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1571 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1572 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1573 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1574 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1575 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1576 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1582 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr)
1584 struct my_softc *sc = ifp->if_softc;
1585 struct ifreq *ifr = (struct ifreq *) data;
1591 if (ifp->if_flags & IFF_UP)
1593 else if (ifp->if_flags & IFF_RUNNING)
1604 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1607 error = ether_ioctl(ifp, command, data);
1616 my_watchdog(struct ifnet * ifp)
1618 struct my_softc *sc = ifp->if_softc;
1622 if (sc->my_autoneg) {
1623 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1628 kprintf("my%d: watchdog timeout\n", sc->my_unit);
1629 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1630 kprintf("my%d: no carrier - transceiver cable problem?\n",
1635 if (!ifq_is_empty(&ifp->if_snd))
1642 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1645 my_stop(struct my_softc * sc)
1647 struct ifnet *ifp = &sc->arpcom.ac_if;
1652 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1653 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1654 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1655 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1658 * Free data in the RX lists.
1660 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1661 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1662 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1663 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1666 bzero((char *)&sc->my_ldata->my_rx_list,
1667 sizeof(sc->my_ldata->my_rx_list));
1669 * Free the TX list buffers.
1671 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1672 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1673 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1674 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1677 bzero((char *)&sc->my_ldata->my_tx_list,
1678 sizeof(sc->my_ldata->my_tx_list));
1679 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1683 * Stop all chip I/O so that the kernel's probe routines don't get confused
1684 * by errant DMAs when rebooting.
1687 my_shutdown(device_t dev)
1689 struct my_softc *sc;
1691 sc = device_get_softc(dev);