2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.55 2008/08/02 01:14:43 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 #include "opt_clock.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/eventhandler.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
70 #include <sys/machintr.h>
72 #include <machine/clock.h>
73 #ifdef CLK_CALIBRATION_LOOP
75 #include <machine/cputypes.h>
76 #include <machine/frame.h>
77 #include <machine/ipl.h>
78 #include <machine/limits.h>
79 #include <machine/md_var.h>
80 #include <machine/psl.h>
81 #include <machine/segments.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
85 #include <machine_base/icu/icu.h>
86 #include <bus/isa/isa.h>
87 #include <bus/isa/rtc.h>
88 #include <machine_base/isa/timerreg.h>
90 #include <machine_base/isa/intr_machdep.h>
93 /* The interrupt triggered by the 8254 (timer) chip */
95 static void setup_8254_mixed_mode (void);
97 static void i8254_restore(void);
98 static void resettodr_on_shutdown(void *arg __unused);
101 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
102 * can use a simple formula for leap years.
104 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
105 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
108 #define TIMER_FREQ 1193182
111 static uint8_t i8254_walltimer_sel;
112 static uint16_t i8254_walltimer_cntr;
114 int adjkerntz; /* local offset from GMT in seconds */
115 int disable_rtc_set; /* disable resettodr() if != 0 */
116 int statclock_disable = 1; /* we don't use the statclock right now */
118 int64_t tsc_frequency;
120 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
122 enum tstate { RELEASED, ACQUIRED };
123 enum tstate timer0_state;
124 enum tstate timer1_state;
125 enum tstate timer2_state;
127 static int beeping = 0;
128 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
129 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
130 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
131 static int rtc_loaded;
133 static int i8254_cputimer_div;
135 static struct callout sysbeepstop_ch;
137 static sysclock_t i8254_cputimer_count(void);
138 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
139 static void i8254_cputimer_destruct(struct cputimer *cputimer);
141 static struct cputimer i8254_cputimer = {
142 SLIST_ENTRY_INITIALIZER,
146 i8254_cputimer_count,
147 cputimer_default_fromhz,
148 cputimer_default_fromus,
149 i8254_cputimer_construct,
150 i8254_cputimer_destruct,
156 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
157 * counting as of this interrupt. We use timer1 in free-running mode (not
158 * generating any interrupts) as our main counter. Each cpu has timeouts
161 * This code is INTR_MPSAFE and may be called without the BGL held.
164 clkintr(void *dummy, void *frame_arg)
166 static sysclock_t sysclock_count; /* NOTE! Must be static */
167 struct globaldata *gd = mycpu;
169 struct globaldata *gscan;
174 * SWSTROBE mode is a one-shot, the timer is no longer running
179 * XXX the dispatcher needs work. right now we call systimer_intr()
180 * directly or via IPI for any cpu with systimers queued, which is
181 * usually *ALL* of them. We need to use the LAPIC timer for this.
183 sysclock_count = sys_cputimer->count();
185 for (n = 0; n < ncpus; ++n) {
186 gscan = globaldata_find(n);
187 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
190 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
193 systimer_intr(&sysclock_count, 0, frame_arg);
197 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
198 systimer_intr(&sysclock_count, 0, frame_arg);
207 acquire_timer2(int mode)
209 if (timer2_state != RELEASED)
211 timer2_state = ACQUIRED;
214 * This access to the timer registers is as atomic as possible
215 * because it is a single instruction. We could do better if we
218 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
225 if (timer2_state != ACQUIRED)
227 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
228 timer2_state = RELEASED;
233 * This routine receives statistical clock interrupts from the RTC.
234 * As explained above, these occur at 128 interrupts per second.
235 * When profiling, we receive interrupts at a rate of 1024 Hz.
237 * This does not actually add as much overhead as it sounds, because
238 * when the statistical clock is active, the hardclock driver no longer
239 * needs to keep (inaccurate) statistics on its own. This decouples
240 * statistics gathering from scheduling interrupts.
242 * The RTC chip requires that we read status register C (RTC_INTR)
243 * to acknowledge an interrupt, before it will generate the next one.
244 * Under high interrupt load, rtcintr() can be indefinitely delayed and
245 * the clock can tick immediately after the read from RTC_INTR. In this
246 * case, the mc146818A interrupt signal will not drop for long enough
247 * to register with the 8259 PIC. If an interrupt is missed, the stat
248 * clock will halt, considerably degrading system performance. This is
249 * why we use 'while' rather than a more straightforward 'if' below.
250 * Stat clock ticks can still be lost, causing minor loss of accuracy
251 * in the statistics, but the stat clock will no longer stop.
254 rtcintr(void *dummy, void *frame)
256 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
258 /* statclock(frame); no longer used */
265 DB_SHOW_COMMAND(rtc, rtc)
267 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
268 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
269 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
270 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
275 * Return the current cpu timer count as a 32 bit integer.
279 i8254_cputimer_count(void)
281 static __uint16_t cputimer_last;
286 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
287 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
288 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
289 count = -count; /* -> countup */
290 if (count < cputimer_last) /* rollover */
291 i8254_cputimer.base += 0x00010000;
292 ret = i8254_cputimer.base | count;
293 cputimer_last = count;
299 * This function is called whenever the system timebase changes, allowing
300 * us to calculate what is needed to convert a system timebase tick
301 * into an 8254 tick for the interrupt timer. If we can convert to a
302 * simple shift, multiplication, or division, we do so. Otherwise 64
303 * bit arithmatic is required every time the interrupt timer is reloaded.
306 cputimer_intr_config(struct cputimer *timer)
312 * Will a simple divide do the trick?
314 div = (timer->freq + (i8254_cputimer.freq / 2)) / i8254_cputimer.freq;
315 freq = i8254_cputimer.freq * div;
317 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
318 i8254_cputimer_div = div;
320 i8254_cputimer_div = 0;
324 * Reload for the next timeout. It is possible for the reload value
325 * to be 0 or negative, indicating that an immediate timer interrupt
326 * is desired. For now make the minimum 2 ticks.
328 * We may have to convert from the system timebase to the 8254 timebase.
331 i8254_intr_reload(sysclock_t reload)
335 if (i8254_cputimer_div)
336 reload /= i8254_cputimer_div;
338 reload = (int64_t)reload * i8254_cputimer.freq / sys_cputimer->freq;
344 if (timer0_running) {
345 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
346 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
347 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
348 if (reload < count) {
349 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
350 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
351 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
356 reload = 0; /* full count */
357 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
358 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
359 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
365 extern int lapic_timer_test;
366 extern void lapic_timer_oneshot_intr_enable(void);
367 extern void lapic_timer_intr_test(void);
371 cputimer_intr_reload(sysclock_t reload)
373 i8254_intr_reload(reload);
375 if (__predict_false(lapic_timer_test))
376 lapic_timer_intr_test();
381 cputimer_intr_enable(void)
384 if (lapic_timer_test)
385 lapic_timer_oneshot_intr_enable();
390 * DELAY(usec) - Spin for the specified number of microseconds.
391 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
392 * but do a thread switch in the loop
394 * Relies on timer 1 counting down from (cputimer_freq / hz)
395 * Note: timer had better have been programmed before this is first used!
398 DODELAY(int n, int doswitch)
400 int delta, prev_tick, tick, ticks_left;
405 static int state = 0;
409 for (n1 = 1; n1 <= 10000000; n1 *= 10)
414 kprintf("DELAY(%d)...", n);
417 * Guard against the timer being uninitialized if we are called
418 * early for console i/o.
420 if (timer0_state == RELEASED)
424 * Read the counter first, so that the rest of the setup overhead is
425 * counted. Then calculate the number of hardware timer ticks
426 * required, rounding up to be sure we delay at least the requested
427 * number of microseconds.
429 prev_tick = sys_cputimer->count();
430 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
436 while (ticks_left > 0) {
437 tick = sys_cputimer->count();
441 delta = tick - prev_tick;
446 if (doswitch && ticks_left > 0)
451 kprintf(" %d calls to getit() at %d usec each\n",
452 getit_calls, (n + 5) / getit_calls);
463 DRIVERSLEEP(int usec)
465 globaldata_t gd = mycpu;
467 if (gd->gd_intr_nesting_level ||
468 gd->gd_spinlock_rd ||
469 gd->gd_spinlocks_wr) {
477 sysbeepstop(void *chan)
479 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
485 sysbeep(int pitch, int period)
487 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
490 * Nobody else is using timer2, we do not need the clock lock
492 outb(TIMER_CNTR2, pitch);
493 outb(TIMER_CNTR2, (pitch>>8));
495 /* enable counter2 output to speaker */
496 outb(IO_PPI, inb(IO_PPI) | 3);
498 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
504 * RTC support routines
515 val = inb(IO_RTC + 1);
522 writertc(u_char reg, u_char val)
528 outb(IO_RTC + 1, val);
529 inb(0x84); /* XXX work around wrong order in rtcin() */
536 return(bcd2bin(rtcin(port)));
540 calibrate_clocks(void)
543 u_int count, prev_count, tot_count;
544 int sec, start_sec, timeout;
547 kprintf("Calibrating clock(s) ... ");
548 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
552 /* Read the mc146818A seconds counter. */
554 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
555 sec = rtcin(RTC_SEC);
562 /* Wait for the mC146818A seconds counter to change. */
565 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
566 sec = rtcin(RTC_SEC);
567 if (sec != start_sec)
574 /* Start keeping track of the i8254 counter. */
575 prev_count = sys_cputimer->count();
581 old_tsc = 0; /* shut up gcc */
584 * Wait for the mc146818A seconds counter to change. Read the i8254
585 * counter for each iteration since this is convenient and only
586 * costs a few usec of inaccuracy. The timing of the final reads
587 * of the counters almost matches the timing of the initial reads,
588 * so the main cause of inaccuracy is the varying latency from
589 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
590 * rtcin(RTC_SEC) that returns a changed seconds count. The
591 * maximum inaccuracy from this cause is < 10 usec on 486's.
595 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
596 sec = rtcin(RTC_SEC);
597 count = sys_cputimer->count();
598 tot_count += (int)(count - prev_count);
600 if (sec != start_sec)
607 * Read the cpu cycle counter. The timing considerations are
608 * similar to those for the i8254 clock.
611 tsc_frequency = rdtsc() - old_tsc;
615 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
616 kprintf("i8254 clock: %u Hz\n", tot_count);
620 kprintf("failed, using default i8254 clock of %u Hz\n",
621 i8254_cputimer.freq);
622 return (i8254_cputimer.freq);
628 timer0_state = ACQUIRED;
633 * Timer0 is our fine-grained variable clock interrupt
635 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
636 outb(TIMER_CNTR0, 2); /* lsb */
637 outb(TIMER_CNTR0, 0); /* msb */
641 * Timer1 or timer2 is our free-running clock, but only if another
642 * has not been selected.
644 cputimer_register(&i8254_cputimer);
645 cputimer_select(&i8254_cputimer, 0);
649 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
654 * Should we use timer 1 or timer 2 ?
657 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
658 if (which != 1 && which != 2)
663 timer->name = "i8254_timer1";
664 timer->type = CPUTIMER_8254_SEL1;
665 i8254_walltimer_sel = TIMER_SEL1;
666 i8254_walltimer_cntr = TIMER_CNTR1;
667 timer1_state = ACQUIRED;
670 timer->name = "i8254_timer2";
671 timer->type = CPUTIMER_8254_SEL2;
672 i8254_walltimer_sel = TIMER_SEL2;
673 i8254_walltimer_cntr = TIMER_CNTR2;
674 timer2_state = ACQUIRED;
678 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
681 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
682 outb(i8254_walltimer_cntr, 0); /* lsb */
683 outb(i8254_walltimer_cntr, 0); /* msb */
684 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
689 i8254_cputimer_destruct(struct cputimer *timer)
691 switch(timer->type) {
692 case CPUTIMER_8254_SEL1:
693 timer1_state = RELEASED;
695 case CPUTIMER_8254_SEL2:
696 timer2_state = RELEASED;
707 /* Restore all of the RTC's "status" (actually, control) registers. */
708 writertc(RTC_STATUSB, RTCSB_24HR);
709 writertc(RTC_STATUSA, rtc_statusa);
710 writertc(RTC_STATUSB, rtc_statusb);
714 * Restore all the timers.
716 * This function is called to resynchronize our core timekeeping after a
717 * long halt, e.g. from apm_default_resume() and friends. It is also
718 * called if after a BIOS call we have detected munging of the 8254.
719 * It is necessary because cputimer_count() counter's delta may have grown
720 * too large for nanouptime() and friends to handle, or (in the case of 8254
721 * munging) might cause the SYSTIMER code to prematurely trigger.
727 i8254_restore(); /* restore timer_freq and hz */
728 rtc_restore(); /* reenable RTC interrupts */
733 * Initialize 8254 timer 0 early so that it can be used in DELAY().
741 * Can we use the TSC?
743 if (cpu_feature & CPUID_TSC)
749 * Initial RTC state, don't do anything unexpected
751 writertc(RTC_STATUSA, rtc_statusa);
752 writertc(RTC_STATUSB, RTCSB_24HR);
755 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
756 * generate an interrupt, which we will ignore for now.
758 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
759 * (so it counts a full 2^16 and repeats). We will use this timer
763 freq = calibrate_clocks();
764 #ifdef CLK_CALIBRATION_LOOP
767 "Press a key on the console to abort clock calibration\n");
768 while (cncheckc() == -1)
774 * Use the calibrated i8254 frequency if it seems reasonable.
775 * Otherwise use the default, and don't use the calibrated i586
778 delta = freq > i8254_cputimer.freq ?
779 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
780 if (delta < i8254_cputimer.freq / 100) {
781 #ifndef CLK_USE_I8254_CALIBRATION
784 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
785 freq = i8254_cputimer.freq;
787 cputimer_set_frequency(&i8254_cputimer, freq);
791 "%d Hz differs from default of %d Hz by more than 1%%\n",
792 freq, i8254_cputimer.freq);
796 #ifndef CLK_USE_TSC_CALIBRATION
797 if (tsc_frequency != 0) {
800 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
804 if (tsc_present && tsc_frequency == 0) {
806 * Calibration of the i586 clock relative to the mc146818A
807 * clock failed. Do a less accurate calibration relative
808 * to the i8254 clock.
810 u_int64_t old_tsc = rdtsc();
813 tsc_frequency = rdtsc() - old_tsc;
814 #ifdef CLK_USE_TSC_CALIBRATION
816 kprintf("TSC clock: %llu Hz (Method B)\n",
822 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
826 * We can not use the TSC in SMP mode, until we figure out a
827 * cheap (impossible), reliable and precise (yeah right!) way
828 * to synchronize the TSCs of all the CPUs.
829 * Curse Intel for leaving the counter out of the I/O APIC.
834 * We can not use the TSC if we support APM. Precise timekeeping
835 * on an APM'ed machine is at best a fools pursuit, since
836 * any and all of the time spent in various SMM code can't
837 * be reliably accounted for. Reading the RTC is your only
838 * source of reliable time info. The i8254 looses too of course
839 * but we need to have some kind of time...
840 * We don't know at this point whether APM is going to be used
841 * or not, nor when it might be activated. Play it safe.
844 #endif /* NAPM > 0 */
846 #endif /* !defined(SMP) */
850 * Sync the time of day back to the RTC on shutdown, but only if
851 * we have already loaded it and have not crashed.
854 resettodr_on_shutdown(void *arg __unused)
856 if (rtc_loaded && panicstr == NULL) {
862 * Initialize the time of day register, based on the time base which is, e.g.
866 inittodr(time_t base)
868 unsigned long sec, days;
880 /* Look if we have a RTC present and the time is valid */
881 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
884 /* wait for time update to complete */
885 /* If RTCSA_TUP is zero, we have at least 244us before next update */
887 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
893 #ifdef USE_RTC_CENTURY
894 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
896 year = readrtc(RTC_YEAR) + 1900;
904 month = readrtc(RTC_MONTH);
905 for (m = 1; m < month; m++)
906 days += daysinmonth[m-1];
907 if ((month > 2) && LEAPYEAR(year))
909 days += readrtc(RTC_DAY) - 1;
911 for (y = 1970; y < year; y++)
912 days += DAYSPERYEAR + LEAPYEAR(y);
913 sec = ((( days * 24 +
914 readrtc(RTC_HRS)) * 60 +
915 readrtc(RTC_MIN)) * 60 +
917 /* sec now contains the number of seconds, since Jan 1 1970,
918 in the local time zone */
920 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
922 y = time_second - sec;
923 if (y <= -2 || y >= 2) {
924 /* badly off, adjust it */
934 kprintf("Invalid time in real time clock.\n");
935 kprintf("Check and reset the date immediately!\n");
939 * Write system time back to RTC
956 /* Disable RTC updates and interrupts. */
957 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
959 /* Calculate local time to put in RTC */
961 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
963 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
964 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
965 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
967 /* We have now the days since 01-01-1970 in tm */
968 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
969 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
971 y++, m = DAYSPERYEAR + LEAPYEAR(y))
974 /* Now we have the years in y and the day-of-the-year in tm */
975 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
976 #ifdef USE_RTC_CENTURY
977 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
983 if (m == 1 && LEAPYEAR(y))
990 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
991 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
993 /* Reenable RTC updates and interrupts. */
994 writertc(RTC_STATUSB, rtc_statusb);
1000 * Start both clocks running. DragonFly note: the stat clock is no longer
1001 * used. Instead, 8254 based systimers are used for all major clock
1002 * interrupts. statclock_disable is set by default.
1005 cpu_initclocks(void *arg __unused)
1009 int apic_8254_trial;
1011 #endif /* APIC_IO */
1013 callout_init(&sysbeepstop_ch);
1015 if (statclock_disable) {
1017 * The stat interrupt mask is different without the
1018 * statistics clock. Also, don't set the interrupt
1019 * flag which would normally cause the RTC to generate
1022 rtc_statusb = RTCSB_24HR;
1024 /* Setting stathz to nonzero early helps avoid races. */
1025 stathz = RTC_NOPROFRATE;
1026 profhz = RTC_PROFRATE;
1029 /* Finish initializing 8253 timer 0. */
1032 apic_8254_intr = isa_apic_irq(0);
1033 apic_8254_trial = 0;
1034 if (apic_8254_intr >= 0 ) {
1035 if (apic_int_type(0, 0) == 3)
1036 apic_8254_trial = 1;
1038 /* look for ExtInt on pin 0 */
1039 if (apic_int_type(0, 0) == 3) {
1040 apic_8254_intr = apic_irq(0, 0);
1041 setup_8254_mixed_mode();
1043 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1046 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1048 INTR_EXCL | INTR_FAST |
1049 INTR_NOPOLL | INTR_MPSAFE |
1051 machintr_intren(apic_8254_intr);
1055 register_int(0, clkintr, NULL, "clk", NULL,
1056 INTR_EXCL | INTR_FAST |
1057 INTR_NOPOLL | INTR_MPSAFE |
1059 machintr_intren(ICU_IRQ0);
1061 #endif /* APIC_IO */
1063 /* Initialize RTC. */
1064 writertc(RTC_STATUSA, rtc_statusa);
1065 writertc(RTC_STATUSB, RTCSB_24HR);
1067 if (statclock_disable == 0) {
1068 diag = rtcin(RTC_DIAG);
1070 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1073 if (isa_apic_irq(8) != 8)
1074 panic("APIC RTC != 8");
1075 #endif /* APIC_IO */
1077 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL,
1078 INTR_EXCL | INTR_FAST | INTR_NOPOLL |
1082 writertc(RTC_STATUSB, rtc_statusb);
1086 if (apic_8254_trial) {
1091 * Following code assumes the 8254 is the cpu timer,
1092 * so make sure it is.
1094 KKASSERT(sys_cputimer == &i8254_cputimer);
1096 lastcnt = get_interrupt_counter(apic_8254_intr);
1099 * Force an 8254 Timer0 interrupt and wait 1/100s for
1100 * it to happen, then see if we got it.
1102 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1103 i8254_intr_reload(2);
1104 base = sys_cputimer->count();
1105 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1107 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1109 * The MP table is broken.
1110 * The 8254 was not connected to the specified pin
1112 * Workaround: Limited variant of mixed mode.
1114 machintr_intrdis(apic_8254_intr);
1115 unregister_int(clkdesc);
1116 kprintf("APIC_IO: Broken MP table detected: "
1117 "8254 is not connected to "
1118 "IOAPIC #%d intpin %d\n",
1119 int_to_apicintpin[apic_8254_intr].ioapic,
1120 int_to_apicintpin[apic_8254_intr].int_pin);
1122 * Revoke current ISA IRQ 0 assignment and
1123 * configure a fallback interrupt routing from
1124 * the 8254 Timer via the 8259 PIC to the
1125 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1126 * We reuse the low level interrupt handler number.
1128 if (apic_irq(0, 0) < 0) {
1129 revoke_apic_irq(apic_8254_intr);
1130 assign_apic_irq(0, 0, apic_8254_intr);
1132 apic_8254_intr = apic_irq(0, 0);
1133 setup_8254_mixed_mode();
1134 register_int(apic_8254_intr, clkintr, NULL, "clk",
1136 INTR_EXCL | INTR_FAST |
1137 INTR_NOPOLL | INTR_MPSAFE |
1139 machintr_intren(apic_8254_intr);
1143 if (apic_int_type(0, 0) != 3 ||
1144 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1145 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1146 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1147 int_to_apicintpin[apic_8254_intr].ioapic,
1148 int_to_apicintpin[apic_8254_intr].int_pin);
1151 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1155 SYSINIT(clocks8254, SI_BOOT2_CLOCKREG, SI_ORDER_FIRST, cpu_initclocks, NULL)
1160 setup_8254_mixed_mode(void)
1163 * Allow 8254 timer to INTerrupt 8259:
1164 * re-initialize master 8259:
1165 * reset; prog 4 bytes, single ICU, edge triggered
1167 outb(IO_ICU1, 0x13);
1168 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1169 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1170 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1171 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1173 /* program IO APIC for type 3 INT on INT0 */
1174 if (ext_int_setup(0, 0) < 0)
1175 panic("8254 redirect via APIC pin0 impossible!");
1180 setstatclockrate(int newhz)
1182 if (newhz == RTC_PROFRATE)
1183 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1185 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1186 writertc(RTC_STATUSA, rtc_statusa);
1191 tsc_get_timecount(struct timecounter *tc)
1197 #ifdef KERN_TIMESTAMP
1198 #define KERN_TIMESTAMP_SIZE 16384
1199 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1200 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1201 sizeof(tsc), "LU", "Kernel timestamps");
1207 tsc[i] = (u_int32_t)rdtsc();
1210 if (i >= KERN_TIMESTAMP_SIZE)
1212 tsc[i] = 0; /* mark last entry */
1214 #endif /* KERN_TIMESTAMP */
1221 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1228 if (sys_cputimer == &i8254_cputimer)
1229 count = sys_cputimer->count();
1237 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1238 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1241 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1242 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1244 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1245 0, 0, hw_i8254_timestamp, "A", "");
1247 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1248 &tsc_present, 0, "TSC Available");
1249 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1250 &tsc_frequency, 0, "TSC Frequency");