1 /* $FreeBSD: src/sys/dev/iir/iir.h,v 1.3.2.2 2002/05/04 08:49:50 msmith Exp $ */
2 /* $DragonFly: src/sys/dev/raid/iir/iir.h,v 1.6 2006/09/10 01:26:35 dillon Exp $ */
4 * Copyright (c) 2000-01 Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * iir.h: Definitions/Constants used by the Intel Integrated RAID driver
37 * Written by: Achim Leubner <achim.leubner@intel.com>
38 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
40 * credits: Niklas Hallqvist; OpenBSD driver for the ICP Controllers.
41 * FreeBSD.ORG; Great O/S to work on and for.
45 #ident "$Id: iir.h 1.3 2001/07/03 11:28:57 achim Exp $"
50 #define IIR_DRIVER_VERSION 1
51 #define IIR_DRIVER_SUBVERSION 1
53 #define IIR_CDEV_MAJOR 164
55 #define GDT_VENDOR_ID 0x1119
56 #define GDT_DEVICE_ID_MIN 0x100
57 #define GDT_DEVICE_ID_MAX 0x2ff
58 #define GDT_DEVICE_ID_NEWRX 0x300
60 #define INTEL_VENDOR_ID 0x8086
61 #define INTEL_DEVICE_ID_IIR 0x600
63 #define GDT_MAXBUS 6 /* XXX Why not 5? */
64 #define GDT_MAX_HDRIVES 100 /* max 100 host drives */
65 #define GDT_MAXID_FC 127 /* Fibre-channel IDs */
66 #define GDT_MAXID 16 /* SCSI IDs */
67 #define GDT_MAXOFFSETS 128
68 #define GDT_MAXSG 32 /* Max. s/g elements */
69 #define GDT_PROTOCOL_VERSION 1
70 #define GDT_LINUX_OS 8 /* Used for cache optimization */
71 #define GDT_SCATTER_GATHER 1 /* s/g feature */
72 #define GDT_SECS32 0x1f /* round capacity */
73 #define GDT_LOCALBOARD 0 /* Board node always 0 */
74 #define GDT_MAXCMDS 124
75 #define GDT_SECTOR_SIZE 0x200 /* Always 512 bytes for cache devs */
76 #define GDT_MAX_EVENTS 0x100 /* event buffer */
79 #define GDT_MPR_MAGIC 0xc0ffee11
80 #define GDT_IC_HEADER_BYTES 48
81 #define GDT_IC_QUEUE_BYTES 4
82 #define GDT_DPMEM_COMMAND_OFFSET \
83 (GDT_IC_HEADER_BYTES + GDT_IC_QUEUE_BYTES * GDT_MAXOFFSETS)
85 /* geometry constants */
86 #define GDT_MAXCYLS 1024
88 #define GDT_SECS 32 /* mapping 64*32 */
89 #define GDT_MEDHEADS 127
90 #define GDT_MEDSECS 63 /* mapping 127*63 */
91 #define GDT_BIGHEADS 255
92 #define GDT_BIGSECS 63 /* mapping 255*63 */
94 /* data direction raw service */
95 #define GDT_DATA_IN 0x01000000L
96 #define GDT_DATA_OUT 0x00000000L
98 /* Cache/raw service commands */
99 #define GDT_INIT 0 /* service initialization */
100 #define GDT_READ 1 /* read command */
101 #define GDT_WRITE 2 /* write command */
102 #define GDT_INFO 3 /* information about devices */
103 #define GDT_FLUSH 4 /* flush dirty cache buffers */
104 #define GDT_IOCTL 5 /* ioctl command */
105 #define GDT_DEVTYPE 9 /* additional information */
106 #define GDT_MOUNT 10 /* mount cache device */
107 #define GDT_UNMOUNT 11 /* unmount cache device */
108 #define GDT_SET_FEAT 12 /* set features (scatter/gather) */
109 #define GDT_GET_FEAT 13 /* get features */
110 #define GDT_WRITE_THR 16 /* write through */
111 #define GDT_READ_THR 17 /* read through */
112 #define GDT_EXT_INFO 18 /* extended info */
113 #define GDT_RESET 19 /* controller reset */
114 #define GDT_FREEZE_IO 25 /* freeze all IOs */
115 #define GDT_UNFREEZE_IO 26 /* unfreeze all IOs */
117 /* Additional raw service commands */
118 #define GDT_RESERVE 14 /* reserve device to raw service */
119 #define GDT_RELEASE 15 /* release device */
120 #define GDT_RESERVE_ALL 16 /* reserve all devices */
121 #define GDT_RELEASE_ALL 17 /* release all devices */
122 #define GDT_RESET_BUS 18 /* reset bus */
123 #define GDT_SCAN_START 19 /* start device scan */
124 #define GDT_SCAN_END 20 /* stop device scan */
126 /* IOCTL command defines */
127 #define GDT_SCSI_DR_INFO 0x00 /* SCSI drive info */
128 #define GDT_SCSI_CHAN_CNT 0x05 /* SCSI channel count */
129 #define GDT_SCSI_DR_LIST 0x06 /* SCSI drive list */
130 #define GDT_SCSI_DEF_CNT 0x15 /* grown/primary defects */
131 #define GDT_DSK_STATISTICS 0x4b /* SCSI disk statistics */
132 #define GDT_IOCHAN_DESC 0x5d /* description of IO channel */
133 #define GDT_IOCHAN_RAW_DESC 0x5e /* description of raw IO channel */
135 #define GDT_L_CTRL_PATTERN 0x20000000 /* SCSI IOCTL mask */
136 #define GDT_ARRAY_INFO 0x12 /* array drive info */
137 #define GDT_ARRAY_DRV_LIST 0x0f /* array drive list */
138 #define GDT_LA_CTRL_PATTERN 0x10000000 /* array IOCTL mask */
139 #define GDT_CACHE_DRV_CNT 0x01 /* cache drive count */
140 #define GDT_CACHE_DRV_LIST 0x02 /* cache drive list */
141 #define GDT_CACHE_INFO 0x04 /* cache info */
142 #define GDT_CACHE_CONFIG 0x05 /* cache configuration */
143 #define GDT_CACHE_DRV_INFO 0x07 /* cache drive info */
144 #define GDT_BOARD_FEATURES 0x15 /* controller features */
145 #define GDT_BOARD_INFO 0x28 /* controller info */
146 #define GDT_HOST_GET 0x10001 /* get host drive list */
147 #define GDT_IO_CHANNEL 0x20000 /* default IO channel */
148 #define GDT_INVALID_CHANNEL 0xffff /* invalid channel */
151 #define GDT_IOCTL_GENERAL _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
152 #define GDT_IOCTL_DRVERS _IOWR('J', 1, int) /* get driver version */
153 #define GDT_IOCTL_CTRTYPE _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */
154 #define GDT_IOCTL_OSVERS _IOR('J', 3, gdt_osv_t) /* get OS version */
155 #define GDT_IOCTL_CTRCNT _IOR('J', 5, int) /* get ctr. count */
156 #define GDT_IOCTL_EVENT _IOWR('J', 8, gdt_event_t) /* get event */
157 #define GDT_IOCTL_STATIST _IOR('J', 9, gdt_statist_t) /* get statistics */
160 #define GDT_S_OK 1 /* no error */
161 #define GDT_S_BSY 7 /* controller busy */
162 #define GDT_S_RAW_SCSI 12 /* raw service: target error */
163 #define GDT_S_RAW_ILL 0xff /* raw service: illegal */
164 #define GDT_S_NO_STATUS 0x1000 /* got no status (driver-generated) */
166 /* Controller services */
167 #define GDT_SCSIRAWSERVICE 3
168 #define GDT_CACHESERVICE 9
169 #define GDT_SCREENSERVICE 11
171 /* Scatter/gather element */
172 #define GDT_SG_PTR 0x00 /* u_int32_t, address */
173 #define GDT_SG_LEN 0x04 /* u_int32_t, length */
174 #define GDT_SG_SZ 0x08
176 /* Cache service command */
177 #define GDT_CACHE_DEVICENO 0x00 /* u_int16_t, number of cache drive */
178 #define GDT_CACHE_BLOCKNO 0x02 /* u_int32_t, block number */
179 #define GDT_CACHE_BLOCKCNT 0x06 /* u_int32_t, block count */
180 #define GDT_CACHE_DESTADDR 0x0a /* u_int32_t, dest. addr. (-1: s/g) */
181 #define GDT_CACHE_SG_CANZ 0x0e /* u_int32_t, s/g element count */
182 #define GDT_CACHE_SG_LST 0x12 /* [GDT_MAXSG], s/g list */
183 #define GDT_CACHE_SZ (0x12 + GDT_MAXSG * GDT_SG_SZ)
186 #define GDT_IOCTL_PARAM_SIZE 0x00 /* u_int16_t, size of buffer */
187 #define GDT_IOCTL_SUBFUNC 0x02 /* u_int32_t, ioctl function */
188 #define GDT_IOCTL_CHANNEL 0x06 /* u_int32_t, device */
189 #define GDT_IOCTL_P_PARAM 0x0a /* u_int32_t, buffer */
190 #define GDT_IOCTL_SZ 0x0e
192 /* Screen service defines */
193 #define GDT_MSG_INV_HANDLE -1 /* special message handle */
194 #define GDT_MSGLEN 16 /* size of message text */
195 #define GDT_MSG_SIZE 34 /* size of message structure */
196 #define GDT_MSG_REQUEST 0 /* async. event. message */
198 /* Screen service command */
199 #define GDT_SCREEN_MSG_HANDLE 0x02 /* u_int32_t, message handle */
200 #define GDT_SCREEN_MSG_ADDR 0x06 /* u_int32_t, message buffer address */
201 #define GDT_SCREEN_SZ 0x0a
203 /* Screen service message */
204 #define GDT_SCR_MSG_HANDLE 0x00 /* u_int32_t, message handle */
205 #define GDT_SCR_MSG_LEN 0x04 /* u_int32_t, size of message */
206 #define GDT_SCR_MSG_ALEN 0x08 /* u_int32_t, answer length */
207 #define GDT_SCR_MSG_ANSWER 0x0c /* u_int8_t, answer flag */
208 #define GDT_SCR_MSG_EXT 0x0d /* u_int8_t, more messages? */
209 #define GDT_SCR_MSG_RES 0x0e /* u_int16_t, reserved */
210 #define GDT_SCR_MSG_TEXT 0x10 /* GDT_MSGLEN+2, message text */
211 #define GDT_SCR_MSG_SZ (0x12 + GDT_MSGLEN)
213 /* Raw service command */
214 #define GDT_RAW_DIRECTION 0x02 /* u_int32_t, data direction */
215 #define GDT_RAW_MDISC_TIME 0x06 /* u_int32_t, disc. time (0: none) */
216 #define GDT_RAW_MCON_TIME 0x0a /* u_int32_t, conn. time (0: none) */
217 #define GDT_RAW_SDATA 0x0e /* u_int32_t, dest. addr. (-1: s/g) */
218 #define GDT_RAW_SDLEN 0x12 /* u_int32_t, data length */
219 #define GDT_RAW_CLEN 0x16 /* u_int32_t, SCSI cmd len (6/10/12) */
220 #define GDT_RAW_CMD 0x1a /* u_int8_t [12], SCSI command */
221 #define GDT_RAW_TARGET 0x26 /* u_int8_t, target ID */
222 #define GDT_RAW_LUN 0x27 /* u_int8_t, LUN */
223 #define GDT_RAW_BUS 0x28 /* u_int8_t, SCSI bus number */
224 #define GDT_RAW_PRIORITY 0x29 /* u_int8_t, only 0 used */
225 #define GDT_RAW_SENSE_LEN 0x2a /* u_int32_t, sense data length */
226 #define GDT_RAW_SENSE_DATA 0x2e /* u_int32_t, sense data address */
227 #define GDT_RAW_SG_RANZ 0x36 /* u_int32_t, s/g element count */
228 #define GDT_RAW_SG_LST 0x3a /* [GDT_MAXSG], s/g list */
229 #define GDT_RAW_SZ (0x3a + GDT_MAXSG * GDT_SG_SZ)
231 /* Command structure */
232 #define GDT_CMD_BOARDNODE 0x00 /* u_int32_t, board node (always 0) */
233 #define GDT_CMD_COMMANDINDEX 0x04 /* u_int32_t, command number */
234 #define GDT_CMD_OPCODE 0x08 /* u_int16_t, opcode (READ, ...) */
235 #define GDT_CMD_UNION 0x0a /* cache/screen/raw service command */
236 #define GDT_CMD_UNION_SZ GDT_RAW_SZ
237 #define GDT_CMD_SZ (0x0a + GDT_CMD_UNION_SZ)
239 /* Command queue entries */
240 #define GDT_OFFSET 0x00 /* u_int16_t, command offset in the DP RAM */
241 #define GDT_SERV_ID 0x02 /* u_int16_t, service */
242 #define GDT_COMM_Q_SZ 0x04
245 #define GDT_S_CMD_INDX 0x00 /* u_int8_t, special command */
246 #define GDT_S_STATUS 0x01 /* volatile u_int8_t, status special command */
247 #define GDT_S_INFO 0x04 /* u_int32_t [4], add. info special command */
248 #define GDT_SEMA0 0x14 /* volatile u_int8_t, command semaphore */
249 #define GDT_CMD_INDEX 0x18 /* u_int8_t, command number */
250 #define GDT_STATUS 0x1c /* volatile u_int16_t, command status */
251 #define GDT_SERVICE 0x1e /* u_int16_t, service (for asynch. events) */
252 #define GDT_DPR_INFO 0x20 /* u_int32_t [2], additional info */
253 #define GDT_COMM_QUEUE 0x28 /* command queue */
254 #define GDT_DPR_CMD (0x30 + GDT_MAXOFFSETS * GDT_COMM_Q_SZ)
255 /* u_int8_t [], commands */
257 /* I/O channel header */
258 #define GDT_IOC_VERSION 0x00 /* u_int32_t, version (~0: newest) */
259 #define GDT_IOC_LIST_ENTRIES 0x04 /* u_int8_t, list entry count */
260 #define GDT_IOC_FIRST_CHAN 0x05 /* u_int8_t, first channel number */
261 #define GDT_IOC_LAST_CHAN 0x06 /* u_int8_t, last channel number */
262 #define GDT_IOC_CHAN_COUNT 0x07 /* u_int8_t, (R) channel count */
263 #define GDT_IOC_LIST_OFFSET 0x08 /* u_int32_t, offset of list[0] */
264 #define GDT_IOC_HDR_SZ 0x0c
266 #define GDT_IOC_NEWEST 0xffffffff /* goes into GDT_IOC_VERSION */
268 /* Get I/O channel description */
269 #define GDT_IOC_ADDRESS 0x00 /* u_int32_t, channel address */
270 #define GDT_IOC_TYPE 0x04 /* u_int8_t, type (SCSI/FCSL) */
271 #define GDT_IOC_LOCAL_NO 0x05 /* u_int8_t, local number */
272 #define GDT_IOC_FEATURES 0x06 /* u_int16_t, channel features */
273 #define GDT_IOC_SZ 0x08
275 /* Get raw I/O channel description */
276 #define GDT_RAWIOC_PROC_ID 0x00 /* u_int8_t, processor id */
277 #define GDT_RAWIOC_PROC_DEFECT 0x01 /* u_int8_t, defect? */
278 #define GDT_RAWIOC_SZ 0x04
280 /* Get SCSI channel count */
281 #define GDT_GETCH_CHANNEL_NO 0x00 /* u_int32_t, channel number */
282 #define GDT_GETCH_DRIVE_CNT 0x04 /* u_int32_t, drive count */
283 #define GDT_GETCH_SIOP_ID 0x08 /* u_int8_t, SCSI processor ID */
284 #define GDT_GETCH_SIOP_STATE 0x09 /* u_int8_t, SCSI processor state */
285 #define GDT_GETCH_SZ 0x0a
287 /* Cache info/config IOCTL structures */
288 #define GDT_CPAR_VERSION 0x00 /* u_int32_t, firmware version */
289 #define GDT_CPAR_STATE 0x04 /* u_int16_t, cache state (on/off) */
290 #define GDT_CPAR_STRATEGY 0x06 /* u_int16_t, cache strategy */
291 #define GDT_CPAR_WRITE_BACK 0x08 /* u_int16_t, write back (on/off) */
292 #define GDT_CPAR_BLOCK_SIZE 0x0a /* u_int16_t, cache block size */
293 #define GDT_CPAR_SZ 0x0c
295 #define GDT_CSTAT_CSIZE 0x00 /* u_int32_t, cache size */
296 #define GDT_CSTAT_READ_CNT 0x04 /* u_int32_t, read counter */
297 #define GDT_CSTAT_WRITE_CNT 0x08 /* u_int32_t, write counter */
298 #define GDT_CSTAT_TR_HITS 0x0c /* u_int32_t, track hits */
299 #define GDT_CSTAT_SEC_HITS 0x10 /* u_int32_t, sector hits */
300 #define GDT_CSTAT_SEC_MISS 0x14 /* u_int32_t, sector misses */
301 #define GDT_CSTAT_SZ 0x18
304 #define GDT_CINFO_CPAR 0x00
305 #define GDT_CINFO_CSTAT GDT_CPAR_SZ
306 #define GDT_CINFO_SZ (GDT_CPAR_SZ + GDT_CSTAT_SZ)
309 #define GDT_BINFO_SER_NO 0x00 /* u_int32_t, serial number */
310 #define GDT_BINFO_OEM_ID 0x04 /* u_int8_t [2], OEM ID */
311 #define GDT_BINFO_EP_FLAGS 0x06 /* u_int16_t, eprom flags */
312 #define GDT_BINFO_PROC_ID 0x08 /* u_int32_t, processor ID */
313 #define GDT_BINFO_MEMSIZE 0x0c /* u_int32_t, memory size (bytes) */
314 #define GDT_BINFO_MEM_BANKS 0x10 /* u_int8_t, memory banks */
315 #define GDT_BINFO_CHAN_TYPE 0x11 /* u_int8_t, channel type */
316 #define GDT_BINFO_CHAN_COUNT 0x12 /* u_int8_t, channel count */
317 #define GDT_BINFO_RDONGLE_PRES 0x13 /* u_int8_t, dongle present */
318 #define GDT_BINFO_EPR_FW_VER 0x14 /* u_int32_t, (eprom) firmware ver */
319 #define GDT_BINFO_UPD_FW_VER 0x18 /* u_int32_t, (update) firmware ver */
320 #define GDT_BINFO_UPD_REVISION 0x1c /* u_int32_t, update revision */
321 #define GDT_BINFO_TYPE_STRING 0x20 /* char [16], controller name */
322 #define GDT_BINFO_RAID_STRING 0x30 /* char [16], RAID firmware name */
323 #define GDT_BINFO_UPDATE_PRES 0x40 /* u_int8_t, update present? */
324 #define GDT_BINFO_XOR_PRES 0x41 /* u_int8_t, XOR engine present */
325 #define GDT_BINFO_PROM_TYPE 0x42 /* u_int8_t, ROM type (eprom/flash) */
326 #define GDT_BINFO_PROM_COUNT 0x43 /* u_int8_t, number of ROM devices */
327 #define GDT_BINFO_DUP_PRES 0x44 /* u_int32_t, duplexing module pres? */
328 #define GDT_BINFO_CHAN_PRES 0x48 /* u_int32_t, # of exp. channels */
329 #define GDT_BINFO_MEM_PRES 0x4c /* u_int32_t, memory expansion inst? */
330 #define GDT_BINFO_FT_BUS_SYSTEM 0x50 /* u_int8_t, fault bus supported? */
331 #define GDT_BINFO_SUBTYPE_VALID 0x51 /* u_int8_t, board_subtype valid */
332 #define GDT_BINFO_BOARD_SUBTYPE 0x52 /* u_int8_t, subtype/hardware level */
333 #define GDT_BINFO_RAMPAR_PRES 0x53 /* u_int8_t, RAM parity check hw? */
334 #define GDT_BINFO_SZ 0x54
336 /* Get board features */
337 #define GDT_BFEAT_CHAINING 0x00 /* u_int8_t, chaining supported */
338 #define GDT_BFEAT_STRIPING 0x01 /* u_int8_t, striping (RAID-0) supp. */
339 #define GDT_BFEAT_MIRRORING 0x02 /* u_int8_t, mirroring (RAID-1) supp */
340 #define GDT_BFEAT_RAID 0x03 /* u_int8_t, RAID-4/5/10 supported */
341 #define GDT_BFEAT_SZ 0x04
344 #define GDT_ASYNCINDEX 0 /* command index asynchronous event */
345 #define GDT_SPEZINDEX 1 /* command index unknown service */
349 #define GDT_D_INTR 0x01
350 #define GDT_D_MISC 0x02
351 #define GDT_D_CMD 0x04
352 #define GDT_D_QUEUE 0x08
353 #define GDT_D_TIMEOUT 0x10
354 #define GDT_D_INIT 0x20
355 #define GDT_D_INVALID 0x40
356 #define GDT_D_DEBUG 0x80
357 extern int gdt_debug;
359 extern int ser_printf(const char *fmt, ...);
360 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) ser_printf args
362 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args
365 #define GDT_DPRINTF(mask, args)
368 /* Miscellaneous constants */
369 #define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
370 #define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
371 #define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
372 #define GDT_WATCH_TIMEOUT 10000000 /* 10000 * 1us = 10s */
373 #define GDT_SCRATCH_SZ 3072 /* 3KB scratch buffer */
376 #define htole32(v) (v)
377 #define htole16(v) (v)
378 #define letoh32(v) (v)
379 #define letoh16(v) (v)
381 /* Map minor numbers to device identity */
382 #define LUN_MASK 0x0007
383 #define TARGET_MASK 0x03f8
384 #define BUS_MASK 0x1c00
385 #define HBA_MASK 0xe000
387 #define minor2lun(minor) ( minor & LUN_MASK )
388 #define minor2target(minor) ( (minor & TARGET_MASK) >> 3 )
389 #define minor2bus(minor) ( (minor & BUS_MASK) >> 10 )
390 #define minor2hba(minor) ( (minor & HBA_MASK) >> 13 )
391 #define hba2minor(hba) ( (hba << 13) & HBA_MASK )
394 /* struct for GDT_IOCTL_GENERAL */
396 typedef struct gdt_ucmd {
403 u_int32_t BoardNode; /* board node (always 0) */
404 u_int32_t CommandIndex; /* command number */
405 u_int16_t OpCode; /* the command (READ,..) */
408 u_int16_t DeviceNo; /* number of cache drive */
409 u_int32_t BlockNo; /* block number */
410 u_int32_t BlockCnt; /* block count */
411 void *DestAddr; /* data */
412 } cache; /* cache service cmd. str. */
414 u_int16_t param_size; /* size of p_param buffer */
415 u_int32_t subfunc; /* IOCTL function */
416 u_int32_t channel; /* device */
417 void *p_param; /* data */
418 } ioctl; /* IOCTL command structure */
421 u_int32_t direction; /* data direction */
422 u_int32_t mdisc_time; /* disc. time (0: no timeout)*/
423 u_int32_t mcon_time; /* connect time(0: no to.) */
424 void *sdata; /* dest. addr. (if s/g: -1) */
425 u_int32_t sdlen; /* data length (bytes) */
426 u_int32_t clen; /* SCSI cmd. length(6,10,12) */
427 u_int8_t cmd[12]; /* SCSI command */
428 u_int8_t target; /* target ID */
429 u_int8_t lun; /* LUN */
430 u_int8_t bus; /* SCSI bus number */
431 u_int8_t priority; /* only 0 used */
432 u_int32_t sense_len; /* sense data length */
433 void *sense_data; /* sense data addr. */
434 u_int32_t link_p; /* linked cmds (not supp.) */
435 } raw; /* raw service cmd. struct. */
437 u_int8_t data[GDT_SCRATCH_SZ];
439 TAILQ_ENTRY(gdt_ucmd) links;
442 /* struct for GDT_IOCTL_CTRTYPE */
443 typedef struct gdt_ctrt {
452 u_int16_t sub_device_id;
455 /* struct for GDT_IOCTL_OSVERS */
456 typedef struct gdt_osv {
464 /* controller event structure */
465 #define GDT_ES_ASYNC 1
466 #define GDT_ES_DRIVER 2
467 #define GDT_ES_TEST 3
468 #define GDT_ES_SYNC 4
470 u_int16_t size; /* size of structure */
483 u_int8_t scsi_coord[3];
491 u_int8_t scsi_coord[3];
495 u_int32_t l1, l2, l3, l4;
499 u_int8_t event_string[256];
502 /* dvrevt structure */
504 u_int32_t first_stamp;
505 u_int32_t last_stamp;
506 u_int16_t same_count;
507 u_int16_t event_source;
509 u_int8_t application;
511 gdt_evt_data event_data;
514 /* struct for GDT_IOCTL_EVENT */
515 typedef struct gdt_event {
521 /* struct for GDT_IOCTL_STATIST */
522 typedef struct gdt_statist {
523 u_int16_t io_count_act;
524 u_int16_t io_count_max;
525 u_int16_t req_queue_act;
526 u_int16_t req_queue_max;
527 u_int16_t cmd_index_act;
528 u_int16_t cmd_index_max;
529 u_int16_t sg_count_act;
530 u_int16_t sg_count_max;
535 /* Context structure for interrupt services */
536 struct gdt_intr_ctx {
537 u_int32_t info, info2;
538 u_int16_t cmd_status, service;
542 /* softc structure */
545 int sc_class; /* Controller class */
547 #define GDT_CLASS_MASK 0x07
549 #define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
551 u_int16_t sc_device, sc_subdevice;
552 u_int16_t sc_fw_vers;
555 #define GDT_NORMAL 0x00
556 #define GDT_POLLING 0x01
557 #define GDT_SHUTDOWN 0x02
558 #define GDT_POLL_WAIT 0x80
559 struct callout watchdog_timer;
561 bus_space_tag_t sc_dpmemt;
562 bus_space_handle_t sc_dpmemh;
563 bus_addr_t sc_dpmembase;
564 bus_dma_tag_t sc_parent_dmat;
565 bus_dma_tag_t sc_buffer_dmat;
566 bus_dma_tag_t sc_gccb_dmat;
567 bus_dmamap_t sc_gccb_dmamap;
568 bus_addr_t sc_gccb_busbase;
570 struct gdt_ccb *sc_gccbs;
571 SLIST_HEAD(, gdt_ccb) sc_free_gccb, sc_pending_gccb;
572 TAILQ_HEAD(, ccb_hdr) sc_ccb_queue;
573 TAILQ_HEAD(, gdt_ucmd) sc_ucmd_queue;
575 u_int16_t sc_ic_all_size;
576 u_int16_t sc_cmd_len;
577 u_int16_t sc_cmd_off;
578 u_int16_t sc_cmd_cnt;
579 u_int8_t sc_cmd[GDT_CMD_SZ];
584 u_int16_t sc_service;
587 u_int8_t sc_virt_bus;
588 u_int8_t sc_bus_id[GDT_MAXBUS];
589 u_int8_t sc_more_proc;
593 u_int8_t hd_is_logdrv;
594 u_int8_t hd_is_arraydrv;
595 u_int8_t hd_is_master;
596 u_int8_t hd_is_parity;
597 u_int8_t hd_is_hotfix;
598 u_int8_t hd_master_no;
602 u_int16_t hd_devtype;
605 u_int8_t hd_rw_attribs;
606 u_int32_t hd_start_sec;
607 } sc_hdr[GDT_MAX_HDRIVES];
609 u_int16_t sc_raw_feat;
610 u_int16_t sc_cache_feat;
614 struct cam_sim *sims[GDT_MAXBUS];
615 struct cam_path *paths[GDT_MAXBUS];
617 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
618 u_int8_t (*sc_get_status)(struct gdt_softc *);
619 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
620 void (*sc_release_event)(struct gdt_softc *);
621 void (*sc_set_sema0)(struct gdt_softc *);
622 int (*sc_test_busy)(struct gdt_softc *);
624 TAILQ_ENTRY(gdt_softc) links;
628 * A command control block, one for each corresponding command index of the
632 u_int8_t gc_scratch[GDT_SCRATCH_SZ];
635 bus_dmamap_t gc_dmamap;
640 u_int8_t gc_cmd_index;
642 #define GDT_GCF_UNUSED 0
643 #define GDT_GCF_INTERNAL 1
644 #define GDT_GCF_SCREEN 2
645 #define GDT_GCF_SCSI 3
646 #define GDT_GCF_IOCTL 4
647 SLIST_ENTRY(gdt_ccb) sle;
651 int iir_init(struct gdt_softc *);
652 void iir_free(struct gdt_softc *);
653 void iir_attach(struct gdt_softc *);
654 void iir_intr(void *arg);
657 /* These all require correctly aligned buffers */
658 static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
659 static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
660 static __inline__ u_int16_t gdt_dec16(u_int8_t *);
661 static __inline__ u_int32_t gdt_dec32(u_int8_t *);
663 static __inline__ void
664 gdt_enc16(u_int8_t *addr, u_int16_t value)
666 *(u_int16_t *)addr = htole16(value);
669 static __inline__ void
670 gdt_enc32(u_int8_t *addr, u_int32_t value)
672 *(u_int32_t *)addr = htole32(value);
675 static __inline__ u_int16_t
676 gdt_dec16(u_int8_t *addr)
678 return letoh16(*(u_int16_t *)addr);
681 static __inline__ u_int32_t
682 gdt_dec32(u_int8_t *addr)
684 return letoh32(*(u_int32_t *)addr);
688 extern TAILQ_HEAD(gdt_softc_list, gdt_softc) gdt_softcs;
689 extern u_int8_t gdt_polling;
691 cdev_t gdt_make_dev(int unit);
692 void gdt_destroy_dev(cdev_t dev);
693 void gdt_next(struct gdt_softc *gdt);
694 void gdt_free_ccb(struct gdt_softc *gdt, struct gdt_ccb *gccb);
696 gdt_evt_str *gdt_store_event(u_int16_t source, u_int16_t idx,
698 int gdt_read_event(int handle, gdt_evt_str *estr);
699 void gdt_readapp_event(u_int8_t app, gdt_evt_str *estr);
700 void gdt_clear_events(void);