2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
53 * $FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 253497 2013-07-20 13:52:40Z kib $
56 #include <sys/resourcevar.h>
57 #include <sys/sfbuf.h>
60 #include <drm/i915_drm.h>
62 #include "intel_drv.h"
63 #include "intel_ringbuffer.h"
64 #include <linux/completion.h>
66 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
67 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
68 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
69 unsigned alignment, bool map_and_fenceable);
71 static int i915_gem_phys_pwrite(struct drm_device *dev,
72 struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
73 uint64_t size, struct drm_file *file_priv);
75 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
77 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
78 uint32_t size, int tiling_mode);
79 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
81 static int i915_gem_object_set_cpu_read_domain_range(
82 struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
83 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
84 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
85 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
86 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
87 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
88 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
89 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
90 uint32_t flush_domains);
91 static void i915_gem_clear_fence_reg(struct drm_device *dev,
92 struct drm_i915_fence_reg *reg);
93 static void i915_gem_reset_fences(struct drm_device *dev);
94 static void i915_gem_lowmem(void *arg);
96 static int i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
97 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file);
99 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
100 long i915_gem_wired_pages_cnt;
102 /* some bookkeeping */
103 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
107 dev_priv->mm.object_count++;
108 dev_priv->mm.object_memory += size;
111 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
115 dev_priv->mm.object_count--;
116 dev_priv->mm.object_memory -= size;
120 i915_gem_wait_for_error(struct drm_device *dev)
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 struct completion *x = &dev_priv->error_completion;
126 if (!atomic_read(&dev_priv->mm.wedged))
130 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
131 * userspace. If it takes that long something really bad is going on and
132 * we should simply try to bail out and fail as gracefully as possible.
134 ret = wait_for_completion_interruptible_timeout(x, 10*hz);
136 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
138 } else if (ret < 0) {
142 if (atomic_read(&dev_priv->mm.wedged)) {
143 /* GPU is hung, bump the completion count to account for
144 * the token we just consumed so that we never hit zero and
145 * end up waiting upon a subsequent completion event that
148 spin_lock(&x->wait.lock);
150 spin_unlock(&x->wait.lock);
155 int i915_mutex_lock_interruptible(struct drm_device *dev)
159 ret = i915_gem_wait_for_error(dev);
163 ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
168 WARN_ON(i915_verify_lists(dev));
174 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
176 return (obj->gtt_space && !obj->active && obj->pin_count == 0);
180 i915_gem_init_ioctl(struct drm_device *dev, void *data,
181 struct drm_file *file)
183 struct drm_i915_gem_init *args;
184 drm_i915_private_t *dev_priv;
186 dev_priv = dev->dev_private;
189 if (args->gtt_start >= args->gtt_end ||
190 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
194 * XXXKIB. The second-time initialization should be guarded
197 lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
198 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
199 lockmgr(&dev->dev_lock, LK_RELEASE);
205 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
206 struct drm_file *file)
208 struct drm_i915_private *dev_priv;
209 struct drm_i915_gem_get_aperture *args;
210 struct drm_i915_gem_object *obj;
213 dev_priv = dev->dev_private;
216 if (!(dev->driver->driver_features & DRIVER_GEM))
221 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
222 pinned += obj->gtt_space->size;
225 args->aper_size = dev_priv->mm.gtt_total;
226 args->aper_available_size = args->aper_size - pinned;
232 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
235 struct drm_i915_gem_object *obj;
239 size = roundup(size, PAGE_SIZE);
243 obj = i915_gem_alloc_object(dev, size);
248 ret = drm_gem_handle_create(file, &obj->base, &handle);
250 drm_gem_object_release(&obj->base);
251 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
252 drm_free(obj, DRM_I915_GEM);
256 /* drop reference from allocate - handle holds it now */
257 drm_gem_object_unreference(&obj->base);
263 i915_gem_dumb_create(struct drm_file *file,
264 struct drm_device *dev,
265 struct drm_mode_create_dumb *args)
268 /* have to work out size/pitch and return them */
269 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
270 args->size = args->pitch * args->height;
271 return (i915_gem_create(file, dev, args->size, &args->handle));
274 int i915_gem_dumb_destroy(struct drm_file *file,
275 struct drm_device *dev,
279 return (drm_gem_handle_delete(file, handle));
283 * Creates a new mm object and returns a handle to it.
286 i915_gem_create_ioctl(struct drm_device *dev, void *data,
287 struct drm_file *file)
289 struct drm_i915_gem_create *args = data;
291 return (i915_gem_create(file, dev, args->size, &args->handle));
294 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
296 drm_i915_private_t *dev_priv;
298 dev_priv = obj->base.dev->dev_private;
299 return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
300 obj->tiling_mode != I915_TILING_NONE);
304 * Reads data from the object referenced by handle.
306 * On error, the contents of *data are undefined.
309 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
310 struct drm_file *file)
312 struct drm_i915_gem_pread *args;
315 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
316 args->offset, UIO_READ, file));
320 * Writes data to the object referenced by handle.
322 * On error, the contents of the buffer that were to be modified are undefined.
325 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
326 struct drm_file *file)
328 struct drm_i915_gem_pwrite *args;
331 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
332 args->offset, UIO_WRITE, file));
336 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
339 if (atomic_read(&dev_priv->mm.wedged)) {
340 struct completion *x = &dev_priv->error_completion;
341 bool recovery_complete;
343 /* Give the error handler a chance to run. */
344 spin_lock(&x->wait.lock);
345 recovery_complete = x->done > 0;
346 spin_unlock(&x->wait.lock);
348 /* Non-interruptible callers can't handle -EAGAIN, hence return
349 * -EIO unconditionally for these. */
353 /* Recovery complete, but still wedged means reset failure. */
354 if (recovery_complete)
364 * __wait_seqno - wait until execution of seqno has finished
365 * @ring: the ring expected to report seqno
367 * @interruptible: do an interruptible wait (normally yes)
368 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
370 * Returns 0 if the seqno was found within the alloted time. Else returns the
371 * errno with remaining time filled in timeout argument.
373 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
374 bool interruptible, struct timespec *timeout)
376 drm_i915_private_t *dev_priv = ring->dev->dev_private;
379 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
382 if (WARN_ON(!ring->irq_get(ring)))
385 if (!i915_seqno_passed(ring->get_seqno(ring,false), seqno)) {
387 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
388 if (ring->irq_get(ring)) {
389 int flags = dev_priv->mm.interruptible ? PCATCH : 0;
390 while (!i915_seqno_passed(ring->get_seqno(ring,false), seqno)
391 && !atomic_read(&dev_priv->mm.wedged) &&
393 ret = -lksleep(ring, &ring->irq_lock, flags,
397 lockmgr(&ring->irq_lock, LK_RELEASE);
399 lockmgr(&ring->irq_lock, LK_RELEASE);
400 if (_intel_wait_for(ring->dev,
401 i915_seqno_passed(ring->get_seqno(ring,false), seqno) ||
402 atomic_read(&dev_priv->mm.wedged), 3000,
415 * Waits for a sequence number to be signaled, and cleans up the
416 * request and object lists appropriately for that event.
419 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
421 struct drm_device *dev = ring->dev;
422 struct drm_i915_private *dev_priv = dev->dev_private;
423 bool interruptible = dev_priv->mm.interruptible;
424 struct drm_i915_gem_request *request;
427 DRM_LOCK_ASSERT(dev);
430 ret = i915_gem_check_wedge(dev_priv, interruptible);
434 if (seqno == ring->outstanding_lazy_request) {
435 request = kmalloc(sizeof(*request), DRM_I915_GEM,
440 ret = i915_add_request(ring, NULL, request);
442 drm_free(request, DRM_I915_GEM);
446 seqno = request->seqno;
449 return __wait_seqno(ring, seqno, interruptible, NULL);
453 * Ensures that all rendering to the object has completed and the object is
454 * safe to unbind from the GTT or access from the CPU.
457 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
463 seqno = obj->last_rendering_seqno;
468 ret = i915_wait_seqno(obj->ring, obj->last_rendering_seqno);
473 /* Manually manage the write flush as we may have not yet
474 * retired the buffer.
476 if (obj->last_rendering_seqno &&
477 i915_seqno_passed(seqno, obj->last_rendering_seqno)) {
478 obj->last_rendering_seqno = 0;
479 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
486 * Called when user space prepares to use an object with the CPU, either
487 * through the mmap ioctl's mapping or a GTT mapping.
490 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
491 struct drm_file *file)
493 struct drm_i915_gem_set_domain *args;
494 struct drm_i915_gem_object *obj;
495 uint32_t read_domains;
496 uint32_t write_domain;
499 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
503 read_domains = args->read_domains;
504 write_domain = args->write_domain;
506 if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
507 (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
508 (write_domain != 0 && read_domains != write_domain))
511 ret = i915_mutex_lock_interruptible(dev);
515 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
516 if (&obj->base == NULL) {
521 if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
522 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
526 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
528 drm_gem_object_unreference(&obj->base);
535 * Called when user space has done writes to this buffer
538 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
539 struct drm_file *file)
541 struct drm_i915_gem_sw_finish *args;
542 struct drm_i915_gem_object *obj;
547 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
549 ret = i915_mutex_lock_interruptible(dev);
552 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
553 if (&obj->base == NULL) {
557 if (obj->pin_count != 0)
558 i915_gem_object_flush_cpu_write_domain(obj);
559 drm_gem_object_unreference(&obj->base);
566 * Maps the contents of an object, returning the address it is mapped
569 * While the mapping holds a reference on the contents of the object, it doesn't
570 * imply a ref on the object itself.
573 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
574 struct drm_file *file)
576 struct drm_i915_gem_mmap *args;
577 struct drm_gem_object *obj;
586 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
589 obj = drm_gem_object_lookup(dev, file, args->handle);
596 map = &p->p_vmspace->vm_map;
597 size = round_page(args->size);
599 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
607 vm_object_hold(obj->vm_obj);
608 vm_object_reference_locked(obj->vm_obj);
609 vm_object_drop(obj->vm_obj);
611 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
612 PAGE_SIZE, /* align */
614 VM_MAPTYPE_NORMAL, /* maptype */
615 VM_PROT_READ | VM_PROT_WRITE, /* prot */
616 VM_PROT_READ | VM_PROT_WRITE, /* max */
617 MAP_SHARED /* cow */);
618 if (rv != KERN_SUCCESS) {
619 vm_object_deallocate(obj->vm_obj);
620 error = -vm_mmap_to_errno(rv);
622 args->addr_ptr = (uint64_t)addr;
626 drm_gem_object_unreference(obj);
631 * i915_gem_release_mmap - remove physical page mappings
632 * @obj: obj in question
634 * Preserve the reservation of the mmapping with the DRM core code, but
635 * relinquish ownership of the pages back to the system.
637 * It is vital that we remove the page mapping if we have mapped a tiled
638 * object through the GTT and then lose the fence register due to
639 * resource pressure. Similarly if the object has been moved out of the
640 * aperture, than pages mapped into userspace must be revoked. Removing the
641 * mapping will then trigger a page fault on the next user access, allowing
642 * fixup by i915_gem_fault().
645 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
651 if (!obj->fault_mappable)
654 devobj = cdev_pager_lookup(obj);
655 if (devobj != NULL) {
656 page_count = OFF_TO_IDX(obj->base.size);
658 VM_OBJECT_LOCK(devobj);
659 for (i = 0; i < page_count; i++) {
660 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
663 cdev_pager_free_page(devobj, m);
665 VM_OBJECT_UNLOCK(devobj);
666 vm_object_deallocate(devobj);
669 obj->fault_mappable = false;
673 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
677 if (INTEL_INFO(dev)->gen >= 4 ||
678 tiling_mode == I915_TILING_NONE)
681 /* Previous chips need a power-of-two fence region when tiling */
682 if (INTEL_INFO(dev)->gen == 3)
683 gtt_size = 1024*1024;
687 while (gtt_size < size)
694 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
695 * @obj: object to check
697 * Return the required GTT alignment for an object, taking into account
698 * potential fence register mapping.
701 i915_gem_get_gtt_alignment(struct drm_device *dev,
707 * Minimum alignment is 4k (GTT page size), but might be greater
708 * if a fence register is needed for the object.
710 if (INTEL_INFO(dev)->gen >= 4 ||
711 tiling_mode == I915_TILING_NONE)
715 * Previous chips need to be aligned to the size of the smallest
716 * fence register that can contain the object.
718 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
722 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
725 * @size: size of the object
726 * @tiling_mode: tiling mode of the object
728 * Return the required GTT alignment for an object, only taking into account
729 * unfenced tiled surface requirements.
732 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
737 if (tiling_mode == I915_TILING_NONE)
741 * Minimum alignment is 4k (GTT page size) for sane hw.
743 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
747 * Previous hardware however needs to be aligned to a power-of-two
748 * tile height. The simplest method for determining this is to reuse
749 * the power-of-tile object size.
751 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
755 i915_gem_mmap_gtt(struct drm_file *file,
756 struct drm_device *dev,
760 struct drm_i915_private *dev_priv;
761 struct drm_i915_gem_object *obj;
764 if (!(dev->driver->driver_features & DRIVER_GEM))
767 dev_priv = dev->dev_private;
769 ret = i915_mutex_lock_interruptible(dev);
773 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
774 if (&obj->base == NULL) {
779 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
784 if (obj->madv != I915_MADV_WILLNEED) {
785 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
790 ret = drm_gem_create_mmap_offset(&obj->base);
794 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
797 drm_gem_object_unreference(&obj->base);
804 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
806 * @data: GTT mapping ioctl data
807 * @file: GEM object info
809 * Simply returns the fake offset to userspace so it can mmap it.
810 * The mmap call will end up in drm_gem_mmap(), which will set things
811 * up so we can get faults in the handler above.
813 * The fault handler will take care of binding the object into the GTT
814 * (since it may have been evicted to make room for something), allocating
815 * a fence register, and mapping the appropriate aperture address into
819 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
820 struct drm_file *file)
822 struct drm_i915_private *dev_priv;
823 struct drm_i915_gem_mmap_gtt *args;
825 dev_priv = dev->dev_private;
828 return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
831 /* Immediately discard the backing storage */
833 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
837 vm_obj = obj->base.vm_obj;
838 VM_OBJECT_LOCK(vm_obj);
839 vm_object_page_remove(vm_obj, 0, 0, false);
840 VM_OBJECT_UNLOCK(vm_obj);
841 obj->madv = __I915_MADV_PURGED;
845 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
847 return obj->madv == I915_MADV_DONTNEED;
850 static inline void vm_page_reference(vm_page_t m)
852 vm_page_flag_set(m, PG_REFERENCED);
856 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
861 BUG_ON(obj->madv == __I915_MADV_PURGED);
863 if (obj->tiling_mode != I915_TILING_NONE)
864 i915_gem_object_save_bit_17_swizzle(obj);
865 if (obj->madv == I915_MADV_DONTNEED)
867 page_count = obj->base.size / PAGE_SIZE;
868 VM_OBJECT_LOCK(obj->base.vm_obj);
869 #if GEM_PARANOID_CHECK_GTT
870 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
872 for (i = 0; i < page_count; i++) {
876 if (obj->madv == I915_MADV_WILLNEED)
877 vm_page_reference(m);
878 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
879 vm_page_unwire(obj->pages[i], 1);
880 vm_page_wakeup(obj->pages[i]);
881 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
883 VM_OBJECT_UNLOCK(obj->base.vm_obj);
885 drm_free(obj->pages, DRM_I915_GEM);
890 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
893 struct drm_device *dev;
896 int page_count, i, j;
899 KASSERT(obj->pages == NULL, ("Obj already has pages"));
900 page_count = obj->base.size / PAGE_SIZE;
901 obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
903 vm_obj = obj->base.vm_obj;
904 VM_OBJECT_LOCK(vm_obj);
905 for (i = 0; i < page_count; i++) {
906 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
909 VM_OBJECT_UNLOCK(vm_obj);
910 if (i915_gem_object_needs_bit17_swizzle(obj))
911 i915_gem_object_do_bit_17_swizzle(obj);
915 for (j = 0; j < i; j++) {
917 vm_page_busy_wait(m, FALSE, "i915gem");
918 vm_page_unwire(m, 0);
920 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
922 VM_OBJECT_UNLOCK(vm_obj);
923 drm_free(obj->pages, DRM_I915_GEM);
929 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
930 struct intel_ring_buffer *ring, uint32_t seqno)
932 struct drm_device *dev = obj->base.dev;
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 struct drm_i915_fence_reg *reg;
937 KASSERT(ring != NULL, ("NULL ring"));
939 /* Add a reference if we're newly entering the active list. */
941 drm_gem_object_reference(&obj->base);
945 /* Move from whatever list we were on to the tail of execution. */
946 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
947 list_move_tail(&obj->ring_list, &ring->active_list);
949 obj->last_rendering_seqno = seqno;
950 if (obj->fenced_gpu_access) {
951 obj->last_fenced_seqno = seqno;
952 obj->last_fenced_ring = ring;
954 /* Bump MRU to take account of the delayed flush */
955 if (obj->fence_reg != I915_FENCE_REG_NONE) {
956 reg = &dev_priv->fence_regs[obj->fence_reg];
957 list_move_tail(®->lru_list,
958 &dev_priv->mm.fence_list);
964 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
966 list_del_init(&obj->ring_list);
967 obj->last_rendering_seqno = 0;
968 obj->last_fenced_seqno = 0;
972 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
974 struct drm_device *dev = obj->base.dev;
975 struct drm_i915_private *dev_priv = dev->dev_private;
977 if (obj->pin_count != 0)
978 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
980 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
982 KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
983 KASSERT(obj->active, ("Object not active"));
985 obj->last_fenced_ring = NULL;
987 i915_gem_object_move_off_active(obj);
988 obj->fenced_gpu_access = false;
991 obj->pending_gpu_write = false;
992 drm_gem_object_unreference(&obj->base);
997 WARN_ON(i915_verify_lists(dev));
1002 i915_gem_get_seqno(struct drm_device *dev)
1004 drm_i915_private_t *dev_priv = dev->dev_private;
1005 u32 seqno = dev_priv->next_seqno;
1007 /* reserve 0 for non-seqno */
1008 if (++dev_priv->next_seqno == 0)
1009 dev_priv->next_seqno = 1;
1015 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
1016 struct drm_i915_gem_request *request)
1018 drm_i915_private_t *dev_priv;
1019 struct drm_i915_file_private *file_priv;
1021 u32 request_ring_position;
1025 KASSERT(request != NULL, ("NULL request in add"));
1026 DRM_LOCK_ASSERT(ring->dev);
1027 dev_priv = ring->dev->dev_private;
1029 seqno = i915_gem_next_request_seqno(ring);
1030 request_ring_position = intel_ring_get_tail(ring);
1032 ret = ring->add_request(ring, &seqno);
1036 request->seqno = seqno;
1037 request->ring = ring;
1038 request->tail = request_ring_position;
1039 request->emitted_jiffies = ticks;
1040 was_empty = list_empty(&ring->request_list);
1041 list_add_tail(&request->list, &ring->request_list);
1044 file_priv = file->driver_priv;
1046 spin_lock(&file_priv->mm.lock);
1047 request->file_priv = file_priv;
1048 list_add_tail(&request->client_list,
1049 &file_priv->mm.request_list);
1050 spin_unlock(&file_priv->mm.lock);
1053 ring->outstanding_lazy_request = 0;
1055 if (!dev_priv->mm.suspended) {
1056 if (i915_enable_hangcheck) {
1057 mod_timer(&dev_priv->hangcheck_timer,
1058 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1061 queue_delayed_work(dev_priv->wq,
1062 &dev_priv->mm.retire_work,
1063 round_jiffies_up_relative(hz));
1064 intel_mark_busy(dev_priv->dev);
1071 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1073 struct drm_i915_file_private *file_priv = request->file_priv;
1078 DRM_LOCK_ASSERT(request->ring->dev);
1080 spin_lock(&file_priv->mm.lock);
1081 if (request->file_priv != NULL) {
1082 list_del(&request->client_list);
1083 request->file_priv = NULL;
1085 spin_unlock(&file_priv->mm.lock);
1089 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1090 struct intel_ring_buffer *ring)
1093 if (ring->dev != NULL)
1094 DRM_LOCK_ASSERT(ring->dev);
1096 while (!list_empty(&ring->request_list)) {
1097 struct drm_i915_gem_request *request;
1099 request = list_first_entry(&ring->request_list,
1100 struct drm_i915_gem_request, list);
1102 list_del(&request->list);
1103 i915_gem_request_remove_from_client(request);
1104 drm_free(request, DRM_I915_GEM);
1107 while (!list_empty(&ring->active_list)) {
1108 struct drm_i915_gem_object *obj;
1110 obj = list_first_entry(&ring->active_list,
1111 struct drm_i915_gem_object, ring_list);
1113 obj->base.write_domain = 0;
1114 list_del_init(&obj->gpu_write_list);
1115 i915_gem_object_move_to_inactive(obj);
1120 i915_gem_reset_fences(struct drm_device *dev)
1122 struct drm_i915_private *dev_priv = dev->dev_private;
1125 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1126 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1127 struct drm_i915_gem_object *obj = reg->obj;
1132 if (obj->tiling_mode)
1133 i915_gem_release_mmap(obj);
1135 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1136 reg->obj->fenced_gpu_access = false;
1137 reg->obj->last_fenced_seqno = 0;
1138 reg->obj->last_fenced_ring = NULL;
1139 i915_gem_clear_fence_reg(dev, reg);
1143 void i915_gem_reset(struct drm_device *dev)
1145 struct drm_i915_private *dev_priv = dev->dev_private;
1146 struct drm_i915_gem_object *obj;
1149 for (i = 0; i < I915_NUM_RINGS; i++)
1150 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1152 /* Remove anything from the flushing lists. The GPU cache is likely
1153 * to be lost on reset along with the data, so simply move the
1154 * lost bo to the inactive list.
1156 while (!list_empty(&dev_priv->mm.flushing_list)) {
1157 obj = list_first_entry(&dev_priv->mm.flushing_list,
1158 struct drm_i915_gem_object,
1161 obj->base.write_domain = 0;
1162 list_del_init(&obj->gpu_write_list);
1163 i915_gem_object_move_to_inactive(obj);
1166 /* Move everything out of the GPU domains to ensure we do any
1167 * necessary invalidation upon reuse.
1169 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
1170 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1173 /* The fence registers are invalidated so clear them out */
1174 i915_gem_reset_fences(dev);
1178 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1180 struct drm_device *dev = obj->base.dev;
1181 drm_i915_private_t *dev_priv = dev->dev_private;
1183 KASSERT(obj->active, ("Object not active"));
1184 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1186 i915_gem_object_move_off_active(obj);
1190 * This function clears the request list as sequence numbers are passed.
1193 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1197 if (list_empty(&ring->request_list))
1200 seqno = ring->get_seqno(ring, true);
1202 while (!list_empty(&ring->request_list)) {
1203 struct drm_i915_gem_request *request;
1205 request = list_first_entry(&ring->request_list,
1206 struct drm_i915_gem_request,
1209 if (!i915_seqno_passed(seqno, request->seqno))
1212 /* We know the GPU must have read the request to have
1213 * sent us the seqno + interrupt, so use the position
1214 * of tail of the request to update the last known position
1217 ring->last_retired_head = request->tail;
1219 list_del(&request->list);
1220 i915_gem_request_remove_from_client(request);
1221 drm_free(request, DRM_I915_GEM);
1224 /* Move any buffers on the active list that are no longer referenced
1225 * by the ringbuffer to the flushing/inactive lists as appropriate.
1227 while (!list_empty(&ring->active_list)) {
1228 struct drm_i915_gem_object *obj;
1230 obj = list_first_entry(&ring->active_list,
1231 struct drm_i915_gem_object,
1234 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1237 if (obj->base.write_domain != 0)
1238 i915_gem_object_move_to_flushing(obj);
1240 i915_gem_object_move_to_inactive(obj);
1243 if (unlikely(ring->trace_irq_seqno &&
1244 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1245 ring->irq_put(ring);
1246 ring->trace_irq_seqno = 0;
1252 i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
1255 i915_gem_retire_requests(struct drm_device *dev)
1257 drm_i915_private_t *dev_priv = dev->dev_private;
1258 struct drm_i915_gem_object *obj, *next;
1261 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1262 list_for_each_entry_safe(obj, next,
1263 &dev_priv->mm.deferred_free_list, mm_list)
1264 i915_gem_free_object_tail(obj);
1267 for (i = 0; i < I915_NUM_RINGS; i++)
1268 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1272 i915_gem_retire_work_handler(struct work_struct *work)
1274 drm_i915_private_t *dev_priv;
1275 struct drm_device *dev;
1276 struct intel_ring_buffer *ring;
1280 dev_priv = container_of(work, drm_i915_private_t,
1281 mm.retire_work.work);
1282 dev = dev_priv->dev;
1284 /* Come back later if the device is busy... */
1285 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
1286 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1287 round_jiffies_up_relative(hz));
1291 i915_gem_retire_requests(dev);
1293 /* Send a periodic flush down the ring so we don't hold onto GEM
1294 * objects indefinitely.
1297 for_each_ring(ring, dev_priv, i) {
1298 if (ring->gpu_caches_dirty)
1299 i915_add_request(ring, NULL, NULL);
1301 idle &= list_empty(&ring->request_list);
1304 if (!dev_priv->mm.suspended && !idle)
1305 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1306 round_jiffies_up_relative(hz));
1308 intel_mark_idle(dev);
1313 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1315 u32 old_write_domain, old_read_domains;
1317 /* Act a barrier for all accesses through the GTT */
1320 /* Force a pagefault for domain tracking on next user access */
1321 i915_gem_release_mmap(obj);
1323 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
1326 old_read_domains = obj->base.read_domains;
1327 old_write_domain = obj->base.write_domain;
1329 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
1330 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
1335 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
1337 drm_i915_private_t *dev_priv;
1340 dev_priv = obj->base.dev->dev_private;
1342 if (obj->gtt_space == NULL)
1344 if (obj->pin_count != 0) {
1345 DRM_ERROR("Attempting to unbind pinned buffer\n");
1349 ret = i915_gem_object_finish_gpu(obj);
1350 if (ret == -ERESTART || ret == -EINTR)
1353 i915_gem_object_finish_gtt(obj);
1356 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1357 if (ret == -ERESTART || ret == -EINTR)
1360 i915_gem_clflush_object(obj);
1361 obj->base.read_domains = obj->base.write_domain =
1362 I915_GEM_DOMAIN_CPU;
1365 ret = i915_gem_object_put_fence(obj);
1366 if (ret == -ERESTART)
1369 i915_gem_gtt_unbind_object(obj);
1370 if (obj->has_aliasing_ppgtt_mapping) {
1371 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
1372 obj->has_aliasing_ppgtt_mapping = 0;
1374 i915_gem_object_put_pages_gtt(obj);
1376 list_del_init(&obj->gtt_list);
1377 list_del_init(&obj->mm_list);
1378 obj->map_and_fenceable = true;
1380 drm_mm_put_block(obj->gtt_space);
1381 obj->gtt_space = NULL;
1382 obj->gtt_offset = 0;
1384 if (i915_gem_object_is_purgeable(obj))
1385 i915_gem_object_truncate(obj);
1390 int i915_gpu_idle(struct drm_device *dev)
1392 drm_i915_private_t *dev_priv = dev->dev_private;
1393 struct intel_ring_buffer *ring;
1396 /* Flush everything onto the inactive list. */
1397 for_each_ring(ring, dev_priv, i) {
1398 ret = intel_ring_idle(ring);
1407 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
1408 struct intel_ring_buffer *pipelined)
1410 struct drm_device *dev = obj->base.dev;
1411 drm_i915_private_t *dev_priv = dev->dev_private;
1412 u32 size = obj->gtt_space->size;
1413 int regnum = obj->fence_reg;
1416 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1418 val |= obj->gtt_offset & 0xfffff000;
1419 val |= (uint64_t)((obj->stride / 128) - 1) <<
1420 SANDYBRIDGE_FENCE_PITCH_SHIFT;
1422 if (obj->tiling_mode == I915_TILING_Y)
1423 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1424 val |= I965_FENCE_REG_VALID;
1427 int ret = intel_ring_begin(pipelined, 6);
1431 intel_ring_emit(pipelined, MI_NOOP);
1432 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
1433 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
1434 intel_ring_emit(pipelined, (u32)val);
1435 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
1436 intel_ring_emit(pipelined, (u32)(val >> 32));
1437 intel_ring_advance(pipelined);
1439 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
1445 i965_write_fence_reg(struct drm_i915_gem_object *obj,
1446 struct intel_ring_buffer *pipelined)
1448 struct drm_device *dev = obj->base.dev;
1449 drm_i915_private_t *dev_priv = dev->dev_private;
1450 u32 size = obj->gtt_space->size;
1451 int regnum = obj->fence_reg;
1454 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1456 val |= obj->gtt_offset & 0xfffff000;
1457 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1458 if (obj->tiling_mode == I915_TILING_Y)
1459 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1460 val |= I965_FENCE_REG_VALID;
1463 int ret = intel_ring_begin(pipelined, 6);
1467 intel_ring_emit(pipelined, MI_NOOP);
1468 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
1469 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
1470 intel_ring_emit(pipelined, (u32)val);
1471 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
1472 intel_ring_emit(pipelined, (u32)(val >> 32));
1473 intel_ring_advance(pipelined);
1475 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
1481 i915_write_fence_reg(struct drm_i915_gem_object *obj,
1482 struct intel_ring_buffer *pipelined)
1484 struct drm_device *dev = obj->base.dev;
1485 drm_i915_private_t *dev_priv = dev->dev_private;
1486 u32 size = obj->gtt_space->size;
1487 u32 fence_reg, val, pitch_val;
1490 if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
1491 (size & -size) != size || (obj->gtt_offset & (size - 1))) {
1493 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
1494 obj->gtt_offset, obj->map_and_fenceable, size);
1498 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1503 /* Note: pitch better be a power of two tile widths */
1504 pitch_val = obj->stride / tile_width;
1505 pitch_val = ffs(pitch_val) - 1;
1507 val = obj->gtt_offset;
1508 if (obj->tiling_mode == I915_TILING_Y)
1509 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1510 val |= I915_FENCE_SIZE_BITS(size);
1511 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1512 val |= I830_FENCE_REG_VALID;
1514 fence_reg = obj->fence_reg;
1516 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
1518 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
1521 int ret = intel_ring_begin(pipelined, 4);
1525 intel_ring_emit(pipelined, MI_NOOP);
1526 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
1527 intel_ring_emit(pipelined, fence_reg);
1528 intel_ring_emit(pipelined, val);
1529 intel_ring_advance(pipelined);
1531 I915_WRITE(fence_reg, val);
1537 i830_write_fence_reg(struct drm_i915_gem_object *obj,
1538 struct intel_ring_buffer *pipelined)
1540 struct drm_device *dev = obj->base.dev;
1541 drm_i915_private_t *dev_priv = dev->dev_private;
1542 u32 size = obj->gtt_space->size;
1543 int regnum = obj->fence_reg;
1547 if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
1548 (size & -size) != size || (obj->gtt_offset & (size - 1))) {
1550 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
1551 obj->gtt_offset, size);
1555 pitch_val = obj->stride / 128;
1556 pitch_val = ffs(pitch_val) - 1;
1558 val = obj->gtt_offset;
1559 if (obj->tiling_mode == I915_TILING_Y)
1560 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1561 val |= I830_FENCE_SIZE_BITS(size);
1562 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1563 val |= I830_FENCE_REG_VALID;
1566 int ret = intel_ring_begin(pipelined, 4);
1570 intel_ring_emit(pipelined, MI_NOOP);
1571 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
1572 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
1573 intel_ring_emit(pipelined, val);
1574 intel_ring_advance(pipelined);
1576 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
1581 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
1583 return i915_seqno_passed(ring->get_seqno(ring,false), seqno);
1587 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
1588 struct intel_ring_buffer *pipelined)
1592 if (obj->fenced_gpu_access) {
1593 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1594 ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
1595 obj->base.write_domain);
1600 obj->fenced_gpu_access = false;
1603 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
1604 if (!ring_passed_seqno(obj->last_fenced_ring,
1605 obj->last_fenced_seqno)) {
1606 ret = i915_wait_seqno(obj->last_fenced_ring,
1607 obj->last_fenced_seqno);
1612 obj->last_fenced_seqno = 0;
1613 obj->last_fenced_ring = NULL;
1616 /* Ensure that all CPU reads are completed before installing a fence
1617 * and all writes before removing the fence.
1619 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
1626 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
1630 if (obj->tiling_mode)
1631 i915_gem_release_mmap(obj);
1633 ret = i915_gem_object_flush_fence(obj, NULL);
1637 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1638 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1640 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
1641 kprintf("%s: pin_count %d\n", __func__,
1642 dev_priv->fence_regs[obj->fence_reg].pin_count);
1643 i915_gem_clear_fence_reg(obj->base.dev,
1644 &dev_priv->fence_regs[obj->fence_reg]);
1646 obj->fence_reg = I915_FENCE_REG_NONE;
1652 static struct drm_i915_fence_reg *
1653 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct drm_i915_fence_reg *reg, *first, *avail;
1659 /* First try to find a free reg */
1661 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1662 reg = &dev_priv->fence_regs[i];
1666 if (!reg->pin_count)
1673 /* None available, try to steal one or wait for a user to finish */
1674 avail = first = NULL;
1675 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
1683 !reg->obj->last_fenced_ring ||
1684 reg->obj->last_fenced_ring == pipelined) {
1697 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1698 struct intel_ring_buffer *pipelined)
1700 struct drm_device *dev = obj->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 struct drm_i915_fence_reg *reg;
1708 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1709 reg = &dev_priv->fence_regs[obj->fence_reg];
1710 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1712 if (obj->tiling_changed) {
1713 ret = i915_gem_object_flush_fence(obj, pipelined);
1717 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
1722 i915_gem_next_request_seqno(pipelined);
1723 obj->last_fenced_seqno = reg->setup_seqno;
1724 obj->last_fenced_ring = pipelined;
1731 if (reg->setup_seqno) {
1732 if (!ring_passed_seqno(obj->last_fenced_ring,
1733 reg->setup_seqno)) {
1734 ret = i915_wait_seqno(
1735 obj->last_fenced_ring,
1741 reg->setup_seqno = 0;
1743 } else if (obj->last_fenced_ring &&
1744 obj->last_fenced_ring != pipelined) {
1745 ret = i915_gem_object_flush_fence(obj, pipelined);
1750 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
1752 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
1754 if (obj->tiling_changed) {
1757 i915_gem_next_request_seqno(pipelined);
1758 obj->last_fenced_seqno = reg->setup_seqno;
1759 obj->last_fenced_ring = pipelined;
1767 reg = i915_find_fence_reg(dev, pipelined);
1771 ret = i915_gem_object_flush_fence(obj, pipelined);
1776 struct drm_i915_gem_object *old = reg->obj;
1778 drm_gem_object_reference(&old->base);
1780 if (old->tiling_mode)
1781 i915_gem_release_mmap(old);
1783 ret = i915_gem_object_flush_fence(old, pipelined);
1785 drm_gem_object_unreference(&old->base);
1789 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
1792 old->fence_reg = I915_FENCE_REG_NONE;
1793 old->last_fenced_ring = pipelined;
1794 old->last_fenced_seqno =
1795 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
1797 drm_gem_object_unreference(&old->base);
1798 } else if (obj->last_fenced_seqno == 0)
1802 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1803 obj->fence_reg = reg - dev_priv->fence_regs;
1804 obj->last_fenced_ring = pipelined;
1807 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
1808 obj->last_fenced_seqno = reg->setup_seqno;
1811 obj->tiling_changed = false;
1812 switch (INTEL_INFO(dev)->gen) {
1815 ret = sandybridge_write_fence_reg(obj, pipelined);
1819 ret = i965_write_fence_reg(obj, pipelined);
1822 ret = i915_write_fence_reg(obj, pipelined);
1825 ret = i830_write_fence_reg(obj, pipelined);
1833 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1834 unsigned alignment, bool map_and_fenceable)
1836 struct drm_device *dev;
1837 struct drm_i915_private *dev_priv;
1838 struct drm_mm_node *free_space;
1839 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1840 bool mappable, fenceable;
1843 dev = obj->base.dev;
1844 dev_priv = dev->dev_private;
1846 if (obj->madv != I915_MADV_WILLNEED) {
1847 DRM_ERROR("Attempting to bind a purgeable object\n");
1851 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1853 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1855 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1856 obj->base.size, obj->tiling_mode);
1858 alignment = map_and_fenceable ? fence_alignment :
1860 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
1861 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1865 size = map_and_fenceable ? fence_size : obj->base.size;
1867 /* If the object is bigger than the entire aperture, reject it early
1868 * before evicting everything in a vain attempt to find space.
1870 if (obj->base.size > (map_and_fenceable ?
1871 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
1873 "Attempting to bind an object larger than the aperture\n");
1878 if (map_and_fenceable)
1879 free_space = drm_mm_search_free_in_range(
1880 &dev_priv->mm.gtt_space, size, alignment, 0,
1881 dev_priv->mm.gtt_mappable_end, 0);
1883 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1884 size, alignment, 0);
1885 if (free_space != NULL) {
1887 if (map_and_fenceable)
1888 obj->gtt_space = drm_mm_get_block_range_generic(
1889 free_space, size, alignment, color, 0,
1890 dev_priv->mm.gtt_mappable_end, 1);
1892 obj->gtt_space = drm_mm_get_block_generic(free_space,
1893 size, alignment, color, 1);
1895 if (obj->gtt_space == NULL) {
1896 ret = i915_gem_evict_something(dev, size, alignment,
1904 * NOTE: i915_gem_object_get_pages_gtt() cannot
1905 * return ENOMEM, since we used VM_ALLOC_RETRY.
1907 ret = i915_gem_object_get_pages_gtt(obj, 0);
1909 drm_mm_put_block(obj->gtt_space);
1910 obj->gtt_space = NULL;
1914 i915_gem_gtt_bind_object(obj, obj->cache_level);
1916 i915_gem_object_put_pages_gtt(obj);
1917 drm_mm_put_block(obj->gtt_space);
1918 obj->gtt_space = NULL;
1919 if (i915_gem_evict_everything(dev, false))
1924 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
1925 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1927 obj->gtt_offset = obj->gtt_space->start;
1930 obj->gtt_space->size == fence_size &&
1931 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
1934 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
1935 obj->map_and_fenceable = mappable && fenceable;
1941 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1944 /* If we don't have a page list set up, then we're not pinned
1945 * to GPU, and we can ignore the cache flush because it'll happen
1946 * again at bind time.
1948 if (obj->pages == NULL)
1951 /* If the GPU is snooping the contents of the CPU cache,
1952 * we do not need to manually clear the CPU cache lines. However,
1953 * the caches are only snooped when the render cache is
1954 * flushed/invalidated. As we always have to emit invalidations
1955 * and flushes when moving into and out of the RENDER domain, correct
1956 * snooping behaviour occurs naturally as the result of our domain
1959 if (obj->cache_level != I915_CACHE_NONE)
1962 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1965 /** Flushes the GTT write domain for the object if it's dirty. */
1967 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1969 uint32_t old_write_domain;
1971 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1974 /* No actual flushing is required for the GTT write domain. Writes
1975 * to it immediately go to main memory as far as we know, so there's
1976 * no chipset flush. It also doesn't land in render cache.
1978 * However, we do have to enforce the order so that all writes through
1979 * the GTT land before any writes to the device, such as updates to
1984 old_write_domain = obj->base.write_domain;
1985 obj->base.write_domain = 0;
1988 /** Flushes the CPU write domain for the object if it's dirty. */
1990 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1992 uint32_t old_write_domain;
1994 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1997 i915_gem_clflush_object(obj);
1998 intel_gtt_chipset_flush();
1999 old_write_domain = obj->base.write_domain;
2000 obj->base.write_domain = 0;
2004 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2007 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2009 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
2013 * Moves a single object to the GTT read, and possibly write domain.
2015 * This function returns when the move is complete, including waiting on
2019 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2021 uint32_t old_write_domain, old_read_domains;
2024 if (obj->gtt_space == NULL)
2027 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2030 ret = i915_gem_object_flush_gpu_write_domain(obj);
2034 if (obj->pending_gpu_write || write) {
2035 ret = i915_gem_object_wait_rendering(obj);
2040 i915_gem_object_flush_cpu_write_domain(obj);
2042 old_write_domain = obj->base.write_domain;
2043 old_read_domains = obj->base.read_domains;
2045 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
2046 ("In GTT write domain"));
2047 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2049 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2050 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2057 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2058 enum i915_cache_level cache_level)
2060 struct drm_device *dev = obj->base.dev;
2061 drm_i915_private_t *dev_priv = dev->dev_private;
2064 if (obj->cache_level == cache_level)
2067 if (obj->pin_count) {
2068 DRM_DEBUG("can not change the cache level of pinned objects\n");
2072 if (obj->gtt_space) {
2073 ret = i915_gem_object_finish_gpu(obj);
2077 i915_gem_object_finish_gtt(obj);
2079 /* Before SandyBridge, you could not use tiling or fence
2080 * registers with snooped memory, so relinquish any fences
2081 * currently pointing to our region in the aperture.
2083 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2084 ret = i915_gem_object_put_fence(obj);
2089 if (obj->has_global_gtt_mapping)
2090 i915_gem_gtt_bind_object(obj, cache_level);
2091 if (obj->has_aliasing_ppgtt_mapping)
2092 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2096 if (cache_level == I915_CACHE_NONE) {
2097 u32 old_read_domains, old_write_domain;
2099 /* If we're coming from LLC cached, then we haven't
2100 * actually been tracking whether the data is in the
2101 * CPU cache or not, since we only allow one bit set
2102 * in obj->write_domain and have been skipping the clflushes.
2103 * Just set it to the CPU cache for now.
2105 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2106 ("obj %p in CPU write domain", obj));
2107 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2108 ("obj %p in CPU read domain", obj));
2110 old_read_domains = obj->base.read_domains;
2111 old_write_domain = obj->base.write_domain;
2113 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2114 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2118 obj->cache_level = cache_level;
2123 * Prepare buffer for display plane (scanout, cursors, etc).
2124 * Can be called from an uninterruptible phase (modesetting) and allows
2125 * any flushes to be pipelined (for pageflips).
2128 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2130 struct intel_ring_buffer *pipelined)
2132 u32 old_read_domains, old_write_domain;
2135 ret = i915_gem_object_flush_gpu_write_domain(obj);
2139 if (pipelined != obj->ring) {
2140 ret = i915_gem_object_wait_rendering(obj);
2141 if (ret == -ERESTART || ret == -EINTR)
2145 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2149 ret = i915_gem_object_pin(obj, alignment, true);
2153 i915_gem_object_flush_cpu_write_domain(obj);
2155 old_write_domain = obj->base.write_domain;
2156 old_read_domains = obj->base.read_domains;
2158 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
2159 ("obj %p in GTT write domain", obj));
2160 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2166 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2170 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2173 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2174 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2179 ret = i915_gem_object_wait_rendering(obj);
2183 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2189 * Moves a single object to the CPU read, and possibly write domain.
2191 * This function returns when the move is complete, including waiting on
2195 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2197 uint32_t old_write_domain, old_read_domains;
2200 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2203 ret = i915_gem_object_flush_gpu_write_domain(obj);
2207 ret = i915_gem_object_wait_rendering(obj);
2211 i915_gem_object_flush_gtt_write_domain(obj);
2213 old_write_domain = obj->base.write_domain;
2214 old_read_domains = obj->base.read_domains;
2216 /* Flush the CPU cache if it's still invalid. */
2217 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2218 i915_gem_clflush_object(obj);
2220 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2223 /* It should now be out of any other write domains, and we can update
2224 * the domain values for our changes.
2226 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2228 /* If we're writing through the CPU, then the GPU read domains will
2229 * need to be invalidated at next use.
2232 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2233 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2239 /* Throttle our rendering by waiting until the ring has completed our requests
2240 * emitted over 20 msec ago.
2242 * Note that if we were to use the current jiffies each time around the loop,
2243 * we wouldn't escape the function with any frames outstanding if the time to
2244 * render a frame was over 20ms.
2246 * This should get us reasonable parallelism between CPU and GPU but also
2247 * relatively low latency when blocking on a particular request to finish.
2250 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2252 struct drm_i915_private *dev_priv = dev->dev_private;
2253 struct drm_i915_file_private *file_priv = file->driver_priv;
2254 unsigned long recent_enough = ticks - (20 * hz / 1000);
2255 struct drm_i915_gem_request *request;
2256 struct intel_ring_buffer *ring = NULL;
2260 if (atomic_read(&dev_priv->mm.wedged))
2263 spin_lock(&file_priv->mm.lock);
2264 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2265 if (time_after_eq(request->emitted_jiffies, recent_enough))
2268 ring = request->ring;
2269 seqno = request->seqno;
2271 spin_unlock(&file_priv->mm.lock);
2276 ret = __wait_seqno(ring, seqno, true, NULL);
2279 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
2285 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
2286 bool map_and_fenceable)
2288 struct drm_device *dev;
2289 struct drm_i915_private *dev_priv;
2292 dev = obj->base.dev;
2293 dev_priv = dev->dev_private;
2295 KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
2298 if (obj->gtt_space != NULL) {
2299 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
2300 (map_and_fenceable && !obj->map_and_fenceable)) {
2301 DRM_DEBUG("bo is already pinned with incorrect alignment:"
2302 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
2303 " obj->map_and_fenceable=%d\n",
2304 obj->gtt_offset, alignment,
2306 obj->map_and_fenceable);
2307 ret = i915_gem_object_unbind(obj);
2313 if (obj->gtt_space == NULL) {
2314 ret = i915_gem_object_bind_to_gtt(obj, alignment,
2320 if (obj->pin_count++ == 0 && !obj->active)
2321 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2322 obj->pin_mappable |= map_and_fenceable;
2327 WARN_ON(i915_verify_lists(dev));
2333 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
2335 struct drm_device *dev;
2336 drm_i915_private_t *dev_priv;
2338 dev = obj->base.dev;
2339 dev_priv = dev->dev_private;
2344 WARN_ON(i915_verify_lists(dev));
2347 KASSERT(obj->pin_count != 0, ("zero pin count"));
2348 KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
2350 if (--obj->pin_count == 0) {
2352 list_move_tail(&obj->mm_list,
2353 &dev_priv->mm.inactive_list);
2354 obj->pin_mappable = false;
2359 WARN_ON(i915_verify_lists(dev));
2364 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2365 struct drm_file *file)
2367 struct drm_i915_gem_pin *args;
2368 struct drm_i915_gem_object *obj;
2369 struct drm_gem_object *gobj;
2374 ret = i915_mutex_lock_interruptible(dev);
2378 gobj = drm_gem_object_lookup(dev, file, args->handle);
2383 obj = to_intel_bo(gobj);
2385 if (obj->madv != I915_MADV_WILLNEED) {
2386 DRM_ERROR("Attempting to pin a purgeable buffer\n");
2391 if (obj->pin_filp != NULL && obj->pin_filp != file) {
2392 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2398 obj->user_pin_count++;
2399 obj->pin_filp = file;
2400 if (obj->user_pin_count == 1) {
2401 ret = i915_gem_object_pin(obj, args->alignment, true);
2406 /* XXX - flush the CPU caches for pinned objects
2407 * as the X server doesn't manage domains yet
2409 i915_gem_object_flush_cpu_write_domain(obj);
2410 args->offset = obj->gtt_offset;
2412 drm_gem_object_unreference(&obj->base);
2419 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2420 struct drm_file *file)
2422 struct drm_i915_gem_pin *args;
2423 struct drm_i915_gem_object *obj;
2427 ret = i915_mutex_lock_interruptible(dev);
2431 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2432 if (&obj->base == NULL) {
2437 if (obj->pin_filp != file) {
2438 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2443 obj->user_pin_count--;
2444 if (obj->user_pin_count == 0) {
2445 obj->pin_filp = NULL;
2446 i915_gem_object_unpin(obj);
2450 drm_gem_object_unreference(&obj->base);
2457 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2458 struct drm_file *file)
2460 struct drm_i915_gem_busy *args;
2461 struct drm_i915_gem_object *obj;
2462 struct drm_i915_gem_request *request;
2467 ret = i915_mutex_lock_interruptible(dev);
2471 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2472 if (&obj->base == NULL) {
2477 args->busy = obj->active;
2479 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2480 ret = i915_gem_flush_ring(obj->ring,
2481 0, obj->base.write_domain);
2482 } else if (obj->ring->outstanding_lazy_request ==
2483 obj->last_rendering_seqno) {
2484 request = kmalloc(sizeof(*request), DRM_I915_GEM,
2486 ret = i915_add_request(obj->ring, NULL, request);
2488 drm_free(request, DRM_I915_GEM);
2491 i915_gem_retire_requests_ring(obj->ring);
2492 args->busy = obj->active;
2495 drm_gem_object_unreference(&obj->base);
2502 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2503 struct drm_file *file_priv)
2506 return (i915_gem_ring_throttle(dev, file_priv));
2510 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2511 struct drm_file *file_priv)
2513 struct drm_i915_gem_madvise *args = data;
2514 struct drm_i915_gem_object *obj;
2517 switch (args->madv) {
2518 case I915_MADV_DONTNEED:
2519 case I915_MADV_WILLNEED:
2525 ret = i915_mutex_lock_interruptible(dev);
2529 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
2530 if (&obj->base == NULL) {
2535 if (obj->pin_count) {
2540 if (obj->madv != __I915_MADV_PURGED)
2541 obj->madv = args->madv;
2543 /* if the object is no longer attached, discard its backing storage */
2544 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
2545 i915_gem_object_truncate(obj);
2547 args->retained = obj->madv != __I915_MADV_PURGED;
2550 drm_gem_object_unreference(&obj->base);
2556 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2559 struct drm_i915_private *dev_priv;
2560 struct drm_i915_gem_object *obj;
2562 dev_priv = dev->dev_private;
2564 obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
2566 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
2567 drm_free(obj, DRM_I915_GEM);
2571 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2572 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2575 obj->cache_level = I915_CACHE_LLC;
2577 obj->cache_level = I915_CACHE_NONE;
2578 obj->base.driver_private = NULL;
2579 obj->fence_reg = I915_FENCE_REG_NONE;
2580 INIT_LIST_HEAD(&obj->mm_list);
2581 INIT_LIST_HEAD(&obj->gtt_list);
2582 INIT_LIST_HEAD(&obj->ring_list);
2583 INIT_LIST_HEAD(&obj->exec_list);
2584 INIT_LIST_HEAD(&obj->gpu_write_list);
2585 obj->madv = I915_MADV_WILLNEED;
2586 /* Avoid an unnecessary call to unbind on the first bind. */
2587 obj->map_and_fenceable = true;
2589 i915_gem_info_add_obj(dev_priv, size);
2594 int i915_gem_init_object(struct drm_gem_object *obj)
2597 kprintf("i915_gem_init_object called\n");
2602 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
2604 struct drm_device *dev;
2605 drm_i915_private_t *dev_priv;
2608 dev = obj->base.dev;
2609 dev_priv = dev->dev_private;
2611 ret = i915_gem_object_unbind(obj);
2612 if (ret == -ERESTART) {
2613 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
2617 drm_gem_free_mmap_offset(&obj->base);
2618 drm_gem_object_release(&obj->base);
2619 i915_gem_info_remove_obj(dev_priv, obj->base.size);
2621 drm_free(obj->page_cpu_valid, DRM_I915_GEM);
2622 drm_free(obj->bit_17, DRM_I915_GEM);
2623 drm_free(obj, DRM_I915_GEM);
2627 i915_gem_free_object(struct drm_gem_object *gem_obj)
2629 struct drm_i915_gem_object *obj;
2630 struct drm_device *dev;
2632 obj = to_intel_bo(gem_obj);
2633 dev = obj->base.dev;
2635 while (obj->pin_count > 0)
2636 i915_gem_object_unpin(obj);
2638 if (obj->phys_obj != NULL)
2639 i915_gem_detach_phys_object(dev, obj);
2641 i915_gem_free_object_tail(obj);
2645 i915_gem_do_init(struct drm_device *dev, unsigned long start,
2646 unsigned long mappable_end, unsigned long end)
2648 drm_i915_private_t *dev_priv;
2649 unsigned long mappable;
2652 dev_priv = dev->dev_private;
2653 mappable = min(end, mappable_end) - start;
2655 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
2657 dev_priv->mm.gtt_start = start;
2658 dev_priv->mm.gtt_mappable_end = mappable_end;
2659 dev_priv->mm.gtt_end = end;
2660 dev_priv->mm.gtt_total = end - start;
2661 dev_priv->mm.mappable_gtt_total = mappable;
2663 /* Take over this portion of the GTT */
2664 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
2665 device_printf(dev->dev,
2666 "taking over the fictitious range 0x%lx-0x%lx\n",
2667 dev->agp->base + start, dev->agp->base + start + mappable);
2668 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
2669 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
2674 i915_gem_idle(struct drm_device *dev)
2676 drm_i915_private_t *dev_priv;
2679 dev_priv = dev->dev_private;
2680 if (dev_priv->mm.suspended)
2683 ret = i915_gpu_idle(dev);
2687 /* Under UMS, be paranoid and evict. */
2688 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
2689 ret = i915_gem_evict_inactive(dev, false);
2694 i915_gem_reset_fences(dev);
2696 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2697 * We need to replace this with a semaphore, or something.
2698 * And not confound mm.suspended!
2700 dev_priv->mm.suspended = 1;
2701 del_timer_sync(&dev_priv->hangcheck_timer);
2703 i915_kernel_lost_context(dev);
2704 i915_gem_cleanup_ringbuffer(dev);
2706 /* Cancel the retire work handler, which should be idle now. */
2707 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2712 void i915_gem_l3_remap(struct drm_device *dev)
2714 drm_i915_private_t *dev_priv = dev->dev_private;
2718 if (!HAS_L3_GPU_CACHE(dev))
2721 if (!dev_priv->l3_parity.remap_info)
2724 misccpctl = I915_READ(GEN7_MISCCPCTL);
2725 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
2726 POSTING_READ(GEN7_MISCCPCTL);
2728 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
2729 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
2730 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
2731 DRM_DEBUG("0x%x was already programmed to %x\n",
2732 GEN7_L3LOG_BASE + i, remap);
2733 if (remap && !dev_priv->l3_parity.remap_info[i/4])
2734 DRM_DEBUG_DRIVER("Clearing remapped register\n");
2735 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
2738 /* Make sure all the writes land before disabling dop clock gating */
2739 POSTING_READ(GEN7_L3LOG_BASE);
2741 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
2745 i915_gem_init_swizzling(struct drm_device *dev)
2747 drm_i915_private_t *dev_priv;
2749 dev_priv = dev->dev_private;
2751 if (INTEL_INFO(dev)->gen < 5 ||
2752 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
2755 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
2756 DISP_TILE_SURFACE_SWIZZLING);
2761 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
2763 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
2765 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
2769 intel_enable_blt(struct drm_device *dev)
2776 /* The blitter was dysfunctional on early prototypes */
2777 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
2778 if (IS_GEN6(dev) && revision < 8) {
2779 DRM_INFO("BLT not supported on this pre-production hardware;"
2780 " graphics performance will be degraded.\n");
2788 i915_gem_init_hw(struct drm_device *dev)
2790 drm_i915_private_t *dev_priv = dev->dev_private;
2793 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
2794 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
2796 i915_gem_l3_remap(dev);
2798 i915_gem_init_swizzling(dev);
2800 ret = intel_init_render_ring_buffer(dev);
2805 ret = intel_init_bsd_ring_buffer(dev);
2807 goto cleanup_render_ring;
2810 if (intel_enable_blt(dev)) {
2811 ret = intel_init_blt_ring_buffer(dev);
2813 goto cleanup_bsd_ring;
2816 dev_priv->next_seqno = 1;
2819 * XXX: There was some w/a described somewhere suggesting loading
2820 * contexts before PPGTT.
2822 #if 0 /* XXX: HW context support */
2823 i915_gem_context_init(dev);
2825 i915_gem_init_ppgtt(dev);
2830 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
2831 cleanup_render_ring:
2832 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
2837 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2839 drm_i915_private_t *dev_priv;
2842 dev_priv = dev->dev_private;
2843 for (i = 0; i < I915_NUM_RINGS; i++)
2844 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
2848 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2849 struct drm_file *file_priv)
2851 drm_i915_private_t *dev_priv = dev->dev_private;
2854 if (drm_core_check_feature(dev, DRIVER_MODESET))
2857 if (atomic_read(&dev_priv->mm.wedged)) {
2858 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2859 atomic_set(&dev_priv->mm.wedged, 0);
2863 dev_priv->mm.suspended = 0;
2865 ret = i915_gem_init_hw(dev);
2871 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
2874 ret = drm_irq_install(dev);
2876 goto cleanup_ringbuffer;
2882 i915_gem_cleanup_ringbuffer(dev);
2883 dev_priv->mm.suspended = 1;
2890 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2891 struct drm_file *file_priv)
2894 if (drm_core_check_feature(dev, DRIVER_MODESET))
2897 drm_irq_uninstall(dev);
2898 return (i915_gem_idle(dev));
2902 i915_gem_lastclose(struct drm_device *dev)
2906 if (drm_core_check_feature(dev, DRIVER_MODESET))
2909 ret = i915_gem_idle(dev);
2911 DRM_ERROR("failed to idle hardware: %d\n", ret);
2915 init_ring_lists(struct intel_ring_buffer *ring)
2918 INIT_LIST_HEAD(&ring->active_list);
2919 INIT_LIST_HEAD(&ring->request_list);
2920 INIT_LIST_HEAD(&ring->gpu_write_list);
2924 i915_gem_load(struct drm_device *dev)
2927 drm_i915_private_t *dev_priv = dev->dev_private;
2929 INIT_LIST_HEAD(&dev_priv->mm.active_list);
2930 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2931 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2932 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
2933 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2934 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
2935 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
2936 for (i = 0; i < I915_NUM_RINGS; i++)
2937 init_ring_lists(&dev_priv->ring[i]);
2938 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
2939 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
2940 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2941 i915_gem_retire_work_handler);
2942 init_completion(&dev_priv->error_completion);
2944 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
2946 I915_WRITE(MI_ARB_STATE,
2947 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
2950 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
2952 /* Old X drivers will take 0-2 for front, back, depth buffers */
2953 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2954 dev_priv->fence_reg_start = 3;
2956 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2957 dev_priv->num_fence_regs = 16;
2959 dev_priv->num_fence_regs = 8;
2961 /* Initialize fence registers to zero */
2962 i915_gem_reset_fences(dev);
2964 i915_gem_detect_bit_6_swizzle(dev);
2966 dev_priv->mm.interruptible = true;
2968 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
2969 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
2973 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
2975 drm_i915_private_t *dev_priv;
2976 struct drm_i915_gem_phys_object *phys_obj;
2979 dev_priv = dev->dev_private;
2980 if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
2983 phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
2988 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
2989 if (phys_obj->handle == NULL) {
2993 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
2994 size / PAGE_SIZE, PAT_WRITE_COMBINING);
2996 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3001 drm_free(phys_obj, DRM_I915_GEM);
3006 i915_gem_free_phys_object(struct drm_device *dev, int id)
3008 drm_i915_private_t *dev_priv;
3009 struct drm_i915_gem_phys_object *phys_obj;
3011 dev_priv = dev->dev_private;
3012 if (dev_priv->mm.phys_objs[id - 1] == NULL)
3015 phys_obj = dev_priv->mm.phys_objs[id - 1];
3016 if (phys_obj->cur_obj != NULL)
3017 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3019 drm_pci_free(dev, phys_obj->handle);
3020 drm_free(phys_obj, DRM_I915_GEM);
3021 dev_priv->mm.phys_objs[id - 1] = NULL;
3025 i915_gem_free_all_phys_object(struct drm_device *dev)
3029 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3030 i915_gem_free_phys_object(dev, i);
3034 i915_gem_detach_phys_object(struct drm_device *dev,
3035 struct drm_i915_gem_object *obj)
3042 if (obj->phys_obj == NULL)
3044 vaddr = obj->phys_obj->handle->vaddr;
3046 page_count = obj->base.size / PAGE_SIZE;
3047 VM_OBJECT_LOCK(obj->base.vm_obj);
3048 for (i = 0; i < page_count; i++) {
3049 m = i915_gem_wire_page(obj->base.vm_obj, i);
3053 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3054 sf = sf_buf_alloc(m);
3056 dst = (char *)sf_buf_kva(sf);
3057 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3060 drm_clflush_pages(&m, 1);
3062 VM_OBJECT_LOCK(obj->base.vm_obj);
3063 vm_page_reference(m);
3065 vm_page_busy_wait(m, FALSE, "i915gem");
3066 vm_page_unwire(m, 0);
3068 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3070 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3071 intel_gtt_chipset_flush();
3073 obj->phys_obj->cur_obj = NULL;
3074 obj->phys_obj = NULL;
3078 i915_gem_attach_phys_object(struct drm_device *dev,
3079 struct drm_i915_gem_object *obj,
3083 drm_i915_private_t *dev_priv;
3087 int i, page_count, ret;
3089 if (id > I915_MAX_PHYS_OBJECT)
3092 if (obj->phys_obj != NULL) {
3093 if (obj->phys_obj->id == id)
3095 i915_gem_detach_phys_object(dev, obj);
3098 dev_priv = dev->dev_private;
3099 if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3100 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3102 DRM_ERROR("failed to init phys object %d size: %zu\n",
3103 id, obj->base.size);
3108 /* bind to the object */
3109 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3110 obj->phys_obj->cur_obj = obj;
3112 page_count = obj->base.size / PAGE_SIZE;
3114 VM_OBJECT_LOCK(obj->base.vm_obj);
3116 for (i = 0; i < page_count; i++) {
3117 m = i915_gem_wire_page(obj->base.vm_obj, i);
3122 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3123 sf = sf_buf_alloc(m);
3124 src = (char *)sf_buf_kva(sf);
3125 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3126 memcpy(dst, src, PAGE_SIZE);
3129 VM_OBJECT_LOCK(obj->base.vm_obj);
3131 vm_page_reference(m);
3132 vm_page_busy_wait(m, FALSE, "i915gem");
3133 vm_page_unwire(m, 0);
3135 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3137 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3143 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3144 uint64_t data_ptr, uint64_t offset, uint64_t size,
3145 struct drm_file *file_priv)
3147 char *user_data, *vaddr;
3150 vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3151 user_data = (char *)(uintptr_t)data_ptr;
3153 if (copyin_nofault(user_data, vaddr, size) != 0) {
3154 /* The physical object once assigned is fixed for the lifetime
3155 * of the obj, so we can safely drop the lock and continue
3159 ret = -copyin(user_data, vaddr, size);
3165 intel_gtt_chipset_flush();
3170 i915_gem_release(struct drm_device *dev, struct drm_file *file)
3172 struct drm_i915_file_private *file_priv;
3173 struct drm_i915_gem_request *request;
3175 file_priv = file->driver_priv;
3177 /* Clean up our request list when the client is going away, so that
3178 * later retire_requests won't dereference our soon-to-be-gone
3181 spin_lock(&file_priv->mm.lock);
3182 while (!list_empty(&file_priv->mm.request_list)) {
3183 request = list_first_entry(&file_priv->mm.request_list,
3184 struct drm_i915_gem_request,
3186 list_del(&request->client_list);
3187 request->file_priv = NULL;
3189 spin_unlock(&file_priv->mm.lock);
3193 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
3194 uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
3195 struct drm_file *file)
3202 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
3204 if (obj->gtt_offset != 0 && rw == UIO_READ)
3205 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
3207 do_bit17_swizzling = 0;
3210 vm_obj = obj->base.vm_obj;
3213 VM_OBJECT_LOCK(vm_obj);
3214 vm_object_pip_add(vm_obj, 1);
3216 obj_pi = OFF_TO_IDX(offset);
3217 obj_po = offset & PAGE_MASK;
3219 m = i915_gem_wire_page(vm_obj, obj_pi);
3220 VM_OBJECT_UNLOCK(vm_obj);
3222 sf = sf_buf_alloc(m);
3223 mkva = sf_buf_kva(sf);
3224 length = min(size, PAGE_SIZE - obj_po);
3225 while (length > 0) {
3226 if (do_bit17_swizzling &&
3227 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
3228 cnt = roundup2(obj_po + 1, 64);
3229 cnt = min(cnt - obj_po, length);
3230 swizzled_po = obj_po ^ 64;
3233 swizzled_po = obj_po;
3236 ret = -copyout_nofault(
3237 (char *)mkva + swizzled_po,
3238 (void *)(uintptr_t)data_ptr, cnt);
3240 ret = -copyin_nofault(
3241 (void *)(uintptr_t)data_ptr,
3242 (char *)mkva + swizzled_po, cnt);
3252 VM_OBJECT_LOCK(vm_obj);
3253 if (rw == UIO_WRITE)
3255 vm_page_reference(m);
3256 vm_page_busy_wait(m, FALSE, "i915gem");
3257 vm_page_unwire(m, 1);
3259 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3264 vm_object_pip_wakeup(vm_obj);
3265 VM_OBJECT_UNLOCK(vm_obj);
3271 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
3272 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
3278 * Pass the unaligned physical address and size to pmap_mapdev_attr()
3279 * so it can properly calculate whether an extra page needs to be
3280 * mapped or not to cover the requested range. The function will
3281 * add the page offset into the returned mkva for us.
3283 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
3284 offset, size, PAT_WRITE_COMBINING);
3285 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
3286 pmap_unmapdev(mkva, size);
3291 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
3292 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
3294 struct drm_i915_gem_object *obj;
3296 vm_offset_t start, end;
3301 start = trunc_page(data_ptr);
3302 end = round_page(data_ptr + size);
3303 npages = howmany(end - start, PAGE_SIZE);
3304 ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
3306 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
3307 (vm_offset_t)data_ptr, size,
3308 (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
3314 ret = i915_mutex_lock_interruptible(dev);
3318 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
3319 if (&obj->base == NULL) {
3323 if (offset > obj->base.size || size > obj->base.size - offset) {
3328 if (rw == UIO_READ) {
3329 ret = i915_gem_object_set_cpu_read_domain_range(obj,
3333 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3336 if (obj->phys_obj) {
3337 ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
3339 } else if (obj->gtt_space &&
3340 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
3341 ret = i915_gem_object_pin(obj, 0, true);
3344 ret = i915_gem_object_set_to_gtt_domain(obj, true);
3347 ret = i915_gem_object_put_fence(obj);
3350 ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
3353 i915_gem_object_unpin(obj);
3355 ret = i915_gem_object_set_to_cpu_domain(obj, true);
3358 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3363 drm_gem_object_unreference(&obj->base);
3367 vm_page_unhold_pages(ma, npages);
3369 drm_free(ma, DRM_I915_GEM);
3374 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
3375 vm_ooffset_t foff, struct ucred *cred, u_short *color)
3378 *color = 0; /* XXXKIB */
3385 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
3388 struct drm_gem_object *gem_obj;
3389 struct drm_i915_gem_object *obj;
3390 struct drm_device *dev;
3391 drm_i915_private_t *dev_priv;
3396 gem_obj = vm_obj->handle;
3397 obj = to_intel_bo(gem_obj);
3398 dev = obj->base.dev;
3399 dev_priv = dev->dev_private;
3401 write = (prot & VM_PROT_WRITE) != 0;
3405 vm_object_pip_add(vm_obj, 1);
3408 * Remove the placeholder page inserted by vm_fault() from the
3409 * object before dropping the object lock. If
3410 * i915_gem_release_mmap() is active in parallel on this gem
3411 * object, then it owns the drm device sx and might find the
3412 * placeholder already. Then, since the page is busy,
3413 * i915_gem_release_mmap() sleeps waiting for the busy state
3414 * of the page cleared. We will be not able to acquire drm
3415 * device lock until i915_gem_release_mmap() is able to make a
3418 if (*mres != NULL) {
3420 vm_page_remove(oldm);
3425 VM_OBJECT_UNLOCK(vm_obj);
3431 ret = i915_mutex_lock_interruptible(dev);
3440 * Since the object lock was dropped, other thread might have
3441 * faulted on the same GTT address and instantiated the
3442 * mapping for the page. Recheck.
3444 VM_OBJECT_LOCK(vm_obj);
3445 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
3447 if ((m->flags & PG_BUSY) != 0) {
3450 vm_page_sleep(m, "915pee");
3456 VM_OBJECT_UNLOCK(vm_obj);
3458 /* Now bind it into the GTT if needed */
3459 if (!obj->map_and_fenceable) {
3460 ret = i915_gem_object_unbind(obj);
3466 if (!obj->gtt_space) {
3467 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
3473 ret = i915_gem_object_set_to_gtt_domain(obj, write);
3480 if (obj->tiling_mode == I915_TILING_NONE)
3481 ret = i915_gem_object_put_fence(obj);
3483 ret = i915_gem_object_get_fence(obj, NULL);
3489 if (i915_gem_object_is_inactive(obj))
3490 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3492 obj->fault_mappable = true;
3493 VM_OBJECT_LOCK(vm_obj);
3494 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
3501 KASSERT((m->flags & PG_FICTITIOUS) != 0,
3502 ("not fictitious %p", m));
3503 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
3505 if ((m->flags & PG_BUSY) != 0) {
3508 vm_page_sleep(m, "915pbs");
3512 m->valid = VM_PAGE_BITS_ALL;
3513 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
3516 vm_page_busy_try(m, false);
3522 vm_object_pip_wakeup(vm_obj);
3523 return (VM_PAGER_OK);
3528 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
3529 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
3530 goto unlocked_vmobj;
3532 VM_OBJECT_LOCK(vm_obj);
3533 vm_object_pip_wakeup(vm_obj);
3534 return (VM_PAGER_ERROR);
3538 i915_gem_pager_dtor(void *handle)
3540 struct drm_gem_object *obj;
3541 struct drm_device *dev;
3547 drm_gem_free_mmap_offset(obj);
3548 i915_gem_release_mmap(to_intel_bo(obj));
3549 drm_gem_object_unreference(obj);
3553 struct cdev_pager_ops i915_gem_pager_ops = {
3554 .cdev_pg_fault = i915_gem_pager_fault,
3555 .cdev_pg_ctor = i915_gem_pager_ctor,
3556 .cdev_pg_dtor = i915_gem_pager_dtor
3560 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3561 uint64_t offset, uint64_t size)
3563 uint32_t old_read_domains;
3566 if (offset == 0 && size == obj->base.size)
3567 return (i915_gem_object_set_to_cpu_domain(obj, 0));
3569 ret = i915_gem_object_flush_gpu_write_domain(obj);
3572 ret = i915_gem_object_wait_rendering(obj);
3576 i915_gem_object_flush_gtt_write_domain(obj);
3578 if (obj->page_cpu_valid == NULL &&
3579 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3582 if (obj->page_cpu_valid == NULL) {
3583 obj->page_cpu_valid = kmalloc(obj->base.size / PAGE_SIZE,
3584 DRM_I915_GEM, M_WAITOK | M_ZERO);
3585 } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3586 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3588 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3590 if (obj->page_cpu_valid[i])
3592 drm_clflush_pages(obj->pages + i, 1);
3593 obj->page_cpu_valid[i] = 1;
3596 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
3597 ("In gpu write domain"));
3599 old_read_domains = obj->base.read_domains;
3600 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3605 #define GEM_PARANOID_CHECK_GTT 0
3606 #if GEM_PARANOID_CHECK_GTT
3608 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
3611 struct drm_i915_private *dev_priv;
3613 unsigned long start, end;
3617 dev_priv = dev->dev_private;
3618 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
3619 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
3620 for (i = start; i < end; i++) {
3621 pa = intel_gtt_read_pte_paddr(i);
3622 for (j = 0; j < page_count; j++) {
3623 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
3624 panic("Page %p in GTT pte index %d pte %x",
3625 ma[i], i, intel_gtt_read_pte(i));
3633 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
3634 uint32_t flush_domains)
3636 struct drm_i915_gem_object *obj, *next;
3637 uint32_t old_write_domain;
3639 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
3641 if (obj->base.write_domain & flush_domains) {
3642 old_write_domain = obj->base.write_domain;
3643 obj->base.write_domain = 0;
3644 list_del_init(&obj->gpu_write_list);
3645 i915_gem_object_move_to_active(obj, ring,
3646 i915_gem_next_request_seqno(ring));
3651 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
3654 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
3659 VM_OBJECT_LOCK_ASSERT_OWNED(object);
3660 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
3661 if (m->valid != VM_PAGE_BITS_ALL) {
3662 if (vm_pager_has_page(object, pindex)) {
3663 rv = vm_pager_get_page(object, &m, 1);
3664 m = vm_page_lookup(object, pindex);
3667 if (rv != VM_PAGER_OK) {
3672 pmap_zero_page(VM_PAGE_TO_PHYS(m));
3673 m->valid = VM_PAGE_BITS_ALL;
3679 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
3684 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
3685 uint32_t flush_domains)
3689 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
3692 ret = ring->flush(ring, invalidate_domains, flush_domains);
3696 if (flush_domains & I915_GEM_GPU_DOMAINS)
3697 i915_gem_process_flushing_list(ring, flush_domains);
3702 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
3704 if (ring->outstanding_lazy_request == 0)
3705 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
3707 return ring->outstanding_lazy_request;
3711 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3713 drm_i915_private_t *dev_priv = dev->dev_private;
3714 uint32_t fence_reg = reg - dev_priv->fence_regs;
3716 switch (INTEL_INFO(dev)->gen) {
3719 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3723 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3727 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3730 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3732 I915_WRITE(fence_reg, 0);
3736 list_del_init(®->lru_list);
3738 reg->setup_seqno = 0;
3743 i915_gpu_is_active(struct drm_device *dev)
3745 drm_i915_private_t *dev_priv;
3747 dev_priv = dev->dev_private;
3748 return (!list_empty(&dev_priv->mm.flushing_list) ||
3749 !list_empty(&dev_priv->mm.active_list));
3753 i915_gem_lowmem(void *arg)
3755 struct drm_device *dev;
3756 struct drm_i915_private *dev_priv;
3757 struct drm_i915_gem_object *obj, *next;
3758 int cnt, cnt_fail, cnt_total;
3761 dev_priv = dev->dev_private;
3763 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3767 /* first scan for clean buffers */
3768 i915_gem_retire_requests(dev);
3770 cnt_total = cnt_fail = cnt = 0;
3772 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3774 if (i915_gem_object_is_purgeable(obj)) {
3775 if (i915_gem_object_unbind(obj) != 0)
3781 /* second pass, evict/count anything still on the inactive list */
3782 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3784 if (i915_gem_object_unbind(obj) == 0)
3790 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3792 * We are desperate for pages, so as a last resort, wait
3793 * for the GPU to finish and discard whatever we can.
3794 * This has a dramatic impact to reduce the number of
3795 * OOM-killer events whilst running the GPU aggressively.
3797 if (i915_gpu_idle(dev) == 0)
3804 i915_gem_unload(struct drm_device *dev)
3806 struct drm_i915_private *dev_priv;
3808 dev_priv = dev->dev_private;
3809 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);