2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 /* RS600 / Radeon X1250/X1270 integrated GPU
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
38 * $FreeBSD: head/sys/dev/drm2/radeon/rs600.c 255573 2013-09-14 17:24:41Z dumbbell $
43 #include "radeon_asic.h"
47 #include "rs600_reg_safe.h"
49 static void rs600_gpu_init(struct radeon_device *rdev);
51 static const u32 crtc_offsets[2] =
54 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
57 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
59 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
65 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
69 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
70 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
79 * avivo_wait_for_vblank - vblank wait asic callback.
81 * @rdev: radeon_device pointer
82 * @crtc: crtc to wait for vblank on
84 * Wait for vblank on the requested crtc (r5xx-r7xx).
86 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
90 if (crtc >= rdev->num_crtc)
93 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
96 /* depending on when we hit vblank, we may be close to active; if so,
97 * wait for another frame.
99 while (avivo_is_in_vblank(rdev, crtc)) {
100 if (i++ % 100 == 0) {
101 if (!avivo_is_counter_moving(rdev, crtc))
106 while (!avivo_is_in_vblank(rdev, crtc)) {
107 if (i++ % 100 == 0) {
108 if (!avivo_is_counter_moving(rdev, crtc))
114 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
116 /* enable the pflip int */
117 radeon_irq_kms_pflip_irq_get(rdev, crtc);
120 void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
122 /* disable the pflip int */
123 radeon_irq_kms_pflip_irq_put(rdev, crtc);
126 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
128 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
129 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
132 /* Lock the graphics update lock */
133 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
134 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
136 /* update the scanout addresses */
137 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
139 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
142 /* Wait for update_pending to go high. */
143 for (i = 0; i < rdev->usec_timeout; i++) {
144 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
148 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
150 /* Unlock the lock, so double-buffering can take place inside vblank */
151 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
152 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
154 /* Return current update_pending status: */
155 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
158 void rs600_pm_misc(struct radeon_device *rdev)
160 int requested_index = rdev->pm.requested_power_state_index;
161 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
162 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
163 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
164 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
166 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
167 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
168 tmp = RREG32(voltage->gpio.reg);
169 if (voltage->active_high)
170 tmp |= voltage->gpio.mask;
172 tmp &= ~(voltage->gpio.mask);
173 WREG32(voltage->gpio.reg, tmp);
175 udelay(voltage->delay);
177 tmp = RREG32(voltage->gpio.reg);
178 if (voltage->active_high)
179 tmp &= ~voltage->gpio.mask;
181 tmp |= voltage->gpio.mask;
182 WREG32(voltage->gpio.reg, tmp);
184 udelay(voltage->delay);
186 } else if (voltage->type == VOLTAGE_VDDC)
187 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
189 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
190 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
191 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
192 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
193 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
194 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
195 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
196 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
197 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
198 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
201 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
202 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
204 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
206 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
207 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
208 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
209 if (voltage->delay) {
210 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
211 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
213 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
215 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
216 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
218 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
219 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
220 hdp_dyn_cntl &= ~HDP_FORCEON;
222 hdp_dyn_cntl |= HDP_FORCEON;
223 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
225 /* mc_host_dyn seems to cause hangs from time to time */
226 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
227 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
228 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
230 mc_host_dyn_cntl |= MC_HOST_FORCEON;
231 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
233 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
234 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
235 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
237 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
238 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
241 if ((rdev->flags & RADEON_IS_PCIE) &&
242 !(rdev->flags & RADEON_IS_IGP) &&
243 rdev->asic->pm.set_pcie_lanes &&
245 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
246 radeon_set_pcie_lanes(rdev,
248 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
252 void rs600_pm_prepare(struct radeon_device *rdev)
254 struct drm_device *ddev = rdev->ddev;
255 struct drm_crtc *crtc;
256 struct radeon_crtc *radeon_crtc;
259 /* disable any active CRTCs */
260 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
261 radeon_crtc = to_radeon_crtc(crtc);
262 if (radeon_crtc->enabled) {
263 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
264 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
265 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
270 void rs600_pm_finish(struct radeon_device *rdev)
272 struct drm_device *ddev = rdev->ddev;
273 struct drm_crtc *crtc;
274 struct radeon_crtc *radeon_crtc;
277 /* enable any active CRTCs */
278 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
279 radeon_crtc = to_radeon_crtc(crtc);
280 if (radeon_crtc->enabled) {
281 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
282 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
283 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
288 /* hpd for digital panel detect/disconnect */
289 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
292 bool connected = false;
296 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
297 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
301 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
302 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
311 void rs600_hpd_set_polarity(struct radeon_device *rdev,
312 enum radeon_hpd_id hpd)
315 bool connected = rs600_hpd_sense(rdev, hpd);
319 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
321 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
323 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
324 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
327 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
329 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
331 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
332 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
339 void rs600_hpd_init(struct radeon_device *rdev)
341 struct drm_device *dev = rdev->ddev;
342 struct drm_connector *connector;
345 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
346 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
347 switch (radeon_connector->hpd.hpd) {
349 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
350 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
353 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
354 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
359 enable |= 1 << radeon_connector->hpd.hpd;
360 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
362 radeon_irq_kms_enable_hpd(rdev, enable);
365 void rs600_hpd_fini(struct radeon_device *rdev)
367 struct drm_device *dev = rdev->ddev;
368 struct drm_connector *connector;
369 unsigned disable = 0;
371 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
372 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
373 switch (radeon_connector->hpd.hpd) {
375 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
376 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
379 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
380 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
385 disable |= 1 << radeon_connector->hpd.hpd;
387 radeon_irq_kms_disable_hpd(rdev, disable);
390 int rs600_asic_reset(struct radeon_device *rdev)
392 struct rv515_mc_save save;
396 status = RREG32(R_000E40_RBBM_STATUS);
397 if (!G_000E40_GUI_ACTIVE(status)) {
400 /* Stops all mc clients */
401 rv515_mc_stop(rdev, &save);
402 status = RREG32(R_000E40_RBBM_STATUS);
403 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
405 WREG32(RADEON_CP_CSQ_CNTL, 0);
406 tmp = RREG32(RADEON_CP_RB_CNTL);
407 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
408 WREG32(RADEON_CP_RB_RPTR_WR, 0);
409 WREG32(RADEON_CP_RB_WPTR, 0);
410 WREG32(RADEON_CP_RB_CNTL, tmp);
411 pci_save_state(device_get_parent(rdev->dev));
412 /* disable bus mastering */
413 pci_disable_busmaster(rdev->dev);
416 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
417 S_0000F0_SOFT_RESET_GA(1));
418 RREG32(R_0000F0_RBBM_SOFT_RESET);
420 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
422 status = RREG32(R_000E40_RBBM_STATUS);
423 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
425 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
426 RREG32(R_0000F0_RBBM_SOFT_RESET);
428 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
430 status = RREG32(R_000E40_RBBM_STATUS);
431 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
433 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
434 RREG32(R_0000F0_RBBM_SOFT_RESET);
436 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
438 status = RREG32(R_000E40_RBBM_STATUS);
439 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
440 /* restore PCI & busmastering */
441 pci_restore_state(device_get_parent(rdev->dev));
442 /* Check if GPU is idle */
443 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
444 dev_err(rdev->dev, "failed to reset GPU\n");
447 dev_info(rdev->dev, "GPU reset succeed\n");
448 rv515_mc_resume(rdev, &save);
455 void rs600_gart_tlb_flush(struct radeon_device *rdev)
459 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
460 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
461 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
463 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
464 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
465 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
467 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
468 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
469 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
470 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
473 static int rs600_gart_init(struct radeon_device *rdev)
477 if (rdev->gart.robj) {
478 WARN(1, "RS600 GART already initialized\n");
481 /* Initialize common gart structure */
482 r = radeon_gart_init(rdev);
486 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
487 return radeon_gart_table_vram_alloc(rdev);
490 static int rs600_gart_enable(struct radeon_device *rdev)
495 if (rdev->gart.robj == NULL) {
496 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
499 r = radeon_gart_table_vram_pin(rdev);
502 radeon_gart_restore(rdev);
503 /* Enable bus master */
504 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
505 WREG32(RADEON_BUS_CNTL, tmp);
506 /* FIXME: setup default page */
507 WREG32_MC(R_000100_MC_PT0_CNTL,
508 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
509 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
511 for (i = 0; i < 19; i++) {
512 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
513 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
514 S_00016C_SYSTEM_ACCESS_MODE_MASK(
515 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
516 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
517 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
518 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
519 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
520 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
522 /* enable first context */
523 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
524 S_000102_ENABLE_PAGE_TABLE(1) |
525 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
527 /* disable all other contexts */
528 for (i = 1; i < 8; i++)
529 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
531 /* setup the page table */
532 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
533 rdev->gart.table_addr);
534 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
535 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
536 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
538 /* System context maps to VRAM space */
539 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
540 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
542 /* enable page tables */
543 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
544 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
545 tmp = RREG32_MC(R_000009_MC_CNTL1);
546 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
547 rs600_gart_tlb_flush(rdev);
548 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
549 (unsigned)(rdev->mc.gtt_size >> 20),
550 (unsigned long long)rdev->gart.table_addr);
551 rdev->gart.ready = true;
555 static void rs600_gart_disable(struct radeon_device *rdev)
559 /* FIXME: disable out of gart access */
560 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
561 tmp = RREG32_MC(R_000009_MC_CNTL1);
562 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
563 radeon_gart_table_vram_unpin(rdev);
566 static void rs600_gart_fini(struct radeon_device *rdev)
568 radeon_gart_fini(rdev);
569 rs600_gart_disable(rdev);
570 radeon_gart_table_vram_free(rdev);
573 #define R600_PTE_VALID (1 << 0)
574 #define R600_PTE_SYSTEM (1 << 1)
575 #define R600_PTE_SNOOPED (1 << 2)
576 #define R600_PTE_READABLE (1 << 5)
577 #define R600_PTE_WRITEABLE (1 << 6)
579 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
581 uint64_t *ptr = rdev->gart.ptr;
583 if (i < 0 || i > rdev->gart.num_gpu_pages) {
586 addr = addr & 0xFFFFFFFFFFFFF000ULL;
587 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
588 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
593 int rs600_irq_set(struct radeon_device *rdev)
596 uint32_t mode_int = 0;
597 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
598 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
599 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
600 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
602 if (ASIC_IS_DCE2(rdev))
603 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
604 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
608 if (!rdev->irq.installed) {
609 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
610 WREG32(R_000040_GEN_INT_CNTL, 0);
613 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
614 tmp |= S_000040_SW_INT_EN(1);
616 if (rdev->irq.crtc_vblank_int[0] ||
617 atomic_read(&rdev->irq.pflip[0])) {
618 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
620 if (rdev->irq.crtc_vblank_int[1] ||
621 atomic_read(&rdev->irq.pflip[1])) {
622 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
624 if (rdev->irq.hpd[0]) {
625 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
627 if (rdev->irq.hpd[1]) {
628 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
630 if (rdev->irq.afmt[0]) {
631 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
633 WREG32(R_000040_GEN_INT_CNTL, tmp);
634 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
635 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
636 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
637 if (ASIC_IS_DCE2(rdev))
638 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
642 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
644 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
645 uint32_t irq_mask = S_000044_SW_INT(1);
648 if (G_000044_DISPLAY_INT_STAT(irqs)) {
649 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
650 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
651 WREG32(R_006534_D1MODE_VBLANK_STATUS,
652 S_006534_D1MODE_VBLANK_ACK(1));
654 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
655 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
656 S_006D34_D2MODE_VBLANK_ACK(1));
658 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
659 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
660 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
661 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
663 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
664 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
665 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
666 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
669 rdev->irq.stat_regs.r500.disp_int = 0;
672 if (ASIC_IS_DCE2(rdev)) {
673 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
674 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
675 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
676 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
677 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
678 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
681 rdev->irq.stat_regs.r500.hdmi0_status = 0;
684 WREG32(R_000044_GEN_INT_STATUS, irqs);
686 return irqs & irq_mask;
689 void rs600_irq_disable(struct radeon_device *rdev)
691 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
692 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
693 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
694 WREG32(R_000040_GEN_INT_CNTL, 0);
695 WREG32(R_006540_DxMODE_INT_MASK, 0);
696 /* Wait and acknowledge irq */
701 irqreturn_t rs600_irq_process(struct radeon_device *rdev)
703 u32 status, msi_rearm;
704 bool queue_hotplug = false;
705 bool queue_hdmi = false;
707 status = rs600_irq_ack(rdev);
709 !rdev->irq.stat_regs.r500.disp_int &&
710 !rdev->irq.stat_regs.r500.hdmi0_status) {
714 rdev->irq.stat_regs.r500.disp_int ||
715 rdev->irq.stat_regs.r500.hdmi0_status) {
717 if (G_000044_SW_INT(status)) {
718 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
720 /* Vertical blank interrupts */
721 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
722 if (rdev->irq.crtc_vblank_int[0]) {
723 drm_handle_vblank(rdev->ddev, 0);
724 rdev->pm.vblank_sync = true;
725 wake_up(&rdev->irq.vblank_queue);
727 if (atomic_read(&rdev->irq.pflip[0]))
728 radeon_crtc_handle_flip(rdev, 0);
730 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
731 if (rdev->irq.crtc_vblank_int[1]) {
732 drm_handle_vblank(rdev->ddev, 1);
733 rdev->pm.vblank_sync = true;
734 wake_up(&rdev->irq.vblank_queue);
736 if (atomic_read(&rdev->irq.pflip[1]))
737 radeon_crtc_handle_flip(rdev, 1);
739 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
740 queue_hotplug = true;
743 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
744 queue_hotplug = true;
747 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
749 DRM_DEBUG("HDMI0\n");
751 status = rs600_irq_ack(rdev);
754 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work);
756 taskqueue_enqueue(rdev->tq, &rdev->audio_work);
757 if (rdev->msi_enabled) {
758 switch (rdev->family) {
762 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
763 WREG32(RADEON_BUS_CNTL, msi_rearm);
764 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
767 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
774 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
777 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
779 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
782 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
786 for (i = 0; i < rdev->usec_timeout; i++) {
787 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
794 static void rs600_gpu_init(struct radeon_device *rdev)
796 r420_pipes_init(rdev);
797 /* Wait for mc idle */
798 if (rs600_mc_wait_for_idle(rdev))
799 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
802 static void rs600_mc_init(struct radeon_device *rdev)
806 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
807 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
808 rdev->mc.vram_is_ddr = true;
809 rdev->mc.vram_width = 128;
810 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
811 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
812 rdev->mc.visible_vram_size = rdev->mc.aper_size;
813 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
814 base = RREG32_MC(R_000004_MC_FB_LOCATION);
815 base = G_000004_MC_FB_START(base) << 16;
816 radeon_vram_location(rdev, &rdev->mc, base);
817 rdev->mc.gtt_base_align = 0;
818 radeon_gtt_location(rdev, &rdev->mc);
819 radeon_update_bandwidth_info(rdev);
822 void rs600_bandwidth_update(struct radeon_device *rdev)
824 struct drm_display_mode *mode0 = NULL;
825 struct drm_display_mode *mode1 = NULL;
826 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
827 /* FIXME: implement full support */
829 radeon_update_display_priority(rdev);
831 if (rdev->mode_info.crtcs[0]->base.enabled)
832 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
833 if (rdev->mode_info.crtcs[1]->base.enabled)
834 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
836 rs690_line_buffer_adjust(rdev, mode0, mode1);
838 if (rdev->disp_priority == 2) {
839 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
840 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
841 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
842 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
843 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
844 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
845 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
846 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
850 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
852 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
853 S_000070_MC_IND_CITF_ARB0(1));
854 return RREG32(R_000074_MC_IND_DATA);
857 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
859 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
860 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
861 WREG32(R_000074_MC_IND_DATA, v);
864 static void rs600_debugfs(struct radeon_device *rdev)
866 if (r100_debugfs_rbbm_init(rdev))
867 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
870 void rs600_set_safe_registers(struct radeon_device *rdev)
872 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
873 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
876 static void rs600_mc_program(struct radeon_device *rdev)
878 struct rv515_mc_save save;
880 /* Stops all mc clients */
881 rv515_mc_stop(rdev, &save);
883 /* Wait for mc idle */
884 if (rs600_mc_wait_for_idle(rdev))
885 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
887 /* FIXME: What does AGP means for such chipset ? */
888 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
889 WREG32_MC(R_000006_AGP_BASE, 0);
890 WREG32_MC(R_000007_AGP_BASE_2, 0);
892 WREG32_MC(R_000004_MC_FB_LOCATION,
893 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
894 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
895 WREG32(R_000134_HDP_FB_LOCATION,
896 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
898 rv515_mc_resume(rdev, &save);
901 static int rs600_startup(struct radeon_device *rdev)
905 rs600_mc_program(rdev);
907 rv515_clock_startup(rdev);
908 /* Initialize GPU configuration (# pipes, ...) */
909 rs600_gpu_init(rdev);
910 /* Initialize GART (initialize after TTM so we can allocate
911 * memory through TTM but finalize after TTM) */
912 r = rs600_gart_enable(rdev);
916 /* allocate wb buffer */
917 r = radeon_wb_init(rdev);
921 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
923 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
928 if (!rdev->irq.installed) {
929 r = radeon_irq_kms_init(rdev);
935 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
937 r = r100_cp_init(rdev, 1024 * 1024);
939 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
943 r = radeon_ib_pool_init(rdev);
945 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
949 r = r600_audio_init(rdev);
951 dev_err(rdev->dev, "failed initializing audio\n");
958 int rs600_resume(struct radeon_device *rdev)
962 /* Make sur GART are not working */
963 rs600_gart_disable(rdev);
964 /* Resume clock before doing reset */
965 rv515_clock_startup(rdev);
966 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
967 if (radeon_asic_reset(rdev)) {
968 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
969 RREG32(R_000E40_RBBM_STATUS),
970 RREG32(R_0007C0_CP_STAT));
973 atom_asic_init(rdev->mode_info.atom_context);
974 /* Resume clock after posting */
975 rv515_clock_startup(rdev);
976 /* Initialize surface registers */
977 radeon_surface_init(rdev);
979 rdev->accel_working = true;
980 r = rs600_startup(rdev);
982 rdev->accel_working = false;
987 int rs600_suspend(struct radeon_device *rdev)
989 r600_audio_fini(rdev);
990 r100_cp_disable(rdev);
991 radeon_wb_disable(rdev);
992 rs600_irq_disable(rdev);
993 rs600_gart_disable(rdev);
997 void rs600_fini(struct radeon_device *rdev)
999 r600_audio_fini(rdev);
1001 radeon_wb_fini(rdev);
1002 radeon_ib_pool_fini(rdev);
1003 radeon_gem_fini(rdev);
1004 rs600_gart_fini(rdev);
1005 radeon_irq_kms_fini(rdev);
1006 radeon_fence_driver_fini(rdev);
1007 radeon_bo_fini(rdev);
1008 radeon_atombios_fini(rdev);
1013 int rs600_init(struct radeon_device *rdev)
1018 rv515_vga_render_disable(rdev);
1019 /* Initialize scratch registers */
1020 radeon_scratch_init(rdev);
1021 /* Initialize surface registers */
1022 radeon_surface_init(rdev);
1023 /* restore some register to sane defaults */
1024 r100_restore_sanity(rdev);
1026 if (!radeon_get_bios(rdev)) {
1027 if (ASIC_IS_AVIVO(rdev))
1030 if (rdev->is_atom_bios) {
1031 r = radeon_atombios_init(rdev);
1035 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1038 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1039 if (radeon_asic_reset(rdev)) {
1041 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1042 RREG32(R_000E40_RBBM_STATUS),
1043 RREG32(R_0007C0_CP_STAT));
1045 /* check if cards are posted or not */
1046 if (radeon_boot_test_post_card(rdev) == false)
1049 /* Initialize clocks */
1050 radeon_get_clock_info(rdev->ddev);
1051 /* initialize memory controller */
1052 rs600_mc_init(rdev);
1053 rs600_debugfs(rdev);
1055 r = radeon_fence_driver_init(rdev);
1058 /* Memory manager */
1059 r = radeon_bo_init(rdev);
1062 r = rs600_gart_init(rdev);
1065 rs600_set_safe_registers(rdev);
1067 rdev->accel_working = true;
1068 r = rs600_startup(rdev);
1070 /* Somethings want wront with the accel init stop accel */
1071 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1073 radeon_wb_fini(rdev);
1074 radeon_ib_pool_fini(rdev);
1075 rs600_gart_fini(rdev);
1076 radeon_irq_kms_fini(rdev);
1077 rdev->accel_working = false;