2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cs.c 254885 2013-08-25 19:37:15Z dumbbell $
31 #include <uapi_drm/radeon_drm.h>
32 #include "radeon_reg.h"
35 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
42 if (p->chunk_relocs_idx == -1) {
45 chunk = &p->chunks[p->chunk_relocs_idx];
47 /* FIXME: we assume that each relocs use 4 dwords */
48 p->nrelocs = chunk->length_dw / 4;
49 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
50 if (p->relocs_ptr == NULL) {
53 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
54 if (p->relocs == NULL) {
57 for (i = 0; i < p->nrelocs; i++) {
58 struct drm_radeon_cs_reloc *r;
61 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
62 for (j = 0; j < i; j++) {
63 if (r->handle == p->relocs[j].handle) {
64 p->relocs_ptr[i] = &p->relocs[j];
70 p->relocs[i].handle = 0;
74 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
76 if (p->relocs[i].gobj == NULL) {
77 DRM_ERROR("gem object lookup failed 0x%x\n",
81 p->relocs_ptr[i] = &p->relocs[i];
82 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
83 p->relocs[i].lobj.bo = p->relocs[i].robj;
84 p->relocs[i].lobj.written = !!r->write_domain;
86 /* the first reloc of an UVD job is the
87 msg and that must be in VRAM */
88 if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) {
89 /* TODO: is this still needed for NI+ ? */
90 p->relocs[i].lobj.domain =
91 RADEON_GEM_DOMAIN_VRAM;
93 p->relocs[i].lobj.alt_domain =
94 RADEON_GEM_DOMAIN_VRAM;
97 uint32_t domain = r->write_domain ?
98 r->write_domain : r->read_domains;
100 p->relocs[i].lobj.domain = domain;
101 if (domain == RADEON_GEM_DOMAIN_VRAM)
102 domain |= RADEON_GEM_DOMAIN_GTT;
103 p->relocs[i].lobj.alt_domain = domain;
106 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
107 p->relocs[i].handle = r->handle;
109 radeon_bo_list_add_object(&p->relocs[i].lobj,
112 return radeon_bo_list_validate(&p->validated, p->ring);
115 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
117 p->priority = priority;
121 DRM_ERROR("unknown ring id: %d\n", ring);
123 case RADEON_CS_RING_GFX:
124 p->ring = RADEON_RING_TYPE_GFX_INDEX;
126 case RADEON_CS_RING_COMPUTE:
127 if (p->rdev->family >= CHIP_TAHITI) {
129 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
131 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
133 p->ring = RADEON_RING_TYPE_GFX_INDEX;
135 case RADEON_CS_RING_DMA:
136 if (p->rdev->family >= CHIP_CAYMAN) {
138 p->ring = R600_RING_TYPE_DMA_INDEX;
140 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
141 } else if (p->rdev->family >= CHIP_R600) {
142 p->ring = R600_RING_TYPE_DMA_INDEX;
147 case RADEON_CS_RING_UVD:
148 p->ring = R600_RING_TYPE_UVD_INDEX;
154 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
158 for (i = 0; i < p->nrelocs; i++) {
159 if (!p->relocs[i].robj)
162 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
166 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
167 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
169 struct drm_radeon_cs *cs = data;
170 uint64_t *chunk_array_ptr;
172 u32 ring = RADEON_CS_RING_GFX;
175 if (!cs->num_chunks) {
179 INIT_LIST_HEAD(&p->validated);
182 p->ib.semaphore = NULL;
183 p->const_ib.sa_bo = NULL;
184 p->const_ib.semaphore = NULL;
185 p->chunk_ib_idx = -1;
186 p->chunk_relocs_idx = -1;
187 p->chunk_flags_idx = -1;
188 p->chunk_const_ib_idx = -1;
189 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
190 if (p->chunks_array == NULL) {
193 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
194 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
195 sizeof(uint64_t)*cs->num_chunks)) {
199 p->nchunks = cs->num_chunks;
200 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
201 if (p->chunks == NULL) {
204 for (i = 0; i < p->nchunks; i++) {
205 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
206 struct drm_radeon_cs_chunk user_chunk;
207 uint32_t __user *cdata;
209 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
210 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
211 sizeof(struct drm_radeon_cs_chunk))) {
214 p->chunks[i].length_dw = user_chunk.length_dw;
215 p->chunks[i].kdata = NULL;
216 p->chunks[i].chunk_id = user_chunk.chunk_id;
217 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
218 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
219 p->chunk_relocs_idx = i;
221 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
223 /* zero length IB isn't useful */
224 if (p->chunks[i].length_dw == 0)
227 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
228 p->chunk_const_ib_idx = i;
229 /* zero length CONST IB isn't useful */
230 if (p->chunks[i].length_dw == 0)
233 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
234 p->chunk_flags_idx = i;
235 /* zero length flags aren't useful */
236 if (p->chunks[i].length_dw == 0)
240 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
241 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
242 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
243 size = p->chunks[i].length_dw * sizeof(uint32_t);
244 p->chunks[i].kdata = kmalloc(size, M_DRM,
246 if (p->chunks[i].kdata == NULL) {
249 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
250 p->chunks[i].user_ptr, size)) {
253 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
254 p->cs_flags = p->chunks[i].kdata[0];
255 if (p->chunks[i].length_dw > 1)
256 ring = p->chunks[i].kdata[1];
257 if (p->chunks[i].length_dw > 2)
258 priority = (s32)p->chunks[i].kdata[2];
263 /* these are KMS only */
265 if ((p->cs_flags & RADEON_CS_USE_VM) &&
266 !p->rdev->vm_manager.enabled) {
267 DRM_ERROR("VM not active on asic!\n");
271 if (radeon_cs_get_ring(p, ring, priority))
274 /* we only support VM on some SI+ rings */
275 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) &&
276 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
277 DRM_ERROR("Ring %d requires VM!\n", p->ring);
282 /* deal with non-vm */
283 if ((p->chunk_ib_idx != -1) &&
284 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
285 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
286 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
287 DRM_ERROR("cs IB too big: %d\n",
288 p->chunks[p->chunk_ib_idx].length_dw);
291 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
292 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE,
295 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE,
298 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
299 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
300 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
301 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
302 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
303 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
307 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
308 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
309 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
310 p->chunks[p->chunk_ib_idx].last_page_index =
311 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
318 * cs_parser_fini() - clean parser states
319 * @parser: parser structure holding parsing context.
320 * @error: error number
322 * If error is set than unvalidate buffer, otherwise just free memory
323 * used by parsing context.
325 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
330 ttm_eu_fence_buffer_objects(&parser->validated,
333 ttm_eu_backoff_reservation(&parser->validated);
336 if (parser->relocs != NULL) {
337 for (i = 0; i < parser->nrelocs; i++) {
338 if (parser->relocs[i].gobj)
339 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
342 kfree(parser->track);
343 kfree(parser->relocs);
344 kfree(parser->relocs_ptr);
345 for (i = 0; i < parser->nchunks; i++) {
346 kfree(parser->chunks[i].kdata);
347 if ((parser->rdev->flags & RADEON_IS_AGP)) {
348 kfree(parser->chunks[i].kpage[0]);
349 kfree(parser->chunks[i].kpage[1]);
352 kfree(parser->chunks);
353 kfree(parser->chunks_array);
354 radeon_ib_free(parser->rdev, &parser->ib);
355 radeon_ib_free(parser->rdev, &parser->const_ib);
358 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
359 struct radeon_cs_parser *parser)
361 struct radeon_cs_chunk *ib_chunk;
364 if (parser->chunk_ib_idx == -1)
367 if (parser->cs_flags & RADEON_CS_USE_VM)
370 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
371 /* Copy the packet into the IB, the parser will read from the
372 * input memory (cached) and write to the IB (which can be
375 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
376 NULL, ib_chunk->length_dw * 4);
378 DRM_ERROR("Failed to get ib !\n");
381 parser->ib.length_dw = ib_chunk->length_dw;
382 r = radeon_cs_parse(rdev, parser->ring, parser);
383 if (r || parser->parser_error) {
384 DRM_ERROR("Invalid command stream !\n");
387 r = radeon_cs_finish_pages(parser);
389 DRM_ERROR("Invalid command stream !\n");
392 radeon_cs_sync_rings(parser);
393 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
395 DRM_ERROR("Failed to schedule IB !\n");
400 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
401 struct radeon_vm *vm)
403 struct radeon_device *rdev = parser->rdev;
404 struct radeon_bo_list *lobj;
405 struct radeon_bo *bo;
408 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
412 list_for_each_entry(lobj, &parser->validated, tv.head) {
414 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
422 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
423 struct radeon_cs_parser *parser)
425 struct radeon_cs_chunk *ib_chunk;
426 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
427 struct radeon_vm *vm = &fpriv->vm;
430 if (parser->chunk_ib_idx == -1)
432 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
435 if ((rdev->family >= CHIP_TAHITI) &&
436 (parser->chunk_const_ib_idx != -1)) {
437 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
438 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
439 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
442 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
443 vm, ib_chunk->length_dw * 4);
445 DRM_ERROR("Failed to get const ib !\n");
448 parser->const_ib.is_const_ib = true;
449 parser->const_ib.length_dw = ib_chunk->length_dw;
450 /* Copy the packet into the IB */
451 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
452 ib_chunk->length_dw * 4)) {
455 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
461 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
462 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
463 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
466 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
467 vm, ib_chunk->length_dw * 4);
469 DRM_ERROR("Failed to get ib !\n");
472 parser->ib.length_dw = ib_chunk->length_dw;
473 /* Copy the packet into the IB */
474 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
475 ib_chunk->length_dw * 4)) {
478 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
483 lockmgr(&rdev->vm_manager.lock, LK_EXCLUSIVE);
484 lockmgr(&vm->mutex, LK_EXCLUSIVE);
485 r = radeon_vm_alloc_pt(rdev, vm);
489 r = radeon_bo_vm_update_pte(parser, vm);
493 radeon_cs_sync_rings(parser);
494 radeon_ib_sync_to(&parser->ib, vm->fence);
495 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
496 rdev, vm, parser->ring));
498 if ((rdev->family >= CHIP_TAHITI) &&
499 (parser->chunk_const_ib_idx != -1)) {
500 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
502 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
506 radeon_vm_fence(rdev, vm, parser->ib.fence);
510 radeon_vm_add_to_lru(rdev, vm);
511 lockmgr(&vm->mutex, LK_RELEASE);
512 lockmgr(&rdev->vm_manager.lock, LK_RELEASE);
516 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
519 r = radeon_gpu_reset(rdev);
526 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
528 struct radeon_device *rdev = dev->dev_private;
529 struct radeon_cs_parser parser;
532 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
533 if (!rdev->accel_working) {
534 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
537 /* initialize parser */
538 memset(&parser, 0, sizeof(struct radeon_cs_parser));
541 parser.dev = rdev->dev;
542 parser.family = rdev->family;
543 r = radeon_cs_parser_init(&parser, data);
545 DRM_ERROR("Failed to initialize parser !\n");
546 radeon_cs_parser_fini(&parser, r);
547 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
548 r = radeon_cs_handle_lockup(rdev, r);
551 r = radeon_cs_parser_relocs(&parser);
553 if (r != -ERESTARTSYS)
554 DRM_ERROR("Failed to parse relocation %d!\n", r);
555 radeon_cs_parser_fini(&parser, r);
556 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
557 r = radeon_cs_handle_lockup(rdev, r);
561 /* XXX pick SD/HD/MVC */
562 if (parser.ring == R600_RING_TYPE_UVD_INDEX)
563 radeon_uvd_note_usage(rdev);
565 r = radeon_cs_ib_chunk(rdev, &parser);
569 r = radeon_cs_ib_vm_chunk(rdev, &parser);
574 radeon_cs_parser_fini(&parser, r);
575 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
576 r = radeon_cs_handle_lockup(rdev, r);
580 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
582 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
584 int size = PAGE_SIZE;
586 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
587 if (i == ibc->last_page_index) {
588 size = (ibc->length_dw * 4) % PAGE_SIZE;
593 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
594 (char *)ibc->user_ptr + (i * PAGE_SIZE),
601 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
604 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
606 int size = PAGE_SIZE;
607 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
610 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
611 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
612 (char *)ibc->user_ptr + (i * PAGE_SIZE),
614 p->parser_error = -EFAULT;
619 if (pg_idx == ibc->last_page_index) {
620 size = (ibc->length_dw * 4) % PAGE_SIZE;
625 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
627 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
629 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
630 (char *)ibc->user_ptr + (pg_idx * PAGE_SIZE),
632 p->parser_error = -EFAULT;
636 /* copy to IB for non single case */
638 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
640 ibc->last_copied_page = pg_idx;
641 ibc->kpage_idx[new_page] = pg_idx;
646 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
648 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
649 u32 pg_idx, pg_offset;
653 pg_idx = (idx * 4) / PAGE_SIZE;
654 pg_offset = (idx * 4) % PAGE_SIZE;
656 if (ibc->kpage_idx[0] == pg_idx)
657 return ibc->kpage[0][pg_offset/4];
658 if (ibc->kpage_idx[1] == pg_idx)
659 return ibc->kpage[1][pg_offset/4];
661 new_page = radeon_cs_update_pages(p, pg_idx);
663 p->parser_error = new_page;
667 idx_value = ibc->kpage[new_page][pg_offset/4];
672 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
673 * @parser: parser structure holding parsing context.
674 * @pkt: where to store packet information
676 * Assume that chunk_ib_index is properly set. Will return -EINVAL
677 * if packet is bigger than remaining ib size. or if packets is unknown.
679 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
680 struct radeon_cs_packet *pkt,
683 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
684 struct radeon_device *rdev = p->rdev;
687 if (idx >= ib_chunk->length_dw) {
688 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
689 idx, ib_chunk->length_dw);
692 header = radeon_get_ib_value(p, idx);
694 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
695 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
698 case RADEON_PACKET_TYPE0:
699 if (rdev->family < CHIP_R600) {
700 pkt->reg = R100_CP_PACKET0_GET_REG(header);
702 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
704 pkt->reg = R600_CP_PACKET0_GET_REG(header);
706 case RADEON_PACKET_TYPE3:
707 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
709 case RADEON_PACKET_TYPE2:
713 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
716 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
717 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
718 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
725 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
726 * @p: structure holding the parser context.
728 * Check if the next packet is NOP relocation packet3.
730 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
732 struct radeon_cs_packet p3reloc;
735 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
738 if (p3reloc.type != RADEON_PACKET_TYPE3)
740 if (p3reloc.opcode != RADEON_PACKET3_NOP)
746 * radeon_cs_dump_packet() - dump raw packet context
747 * @p: structure holding the parser context.
748 * @pkt: structure holding the packet.
750 * Used mostly for debugging and error reporting.
752 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
753 struct radeon_cs_packet *pkt)
755 volatile uint32_t *ib;
761 for (i = 0; i <= (pkt->count + 1); i++, idx++)
762 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
766 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
767 * @parser: parser structure holding parsing context.
768 * @data: pointer to relocation data
769 * @offset_start: starting offset
770 * @offset_mask: offset mask (to align start offset on)
771 * @reloc: reloc informations
773 * Check if next packet is relocation packet3, do bo validation and compute
774 * GPU offset using the provided start.
776 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
777 struct radeon_cs_reloc **cs_reloc,
780 struct radeon_cs_chunk *relocs_chunk;
781 struct radeon_cs_packet p3reloc;
785 if (p->chunk_relocs_idx == -1) {
786 DRM_ERROR("No relocation chunk !\n");
790 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
791 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
794 p->idx += p3reloc.count + 2;
795 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
796 p3reloc.opcode != RADEON_PACKET3_NOP) {
797 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
799 radeon_cs_dump_packet(p, &p3reloc);
802 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
803 if (idx >= relocs_chunk->length_dw) {
804 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
805 idx, relocs_chunk->length_dw);
806 radeon_cs_dump_packet(p, &p3reloc);
809 /* FIXME: we assume reloc size is 4 dwords */
811 *cs_reloc = p->relocs;
812 (*cs_reloc)->lobj.gpu_offset =
813 (u64)relocs_chunk->kdata[idx + 3] << 32;
814 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
816 *cs_reloc = p->relocs_ptr[(idx / 4)];