2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
59 #include <drm/i915_drm.h>
61 #include "intel_drv.h"
62 #include <linux/shmem_fs.h>
63 #include <linux/completion.h>
64 #include <linux/highmem.h>
65 #include <linux/jiffies.h>
66 #include <linux/time.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
70 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
72 bool map_and_fenceable,
74 static int i915_gem_phys_pwrite(struct drm_device *dev,
75 struct drm_i915_gem_object *obj,
76 struct drm_i915_gem_pwrite *args,
77 struct drm_file *file);
79 static void i915_gem_write_fence(struct drm_device *dev, int reg,
80 struct drm_i915_gem_object *obj);
81 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
82 struct drm_i915_fence_reg *fence,
85 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
87 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
88 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
90 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
93 i915_gem_release_mmap(obj);
95 /* As we do not have an associated fence register, we will force
96 * a tiling change if we ever need to acquire one.
98 obj->fence_dirty = false;
99 obj->fence_reg = I915_FENCE_REG_NONE;
102 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
103 static void i915_gem_lowmem(void *arg);
105 /* some bookkeeping */
106 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
109 dev_priv->mm.object_count++;
110 dev_priv->mm.object_memory += size;
113 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
116 dev_priv->mm.object_count--;
117 dev_priv->mm.object_memory -= size;
121 i915_gem_wait_for_error(struct i915_gpu_error *error)
125 #define EXIT_COND (!i915_reset_in_progress(error) || \
126 i915_terminally_wedged(error))
131 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
132 * userspace. If it takes that long something really bad is going on and
133 * we should simply try to bail out and fail as gracefully as possible.
135 ret = wait_event_interruptible_timeout(error->reset_queue,
139 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
141 } else if (ret < 0) {
149 int i915_mutex_lock_interruptible(struct drm_device *dev)
151 struct drm_i915_private *dev_priv = dev->dev_private;
154 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
158 ret = lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
162 WARN_ON(i915_verify_lists(dev));
167 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
173 i915_gem_init_ioctl(struct drm_device *dev, void *data,
174 struct drm_file *file)
176 struct drm_i915_gem_init *args = data;
178 if (drm_core_check_feature(dev, DRIVER_MODESET))
181 if (args->gtt_start >= args->gtt_end ||
182 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
185 /* GEM with user mode setting was never supported on ilk and later. */
186 if (INTEL_INFO(dev)->gen >= 5)
189 mutex_lock(&dev->struct_mutex);
190 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
192 mutex_unlock(&dev->struct_mutex);
198 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
199 struct drm_file *file)
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct drm_i915_gem_get_aperture *args = data;
203 struct drm_i915_gem_object *obj;
207 mutex_lock(&dev->struct_mutex);
208 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
210 pinned += obj->gtt_space->size;
211 mutex_unlock(&dev->struct_mutex);
213 args->aper_size = dev_priv->gtt.total;
214 args->aper_available_size = args->aper_size - pinned;
220 i915_gem_create(struct drm_file *file,
221 struct drm_device *dev,
225 struct drm_i915_gem_object *obj;
229 size = roundup(size, PAGE_SIZE);
233 /* Allocate the new object */
234 obj = i915_gem_alloc_object(dev, size);
239 ret = drm_gem_handle_create(file, &obj->base, &handle);
241 drm_gem_object_release(&obj->base);
242 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
243 drm_free(obj, M_DRM);
247 /* drop reference from allocate - handle holds it now */
248 drm_gem_object_unreference(&obj->base);
254 i915_gem_dumb_create(struct drm_file *file,
255 struct drm_device *dev,
256 struct drm_mode_create_dumb *args)
259 /* have to work out size/pitch and return them */
260 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
261 args->size = args->pitch * args->height;
262 return i915_gem_create(file, dev,
263 args->size, &args->handle);
266 int i915_gem_dumb_destroy(struct drm_file *file,
267 struct drm_device *dev,
271 return drm_gem_handle_delete(file, handle);
275 * Creates a new mm object and returns a handle to it.
278 i915_gem_create_ioctl(struct drm_device *dev, void *data,
279 struct drm_file *file)
281 struct drm_i915_gem_create *args = data;
283 return i915_gem_create(file, dev,
284 args->size, &args->handle);
287 static inline void vm_page_reference(vm_page_t m)
289 vm_page_flag_set(m, PG_REFERENCED);
293 i915_gem_shmem_pread(struct drm_device *dev,
294 struct drm_i915_gem_object *obj,
295 struct drm_i915_gem_pread *args,
296 struct drm_file *file)
303 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
305 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
308 vm_obj = obj->base.vm_obj;
311 VM_OBJECT_LOCK(vm_obj);
312 vm_object_pip_add(vm_obj, 1);
313 while (args->size > 0) {
314 obj_pi = OFF_TO_IDX(args->offset);
315 obj_po = args->offset & PAGE_MASK;
317 m = shmem_read_mapping_page(vm_obj, obj_pi);
318 VM_OBJECT_UNLOCK(vm_obj);
320 sf = sf_buf_alloc(m);
321 mkva = sf_buf_kva(sf);
322 length = min(args->size, PAGE_SIZE - obj_po);
324 if (do_bit17_swizzling &&
325 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
326 cnt = roundup2(obj_po + 1, 64);
327 cnt = min(cnt - obj_po, length);
328 swizzled_po = obj_po ^ 64;
331 swizzled_po = obj_po;
333 ret = -copyout_nofault(
334 (char *)mkva + swizzled_po,
335 (void *)(uintptr_t)args->data_ptr, cnt);
338 args->data_ptr += cnt;
345 VM_OBJECT_LOCK(vm_obj);
346 vm_page_reference(m);
347 vm_page_busy_wait(m, FALSE, "i915gem");
348 vm_page_unwire(m, 1);
354 vm_object_pip_wakeup(vm_obj);
355 VM_OBJECT_UNLOCK(vm_obj);
361 * Reads data from the object referenced by handle.
363 * On error, the contents of *data are undefined.
366 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
367 struct drm_file *file)
369 struct drm_i915_gem_pread *args = data;
370 struct drm_i915_gem_object *obj;
376 ret = i915_mutex_lock_interruptible(dev);
380 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
381 if (&obj->base == NULL) {
386 /* Bounds check source. */
387 if (args->offset > obj->base.size ||
388 args->size > obj->base.size - args->offset) {
393 ret = i915_gem_shmem_pread(dev, obj, args, file);
395 drm_gem_object_unreference(&obj->base);
397 mutex_unlock(&dev->struct_mutex);
402 /* This is the fast write path which cannot handle
403 * page faults in the source data
407 fast_user_write(struct io_mapping *mapping,
408 loff_t page_base, int page_offset,
409 char __user *user_data,
412 void __iomem *vaddr_atomic;
414 unsigned long unwritten;
416 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
417 /* We can use the cpu mem copy function because this is X86. */
418 vaddr = (void __force*)vaddr_atomic + page_offset;
419 unwritten = __copy_from_user_inatomic_nocache(vaddr,
421 io_mapping_unmap_atomic(vaddr_atomic);
426 * This is the fast pwrite path, where we copy the data directly from the
427 * user into the GTT, uncached.
430 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
431 struct drm_i915_gem_object *obj,
432 struct drm_i915_gem_pwrite *args,
433 struct drm_file *file)
435 drm_i915_private_t *dev_priv = dev->dev_private;
437 loff_t offset, page_base;
438 char __user *user_data;
439 int page_offset, page_length, ret;
441 ret = i915_gem_object_pin(obj, 0, true, true);
445 ret = i915_gem_object_set_to_gtt_domain(obj, true);
449 ret = i915_gem_object_put_fence(obj);
453 user_data = to_user_ptr(args->data_ptr);
456 offset = obj->gtt_offset + args->offset;
459 /* Operation in this page
461 * page_base = page offset within aperture
462 * page_offset = offset within page
463 * page_length = bytes to copy for this page
465 page_base = offset & PAGE_MASK;
466 page_offset = offset_in_page(offset);
467 page_length = remain;
468 if ((page_offset + remain) > PAGE_SIZE)
469 page_length = PAGE_SIZE - page_offset;
471 /* If we get a fault while copying data, then (presumably) our
472 * source page isn't available. Return the error and we'll
473 * retry in the slow path.
475 if (fast_user_write(dev_priv->gtt.mappable, page_base,
476 page_offset, user_data, page_length)) {
481 remain -= page_length;
482 user_data += page_length;
483 offset += page_length;
487 i915_gem_object_unpin(obj);
494 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
495 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
501 * Pass the unaligned physical address and size to pmap_mapdev_attr()
502 * so it can properly calculate whether an extra page needs to be
503 * mapped or not to cover the requested range. The function will
504 * add the page offset into the returned mkva for us.
506 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
507 offset, size, PAT_WRITE_COMBINING);
508 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
509 pmap_unmapdev(mkva, size);
514 i915_gem_shmem_pwrite(struct drm_device *dev,
515 struct drm_i915_gem_object *obj,
516 struct drm_i915_gem_pwrite *args,
517 struct drm_file *file)
524 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
526 do_bit17_swizzling = 0;
529 vm_obj = obj->base.vm_obj;
532 VM_OBJECT_LOCK(vm_obj);
533 vm_object_pip_add(vm_obj, 1);
534 while (args->size > 0) {
535 obj_pi = OFF_TO_IDX(args->offset);
536 obj_po = args->offset & PAGE_MASK;
538 m = shmem_read_mapping_page(vm_obj, obj_pi);
539 VM_OBJECT_UNLOCK(vm_obj);
541 sf = sf_buf_alloc(m);
542 mkva = sf_buf_kva(sf);
543 length = min(args->size, PAGE_SIZE - obj_po);
545 if (do_bit17_swizzling &&
546 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
547 cnt = roundup2(obj_po + 1, 64);
548 cnt = min(cnt - obj_po, length);
549 swizzled_po = obj_po ^ 64;
552 swizzled_po = obj_po;
554 ret = -copyin_nofault(
555 (void *)(uintptr_t)args->data_ptr,
556 (char *)mkva + swizzled_po, cnt);
559 args->data_ptr += cnt;
566 VM_OBJECT_LOCK(vm_obj);
568 vm_page_reference(m);
569 vm_page_busy_wait(m, FALSE, "i915gem");
570 vm_page_unwire(m, 1);
576 vm_object_pip_wakeup(vm_obj);
577 VM_OBJECT_UNLOCK(vm_obj);
583 * Writes data to the object referenced by handle.
585 * On error, the contents of the buffer that were to be modified are undefined.
588 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
589 struct drm_file *file)
591 struct drm_i915_gem_pwrite *args = data;
592 struct drm_i915_gem_object *obj;
594 vm_offset_t start, end;
600 start = trunc_page(args->data_ptr);
601 end = round_page(args->data_ptr + args->size);
602 npages = howmany(end - start, PAGE_SIZE);
603 ma = kmalloc(npages * sizeof(vm_page_t), M_DRM, M_WAITOK |
605 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
606 (vm_offset_t)args->data_ptr, args->size,
607 VM_PROT_READ, ma, npages);
613 ret = i915_mutex_lock_interruptible(dev);
617 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
618 if (&obj->base == NULL) {
623 /* Bounds check destination. */
624 if (args->offset > obj->base.size ||
625 args->size > obj->base.size - args->offset) {
631 ret = i915_gem_phys_pwrite(dev, obj, args, file);
632 } else if (obj->gtt_space &&
633 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
634 ret = i915_gem_object_pin(obj, 0, true, false);
637 ret = i915_gem_object_set_to_gtt_domain(obj, true);
640 ret = i915_gem_object_put_fence(obj);
643 ret = i915_gem_gtt_write(dev, obj, args->data_ptr, args->size,
646 i915_gem_object_unpin(obj);
648 ret = i915_gem_object_set_to_cpu_domain(obj, true);
651 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
654 drm_gem_object_unreference(&obj->base);
656 mutex_unlock(&dev->struct_mutex);
658 vm_page_unhold_pages(ma, npages);
665 i915_gem_check_wedge(struct i915_gpu_error *error,
668 if (i915_reset_in_progress(error)) {
669 /* Non-interruptible callers can't handle -EAGAIN, hence return
670 * -EIO unconditionally for these. */
674 /* Recovery complete, but the reset failed ... */
675 if (i915_terminally_wedged(error))
685 * Compare seqno against outstanding lazy request. Emit a request if they are
689 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
693 DRM_LOCK_ASSERT(ring->dev);
696 if (seqno == ring->outstanding_lazy_request)
697 ret = i915_add_request(ring, NULL, NULL);
703 * __wait_seqno - wait until execution of seqno has finished
704 * @ring: the ring expected to report seqno
706 * @reset_counter: reset sequence associated with the given seqno
707 * @interruptible: do an interruptible wait (normally yes)
708 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
710 * Note: It is of utmost importance that the passed in seqno and reset_counter
711 * values have been read by the caller in an smp safe manner. Where read-side
712 * locks are involved, it is sufficient to read the reset_counter before
713 * unlocking the lock that protects the seqno. For lockless tricks, the
714 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
717 * Returns 0 if the seqno was found within the alloted time. Else returns the
718 * errno with remaining time filled in timeout argument.
720 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
721 unsigned reset_counter,
722 bool interruptible, struct timespec *timeout)
724 drm_i915_private_t *dev_priv = ring->dev->dev_private;
725 struct timespec before, now, wait_time={1,0};
726 unsigned long timeout_jiffies;
728 bool wait_forever = true;
731 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
734 if (timeout != NULL) {
735 wait_time = *timeout;
736 wait_forever = false;
739 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
741 if (WARN_ON(!ring->irq_get(ring)))
744 /* Record current time in case interrupted by signal, or wedged * */
745 getrawmonotonic(&before);
748 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
749 i915_reset_in_progress(&dev_priv->gpu_error) || \
750 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
753 end = wait_event_interruptible_timeout(ring->irq_queue,
757 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
760 /* We need to check whether any gpu reset happened in between
761 * the caller grabbing the seqno and now ... */
762 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
765 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
767 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
770 } while (end == 0 && wait_forever);
772 getrawmonotonic(&now);
778 struct timespec sleep_time = timespec_sub(now, before);
779 *timeout = timespec_sub(*timeout, sleep_time);
780 if (!timespec_valid(timeout)) /* i.e. negative time remains */
781 set_normalized_timespec(timeout, 0, 0);
786 case -EAGAIN: /* Wedged */
787 case -ERESTARTSYS: /* Signal */
789 case 0: /* Timeout */
790 return -ETIMEDOUT; /* -ETIME on Linux */
791 default: /* Completed */
792 WARN_ON(end < 0); /* We're not aware of other errors */
798 * Waits for a sequence number to be signaled, and cleans up the
799 * request and object lists appropriately for that event.
802 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
804 struct drm_device *dev = ring->dev;
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 bool interruptible = dev_priv->mm.interruptible;
809 DRM_LOCK_ASSERT(dev);
812 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
816 ret = i915_gem_check_olr(ring, seqno);
820 return __wait_seqno(ring, seqno,
821 atomic_read(&dev_priv->gpu_error.reset_counter),
822 interruptible, NULL);
826 * Ensures that all rendering to the object has completed and the object is
827 * safe to unbind from the GTT or access from the CPU.
829 static __must_check int
830 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
833 struct intel_ring_buffer *ring = obj->ring;
837 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
841 ret = i915_wait_seqno(ring, seqno);
845 i915_gem_retire_requests_ring(ring);
847 /* Manually manage the write flush as we may have not yet
848 * retired the buffer.
850 if (obj->last_write_seqno &&
851 i915_seqno_passed(seqno, obj->last_write_seqno)) {
852 obj->last_write_seqno = 0;
853 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
859 /* A nonblocking variant of the above wait. This is a highly dangerous routine
860 * as the object state may change during this call.
862 static __must_check int
863 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
866 struct drm_device *dev = obj->base.dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
868 struct intel_ring_buffer *ring = obj->ring;
869 unsigned reset_counter;
873 DRM_LOCK_ASSERT(dev);
874 BUG_ON(!dev_priv->mm.interruptible);
876 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
880 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
884 ret = i915_gem_check_olr(ring, seqno);
888 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
889 mutex_unlock(&dev->struct_mutex);
890 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
891 mutex_lock(&dev->struct_mutex);
893 i915_gem_retire_requests_ring(ring);
895 /* Manually manage the write flush as we may have not yet
896 * retired the buffer.
898 if (obj->last_write_seqno &&
899 i915_seqno_passed(seqno, obj->last_write_seqno)) {
900 obj->last_write_seqno = 0;
901 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
908 * Called when user space prepares to use an object with the CPU, either
909 * through the mmap ioctl's mapping or a GTT mapping.
912 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
913 struct drm_file *file)
915 struct drm_i915_gem_set_domain *args = data;
916 struct drm_i915_gem_object *obj;
917 uint32_t read_domains = args->read_domains;
918 uint32_t write_domain = args->write_domain;
921 /* Only handle setting domains to types used by the CPU. */
922 if (write_domain & I915_GEM_GPU_DOMAINS)
925 if (read_domains & I915_GEM_GPU_DOMAINS)
928 /* Having something in the write domain implies it's in the read
929 * domain, and only that read domain. Enforce that in the request.
931 if (write_domain != 0 && read_domains != write_domain)
934 ret = i915_mutex_lock_interruptible(dev);
938 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
939 if (&obj->base == NULL) {
944 /* Try to flush the object off the GPU without holding the lock.
945 * We will repeat the flush holding the lock in the normal manner
946 * to catch cases where we are gazumped.
948 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
952 if (read_domains & I915_GEM_DOMAIN_GTT) {
953 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
955 /* Silently promote "you're not bound, there was nothing to do"
956 * to success, since the client was just asking us to
957 * make sure everything was done.
962 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
966 drm_gem_object_unreference(&obj->base);
968 mutex_unlock(&dev->struct_mutex);
973 * Called when user space has done writes to this buffer
976 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *file)
979 struct drm_i915_gem_sw_finish *args = data;
980 struct drm_i915_gem_object *obj;
983 ret = i915_mutex_lock_interruptible(dev);
986 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
987 if (&obj->base == NULL) {
992 /* Pinned buffers may be scanout, so flush the cache */
994 i915_gem_object_flush_cpu_write_domain(obj);
996 drm_gem_object_unreference(&obj->base);
998 mutex_unlock(&dev->struct_mutex);
1003 * Maps the contents of an object, returning the address it is mapped
1006 * While the mapping holds a reference on the contents of the object, it doesn't
1007 * imply a ref on the object itself.
1010 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1011 struct drm_file *file)
1013 struct drm_i915_gem_mmap *args = data;
1014 struct drm_gem_object *obj;
1015 struct proc *p = curproc;
1016 vm_map_t map = &p->p_vmspace->vm_map;
1021 obj = drm_gem_object_lookup(dev, file, args->handle);
1025 if (args->size == 0)
1028 size = round_page(args->size);
1029 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1035 vm_object_hold(obj->vm_obj);
1036 vm_object_reference_locked(obj->vm_obj);
1037 vm_object_drop(obj->vm_obj);
1038 rv = vm_map_find(map, obj->vm_obj, NULL,
1039 args->offset, &addr, args->size,
1040 PAGE_SIZE, /* align */
1042 VM_MAPTYPE_NORMAL, /* maptype */
1043 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1044 VM_PROT_READ | VM_PROT_WRITE, /* max */
1045 MAP_SHARED /* cow */);
1046 if (rv != KERN_SUCCESS) {
1047 vm_object_deallocate(obj->vm_obj);
1048 error = -vm_mmap_to_errno(rv);
1050 args->addr_ptr = (uint64_t)addr;
1053 drm_gem_object_unreference(obj);
1058 * i915_gem_fault - fault a page into the GTT
1059 * vma: VMA in question
1062 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1063 * from userspace. The fault handler takes care of binding the object to
1064 * the GTT (if needed), allocating and programming a fence register (again,
1065 * only if needed based on whether the old reg is still valid or the object
1066 * is tiled) and inserting a new PTE into the faulting process.
1068 * Note that the faulting process may involve evicting existing objects
1069 * from the GTT and/or fence registers to make room. So performance may
1070 * suffer if the GTT working set is large or there are few fence registers
1074 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1076 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1077 struct drm_device *dev = obj->base.dev;
1078 drm_i915_private_t *dev_priv = dev->dev_private;
1079 pgoff_t page_offset;
1082 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1084 /* We don't use vmf->pgoff since that has the fake offset */
1085 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1088 ret = i915_mutex_lock_interruptible(dev);
1092 trace_i915_gem_object_fault(obj, page_offset, true, write);
1094 /* Access to snoopable pages through the GTT is incoherent. */
1095 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1100 /* Now bind it into the GTT if needed */
1101 ret = i915_gem_object_pin(obj, 0, true, false);
1105 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1109 ret = i915_gem_object_get_fence(obj);
1113 obj->fault_mappable = true;
1115 pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1118 /* Finally, remap it using the new GTT offset */
1119 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1121 i915_gem_object_unpin(obj);
1123 mutex_unlock(&dev->struct_mutex);
1127 /* If this -EIO is due to a gpu hang, give the reset code a
1128 * chance to clean up the mess. Otherwise return the proper
1130 if (i915_terminally_wedged(&dev_priv->gpu_error))
1131 return VM_FAULT_SIGBUS;
1133 /* Give the error handler a chance to run and move the
1134 * objects off the GPU active list. Next time we service the
1135 * fault, we should be able to transition the page into the
1136 * GTT without touching the GPU (and so avoid further
1137 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1138 * with coherency, just lost writes.
1146 * EBUSY is ok: this just means that another thread
1147 * already did the job.
1149 return VM_FAULT_NOPAGE;
1151 return VM_FAULT_OOM;
1153 return VM_FAULT_SIGBUS;
1155 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1156 return VM_FAULT_SIGBUS;
1162 * i915_gem_release_mmap - remove physical page mappings
1163 * @obj: obj in question
1165 * Preserve the reservation of the mmapping with the DRM core code, but
1166 * relinquish ownership of the pages back to the system.
1168 * It is vital that we remove the page mapping if we have mapped a tiled
1169 * object through the GTT and then lose the fence register due to
1170 * resource pressure. Similarly if the object has been moved out of the
1171 * aperture, than pages mapped into userspace must be revoked. Removing the
1172 * mapping will then trigger a page fault on the next user access, allowing
1173 * fixup by i915_gem_fault().
1176 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1182 if (!obj->fault_mappable)
1185 devobj = cdev_pager_lookup(obj);
1186 if (devobj != NULL) {
1187 page_count = OFF_TO_IDX(obj->base.size);
1189 VM_OBJECT_LOCK(devobj);
1190 for (i = 0; i < page_count; i++) {
1191 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1194 cdev_pager_free_page(devobj, m);
1196 VM_OBJECT_UNLOCK(devobj);
1197 vm_object_deallocate(devobj);
1200 obj->fault_mappable = false;
1204 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1208 if (INTEL_INFO(dev)->gen >= 4 ||
1209 tiling_mode == I915_TILING_NONE)
1212 /* Previous chips need a power-of-two fence region when tiling */
1213 if (INTEL_INFO(dev)->gen == 3)
1214 gtt_size = 1024*1024;
1216 gtt_size = 512*1024;
1218 while (gtt_size < size)
1225 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1226 * @obj: object to check
1228 * Return the required GTT alignment for an object, taking into account
1229 * potential fence register mapping.
1232 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1233 int tiling_mode, bool fenced)
1237 * Minimum alignment is 4k (GTT page size), but might be greater
1238 * if a fence register is needed for the object.
1240 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1241 tiling_mode == I915_TILING_NONE)
1245 * Previous chips need to be aligned to the size of the smallest
1246 * fence register that can contain the object.
1248 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1252 i915_gem_mmap_gtt(struct drm_file *file,
1253 struct drm_device *dev,
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 struct drm_i915_gem_object *obj;
1261 ret = i915_mutex_lock_interruptible(dev);
1265 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1266 if (&obj->base == NULL) {
1271 if (obj->base.size > dev_priv->gtt.mappable_end) {
1276 if (obj->madv != I915_MADV_WILLNEED) {
1277 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1282 ret = drm_gem_create_mmap_offset(&obj->base);
1286 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1287 DRM_GEM_MAPPING_KEY;
1289 drm_gem_object_unreference(&obj->base);
1291 mutex_unlock(&dev->struct_mutex);
1296 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1298 * @data: GTT mapping ioctl data
1299 * @file: GEM object info
1301 * Simply returns the fake offset to userspace so it can mmap it.
1302 * The mmap call will end up in drm_gem_mmap(), which will set things
1303 * up so we can get faults in the handler above.
1305 * The fault handler will take care of binding the object into the GTT
1306 * (since it may have been evicted to make room for something), allocating
1307 * a fence register, and mapping the appropriate aperture address into
1311 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1312 struct drm_file *file)
1314 struct drm_i915_gem_mmap_gtt *args = data;
1316 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1319 /* Immediately discard the backing storage */
1321 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1325 vm_obj = obj->base.vm_obj;
1326 VM_OBJECT_LOCK(vm_obj);
1327 vm_object_page_remove(vm_obj, 0, 0, false);
1328 VM_OBJECT_UNLOCK(vm_obj);
1329 obj->madv = __I915_MADV_PURGED;
1333 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1335 return obj->madv == I915_MADV_DONTNEED;
1339 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1344 BUG_ON(obj->madv == __I915_MADV_PURGED);
1346 if (obj->tiling_mode != I915_TILING_NONE)
1347 i915_gem_object_save_bit_17_swizzle(obj);
1348 if (obj->madv == I915_MADV_DONTNEED)
1350 page_count = obj->base.size / PAGE_SIZE;
1351 VM_OBJECT_LOCK(obj->base.vm_obj);
1352 #if GEM_PARANOID_CHECK_GTT
1353 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
1355 for (i = 0; i < page_count; i++) {
1359 if (obj->madv == I915_MADV_WILLNEED)
1360 vm_page_reference(m);
1361 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
1362 vm_page_unwire(obj->pages[i], 1);
1363 vm_page_wakeup(obj->pages[i]);
1365 VM_OBJECT_UNLOCK(obj->base.vm_obj);
1367 drm_free(obj->pages, M_DRM);
1372 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1374 const struct drm_i915_gem_object_ops *ops = obj->ops;
1376 if (obj->pages == NULL)
1379 BUG_ON(obj->gtt_space);
1381 if (obj->pages_pin_count)
1384 /* ->put_pages might need to allocate memory for the bit17 swizzle
1385 * array, hence protect them from being reaped by removing them from gtt
1387 list_del(&obj->gtt_list);
1389 ops->put_pages(obj);
1392 if (i915_gem_object_is_purgeable(obj))
1393 i915_gem_object_truncate(obj);
1399 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1401 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1402 struct drm_device *dev;
1404 int page_count, i, j;
1405 struct vm_page *page;
1407 dev = obj->base.dev;
1408 KASSERT(obj->pages == NULL, ("Obj already has pages"));
1409 page_count = obj->base.size / PAGE_SIZE;
1410 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
1413 vm_obj = obj->base.vm_obj;
1414 VM_OBJECT_LOCK(vm_obj);
1416 for (i = 0; i < page_count; i++) {
1417 page = shmem_read_mapping_page(vm_obj, i);
1419 i915_gem_purge(dev_priv, page_count);
1423 obj->pages[i] = page;
1426 VM_OBJECT_UNLOCK(vm_obj);
1427 if (i915_gem_object_needs_bit17_swizzle(obj))
1428 i915_gem_object_do_bit_17_swizzle(obj);
1433 for (j = 0; j < i; j++) {
1434 page = obj->pages[j];
1435 vm_page_busy_wait(page, FALSE, "i915gem");
1436 vm_page_unwire(page, 0);
1437 vm_page_wakeup(page);
1439 VM_OBJECT_UNLOCK(vm_obj);
1440 drm_free(obj->pages, M_DRM);
1445 /* Ensure that the associated pages are gathered from the backing storage
1446 * and pinned into our object. i915_gem_object_get_pages() may be called
1447 * multiple times before they are released by a single call to
1448 * i915_gem_object_put_pages() - once the pages are no longer referenced
1449 * either as a result of memory pressure (reaping pages under the shrinker)
1450 * or as the object is itself released.
1453 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1455 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1456 const struct drm_i915_gem_object_ops *ops = obj->ops;
1462 if (obj->madv != I915_MADV_WILLNEED) {
1463 DRM_ERROR("Attempting to obtain a purgeable object\n");
1467 BUG_ON(obj->pages_pin_count);
1469 ret = ops->get_pages(obj);
1473 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1478 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1479 struct intel_ring_buffer *ring)
1481 struct drm_device *dev = obj->base.dev;
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483 u32 seqno = intel_ring_get_seqno(ring);
1485 BUG_ON(ring == NULL);
1488 /* Add a reference if we're newly entering the active list. */
1490 drm_gem_object_reference(&obj->base);
1494 /* Move from whatever list we were on to the tail of execution. */
1495 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1496 list_move_tail(&obj->ring_list, &ring->active_list);
1498 obj->last_read_seqno = seqno;
1500 if (obj->fenced_gpu_access) {
1501 obj->last_fenced_seqno = seqno;
1503 /* Bump MRU to take account of the delayed flush */
1504 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1505 struct drm_i915_fence_reg *reg;
1507 reg = &dev_priv->fence_regs[obj->fence_reg];
1508 list_move_tail(®->lru_list,
1509 &dev_priv->mm.fence_list);
1515 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1517 struct drm_device *dev = obj->base.dev;
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1520 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1521 BUG_ON(!obj->active);
1523 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1525 list_del_init(&obj->ring_list);
1528 obj->last_read_seqno = 0;
1529 obj->last_write_seqno = 0;
1530 obj->base.write_domain = 0;
1532 obj->last_fenced_seqno = 0;
1533 obj->fenced_gpu_access = false;
1536 drm_gem_object_unreference(&obj->base);
1538 WARN_ON(i915_verify_lists(dev));
1542 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 struct intel_ring_buffer *ring;
1548 /* Carefully retire all requests without writing to the rings */
1549 for_each_ring(ring, dev_priv, i) {
1550 ret = intel_ring_idle(ring);
1554 i915_gem_retire_requests(dev);
1556 /* Finally reset hw state */
1557 for_each_ring(ring, dev_priv, i) {
1558 intel_ring_init_seqno(ring, seqno);
1560 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1561 ring->sync_seqno[j] = 0;
1567 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1569 struct drm_i915_private *dev_priv = dev->dev_private;
1575 /* HWS page needs to be set less than what we
1576 * will inject to ring
1578 ret = i915_gem_init_seqno(dev, seqno - 1);
1582 /* Carefully set the last_seqno value so that wrap
1583 * detection still works
1585 dev_priv->next_seqno = seqno;
1586 dev_priv->last_seqno = seqno - 1;
1587 if (dev_priv->last_seqno == 0)
1588 dev_priv->last_seqno--;
1594 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1598 /* reserve 0 for non-seqno */
1599 if (dev_priv->next_seqno == 0) {
1600 int ret = i915_gem_init_seqno(dev, 0);
1604 dev_priv->next_seqno = 1;
1607 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
1612 i915_add_request(struct intel_ring_buffer *ring,
1613 struct drm_file *file,
1616 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1617 struct drm_i915_gem_request *request;
1618 u32 request_ring_position;
1623 * Emit any outstanding flushes - execbuf can fail to emit the flush
1624 * after having emitted the batchbuffer command. Hence we need to fix
1625 * things up similar to emitting the lazy request. The difference here
1626 * is that the flush _must_ happen before the next request, no matter
1629 ret = intel_ring_flush_all_caches(ring);
1633 request = kmalloc(sizeof(*request), M_DRM, M_WAITOK);
1634 if (request == NULL)
1638 /* Record the position of the start of the request so that
1639 * should we detect the updated seqno part-way through the
1640 * GPU processing the request, we never over-estimate the
1641 * position of the head.
1643 request_ring_position = intel_ring_get_tail(ring);
1645 ret = ring->add_request(ring);
1651 request->seqno = intel_ring_get_seqno(ring);
1652 request->ring = ring;
1653 request->tail = request_ring_position;
1654 request->emitted_jiffies = jiffies;
1655 was_empty = list_empty(&ring->request_list);
1656 list_add_tail(&request->list, &ring->request_list);
1657 request->file_priv = NULL;
1660 struct drm_i915_file_private *file_priv = file->driver_priv;
1662 spin_lock(&file_priv->mm.lock);
1663 request->file_priv = file_priv;
1664 list_add_tail(&request->client_list,
1665 &file_priv->mm.request_list);
1666 spin_unlock(&file_priv->mm.lock);
1669 ring->outstanding_lazy_request = 0;
1671 if (!dev_priv->mm.suspended) {
1672 if (i915_enable_hangcheck) {
1673 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
1674 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1677 queue_delayed_work(dev_priv->wq,
1678 &dev_priv->mm.retire_work,
1679 round_jiffies_up_relative(hz));
1680 intel_mark_busy(dev_priv->dev);
1685 *out_seqno = request->seqno;
1690 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1692 struct drm_i915_file_private *file_priv = request->file_priv;
1697 spin_lock(&file_priv->mm.lock);
1698 if (request->file_priv) {
1699 list_del(&request->client_list);
1700 request->file_priv = NULL;
1702 spin_unlock(&file_priv->mm.lock);
1705 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1706 struct intel_ring_buffer *ring)
1708 while (!list_empty(&ring->request_list)) {
1709 struct drm_i915_gem_request *request;
1711 request = list_first_entry(&ring->request_list,
1712 struct drm_i915_gem_request,
1715 list_del(&request->list);
1716 i915_gem_request_remove_from_client(request);
1717 drm_free(request, M_DRM);
1720 while (!list_empty(&ring->active_list)) {
1721 struct drm_i915_gem_object *obj;
1723 obj = list_first_entry(&ring->active_list,
1724 struct drm_i915_gem_object,
1727 i915_gem_object_move_to_inactive(obj);
1731 void i915_gem_restore_fences(struct drm_device *dev)
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1736 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1737 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1738 i915_gem_write_fence(dev, i, reg->obj);
1742 void i915_gem_reset(struct drm_device *dev)
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 struct drm_i915_gem_object *obj;
1746 struct intel_ring_buffer *ring;
1749 for_each_ring(ring, dev_priv, i)
1750 i915_gem_reset_ring_lists(dev_priv, ring);
1752 /* Move everything out of the GPU domains to ensure we do any
1753 * necessary invalidation upon reuse.
1755 list_for_each_entry(obj,
1756 &dev_priv->mm.inactive_list,
1759 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1762 i915_gem_restore_fences(dev);
1766 * This function clears the request list as sequence numbers are passed.
1769 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1773 if (list_empty(&ring->request_list))
1776 WARN_ON(i915_verify_lists(ring->dev));
1778 seqno = ring->get_seqno(ring, true);
1780 while (!list_empty(&ring->request_list)) {
1781 struct drm_i915_gem_request *request;
1783 request = list_first_entry(&ring->request_list,
1784 struct drm_i915_gem_request,
1787 if (!i915_seqno_passed(seqno, request->seqno))
1790 /* We know the GPU must have read the request to have
1791 * sent us the seqno + interrupt, so use the position
1792 * of tail of the request to update the last known position
1795 ring->last_retired_head = request->tail;
1797 list_del(&request->list);
1798 i915_gem_request_remove_from_client(request);
1802 /* Move any buffers on the active list that are no longer referenced
1803 * by the ringbuffer to the flushing/inactive lists as appropriate.
1805 while (!list_empty(&ring->active_list)) {
1806 struct drm_i915_gem_object *obj;
1808 obj = list_first_entry(&ring->active_list,
1809 struct drm_i915_gem_object,
1812 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1815 i915_gem_object_move_to_inactive(obj);
1818 if (unlikely(ring->trace_irq_seqno &&
1819 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1820 ring->irq_put(ring);
1821 ring->trace_irq_seqno = 0;
1827 i915_gem_retire_requests(struct drm_device *dev)
1829 drm_i915_private_t *dev_priv = dev->dev_private;
1830 struct intel_ring_buffer *ring;
1833 for_each_ring(ring, dev_priv, i)
1834 i915_gem_retire_requests_ring(ring);
1838 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1839 bool purgeable_only)
1841 struct drm_i915_gem_object *obj, *next;
1844 list_for_each_entry_safe(obj, next,
1845 &dev_priv->mm.unbound_list,
1848 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1849 i915_gem_object_put_pages(obj) == 0) {
1850 count += obj->base.size >> PAGE_SHIFT;
1851 if (count >= target)
1857 list_for_each_entry_safe(obj, next,
1858 &dev_priv->mm.inactive_list,
1861 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1862 i915_gem_object_unbind(obj) == 0 &&
1863 i915_gem_object_put_pages(obj) == 0) {
1864 count += obj->base.size >> PAGE_SHIFT;
1865 if (count >= target)
1875 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1877 return __i915_gem_shrink(dev_priv, target, true);
1881 i915_gem_retire_work_handler(struct work_struct *work)
1883 drm_i915_private_t *dev_priv;
1884 struct drm_device *dev;
1885 struct intel_ring_buffer *ring;
1889 dev_priv = container_of(work, drm_i915_private_t,
1890 mm.retire_work.work);
1891 dev = dev_priv->dev;
1893 /* Come back later if the device is busy... */
1894 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT)) {
1895 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1896 round_jiffies_up_relative(hz));
1900 i915_gem_retire_requests(dev);
1902 /* Send a periodic flush down the ring so we don't hold onto GEM
1903 * objects indefinitely.
1906 for_each_ring(ring, dev_priv, i) {
1907 if (ring->gpu_caches_dirty)
1908 i915_add_request(ring, NULL, NULL);
1910 idle &= list_empty(&ring->request_list);
1913 if (!dev_priv->mm.suspended && !idle)
1914 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1915 round_jiffies_up_relative(hz));
1917 intel_mark_idle(dev);
1919 mutex_unlock(&dev->struct_mutex);
1922 * Ensures that an object will eventually get non-busy by flushing any required
1923 * write domains, emitting any outstanding lazy request and retiring and
1924 * completed requests.
1927 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
1932 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
1936 i915_gem_retire_requests_ring(obj->ring);
1943 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
1944 * @DRM_IOCTL_ARGS: standard ioctl arguments
1946 * Returns 0 if successful, else an error is returned with the remaining time in
1947 * the timeout parameter.
1948 * -ETIME: object is still busy after timeout
1949 * -ERESTARTSYS: signal interrupted the wait
1950 * -ENONENT: object doesn't exist
1951 * Also possible, but rare:
1952 * -EAGAIN: GPU wedged
1954 * -ENODEV: Internal IRQ fail
1955 * -E?: The add request failed
1957 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
1958 * non-zero timeout parameter the wait ioctl will wait for the given number of
1959 * nanoseconds on an object becoming unbusy. Since the wait itself does so
1960 * without holding struct_mutex the object may become re-busied before this
1961 * function completes. A similar but shorter * race condition exists in the busy
1965 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1967 drm_i915_private_t *dev_priv = dev->dev_private;
1968 struct drm_i915_gem_wait *args = data;
1969 struct drm_i915_gem_object *obj;
1970 struct intel_ring_buffer *ring = NULL;
1971 struct timespec timeout_stack, *timeout = NULL;
1972 unsigned reset_counter;
1976 if (args->timeout_ns >= 0) {
1977 timeout_stack = ns_to_timespec(args->timeout_ns);
1978 timeout = &timeout_stack;
1981 ret = i915_mutex_lock_interruptible(dev);
1985 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
1986 if (&obj->base == NULL) {
1987 mutex_unlock(&dev->struct_mutex);
1991 /* Need to make sure the object gets inactive eventually. */
1992 ret = i915_gem_object_flush_active(obj);
1997 seqno = obj->last_read_seqno;
2004 /* Do this after OLR check to make sure we make forward progress polling
2005 * on this IOCTL with a 0 timeout (like busy ioctl)
2007 if (!args->timeout_ns) {
2012 drm_gem_object_unreference(&obj->base);
2013 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2014 mutex_unlock(&dev->struct_mutex);
2016 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2018 args->timeout_ns = timespec_to_ns(timeout);
2022 drm_gem_object_unreference(&obj->base);
2023 mutex_unlock(&dev->struct_mutex);
2028 * i915_gem_object_sync - sync an object to a ring.
2030 * @obj: object which may be in use on another ring.
2031 * @to: ring we wish to use the object on. May be NULL.
2033 * This code is meant to abstract object synchronization with the GPU.
2034 * Calling with NULL implies synchronizing the object with the CPU
2035 * rather than a particular GPU ring.
2037 * Returns 0 if successful, else propagates up the lower layer error.
2040 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2041 struct intel_ring_buffer *to)
2043 struct intel_ring_buffer *from = obj->ring;
2047 if (from == NULL || to == from)
2050 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2051 return i915_gem_object_wait_rendering(obj, false);
2053 idx = intel_ring_sync_index(from, to);
2055 seqno = obj->last_read_seqno;
2056 if (seqno <= from->sync_seqno[idx])
2059 ret = i915_gem_check_olr(obj->ring, seqno);
2063 ret = to->sync_to(to, from, seqno);
2065 /* We use last_read_seqno because sync_to()
2066 * might have just caused seqno wrap under
2069 from->sync_seqno[idx] = obj->last_read_seqno;
2074 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2076 u32 old_write_domain, old_read_domains;
2078 /* Force a pagefault for domain tracking on next user access */
2079 i915_gem_release_mmap(obj);
2081 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2084 /* Wait for any direct GTT access to complete */
2087 old_read_domains = obj->base.read_domains;
2088 old_write_domain = obj->base.write_domain;
2090 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2091 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2096 * Unbinds an object from the GTT aperture.
2099 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2101 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2104 if (obj->gtt_space == NULL)
2110 BUG_ON(obj->pages == NULL);
2112 ret = i915_gem_object_finish_gpu(obj);
2115 /* Continue on if we fail due to EIO, the GPU is hung so we
2116 * should be safe and we need to cleanup or else we might
2117 * cause memory corruption through use-after-free.
2120 i915_gem_object_finish_gtt(obj);
2122 /* Move the object to the CPU domain to ensure that
2123 * any possible CPU writes while it's not in the GTT
2124 * are flushed when we go to remap it.
2127 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2128 if (ret == -ERESTARTSYS)
2131 /* In the event of a disaster, abandon all caches and
2132 * hope for the best.
2134 i915_gem_clflush_object(obj);
2135 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2138 /* release the fence reg _after_ flushing */
2139 ret = i915_gem_object_put_fence(obj);
2143 if (obj->has_global_gtt_mapping)
2144 i915_gem_gtt_unbind_object(obj);
2145 if (obj->has_aliasing_ppgtt_mapping) {
2146 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2147 obj->has_aliasing_ppgtt_mapping = 0;
2149 i915_gem_gtt_finish_object(obj);
2151 i915_gem_object_put_pages_gtt(obj);
2153 list_del_init(&obj->gtt_list);
2154 list_del_init(&obj->mm_list);
2155 /* Avoid an unnecessary call to unbind on rebind. */
2156 obj->map_and_fenceable = true;
2158 drm_mm_put_block(obj->gtt_space);
2159 obj->gtt_space = NULL;
2160 obj->gtt_offset = 0;
2162 if (i915_gem_object_is_purgeable(obj))
2163 i915_gem_object_truncate(obj);
2168 int i915_gpu_idle(struct drm_device *dev)
2170 drm_i915_private_t *dev_priv = dev->dev_private;
2171 struct intel_ring_buffer *ring;
2174 /* Flush everything onto the inactive list. */
2175 for_each_ring(ring, dev_priv, i) {
2176 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2180 ret = intel_ring_idle(ring);
2188 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2189 struct drm_i915_gem_object *obj)
2191 drm_i915_private_t *dev_priv = dev->dev_private;
2193 int fence_pitch_shift;
2196 if (INTEL_INFO(dev)->gen >= 6) {
2197 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2198 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2200 fence_reg = FENCE_REG_965_0;
2201 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2205 u32 size = obj->gtt_space->size;
2207 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2209 val |= obj->gtt_offset & 0xfffff000;
2210 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2211 if (obj->tiling_mode == I915_TILING_Y)
2212 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2213 val |= I965_FENCE_REG_VALID;
2217 fence_reg += reg * 8;
2218 I915_WRITE64(fence_reg, val);
2219 POSTING_READ(fence_reg);
2222 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2223 struct drm_i915_gem_object *obj)
2225 drm_i915_private_t *dev_priv = dev->dev_private;
2229 u32 size = obj->gtt_space->size;
2233 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2234 (size & -size) != size ||
2235 (obj->gtt_offset & (size - 1)),
2236 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2237 obj->gtt_offset, obj->map_and_fenceable, size);
2239 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2244 /* Note: pitch better be a power of two tile widths */
2245 pitch_val = obj->stride / tile_width;
2246 pitch_val = ffs(pitch_val) - 1;
2248 val = obj->gtt_offset;
2249 if (obj->tiling_mode == I915_TILING_Y)
2250 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2251 val |= I915_FENCE_SIZE_BITS(size);
2252 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2253 val |= I830_FENCE_REG_VALID;
2258 reg = FENCE_REG_830_0 + reg * 4;
2260 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2262 I915_WRITE(reg, val);
2266 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2267 struct drm_i915_gem_object *obj)
2269 drm_i915_private_t *dev_priv = dev->dev_private;
2273 u32 size = obj->gtt_space->size;
2276 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2277 (size & -size) != size ||
2278 (obj->gtt_offset & (size - 1)),
2279 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2280 obj->gtt_offset, size);
2282 pitch_val = obj->stride / 128;
2283 pitch_val = ffs(pitch_val) - 1;
2285 val = obj->gtt_offset;
2286 if (obj->tiling_mode == I915_TILING_Y)
2287 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2288 val |= I830_FENCE_SIZE_BITS(size);
2289 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2290 val |= I830_FENCE_REG_VALID;
2294 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2295 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2298 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2300 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2303 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2304 struct drm_i915_gem_object *obj)
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2308 /* Ensure that all CPU reads are completed before installing a fence
2309 * and all writes before removing the fence.
2311 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2314 switch (INTEL_INFO(dev)->gen) {
2318 case 4: i965_write_fence_reg(dev, reg, obj); break;
2319 case 3: i915_write_fence_reg(dev, reg, obj); break;
2320 case 2: i830_write_fence_reg(dev, reg, obj); break;
2324 /* And similarly be paranoid that no direct access to this region
2325 * is reordered to before the fence is installed.
2327 if (i915_gem_object_needs_mb(obj))
2331 static inline int fence_number(struct drm_i915_private *dev_priv,
2332 struct drm_i915_fence_reg *fence)
2334 return fence - dev_priv->fence_regs;
2337 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2338 struct drm_i915_fence_reg *fence,
2341 struct drm_device *dev = obj->base.dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 int fence_reg = fence_number(dev_priv, fence);
2345 /* In order to fully serialize access to the fenced region and
2346 * the update to the fence register we need to take extreme
2347 * measures on SNB+. In theory, the write to the fence register
2348 * flushes all memory transactions before, and coupled with the
2349 * mb() placed around the register write we serialise all memory
2350 * operations with respect to the changes in the tiler. Yet, on
2351 * SNB+ we need to take a step further and emit an explicit wbinvd()
2352 * on each processor in order to manually flush all memory
2353 * transactions before updating the fence register.
2355 if (HAS_LLC(obj->base.dev))
2356 cpu_wbinvd_on_all_cpus();
2357 i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
2360 obj->fence_reg = fence_reg;
2362 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2364 obj->fence_reg = I915_FENCE_REG_NONE;
2366 list_del_init(&fence->lru_list);
2371 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2373 if (obj->last_fenced_seqno) {
2374 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2378 obj->last_fenced_seqno = 0;
2381 obj->fenced_gpu_access = false;
2386 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2388 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2389 struct drm_i915_fence_reg *fence;
2392 ret = i915_gem_object_wait_fence(obj);
2396 if (obj->fence_reg == I915_FENCE_REG_NONE)
2399 fence = &dev_priv->fence_regs[obj->fence_reg];
2401 i915_gem_object_fence_lost(obj);
2402 i915_gem_object_update_fence(obj, fence, false);
2407 static struct drm_i915_fence_reg *
2408 i915_find_fence_reg(struct drm_device *dev)
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct drm_i915_fence_reg *reg, *avail;
2414 /* First try to find a free reg */
2416 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2417 reg = &dev_priv->fence_regs[i];
2421 if (!reg->pin_count)
2428 /* None available, try to steal one or wait for a user to finish */
2429 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2440 * i915_gem_object_get_fence - set up fencing for an object
2441 * @obj: object to map through a fence reg
2443 * When mapping objects through the GTT, userspace wants to be able to write
2444 * to them without having to worry about swizzling if the object is tiled.
2445 * This function walks the fence regs looking for a free one for @obj,
2446 * stealing one if it can't find any.
2448 * It then sets up the reg based on the object's properties: address, pitch
2449 * and tiling format.
2451 * For an untiled surface, this removes any existing fence.
2454 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2456 struct drm_device *dev = obj->base.dev;
2457 struct drm_i915_private *dev_priv = dev->dev_private;
2458 bool enable = obj->tiling_mode != I915_TILING_NONE;
2459 struct drm_i915_fence_reg *reg;
2462 /* Have we updated the tiling parameters upon the object and so
2463 * will need to serialise the write to the associated fence register?
2465 if (obj->fence_dirty) {
2466 ret = i915_gem_object_wait_fence(obj);
2471 /* Just update our place in the LRU if our fence is getting reused. */
2472 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2473 reg = &dev_priv->fence_regs[obj->fence_reg];
2474 if (!obj->fence_dirty) {
2475 list_move_tail(®->lru_list,
2476 &dev_priv->mm.fence_list);
2479 } else if (enable) {
2480 reg = i915_find_fence_reg(dev);
2485 struct drm_i915_gem_object *old = reg->obj;
2487 ret = i915_gem_object_wait_fence(old);
2491 i915_gem_object_fence_lost(old);
2496 i915_gem_object_update_fence(obj, reg, enable);
2497 obj->fence_dirty = false;
2502 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2503 struct drm_mm_node *gtt_space,
2504 unsigned long cache_level)
2506 struct drm_mm_node *other;
2508 /* On non-LLC machines we have to be careful when putting differing
2509 * types of snoopable memory together to avoid the prefetcher
2510 * crossing memory domains and dying.
2515 if (gtt_space == NULL)
2518 if (list_empty(>t_space->node_list))
2521 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2522 if (other->allocated && !other->hole_follows && other->color != cache_level)
2525 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2526 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2532 static void i915_gem_verify_gtt(struct drm_device *dev)
2535 struct drm_i915_private *dev_priv = dev->dev_private;
2536 struct drm_i915_gem_object *obj;
2539 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2540 if (obj->gtt_space == NULL) {
2541 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2546 if (obj->cache_level != obj->gtt_space->color) {
2547 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2548 obj->gtt_space->start,
2549 obj->gtt_space->start + obj->gtt_space->size,
2551 obj->gtt_space->color);
2556 if (!i915_gem_valid_gtt_space(dev,
2558 obj->cache_level)) {
2559 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2560 obj->gtt_space->start,
2561 obj->gtt_space->start + obj->gtt_space->size,
2573 * Finds free space in the GTT aperture and binds the object there.
2576 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2578 bool map_and_fenceable,
2581 struct drm_device *dev = obj->base.dev;
2582 drm_i915_private_t *dev_priv = dev->dev_private;
2583 struct drm_mm_node *free_space;
2584 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
2585 bool mappable, fenceable;
2588 fence_size = i915_gem_get_gtt_size(dev,
2591 fence_alignment = i915_gem_get_gtt_alignment(dev,
2593 obj->tiling_mode, true);
2594 unfenced_alignment =
2595 i915_gem_get_gtt_alignment(dev,
2597 obj->tiling_mode, false);
2600 alignment = map_and_fenceable ? fence_alignment :
2602 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2603 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2607 size = map_and_fenceable ? fence_size : obj->base.size;
2609 /* If the object is bigger than the entire aperture, reject it early
2610 * before evicting everything in a vain attempt to find space.
2612 if (obj->base.size >
2613 (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) {
2614 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2619 if (map_and_fenceable)
2621 drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2622 size, alignment, obj->cache_level,
2623 0, dev_priv->gtt.mappable_end,
2626 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2627 size, alignment, obj->cache_level,
2629 if (free_space != NULL) {
2630 if (map_and_fenceable)
2632 drm_mm_get_block_range_generic(free_space,
2633 size, alignment, obj->cache_level,
2634 0, dev_priv->gtt.mappable_end,
2638 drm_mm_get_block_generic(free_space,
2639 size, alignment, obj->cache_level,
2642 if (obj->gtt_space == NULL) {
2643 ret = i915_gem_evict_something(dev, size, alignment,
2654 * NOTE: i915_gem_object_get_pages_gtt() cannot
2655 * return ENOMEM, since we used VM_ALLOC_RETRY.
2657 ret = i915_gem_object_get_pages_gtt(obj);
2659 drm_mm_put_block(obj->gtt_space);
2660 obj->gtt_space = NULL;
2664 i915_gem_gtt_bind_object(obj, obj->cache_level);
2666 i915_gem_object_put_pages_gtt(obj);
2667 drm_mm_put_block(obj->gtt_space);
2668 obj->gtt_space = NULL;
2669 if (i915_gem_evict_everything(dev))
2674 list_add_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2675 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2677 obj->gtt_offset = obj->gtt_space->start;
2680 obj->gtt_space->size == fence_size &&
2681 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2684 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
2686 obj->map_and_fenceable = mappable && fenceable;
2688 i915_gem_verify_gtt(dev);
2693 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2696 /* If we don't have a page list set up, then we're not pinned
2697 * to GPU, and we can ignore the cache flush because it'll happen
2698 * again at bind time.
2700 if (obj->pages == NULL)
2704 * Stolen memory is always coherent with the GPU as it is explicitly
2705 * marked as wc by the system, or the system is cache-coherent.
2710 /* If the GPU is snooping the contents of the CPU cache,
2711 * we do not need to manually clear the CPU cache lines. However,
2712 * the caches are only snooped when the render cache is
2713 * flushed/invalidated. As we always have to emit invalidations
2714 * and flushes when moving into and out of the RENDER domain, correct
2715 * snooping behaviour occurs naturally as the result of our domain
2718 if (obj->cache_level != I915_CACHE_NONE)
2721 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2724 /** Flushes the GTT write domain for the object if it's dirty. */
2726 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2728 uint32_t old_write_domain;
2730 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2733 /* No actual flushing is required for the GTT write domain. Writes
2734 * to it immediately go to main memory as far as we know, so there's
2735 * no chipset flush. It also doesn't land in render cache.
2737 * However, we do have to enforce the order so that all writes through
2738 * the GTT land before any writes to the device, such as updates to
2743 old_write_domain = obj->base.write_domain;
2744 obj->base.write_domain = 0;
2747 /** Flushes the CPU write domain for the object if it's dirty. */
2749 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2751 uint32_t old_write_domain;
2753 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2756 i915_gem_clflush_object(obj);
2757 i915_gem_chipset_flush(obj->base.dev);
2758 old_write_domain = obj->base.write_domain;
2759 obj->base.write_domain = 0;
2763 * Moves a single object to the GTT read, and possibly write domain.
2765 * This function returns when the move is complete, including waiting on
2769 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2771 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2772 uint32_t old_write_domain, old_read_domains;
2775 /* Not valid to be called on unbound objects. */
2776 if (obj->gtt_space == NULL)
2779 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2782 ret = i915_gem_object_wait_rendering(obj, !write);
2786 i915_gem_object_flush_cpu_write_domain(obj);
2788 /* Serialise direct access to this object with the barriers for
2789 * coherent writes from the GPU, by effectively invalidating the
2790 * GTT domain upon first access.
2792 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2795 old_write_domain = obj->base.write_domain;
2796 old_read_domains = obj->base.read_domains;
2798 /* It should now be out of any other write domains, and we can update
2799 * the domain values for our changes.
2801 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2802 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2804 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2805 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2809 /* And bump the LRU for this access */
2810 if (i915_gem_object_is_inactive(obj))
2811 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2816 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2817 enum i915_cache_level cache_level)
2819 struct drm_device *dev = obj->base.dev;
2820 drm_i915_private_t *dev_priv = dev->dev_private;
2823 if (obj->cache_level == cache_level)
2826 if (obj->pin_count) {
2827 DRM_DEBUG("can not change the cache level of pinned objects\n");
2831 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
2832 ret = i915_gem_object_unbind(obj);
2837 if (obj->gtt_space) {
2838 ret = i915_gem_object_finish_gpu(obj);
2842 i915_gem_object_finish_gtt(obj);
2844 /* Before SandyBridge, you could not use tiling or fence
2845 * registers with snooped memory, so relinquish any fences
2846 * currently pointing to our region in the aperture.
2848 if (INTEL_INFO(dev)->gen < 6) {
2849 ret = i915_gem_object_put_fence(obj);
2854 if (obj->has_global_gtt_mapping)
2855 i915_gem_gtt_bind_object(obj, cache_level);
2856 if (obj->has_aliasing_ppgtt_mapping)
2857 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2860 obj->gtt_space->color = cache_level;
2863 if (cache_level == I915_CACHE_NONE) {
2864 u32 old_read_domains, old_write_domain;
2866 /* If we're coming from LLC cached, then we haven't
2867 * actually been tracking whether the data is in the
2868 * CPU cache or not, since we only allow one bit set
2869 * in obj->write_domain and have been skipping the clflushes.
2870 * Just set it to the CPU cache for now.
2872 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2873 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2875 old_read_domains = obj->base.read_domains;
2876 old_write_domain = obj->base.write_domain;
2878 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2879 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2883 obj->cache_level = cache_level;
2884 i915_gem_verify_gtt(dev);
2888 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2889 struct drm_file *file)
2891 struct drm_i915_gem_caching *args = data;
2892 struct drm_i915_gem_object *obj;
2895 ret = i915_mutex_lock_interruptible(dev);
2899 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2900 if (&obj->base == NULL) {
2905 args->caching = obj->cache_level != I915_CACHE_NONE;
2907 drm_gem_object_unreference(&obj->base);
2909 mutex_unlock(&dev->struct_mutex);
2913 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2914 struct drm_file *file)
2916 struct drm_i915_gem_caching *args = data;
2917 struct drm_i915_gem_object *obj;
2918 enum i915_cache_level level;
2921 switch (args->caching) {
2922 case I915_CACHING_NONE:
2923 level = I915_CACHE_NONE;
2925 case I915_CACHING_CACHED:
2926 level = I915_CACHE_LLC;
2932 ret = i915_mutex_lock_interruptible(dev);
2936 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2937 if (&obj->base == NULL) {
2942 ret = i915_gem_object_set_cache_level(obj, level);
2944 drm_gem_object_unreference(&obj->base);
2946 mutex_unlock(&dev->struct_mutex);
2951 * Prepare buffer for display plane (scanout, cursors, etc).
2952 * Can be called from an uninterruptible phase (modesetting) and allows
2953 * any flushes to be pipelined (for pageflips).
2956 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2958 struct intel_ring_buffer *pipelined)
2960 u32 old_read_domains, old_write_domain;
2963 if (pipelined != obj->ring) {
2964 ret = i915_gem_object_sync(obj, pipelined);
2969 /* The display engine is not coherent with the LLC cache on gen6. As
2970 * a result, we make sure that the pinning that is about to occur is
2971 * done with uncached PTEs. This is lowest common denominator for all
2974 * However for gen6+, we could do better by using the GFDT bit instead
2975 * of uncaching, which would allow us to flush all the LLC-cached data
2976 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2978 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2982 /* As the user may map the buffer once pinned in the display plane
2983 * (e.g. libkms for the bootup splash), we have to ensure that we
2984 * always use map_and_fenceable for all scanout buffers.
2986 ret = i915_gem_object_pin(obj, alignment, true, false);
2990 i915_gem_object_flush_cpu_write_domain(obj);
2992 old_write_domain = obj->base.write_domain;
2993 old_read_domains = obj->base.read_domains;
2995 /* It should now be out of any other write domains, and we can update
2996 * the domain values for our changes.
2998 obj->base.write_domain = 0;
2999 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3005 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3009 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3012 ret = i915_gem_object_wait_rendering(obj, false);
3016 /* Ensure that we invalidate the GPU's caches and TLBs. */
3017 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3022 * Moves a single object to the CPU read, and possibly write domain.
3024 * This function returns when the move is complete, including waiting on
3028 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3030 uint32_t old_write_domain, old_read_domains;
3033 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3036 ret = i915_gem_object_wait_rendering(obj, !write);
3040 i915_gem_object_flush_gtt_write_domain(obj);
3042 old_write_domain = obj->base.write_domain;
3043 old_read_domains = obj->base.read_domains;
3045 /* Flush the CPU cache if it's still invalid. */
3046 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3047 i915_gem_clflush_object(obj);
3049 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3052 /* It should now be out of any other write domains, and we can update
3053 * the domain values for our changes.
3055 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3057 /* If we're writing through the CPU, then the GPU read domains will
3058 * need to be invalidated at next use.
3061 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3062 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3068 /* Throttle our rendering by waiting until the ring has completed our requests
3069 * emitted over 20 msec ago.
3071 * Note that if we were to use the current jiffies each time around the loop,
3072 * we wouldn't escape the function with any frames outstanding if the time to
3073 * render a frame was over 20ms.
3075 * This should get us reasonable parallelism between CPU and GPU but also
3076 * relatively low latency when blocking on a particular request to finish.
3079 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 struct drm_i915_file_private *file_priv = file->driver_priv;
3083 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3084 struct drm_i915_gem_request *request;
3085 struct intel_ring_buffer *ring = NULL;
3086 unsigned reset_counter;
3090 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3094 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3098 spin_lock(&file_priv->mm.lock);
3099 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3100 if (time_after_eq(request->emitted_jiffies, recent_enough))
3103 ring = request->ring;
3104 seqno = request->seqno;
3106 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3107 spin_unlock(&file_priv->mm.lock);
3112 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3114 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3120 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3122 bool map_and_fenceable,
3127 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3130 if (obj->gtt_space != NULL) {
3131 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3132 (map_and_fenceable && !obj->map_and_fenceable)) {
3133 WARN(obj->pin_count,
3134 "bo is already pinned with incorrect alignment:"
3135 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3136 " obj->map_and_fenceable=%d\n",
3137 obj->gtt_offset, alignment,
3139 obj->map_and_fenceable);
3140 ret = i915_gem_object_unbind(obj);
3146 if (obj->gtt_space == NULL) {
3147 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3149 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3155 if (!dev_priv->mm.aliasing_ppgtt)
3156 i915_gem_gtt_bind_object(obj, obj->cache_level);
3159 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3160 i915_gem_gtt_bind_object(obj, obj->cache_level);
3163 obj->pin_mappable |= map_and_fenceable;
3169 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3171 BUG_ON(obj->pin_count == 0);
3172 BUG_ON(obj->gtt_space == NULL);
3174 if (--obj->pin_count == 0)
3175 obj->pin_mappable = false;
3179 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3180 struct drm_file *file)
3182 struct drm_i915_gem_pin *args = data;
3183 struct drm_i915_gem_object *obj;
3186 ret = i915_mutex_lock_interruptible(dev);
3190 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3191 if (&obj->base == NULL) {
3196 if (obj->madv != I915_MADV_WILLNEED) {
3197 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3202 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3203 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3209 if (obj->user_pin_count == 0) {
3210 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3215 obj->user_pin_count++;
3216 obj->pin_filp = file;
3218 /* XXX - flush the CPU caches for pinned objects
3219 * as the X server doesn't manage domains yet
3221 i915_gem_object_flush_cpu_write_domain(obj);
3222 args->offset = obj->gtt_offset;
3224 drm_gem_object_unreference(&obj->base);
3226 mutex_unlock(&dev->struct_mutex);
3231 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3232 struct drm_file *file)
3234 struct drm_i915_gem_pin *args = data;
3235 struct drm_i915_gem_object *obj;
3238 ret = i915_mutex_lock_interruptible(dev);
3242 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3243 if (&obj->base == NULL) {
3248 if (obj->pin_filp != file) {
3249 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3254 obj->user_pin_count--;
3255 if (obj->user_pin_count == 0) {
3256 obj->pin_filp = NULL;
3257 i915_gem_object_unpin(obj);
3261 drm_gem_object_unreference(&obj->base);
3263 mutex_unlock(&dev->struct_mutex);
3268 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3269 struct drm_file *file)
3271 struct drm_i915_gem_busy *args = data;
3272 struct drm_i915_gem_object *obj;
3275 ret = i915_mutex_lock_interruptible(dev);
3279 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3280 if (&obj->base == NULL) {
3285 /* Count all active objects as busy, even if they are currently not used
3286 * by the gpu. Users of this interface expect objects to eventually
3287 * become non-busy without any further actions, therefore emit any
3288 * necessary flushes here.
3290 ret = i915_gem_object_flush_active(obj);
3292 args->busy = obj->active;
3294 args->busy |= intel_ring_flag(obj->ring) << 16;
3297 drm_gem_object_unreference(&obj->base);
3299 mutex_unlock(&dev->struct_mutex);
3304 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3305 struct drm_file *file_priv)
3307 return i915_gem_ring_throttle(dev, file_priv);
3311 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3312 struct drm_file *file_priv)
3314 struct drm_i915_gem_madvise *args = data;
3315 struct drm_i915_gem_object *obj;
3318 switch (args->madv) {
3319 case I915_MADV_DONTNEED:
3320 case I915_MADV_WILLNEED:
3326 ret = i915_mutex_lock_interruptible(dev);
3330 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3331 if (&obj->base == NULL) {
3336 if (obj->pin_count) {
3341 if (obj->madv != __I915_MADV_PURGED)
3342 obj->madv = args->madv;
3344 /* if the object is no longer attached, discard its backing storage */
3345 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3346 i915_gem_object_truncate(obj);
3348 args->retained = obj->madv != __I915_MADV_PURGED;
3351 drm_gem_object_unreference(&obj->base);
3353 mutex_unlock(&dev->struct_mutex);
3357 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3358 const struct drm_i915_gem_object_ops *ops)
3360 INIT_LIST_HEAD(&obj->mm_list);
3361 INIT_LIST_HEAD(&obj->gtt_list);
3362 INIT_LIST_HEAD(&obj->ring_list);
3363 INIT_LIST_HEAD(&obj->exec_list);
3367 obj->fence_reg = I915_FENCE_REG_NONE;
3368 obj->madv = I915_MADV_WILLNEED;
3369 /* Avoid an unnecessary call to unbind on the first bind. */
3370 obj->map_and_fenceable = true;
3372 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3375 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3376 .get_pages = i915_gem_object_get_pages_gtt,
3377 .put_pages = i915_gem_object_put_pages_gtt,
3380 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3383 struct drm_i915_gem_object *obj;
3385 struct address_space *mapping;
3389 obj = kmalloc(sizeof(*obj), M_DRM, M_WAITOK | M_ZERO);
3393 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3399 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3400 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3401 /* 965gm cannot relocate objects above 4GiB. */
3402 mask &= ~__GFP_HIGHMEM;
3403 mask |= __GFP_DMA32;
3406 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3407 mapping_set_gfp_mask(mapping, mask);
3410 i915_gem_object_init(obj, &i915_gem_object_ops);
3412 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3413 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3416 /* On some devices, we can have the GPU use the LLC (the CPU
3417 * cache) for about a 10% performance improvement
3418 * compared to uncached. Graphics requests other than
3419 * display scanout are coherent with the CPU in
3420 * accessing this cache. This means in this mode we
3421 * don't need to clflush on the CPU side, and on the
3422 * GPU side we only need to flush internal caches to
3423 * get data visible to the CPU.
3425 * However, we maintain the display planes as UC, and so
3426 * need to rebind when first used as such.
3428 obj->cache_level = I915_CACHE_LLC;
3430 obj->cache_level = I915_CACHE_NONE;
3435 int i915_gem_init_object(struct drm_gem_object *obj)
3442 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3444 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3445 struct drm_device *dev = obj->base.dev;
3446 drm_i915_private_t *dev_priv = dev->dev_private;
3449 i915_gem_detach_phys_object(dev, obj);
3452 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3453 bool was_interruptible;
3455 was_interruptible = dev_priv->mm.interruptible;
3456 dev_priv->mm.interruptible = false;
3458 WARN_ON(i915_gem_object_unbind(obj));
3460 dev_priv->mm.interruptible = was_interruptible;
3463 drm_gem_free_mmap_offset(&obj->base);
3465 drm_gem_object_release(&obj->base);
3466 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3468 drm_free(obj->bit_17, M_DRM);
3469 drm_free(obj, M_DRM);
3473 i915_gem_idle(struct drm_device *dev)
3475 drm_i915_private_t *dev_priv = dev->dev_private;
3478 mutex_lock(&dev->struct_mutex);
3480 if (dev_priv->mm.suspended) {
3481 mutex_unlock(&dev->struct_mutex);
3485 ret = i915_gpu_idle(dev);
3487 mutex_unlock(&dev->struct_mutex);
3490 i915_gem_retire_requests(dev);
3492 /* Under UMS, be paranoid and evict. */
3493 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3494 i915_gem_evict_everything(dev);
3496 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3497 * We need to replace this with a semaphore, or something.
3498 * And not confound mm.suspended!
3500 dev_priv->mm.suspended = 1;
3501 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
3503 i915_kernel_lost_context(dev);
3504 i915_gem_cleanup_ringbuffer(dev);
3506 mutex_unlock(&dev->struct_mutex);
3508 /* Cancel the retire work handler, which should be idle now. */
3509 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3514 void i915_gem_l3_remap(struct drm_device *dev)
3516 drm_i915_private_t *dev_priv = dev->dev_private;
3520 if (!HAS_L3_GPU_CACHE(dev))
3523 if (!dev_priv->l3_parity.remap_info)
3526 misccpctl = I915_READ(GEN7_MISCCPCTL);
3527 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3528 POSTING_READ(GEN7_MISCCPCTL);
3530 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3531 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3532 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3533 DRM_DEBUG("0x%x was already programmed to %x\n",
3534 GEN7_L3LOG_BASE + i, remap);
3535 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3536 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3537 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3540 /* Make sure all the writes land before disabling dop clock gating */
3541 POSTING_READ(GEN7_L3LOG_BASE);
3543 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3546 void i915_gem_init_swizzling(struct drm_device *dev)
3548 drm_i915_private_t *dev_priv = dev->dev_private;
3550 if (INTEL_INFO(dev)->gen < 5 ||
3551 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3554 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3555 DISP_TILE_SURFACE_SWIZZLING);
3560 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3562 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3563 else if (IS_GEN7(dev))
3564 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3570 intel_enable_blt(struct drm_device *dev)
3577 /* The blitter was dysfunctional on early prototypes */
3578 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
3579 if (IS_GEN6(dev) && revision < 8) {
3580 DRM_INFO("BLT not supported on this pre-production hardware;"
3581 " graphics performance will be degraded.\n");
3588 static int i915_gem_init_rings(struct drm_device *dev)
3590 struct drm_i915_private *dev_priv = dev->dev_private;
3593 ret = intel_init_render_ring_buffer(dev);
3598 ret = intel_init_bsd_ring_buffer(dev);
3600 goto cleanup_render_ring;
3603 if (intel_enable_blt(dev)) {
3604 ret = intel_init_blt_ring_buffer(dev);
3606 goto cleanup_bsd_ring;
3609 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
3611 goto cleanup_blt_ring;
3616 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
3618 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3619 cleanup_render_ring:
3620 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3626 i915_gem_init_hw(struct drm_device *dev)
3628 drm_i915_private_t *dev_priv = dev->dev_private;
3632 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3636 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3637 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3639 if (HAS_PCH_NOP(dev)) {
3640 u32 temp = I915_READ(GEN7_MSG_CTL);
3641 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
3642 I915_WRITE(GEN7_MSG_CTL, temp);
3645 i915_gem_l3_remap(dev);
3647 i915_gem_init_swizzling(dev);
3649 ret = i915_gem_init_rings(dev);
3654 * XXX: There was some w/a described somewhere suggesting loading
3655 * contexts before PPGTT.
3657 i915_gem_context_init(dev);
3658 if (dev_priv->mm.aliasing_ppgtt) {
3659 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
3661 i915_gem_cleanup_aliasing_ppgtt(dev);
3662 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
3669 int i915_gem_init(struct drm_device *dev)
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3674 mutex_lock(&dev->struct_mutex);
3676 if (IS_VALLEYVIEW(dev)) {
3677 /* VLVA0 (potential hack), BIOS isn't actually waking us */
3678 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
3679 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
3680 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
3683 i915_gem_init_global_gtt(dev);
3685 ret = i915_gem_init_hw(dev);
3686 mutex_unlock(&dev->struct_mutex);
3688 i915_gem_cleanup_aliasing_ppgtt(dev);
3692 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3693 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3694 dev_priv->dri1.allow_batchbuffer = 1;
3699 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3701 drm_i915_private_t *dev_priv = dev->dev_private;
3702 struct intel_ring_buffer *ring;
3705 for_each_ring(ring, dev_priv, i)
3706 intel_cleanup_ring_buffer(ring);
3710 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3711 struct drm_file *file_priv)
3713 drm_i915_private_t *dev_priv = dev->dev_private;
3716 if (drm_core_check_feature(dev, DRIVER_MODESET))
3719 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
3720 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3721 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
3724 mutex_lock(&dev->struct_mutex);
3725 dev_priv->mm.suspended = 0;
3727 ret = i915_gem_init_hw(dev);
3729 mutex_unlock(&dev->struct_mutex);
3733 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
3734 mutex_unlock(&dev->struct_mutex);
3736 ret = drm_irq_install(dev);
3738 goto cleanup_ringbuffer;
3743 mutex_lock(&dev->struct_mutex);
3744 i915_gem_cleanup_ringbuffer(dev);
3745 dev_priv->mm.suspended = 1;
3746 mutex_unlock(&dev->struct_mutex);
3752 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3753 struct drm_file *file_priv)
3755 if (drm_core_check_feature(dev, DRIVER_MODESET))
3758 drm_irq_uninstall(dev);
3759 return i915_gem_idle(dev);
3763 i915_gem_lastclose(struct drm_device *dev)
3767 if (drm_core_check_feature(dev, DRIVER_MODESET))
3770 ret = i915_gem_idle(dev);
3772 DRM_ERROR("failed to idle hardware: %d\n", ret);
3776 init_ring_lists(struct intel_ring_buffer *ring)
3778 INIT_LIST_HEAD(&ring->active_list);
3779 INIT_LIST_HEAD(&ring->request_list);
3783 i915_gem_load(struct drm_device *dev)
3786 drm_i915_private_t *dev_priv = dev->dev_private;
3788 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3789 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3790 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
3791 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
3792 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3793 for (i = 0; i < I915_NUM_RINGS; i++)
3794 init_ring_lists(&dev_priv->ring[i]);
3795 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3796 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3797 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3798 i915_gem_retire_work_handler);
3799 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
3801 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3803 I915_WRITE(MI_ARB_STATE,
3804 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3807 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3809 /* Old X drivers will take 0-2 for front, back, depth buffers */
3810 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3811 dev_priv->fence_reg_start = 3;
3813 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
3814 dev_priv->num_fence_regs = 32;
3815 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3816 dev_priv->num_fence_regs = 16;
3818 dev_priv->num_fence_regs = 8;
3820 /* Initialize fence registers to zero */
3821 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3822 i915_gem_restore_fences(dev);
3824 i915_gem_detect_bit_6_swizzle(dev);
3825 init_waitqueue_head(&dev_priv->pending_flip_queue);
3827 dev_priv->mm.interruptible = true;
3830 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3831 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3832 register_shrinker(&dev_priv->mm.inactive_shrinker);
3834 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
3835 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
3840 * Create a physically contiguous memory object for this object
3841 * e.g. for cursor + overlay regs
3843 static int i915_gem_init_phys_object(struct drm_device *dev,
3844 int id, int size, int align)
3846 drm_i915_private_t *dev_priv = dev->dev_private;
3847 struct drm_i915_gem_phys_object *phys_obj;
3850 if (dev_priv->mm.phys_objs[id - 1] || !size)
3853 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3859 phys_obj->handle = drm_pci_alloc(dev, size, align);
3860 if (!phys_obj->handle) {
3864 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3865 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3867 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3872 drm_free(phys_obj, M_DRM);
3876 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3878 drm_i915_private_t *dev_priv = dev->dev_private;
3879 struct drm_i915_gem_phys_object *phys_obj;
3881 if (!dev_priv->mm.phys_objs[id - 1])
3884 phys_obj = dev_priv->mm.phys_objs[id - 1];
3885 if (phys_obj->cur_obj) {
3886 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3889 drm_pci_free(dev, phys_obj->handle);
3890 drm_free(phys_obj, M_DRM);
3891 dev_priv->mm.phys_objs[id - 1] = NULL;
3894 void i915_gem_free_all_phys_object(struct drm_device *dev)
3898 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3899 i915_gem_free_phys_object(dev, i);
3902 void i915_gem_detach_phys_object(struct drm_device *dev,
3903 struct drm_i915_gem_object *obj)
3905 struct vm_object *mapping = obj->base.vm_obj;
3912 vaddr = obj->phys_obj->handle->vaddr;
3914 page_count = obj->base.size / PAGE_SIZE;
3915 VM_OBJECT_LOCK(obj->base.vm_obj);
3916 for (i = 0; i < page_count; i++) {
3917 struct vm_page *page = shmem_read_mapping_page(mapping, i);
3918 if (!IS_ERR(page)) {
3919 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3920 char *dst = kmap_atomic(page);
3921 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3924 drm_clflush_pages(&page, 1);
3927 set_page_dirty(page);
3928 mark_page_accessed(page);
3929 page_cache_release(page);
3931 VM_OBJECT_LOCK(obj->base.vm_obj);
3932 vm_page_reference(page);
3933 vm_page_dirty(page);
3934 vm_page_busy_wait(page, FALSE, "i915gem");
3935 vm_page_unwire(page, 0);
3936 vm_page_wakeup(page);
3939 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3940 intel_gtt_chipset_flush();
3942 obj->phys_obj->cur_obj = NULL;
3943 obj->phys_obj = NULL;
3947 i915_gem_attach_phys_object(struct drm_device *dev,
3948 struct drm_i915_gem_object *obj,
3952 struct vm_object *mapping = obj->base.vm_obj;
3953 drm_i915_private_t *dev_priv = dev->dev_private;
3958 if (id > I915_MAX_PHYS_OBJECT)
3961 if (obj->phys_obj) {
3962 if (obj->phys_obj->id == id)
3964 i915_gem_detach_phys_object(dev, obj);
3967 /* create a new object */
3968 if (!dev_priv->mm.phys_objs[id - 1]) {
3969 ret = i915_gem_init_phys_object(dev, id,
3970 obj->base.size, align);
3972 DRM_ERROR("failed to init phys object %d size: %zu\n",
3973 id, obj->base.size);
3978 /* bind to the object */
3979 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3980 obj->phys_obj->cur_obj = obj;
3982 page_count = obj->base.size / PAGE_SIZE;
3984 VM_OBJECT_LOCK(obj->base.vm_obj);
3985 for (i = 0; i < page_count; i++) {
3986 struct vm_page *page;
3989 page = shmem_read_mapping_page(mapping, i);
3990 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3992 return PTR_ERR(page);
3994 src = kmap_atomic(page);
3995 dst = (char*)obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3996 memcpy(dst, src, PAGE_SIZE);
4000 mark_page_accessed(page);
4001 page_cache_release(page);
4003 VM_OBJECT_LOCK(obj->base.vm_obj);
4004 vm_page_reference(page);
4005 vm_page_busy_wait(page, FALSE, "i915gem");
4006 vm_page_unwire(page, 0);
4007 vm_page_wakeup(page);
4009 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4015 i915_gem_phys_pwrite(struct drm_device *dev,
4016 struct drm_i915_gem_object *obj,
4017 struct drm_i915_gem_pwrite *args,
4018 struct drm_file *file_priv)
4020 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4021 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4023 if (copyin_nofault(user_data, vaddr, args->size) != 0) {
4024 unsigned long unwritten;
4026 /* The physical object once assigned is fixed for the lifetime
4027 * of the obj, so we can safely drop the lock and continue
4030 mutex_unlock(&dev->struct_mutex);
4031 unwritten = copy_from_user(vaddr, user_data, args->size);
4032 mutex_lock(&dev->struct_mutex);
4037 i915_gem_chipset_flush(dev);
4041 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4043 struct drm_i915_file_private *file_priv = file->driver_priv;
4045 /* Clean up our request list when the client is going away, so that
4046 * later retire_requests won't dereference our soon-to-be-gone
4049 spin_lock(&file_priv->mm.lock);
4050 while (!list_empty(&file_priv->mm.request_list)) {
4051 struct drm_i915_gem_request *request;
4053 request = list_first_entry(&file_priv->mm.request_list,
4054 struct drm_i915_gem_request,
4056 list_del(&request->client_list);
4057 request->file_priv = NULL;
4059 spin_unlock(&file_priv->mm.lock);
4063 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
4064 vm_ooffset_t foff, struct ucred *cred, u_short *color)
4067 *color = 0; /* XXXKIB */
4074 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
4077 struct drm_gem_object *gem_obj;
4078 struct drm_i915_gem_object *obj;
4079 struct drm_device *dev;
4080 drm_i915_private_t *dev_priv;
4085 gem_obj = vm_obj->handle;
4086 obj = to_intel_bo(gem_obj);
4087 dev = obj->base.dev;
4088 dev_priv = dev->dev_private;
4090 write = (prot & VM_PROT_WRITE) != 0;
4094 vm_object_pip_add(vm_obj, 1);
4097 * Remove the placeholder page inserted by vm_fault() from the
4098 * object before dropping the object lock. If
4099 * i915_gem_release_mmap() is active in parallel on this gem
4100 * object, then it owns the drm device sx and might find the
4101 * placeholder already. Then, since the page is busy,
4102 * i915_gem_release_mmap() sleeps waiting for the busy state
4103 * of the page cleared. We will be not able to acquire drm
4104 * device lock until i915_gem_release_mmap() is able to make a
4107 if (*mres != NULL) {
4109 vm_page_remove(oldm);
4114 VM_OBJECT_UNLOCK(vm_obj);
4120 ret = i915_mutex_lock_interruptible(dev);
4126 mutex_lock(&dev->struct_mutex);
4129 * Since the object lock was dropped, other thread might have
4130 * faulted on the same GTT address and instantiated the
4131 * mapping for the page. Recheck.
4133 VM_OBJECT_LOCK(vm_obj);
4134 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
4136 if ((m->flags & PG_BUSY) != 0) {
4137 mutex_unlock(&dev->struct_mutex);
4139 vm_page_sleep(m, "915pee");
4145 VM_OBJECT_UNLOCK(vm_obj);
4147 /* Access to snoopable pages through the GTT is incoherent. */
4148 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
4153 /* Now bind it into the GTT if needed */
4154 if (!obj->map_and_fenceable) {
4155 ret = i915_gem_object_unbind(obj);
4161 if (!obj->gtt_space) {
4162 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
4168 ret = i915_gem_object_set_to_gtt_domain(obj, write);
4175 if (obj->tiling_mode == I915_TILING_NONE)
4176 ret = i915_gem_object_put_fence(obj);
4178 ret = i915_gem_object_get_fence(obj);
4184 if (i915_gem_object_is_inactive(obj))
4185 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
4187 obj->fault_mappable = true;
4188 VM_OBJECT_LOCK(vm_obj);
4189 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
4196 KASSERT((m->flags & PG_FICTITIOUS) != 0,
4197 ("not fictitious %p", m));
4198 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
4200 if ((m->flags & PG_BUSY) != 0) {
4201 mutex_unlock(&dev->struct_mutex);
4203 vm_page_sleep(m, "915pbs");
4207 m->valid = VM_PAGE_BITS_ALL;
4208 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
4211 vm_page_busy_try(m, false);
4213 mutex_unlock(&dev->struct_mutex);
4217 vm_object_pip_wakeup(vm_obj);
4218 return (VM_PAGER_OK);
4221 mutex_unlock(&dev->struct_mutex);
4223 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
4224 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
4225 goto unlocked_vmobj;
4227 VM_OBJECT_LOCK(vm_obj);
4228 vm_object_pip_wakeup(vm_obj);
4229 return (VM_PAGER_ERROR);
4233 i915_gem_pager_dtor(void *handle)
4235 struct drm_gem_object *obj;
4236 struct drm_device *dev;
4241 mutex_lock(&dev->struct_mutex);
4242 drm_gem_free_mmap_offset(obj);
4243 i915_gem_release_mmap(to_intel_bo(obj));
4244 drm_gem_object_unreference(obj);
4245 mutex_unlock(&dev->struct_mutex);
4248 struct cdev_pager_ops i915_gem_pager_ops = {
4249 .cdev_pg_fault = i915_gem_pager_fault,
4250 .cdev_pg_ctor = i915_gem_pager_ctor,
4251 .cdev_pg_dtor = i915_gem_pager_dtor
4254 #define GEM_PARANOID_CHECK_GTT 0
4255 #if GEM_PARANOID_CHECK_GTT
4257 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
4260 struct drm_i915_private *dev_priv;
4262 unsigned long start, end;
4266 dev_priv = dev->dev_private;
4267 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
4268 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
4269 for (i = start; i < end; i++) {
4270 pa = intel_gtt_read_pte_paddr(i);
4271 for (j = 0; j < page_count; j++) {
4272 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
4273 panic("Page %p in GTT pte index %d pte %x",
4274 ma[i], i, intel_gtt_read_pte(i));
4282 i915_gpu_is_active(struct drm_device *dev)
4284 drm_i915_private_t *dev_priv = dev->dev_private;
4286 return !list_empty(&dev_priv->mm.active_list);
4290 i915_gem_lowmem(void *arg)
4292 struct drm_device *dev;
4293 struct drm_i915_private *dev_priv;
4294 struct drm_i915_gem_object *obj, *next;
4295 int cnt, cnt_fail, cnt_total;
4298 dev_priv = dev->dev_private;
4300 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT))
4304 /* first scan for clean buffers */
4305 i915_gem_retire_requests(dev);
4307 cnt_total = cnt_fail = cnt = 0;
4309 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4311 if (i915_gem_object_is_purgeable(obj)) {
4312 if (i915_gem_object_unbind(obj) != 0)
4318 /* second pass, evict/count anything still on the inactive list */
4319 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4321 if (i915_gem_object_unbind(obj) == 0)
4327 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
4329 * We are desperate for pages, so as a last resort, wait
4330 * for the GPU to finish and discard whatever we can.
4331 * This has a dramatic impact to reduce the number of
4332 * OOM-killer events whilst running the GPU aggressively.
4334 if (i915_gpu_idle(dev) == 0)
4337 mutex_unlock(&dev->struct_mutex);