2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
53 * $FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 253497 2013-07-20 13:52:40Z kib $
56 #include <sys/resourcevar.h>
57 #include <sys/sfbuf.h>
60 #include <drm/i915_drm.h>
62 #include "intel_drv.h"
63 #include "intel_ringbuffer.h"
64 #include <linux/completion.h>
65 #include <linux/jiffies.h>
66 #include <linux/time.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
70 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
71 unsigned alignment, bool map_and_fenceable);
73 static int i915_gem_phys_pwrite(struct drm_device *dev,
74 struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
75 uint64_t size, struct drm_file *file_priv);
77 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
79 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
80 uint32_t size, int tiling_mode);
81 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
83 static int i915_gem_object_set_cpu_read_domain_range(
84 struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
85 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
86 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
87 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
88 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
89 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
90 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
91 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
92 uint32_t flush_domains);
93 static void i915_gem_clear_fence_reg(struct drm_device *dev,
94 struct drm_i915_fence_reg *reg);
95 static void i915_gem_reset_fences(struct drm_device *dev);
96 static void i915_gem_lowmem(void *arg);
98 static int i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
99 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file);
101 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
102 long i915_gem_wired_pages_cnt;
104 /* some bookkeeping */
105 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
109 dev_priv->mm.object_count++;
110 dev_priv->mm.object_memory += size;
113 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
117 dev_priv->mm.object_count--;
118 dev_priv->mm.object_memory -= size;
122 i915_gem_wait_for_error(struct drm_device *dev)
124 struct drm_i915_private *dev_priv = dev->dev_private;
125 struct completion *x = &dev_priv->error_completion;
128 if (!atomic_read(&dev_priv->mm.wedged))
132 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
133 * userspace. If it takes that long something really bad is going on and
134 * we should simply try to bail out and fail as gracefully as possible.
136 ret = wait_for_completion_interruptible_timeout(x, 10*hz);
138 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
140 } else if (ret < 0) {
144 if (atomic_read(&dev_priv->mm.wedged)) {
145 /* GPU is hung, bump the completion count to account for
146 * the token we just consumed so that we never hit zero and
147 * end up waiting upon a subsequent completion event that
150 spin_lock(&x->wait.lock);
152 spin_unlock(&x->wait.lock);
157 int i915_mutex_lock_interruptible(struct drm_device *dev)
161 ret = i915_gem_wait_for_error(dev);
165 ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
170 WARN_ON(i915_verify_lists(dev));
176 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
178 return (obj->gtt_space && !obj->active && obj->pin_count == 0);
182 i915_gem_init_ioctl(struct drm_device *dev, void *data,
183 struct drm_file *file)
185 struct drm_i915_gem_init *args;
186 drm_i915_private_t *dev_priv;
188 dev_priv = dev->dev_private;
191 if (args->gtt_start >= args->gtt_end ||
192 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
196 * XXXKIB. The second-time initialization should be guarded
199 lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
200 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
201 lockmgr(&dev->dev_lock, LK_RELEASE);
207 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
208 struct drm_file *file)
210 struct drm_i915_private *dev_priv;
211 struct drm_i915_gem_get_aperture *args;
212 struct drm_i915_gem_object *obj;
215 dev_priv = dev->dev_private;
218 if (!(dev->driver->driver_features & DRIVER_GEM))
223 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
224 pinned += obj->gtt_space->size;
227 args->aper_size = dev_priv->mm.gtt_total;
228 args->aper_available_size = args->aper_size - pinned;
234 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
237 struct drm_i915_gem_object *obj;
241 size = roundup(size, PAGE_SIZE);
245 obj = i915_gem_alloc_object(dev, size);
250 ret = drm_gem_handle_create(file, &obj->base, &handle);
252 drm_gem_object_release(&obj->base);
253 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
254 drm_free(obj, DRM_I915_GEM);
258 /* drop reference from allocate - handle holds it now */
259 drm_gem_object_unreference(&obj->base);
265 i915_gem_dumb_create(struct drm_file *file,
266 struct drm_device *dev,
267 struct drm_mode_create_dumb *args)
270 /* have to work out size/pitch and return them */
271 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
272 args->size = args->pitch * args->height;
273 return (i915_gem_create(file, dev, args->size, &args->handle));
276 int i915_gem_dumb_destroy(struct drm_file *file,
277 struct drm_device *dev,
281 return (drm_gem_handle_delete(file, handle));
285 * Creates a new mm object and returns a handle to it.
288 i915_gem_create_ioctl(struct drm_device *dev, void *data,
289 struct drm_file *file)
291 struct drm_i915_gem_create *args = data;
293 return (i915_gem_create(file, dev, args->size, &args->handle));
296 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
298 drm_i915_private_t *dev_priv;
300 dev_priv = obj->base.dev->dev_private;
301 return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
302 obj->tiling_mode != I915_TILING_NONE);
306 * Reads data from the object referenced by handle.
308 * On error, the contents of *data are undefined.
311 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
312 struct drm_file *file)
314 struct drm_i915_gem_pread *args;
317 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
318 args->offset, UIO_READ, file));
322 * Writes data to the object referenced by handle.
324 * On error, the contents of the buffer that were to be modified are undefined.
327 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
328 struct drm_file *file)
330 struct drm_i915_gem_pwrite *args;
333 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
334 args->offset, UIO_WRITE, file));
338 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
341 if (atomic_read(&dev_priv->mm.wedged)) {
342 struct completion *x = &dev_priv->error_completion;
343 bool recovery_complete;
345 /* Give the error handler a chance to run. */
346 spin_lock(&x->wait.lock);
347 recovery_complete = x->done > 0;
348 spin_unlock(&x->wait.lock);
350 /* Non-interruptible callers can't handle -EAGAIN, hence return
351 * -EIO unconditionally for these. */
355 /* Recovery complete, but still wedged means reset failure. */
356 if (recovery_complete)
366 * __wait_seqno - wait until execution of seqno has finished
367 * @ring: the ring expected to report seqno
369 * @interruptible: do an interruptible wait (normally yes)
370 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
372 * Returns 0 if the seqno was found within the alloted time. Else returns the
373 * errno with remaining time filled in timeout argument.
375 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
376 bool interruptible, struct timespec *timeout)
378 drm_i915_private_t *dev_priv = ring->dev->dev_private;
379 struct timespec before, now, wait_time={1,0};
380 unsigned long timeout_jiffies;
382 bool wait_forever = true;
385 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
388 if (timeout != NULL) {
389 wait_time = *timeout;
390 wait_forever = false;
393 timeout_jiffies = timespec_to_jiffies(&wait_time);
395 if (WARN_ON(!ring->irq_get(ring)))
398 /* Record current time in case interrupted by signal, or wedged * */
399 getrawmonotonic(&before);
402 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
403 atomic_read(&dev_priv->mm.wedged))
406 end = wait_event_interruptible_timeout(ring->irq_queue,
410 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
413 ret = i915_gem_check_wedge(dev_priv, interruptible);
416 } while (end == 0 && wait_forever);
418 getrawmonotonic(&now);
424 struct timespec sleep_time = timespec_sub(now, before);
425 *timeout = timespec_sub(*timeout, sleep_time);
430 case -EAGAIN: /* Wedged */
431 case -ERESTARTSYS: /* Signal */
433 case 0: /* Timeout */
435 set_normalized_timespec(timeout, 0, 0);
436 return -ETIMEDOUT; /* -ETIME on Linux */
437 default: /* Completed */
438 WARN_ON(end < 0); /* We're not aware of other errors */
444 * Waits for a sequence number to be signaled, and cleans up the
445 * request and object lists appropriately for that event.
448 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
450 struct drm_device *dev = ring->dev;
451 struct drm_i915_private *dev_priv = dev->dev_private;
452 bool interruptible = dev_priv->mm.interruptible;
453 struct drm_i915_gem_request *request;
456 DRM_LOCK_ASSERT(dev);
459 ret = i915_gem_check_wedge(dev_priv, interruptible);
463 if (seqno == ring->outstanding_lazy_request) {
464 request = kmalloc(sizeof(*request), DRM_I915_GEM,
469 ret = i915_add_request(ring, NULL, request);
471 drm_free(request, DRM_I915_GEM);
475 seqno = request->seqno;
478 return __wait_seqno(ring, seqno, interruptible, NULL);
482 * Ensures that all rendering to the object has completed and the object is
483 * safe to unbind from the GTT or access from the CPU.
486 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
492 seqno = obj->last_rendering_seqno;
497 ret = i915_wait_seqno(obj->ring, obj->last_rendering_seqno);
502 /* Manually manage the write flush as we may have not yet
503 * retired the buffer.
505 if (obj->last_rendering_seqno &&
506 i915_seqno_passed(seqno, obj->last_rendering_seqno)) {
507 obj->last_rendering_seqno = 0;
508 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
515 * Called when user space prepares to use an object with the CPU, either
516 * through the mmap ioctl's mapping or a GTT mapping.
519 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
520 struct drm_file *file)
522 struct drm_i915_gem_set_domain *args;
523 struct drm_i915_gem_object *obj;
524 uint32_t read_domains;
525 uint32_t write_domain;
528 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
532 read_domains = args->read_domains;
533 write_domain = args->write_domain;
535 if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
536 (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
537 (write_domain != 0 && read_domains != write_domain))
540 ret = i915_mutex_lock_interruptible(dev);
544 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
545 if (&obj->base == NULL) {
550 if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
551 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
555 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
557 drm_gem_object_unreference(&obj->base);
564 * Called when user space has done writes to this buffer
567 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
568 struct drm_file *file)
570 struct drm_i915_gem_sw_finish *args;
571 struct drm_i915_gem_object *obj;
576 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
578 ret = i915_mutex_lock_interruptible(dev);
581 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
582 if (&obj->base == NULL) {
586 if (obj->pin_count != 0)
587 i915_gem_object_flush_cpu_write_domain(obj);
588 drm_gem_object_unreference(&obj->base);
595 * Maps the contents of an object, returning the address it is mapped
598 * While the mapping holds a reference on the contents of the object, it doesn't
599 * imply a ref on the object itself.
602 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
603 struct drm_file *file)
605 struct drm_i915_gem_mmap *args;
606 struct drm_gem_object *obj;
615 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
618 obj = drm_gem_object_lookup(dev, file, args->handle);
625 map = &p->p_vmspace->vm_map;
626 size = round_page(args->size);
628 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
636 vm_object_hold(obj->vm_obj);
637 vm_object_reference_locked(obj->vm_obj);
638 vm_object_drop(obj->vm_obj);
640 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
641 PAGE_SIZE, /* align */
643 VM_MAPTYPE_NORMAL, /* maptype */
644 VM_PROT_READ | VM_PROT_WRITE, /* prot */
645 VM_PROT_READ | VM_PROT_WRITE, /* max */
646 MAP_SHARED /* cow */);
647 if (rv != KERN_SUCCESS) {
648 vm_object_deallocate(obj->vm_obj);
649 error = -vm_mmap_to_errno(rv);
651 args->addr_ptr = (uint64_t)addr;
655 drm_gem_object_unreference(obj);
660 * i915_gem_release_mmap - remove physical page mappings
661 * @obj: obj in question
663 * Preserve the reservation of the mmapping with the DRM core code, but
664 * relinquish ownership of the pages back to the system.
666 * It is vital that we remove the page mapping if we have mapped a tiled
667 * object through the GTT and then lose the fence register due to
668 * resource pressure. Similarly if the object has been moved out of the
669 * aperture, than pages mapped into userspace must be revoked. Removing the
670 * mapping will then trigger a page fault on the next user access, allowing
671 * fixup by i915_gem_fault().
674 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
680 if (!obj->fault_mappable)
683 devobj = cdev_pager_lookup(obj);
684 if (devobj != NULL) {
685 page_count = OFF_TO_IDX(obj->base.size);
687 VM_OBJECT_LOCK(devobj);
688 for (i = 0; i < page_count; i++) {
689 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
692 cdev_pager_free_page(devobj, m);
694 VM_OBJECT_UNLOCK(devobj);
695 vm_object_deallocate(devobj);
698 obj->fault_mappable = false;
702 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
706 if (INTEL_INFO(dev)->gen >= 4 ||
707 tiling_mode == I915_TILING_NONE)
710 /* Previous chips need a power-of-two fence region when tiling */
711 if (INTEL_INFO(dev)->gen == 3)
712 gtt_size = 1024*1024;
716 while (gtt_size < size)
723 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
724 * @obj: object to check
726 * Return the required GTT alignment for an object, taking into account
727 * potential fence register mapping.
730 i915_gem_get_gtt_alignment(struct drm_device *dev,
736 * Minimum alignment is 4k (GTT page size), but might be greater
737 * if a fence register is needed for the object.
739 if (INTEL_INFO(dev)->gen >= 4 ||
740 tiling_mode == I915_TILING_NONE)
744 * Previous chips need to be aligned to the size of the smallest
745 * fence register that can contain the object.
747 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
751 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
754 * @size: size of the object
755 * @tiling_mode: tiling mode of the object
757 * Return the required GTT alignment for an object, only taking into account
758 * unfenced tiled surface requirements.
761 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
766 if (tiling_mode == I915_TILING_NONE)
770 * Minimum alignment is 4k (GTT page size) for sane hw.
772 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
776 * Previous hardware however needs to be aligned to a power-of-two
777 * tile height. The simplest method for determining this is to reuse
778 * the power-of-tile object size.
780 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
784 i915_gem_mmap_gtt(struct drm_file *file,
785 struct drm_device *dev,
789 struct drm_i915_private *dev_priv;
790 struct drm_i915_gem_object *obj;
793 if (!(dev->driver->driver_features & DRIVER_GEM))
796 dev_priv = dev->dev_private;
798 ret = i915_mutex_lock_interruptible(dev);
802 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
803 if (&obj->base == NULL) {
808 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
813 if (obj->madv != I915_MADV_WILLNEED) {
814 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
819 ret = drm_gem_create_mmap_offset(&obj->base);
823 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
826 drm_gem_object_unreference(&obj->base);
833 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
835 * @data: GTT mapping ioctl data
836 * @file: GEM object info
838 * Simply returns the fake offset to userspace so it can mmap it.
839 * The mmap call will end up in drm_gem_mmap(), which will set things
840 * up so we can get faults in the handler above.
842 * The fault handler will take care of binding the object into the GTT
843 * (since it may have been evicted to make room for something), allocating
844 * a fence register, and mapping the appropriate aperture address into
848 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file)
851 struct drm_i915_private *dev_priv;
852 struct drm_i915_gem_mmap_gtt *args;
854 dev_priv = dev->dev_private;
857 return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
860 /* Immediately discard the backing storage */
862 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
866 vm_obj = obj->base.vm_obj;
867 VM_OBJECT_LOCK(vm_obj);
868 vm_object_page_remove(vm_obj, 0, 0, false);
869 VM_OBJECT_UNLOCK(vm_obj);
870 obj->madv = __I915_MADV_PURGED;
874 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
876 return obj->madv == I915_MADV_DONTNEED;
879 static inline void vm_page_reference(vm_page_t m)
881 vm_page_flag_set(m, PG_REFERENCED);
885 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
890 BUG_ON(obj->madv == __I915_MADV_PURGED);
892 if (obj->tiling_mode != I915_TILING_NONE)
893 i915_gem_object_save_bit_17_swizzle(obj);
894 if (obj->madv == I915_MADV_DONTNEED)
896 page_count = obj->base.size / PAGE_SIZE;
897 VM_OBJECT_LOCK(obj->base.vm_obj);
898 #if GEM_PARANOID_CHECK_GTT
899 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
901 for (i = 0; i < page_count; i++) {
905 if (obj->madv == I915_MADV_WILLNEED)
906 vm_page_reference(m);
907 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
908 vm_page_unwire(obj->pages[i], 1);
909 vm_page_wakeup(obj->pages[i]);
910 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
912 VM_OBJECT_UNLOCK(obj->base.vm_obj);
914 drm_free(obj->pages, DRM_I915_GEM);
919 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
922 struct drm_device *dev;
925 int page_count, i, j;
928 KASSERT(obj->pages == NULL, ("Obj already has pages"));
929 page_count = obj->base.size / PAGE_SIZE;
930 obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
932 vm_obj = obj->base.vm_obj;
933 VM_OBJECT_LOCK(vm_obj);
934 for (i = 0; i < page_count; i++) {
935 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
938 VM_OBJECT_UNLOCK(vm_obj);
939 if (i915_gem_object_needs_bit17_swizzle(obj))
940 i915_gem_object_do_bit_17_swizzle(obj);
944 for (j = 0; j < i; j++) {
946 vm_page_busy_wait(m, FALSE, "i915gem");
947 vm_page_unwire(m, 0);
949 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
951 VM_OBJECT_UNLOCK(vm_obj);
952 drm_free(obj->pages, DRM_I915_GEM);
958 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
959 struct intel_ring_buffer *ring, uint32_t seqno)
961 struct drm_device *dev = obj->base.dev;
962 struct drm_i915_private *dev_priv = dev->dev_private;
963 struct drm_i915_fence_reg *reg;
966 KASSERT(ring != NULL, ("NULL ring"));
968 /* Add a reference if we're newly entering the active list. */
970 drm_gem_object_reference(&obj->base);
974 /* Move from whatever list we were on to the tail of execution. */
975 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
976 list_move_tail(&obj->ring_list, &ring->active_list);
978 obj->last_rendering_seqno = seqno;
979 if (obj->fenced_gpu_access) {
980 obj->last_fenced_seqno = seqno;
981 obj->last_fenced_ring = ring;
983 /* Bump MRU to take account of the delayed flush */
984 if (obj->fence_reg != I915_FENCE_REG_NONE) {
985 reg = &dev_priv->fence_regs[obj->fence_reg];
986 list_move_tail(®->lru_list,
987 &dev_priv->mm.fence_list);
993 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
995 list_del_init(&obj->ring_list);
996 obj->last_rendering_seqno = 0;
997 obj->last_fenced_seqno = 0;
1001 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1003 struct drm_device *dev = obj->base.dev;
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1006 if (obj->pin_count != 0)
1007 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1009 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1011 KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
1012 KASSERT(obj->active, ("Object not active"));
1014 obj->last_fenced_ring = NULL;
1016 i915_gem_object_move_off_active(obj);
1017 obj->fenced_gpu_access = false;
1020 obj->pending_gpu_write = false;
1021 drm_gem_object_unreference(&obj->base);
1026 WARN_ON(i915_verify_lists(dev));
1031 i915_gem_get_seqno(struct drm_device *dev)
1033 drm_i915_private_t *dev_priv = dev->dev_private;
1034 u32 seqno = dev_priv->next_seqno;
1036 /* reserve 0 for non-seqno */
1037 if (++dev_priv->next_seqno == 0)
1038 dev_priv->next_seqno = 1;
1044 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
1045 struct drm_i915_gem_request *request)
1047 drm_i915_private_t *dev_priv;
1048 struct drm_i915_file_private *file_priv;
1050 u32 request_ring_position;
1054 KASSERT(request != NULL, ("NULL request in add"));
1055 DRM_LOCK_ASSERT(ring->dev);
1056 dev_priv = ring->dev->dev_private;
1058 seqno = i915_gem_next_request_seqno(ring);
1059 request_ring_position = intel_ring_get_tail(ring);
1061 ret = ring->add_request(ring, &seqno);
1065 request->seqno = seqno;
1066 request->ring = ring;
1067 request->tail = request_ring_position;
1068 request->emitted_jiffies = ticks;
1069 was_empty = list_empty(&ring->request_list);
1070 list_add_tail(&request->list, &ring->request_list);
1073 file_priv = file->driver_priv;
1075 spin_lock(&file_priv->mm.lock);
1076 request->file_priv = file_priv;
1077 list_add_tail(&request->client_list,
1078 &file_priv->mm.request_list);
1079 spin_unlock(&file_priv->mm.lock);
1082 ring->outstanding_lazy_request = 0;
1084 if (!dev_priv->mm.suspended) {
1085 if (i915_enable_hangcheck) {
1086 mod_timer(&dev_priv->hangcheck_timer,
1087 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1090 queue_delayed_work(dev_priv->wq,
1091 &dev_priv->mm.retire_work,
1092 round_jiffies_up_relative(hz));
1093 intel_mark_busy(dev_priv->dev);
1100 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1102 struct drm_i915_file_private *file_priv = request->file_priv;
1107 DRM_LOCK_ASSERT(request->ring->dev);
1109 spin_lock(&file_priv->mm.lock);
1110 if (request->file_priv != NULL) {
1111 list_del(&request->client_list);
1112 request->file_priv = NULL;
1114 spin_unlock(&file_priv->mm.lock);
1118 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1119 struct intel_ring_buffer *ring)
1122 if (ring->dev != NULL)
1123 DRM_LOCK_ASSERT(ring->dev);
1125 while (!list_empty(&ring->request_list)) {
1126 struct drm_i915_gem_request *request;
1128 request = list_first_entry(&ring->request_list,
1129 struct drm_i915_gem_request, list);
1131 list_del(&request->list);
1132 i915_gem_request_remove_from_client(request);
1133 drm_free(request, DRM_I915_GEM);
1136 while (!list_empty(&ring->active_list)) {
1137 struct drm_i915_gem_object *obj;
1139 obj = list_first_entry(&ring->active_list,
1140 struct drm_i915_gem_object, ring_list);
1142 obj->base.write_domain = 0;
1143 list_del_init(&obj->gpu_write_list);
1144 i915_gem_object_move_to_inactive(obj);
1149 i915_gem_reset_fences(struct drm_device *dev)
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1154 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1155 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1156 struct drm_i915_gem_object *obj = reg->obj;
1161 if (obj->tiling_mode)
1162 i915_gem_release_mmap(obj);
1164 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1165 reg->obj->fenced_gpu_access = false;
1166 reg->obj->last_fenced_seqno = 0;
1167 reg->obj->last_fenced_ring = NULL;
1168 i915_gem_clear_fence_reg(dev, reg);
1172 void i915_gem_reset(struct drm_device *dev)
1174 struct drm_i915_private *dev_priv = dev->dev_private;
1175 struct drm_i915_gem_object *obj;
1178 for (i = 0; i < I915_NUM_RINGS; i++)
1179 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1181 /* Remove anything from the flushing lists. The GPU cache is likely
1182 * to be lost on reset along with the data, so simply move the
1183 * lost bo to the inactive list.
1185 while (!list_empty(&dev_priv->mm.flushing_list)) {
1186 obj = list_first_entry(&dev_priv->mm.flushing_list,
1187 struct drm_i915_gem_object,
1190 obj->base.write_domain = 0;
1191 list_del_init(&obj->gpu_write_list);
1192 i915_gem_object_move_to_inactive(obj);
1195 /* Move everything out of the GPU domains to ensure we do any
1196 * necessary invalidation upon reuse.
1198 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
1199 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1202 /* The fence registers are invalidated so clear them out */
1203 i915_gem_reset_fences(dev);
1207 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1209 struct drm_device *dev = obj->base.dev;
1210 drm_i915_private_t *dev_priv = dev->dev_private;
1212 KASSERT(obj->active, ("Object not active"));
1213 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1215 i915_gem_object_move_off_active(obj);
1219 * This function clears the request list as sequence numbers are passed.
1222 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1226 if (list_empty(&ring->request_list))
1229 seqno = ring->get_seqno(ring, true);
1231 while (!list_empty(&ring->request_list)) {
1232 struct drm_i915_gem_request *request;
1234 request = list_first_entry(&ring->request_list,
1235 struct drm_i915_gem_request,
1238 if (!i915_seqno_passed(seqno, request->seqno))
1241 /* We know the GPU must have read the request to have
1242 * sent us the seqno + interrupt, so use the position
1243 * of tail of the request to update the last known position
1246 ring->last_retired_head = request->tail;
1248 list_del(&request->list);
1249 i915_gem_request_remove_from_client(request);
1250 drm_free(request, DRM_I915_GEM);
1253 /* Move any buffers on the active list that are no longer referenced
1254 * by the ringbuffer to the flushing/inactive lists as appropriate.
1256 while (!list_empty(&ring->active_list)) {
1257 struct drm_i915_gem_object *obj;
1259 obj = list_first_entry(&ring->active_list,
1260 struct drm_i915_gem_object,
1263 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1266 if (obj->base.write_domain != 0)
1267 i915_gem_object_move_to_flushing(obj);
1269 i915_gem_object_move_to_inactive(obj);
1272 if (unlikely(ring->trace_irq_seqno &&
1273 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1274 ring->irq_put(ring);
1275 ring->trace_irq_seqno = 0;
1281 i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
1284 i915_gem_retire_requests(struct drm_device *dev)
1286 drm_i915_private_t *dev_priv = dev->dev_private;
1287 struct drm_i915_gem_object *obj, *next;
1290 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1291 list_for_each_entry_safe(obj, next,
1292 &dev_priv->mm.deferred_free_list, mm_list)
1293 i915_gem_free_object_tail(obj);
1296 for (i = 0; i < I915_NUM_RINGS; i++)
1297 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1301 i915_gem_retire_work_handler(struct work_struct *work)
1303 drm_i915_private_t *dev_priv;
1304 struct drm_device *dev;
1305 struct intel_ring_buffer *ring;
1309 dev_priv = container_of(work, drm_i915_private_t,
1310 mm.retire_work.work);
1311 dev = dev_priv->dev;
1313 /* Come back later if the device is busy... */
1314 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
1315 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1316 round_jiffies_up_relative(hz));
1320 i915_gem_retire_requests(dev);
1322 /* Send a periodic flush down the ring so we don't hold onto GEM
1323 * objects indefinitely.
1326 for_each_ring(ring, dev_priv, i) {
1327 if (ring->gpu_caches_dirty)
1328 i915_add_request(ring, NULL, NULL);
1330 idle &= list_empty(&ring->request_list);
1333 if (!dev_priv->mm.suspended && !idle)
1334 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1335 round_jiffies_up_relative(hz));
1337 intel_mark_idle(dev);
1343 * i915_gem_object_sync - sync an object to a ring.
1345 * @obj: object which may be in use on another ring.
1346 * @to: ring we wish to use the object on. May be NULL.
1348 * This code is meant to abstract object synchronization with the GPU.
1349 * Calling with NULL implies synchronizing the object with the CPU
1350 * rather than a particular GPU ring.
1352 * Returns 0 if successful, else propagates up the lower layer error.
1355 i915_gem_object_sync(struct drm_i915_gem_object *obj,
1356 struct intel_ring_buffer *to)
1358 struct intel_ring_buffer *from = obj->ring;
1362 if (from == NULL || to == from)
1365 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
1366 return i915_gem_object_wait_rendering(obj);
1368 idx = intel_ring_sync_index(from, to);
1370 seqno = obj->last_rendering_seqno;
1371 if (seqno <= from->sync_seqno[idx])
1374 if (seqno == from->outstanding_lazy_request) {
1375 struct drm_i915_gem_request *request;
1377 request = kmalloc(sizeof(*request), DRM_I915_GEM,
1379 if (request == NULL)
1382 ret = i915_add_request(from, NULL, request);
1384 kfree(request, DRM_I915_GEM);
1388 seqno = request->seqno;
1391 from->sync_seqno[idx] = seqno;
1393 return to->sync_to(to, from, seqno - 1);
1396 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1398 u32 old_write_domain, old_read_domains;
1400 /* Act a barrier for all accesses through the GTT */
1403 /* Force a pagefault for domain tracking on next user access */
1404 i915_gem_release_mmap(obj);
1406 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
1409 old_read_domains = obj->base.read_domains;
1410 old_write_domain = obj->base.write_domain;
1412 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
1413 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
1418 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
1420 drm_i915_private_t *dev_priv;
1423 dev_priv = obj->base.dev->dev_private;
1425 if (obj->gtt_space == NULL)
1427 if (obj->pin_count != 0) {
1428 DRM_ERROR("Attempting to unbind pinned buffer\n");
1432 ret = i915_gem_object_finish_gpu(obj);
1433 if (ret == -ERESTART || ret == -EINTR)
1436 i915_gem_object_finish_gtt(obj);
1439 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1440 if (ret == -ERESTART || ret == -EINTR)
1443 i915_gem_clflush_object(obj);
1444 obj->base.read_domains = obj->base.write_domain =
1445 I915_GEM_DOMAIN_CPU;
1448 ret = i915_gem_object_put_fence(obj);
1449 if (ret == -ERESTART)
1452 i915_gem_gtt_unbind_object(obj);
1453 if (obj->has_aliasing_ppgtt_mapping) {
1454 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
1455 obj->has_aliasing_ppgtt_mapping = 0;
1457 i915_gem_object_put_pages_gtt(obj);
1459 list_del_init(&obj->gtt_list);
1460 list_del_init(&obj->mm_list);
1461 obj->map_and_fenceable = true;
1463 drm_mm_put_block(obj->gtt_space);
1464 obj->gtt_space = NULL;
1465 obj->gtt_offset = 0;
1467 if (i915_gem_object_is_purgeable(obj))
1468 i915_gem_object_truncate(obj);
1473 int i915_gpu_idle(struct drm_device *dev)
1475 drm_i915_private_t *dev_priv = dev->dev_private;
1476 struct intel_ring_buffer *ring;
1479 /* Flush everything onto the inactive list. */
1480 for_each_ring(ring, dev_priv, i) {
1481 ret = intel_ring_idle(ring);
1490 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
1491 struct intel_ring_buffer *pipelined)
1493 struct drm_device *dev = obj->base.dev;
1494 drm_i915_private_t *dev_priv = dev->dev_private;
1495 u32 size = obj->gtt_space->size;
1496 int regnum = obj->fence_reg;
1499 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1501 val |= obj->gtt_offset & 0xfffff000;
1502 val |= (uint64_t)((obj->stride / 128) - 1) <<
1503 SANDYBRIDGE_FENCE_PITCH_SHIFT;
1505 if (obj->tiling_mode == I915_TILING_Y)
1506 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1507 val |= I965_FENCE_REG_VALID;
1510 int ret = intel_ring_begin(pipelined, 6);
1514 intel_ring_emit(pipelined, MI_NOOP);
1515 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
1516 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
1517 intel_ring_emit(pipelined, (u32)val);
1518 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
1519 intel_ring_emit(pipelined, (u32)(val >> 32));
1520 intel_ring_advance(pipelined);
1522 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
1528 i965_write_fence_reg(struct drm_i915_gem_object *obj,
1529 struct intel_ring_buffer *pipelined)
1531 struct drm_device *dev = obj->base.dev;
1532 drm_i915_private_t *dev_priv = dev->dev_private;
1533 u32 size = obj->gtt_space->size;
1534 int regnum = obj->fence_reg;
1537 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1539 val |= obj->gtt_offset & 0xfffff000;
1540 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1541 if (obj->tiling_mode == I915_TILING_Y)
1542 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1543 val |= I965_FENCE_REG_VALID;
1546 int ret = intel_ring_begin(pipelined, 6);
1550 intel_ring_emit(pipelined, MI_NOOP);
1551 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
1552 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
1553 intel_ring_emit(pipelined, (u32)val);
1554 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
1555 intel_ring_emit(pipelined, (u32)(val >> 32));
1556 intel_ring_advance(pipelined);
1558 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
1564 i915_write_fence_reg(struct drm_i915_gem_object *obj,
1565 struct intel_ring_buffer *pipelined)
1567 struct drm_device *dev = obj->base.dev;
1568 drm_i915_private_t *dev_priv = dev->dev_private;
1569 u32 size = obj->gtt_space->size;
1570 u32 fence_reg, val, pitch_val;
1573 if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
1574 (size & -size) != size || (obj->gtt_offset & (size - 1))) {
1576 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
1577 obj->gtt_offset, obj->map_and_fenceable, size);
1581 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1586 /* Note: pitch better be a power of two tile widths */
1587 pitch_val = obj->stride / tile_width;
1588 pitch_val = ffs(pitch_val) - 1;
1590 val = obj->gtt_offset;
1591 if (obj->tiling_mode == I915_TILING_Y)
1592 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1593 val |= I915_FENCE_SIZE_BITS(size);
1594 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1595 val |= I830_FENCE_REG_VALID;
1597 fence_reg = obj->fence_reg;
1599 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
1601 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
1604 int ret = intel_ring_begin(pipelined, 4);
1608 intel_ring_emit(pipelined, MI_NOOP);
1609 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
1610 intel_ring_emit(pipelined, fence_reg);
1611 intel_ring_emit(pipelined, val);
1612 intel_ring_advance(pipelined);
1614 I915_WRITE(fence_reg, val);
1620 i830_write_fence_reg(struct drm_i915_gem_object *obj,
1621 struct intel_ring_buffer *pipelined)
1623 struct drm_device *dev = obj->base.dev;
1624 drm_i915_private_t *dev_priv = dev->dev_private;
1625 u32 size = obj->gtt_space->size;
1626 int regnum = obj->fence_reg;
1630 if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
1631 (size & -size) != size || (obj->gtt_offset & (size - 1))) {
1633 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
1634 obj->gtt_offset, size);
1638 pitch_val = obj->stride / 128;
1639 pitch_val = ffs(pitch_val) - 1;
1641 val = obj->gtt_offset;
1642 if (obj->tiling_mode == I915_TILING_Y)
1643 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1644 val |= I830_FENCE_SIZE_BITS(size);
1645 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1646 val |= I830_FENCE_REG_VALID;
1649 int ret = intel_ring_begin(pipelined, 4);
1653 intel_ring_emit(pipelined, MI_NOOP);
1654 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
1655 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
1656 intel_ring_emit(pipelined, val);
1657 intel_ring_advance(pipelined);
1659 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
1664 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
1666 return i915_seqno_passed(ring->get_seqno(ring,false), seqno);
1670 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
1671 struct intel_ring_buffer *pipelined)
1675 if (obj->fenced_gpu_access) {
1676 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1677 ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
1678 obj->base.write_domain);
1683 obj->fenced_gpu_access = false;
1686 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
1687 if (!ring_passed_seqno(obj->last_fenced_ring,
1688 obj->last_fenced_seqno)) {
1689 ret = i915_wait_seqno(obj->last_fenced_ring,
1690 obj->last_fenced_seqno);
1695 obj->last_fenced_seqno = 0;
1696 obj->last_fenced_ring = NULL;
1699 /* Ensure that all CPU reads are completed before installing a fence
1700 * and all writes before removing the fence.
1702 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
1709 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
1713 if (obj->tiling_mode)
1714 i915_gem_release_mmap(obj);
1716 ret = i915_gem_object_flush_fence(obj, NULL);
1720 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1721 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1723 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
1724 kprintf("%s: pin_count %d\n", __func__,
1725 dev_priv->fence_regs[obj->fence_reg].pin_count);
1726 i915_gem_clear_fence_reg(obj->base.dev,
1727 &dev_priv->fence_regs[obj->fence_reg]);
1729 obj->fence_reg = I915_FENCE_REG_NONE;
1735 static struct drm_i915_fence_reg *
1736 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
1738 struct drm_i915_private *dev_priv = dev->dev_private;
1739 struct drm_i915_fence_reg *reg, *first, *avail;
1742 /* First try to find a free reg */
1744 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1745 reg = &dev_priv->fence_regs[i];
1749 if (!reg->pin_count)
1756 /* None available, try to steal one or wait for a user to finish */
1757 avail = first = NULL;
1758 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
1766 !reg->obj->last_fenced_ring ||
1767 reg->obj->last_fenced_ring == pipelined) {
1780 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1781 struct intel_ring_buffer *pipelined)
1783 struct drm_device *dev = obj->base.dev;
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785 struct drm_i915_fence_reg *reg;
1791 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1792 reg = &dev_priv->fence_regs[obj->fence_reg];
1793 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1795 if (obj->tiling_changed) {
1796 ret = i915_gem_object_flush_fence(obj, pipelined);
1800 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
1805 i915_gem_next_request_seqno(pipelined);
1806 obj->last_fenced_seqno = reg->setup_seqno;
1807 obj->last_fenced_ring = pipelined;
1814 if (reg->setup_seqno) {
1815 if (!ring_passed_seqno(obj->last_fenced_ring,
1816 reg->setup_seqno)) {
1817 ret = i915_wait_seqno(
1818 obj->last_fenced_ring,
1824 reg->setup_seqno = 0;
1826 } else if (obj->last_fenced_ring &&
1827 obj->last_fenced_ring != pipelined) {
1828 ret = i915_gem_object_flush_fence(obj, pipelined);
1833 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
1835 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
1837 if (obj->tiling_changed) {
1840 i915_gem_next_request_seqno(pipelined);
1841 obj->last_fenced_seqno = reg->setup_seqno;
1842 obj->last_fenced_ring = pipelined;
1850 reg = i915_find_fence_reg(dev, pipelined);
1854 ret = i915_gem_object_flush_fence(obj, pipelined);
1859 struct drm_i915_gem_object *old = reg->obj;
1861 drm_gem_object_reference(&old->base);
1863 if (old->tiling_mode)
1864 i915_gem_release_mmap(old);
1866 ret = i915_gem_object_flush_fence(old, pipelined);
1868 drm_gem_object_unreference(&old->base);
1872 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
1875 old->fence_reg = I915_FENCE_REG_NONE;
1876 old->last_fenced_ring = pipelined;
1877 old->last_fenced_seqno =
1878 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
1880 drm_gem_object_unreference(&old->base);
1881 } else if (obj->last_fenced_seqno == 0)
1885 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1886 obj->fence_reg = reg - dev_priv->fence_regs;
1887 obj->last_fenced_ring = pipelined;
1890 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
1891 obj->last_fenced_seqno = reg->setup_seqno;
1894 obj->tiling_changed = false;
1895 switch (INTEL_INFO(dev)->gen) {
1898 ret = sandybridge_write_fence_reg(obj, pipelined);
1902 ret = i965_write_fence_reg(obj, pipelined);
1905 ret = i915_write_fence_reg(obj, pipelined);
1908 ret = i830_write_fence_reg(obj, pipelined);
1916 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1917 unsigned alignment, bool map_and_fenceable)
1919 struct drm_device *dev;
1920 struct drm_i915_private *dev_priv;
1921 struct drm_mm_node *free_space;
1922 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1923 bool mappable, fenceable;
1926 dev = obj->base.dev;
1927 dev_priv = dev->dev_private;
1929 if (obj->madv != I915_MADV_WILLNEED) {
1930 DRM_ERROR("Attempting to bind a purgeable object\n");
1934 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1936 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1938 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1939 obj->base.size, obj->tiling_mode);
1941 alignment = map_and_fenceable ? fence_alignment :
1943 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
1944 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1948 size = map_and_fenceable ? fence_size : obj->base.size;
1950 /* If the object is bigger than the entire aperture, reject it early
1951 * before evicting everything in a vain attempt to find space.
1953 if (obj->base.size > (map_and_fenceable ?
1954 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
1956 "Attempting to bind an object larger than the aperture\n");
1961 if (map_and_fenceable)
1962 free_space = drm_mm_search_free_in_range(
1963 &dev_priv->mm.gtt_space, size, alignment, 0,
1964 dev_priv->mm.gtt_mappable_end, 0);
1966 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1967 size, alignment, 0);
1968 if (free_space != NULL) {
1970 if (map_and_fenceable)
1971 obj->gtt_space = drm_mm_get_block_range_generic(
1972 free_space, size, alignment, color, 0,
1973 dev_priv->mm.gtt_mappable_end, 1);
1975 obj->gtt_space = drm_mm_get_block_generic(free_space,
1976 size, alignment, color, 1);
1978 if (obj->gtt_space == NULL) {
1979 ret = i915_gem_evict_something(dev, size, alignment,
1987 * NOTE: i915_gem_object_get_pages_gtt() cannot
1988 * return ENOMEM, since we used VM_ALLOC_RETRY.
1990 ret = i915_gem_object_get_pages_gtt(obj, 0);
1992 drm_mm_put_block(obj->gtt_space);
1993 obj->gtt_space = NULL;
1997 i915_gem_gtt_bind_object(obj, obj->cache_level);
1999 i915_gem_object_put_pages_gtt(obj);
2000 drm_mm_put_block(obj->gtt_space);
2001 obj->gtt_space = NULL;
2002 if (i915_gem_evict_everything(dev, false))
2007 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2008 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2010 obj->gtt_offset = obj->gtt_space->start;
2013 obj->gtt_space->size == fence_size &&
2014 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2017 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2018 obj->map_and_fenceable = mappable && fenceable;
2024 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2027 /* If we don't have a page list set up, then we're not pinned
2028 * to GPU, and we can ignore the cache flush because it'll happen
2029 * again at bind time.
2031 if (obj->pages == NULL)
2034 /* If the GPU is snooping the contents of the CPU cache,
2035 * we do not need to manually clear the CPU cache lines. However,
2036 * the caches are only snooped when the render cache is
2037 * flushed/invalidated. As we always have to emit invalidations
2038 * and flushes when moving into and out of the RENDER domain, correct
2039 * snooping behaviour occurs naturally as the result of our domain
2042 if (obj->cache_level != I915_CACHE_NONE)
2045 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2048 /** Flushes the GTT write domain for the object if it's dirty. */
2050 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2052 uint32_t old_write_domain;
2054 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2057 /* No actual flushing is required for the GTT write domain. Writes
2058 * to it immediately go to main memory as far as we know, so there's
2059 * no chipset flush. It also doesn't land in render cache.
2061 * However, we do have to enforce the order so that all writes through
2062 * the GTT land before any writes to the device, such as updates to
2067 old_write_domain = obj->base.write_domain;
2068 obj->base.write_domain = 0;
2071 /** Flushes the CPU write domain for the object if it's dirty. */
2073 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2075 uint32_t old_write_domain;
2077 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2080 i915_gem_clflush_object(obj);
2081 intel_gtt_chipset_flush();
2082 old_write_domain = obj->base.write_domain;
2083 obj->base.write_domain = 0;
2087 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2090 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2092 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
2096 * Moves a single object to the GTT read, and possibly write domain.
2098 * This function returns when the move is complete, including waiting on
2102 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2104 uint32_t old_write_domain, old_read_domains;
2107 if (obj->gtt_space == NULL)
2110 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2113 ret = i915_gem_object_flush_gpu_write_domain(obj);
2117 if (obj->pending_gpu_write || write) {
2118 ret = i915_gem_object_wait_rendering(obj);
2123 i915_gem_object_flush_cpu_write_domain(obj);
2125 old_write_domain = obj->base.write_domain;
2126 old_read_domains = obj->base.read_domains;
2128 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
2129 ("In GTT write domain"));
2130 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2132 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2133 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2140 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2141 enum i915_cache_level cache_level)
2143 struct drm_device *dev = obj->base.dev;
2144 drm_i915_private_t *dev_priv = dev->dev_private;
2147 if (obj->cache_level == cache_level)
2150 if (obj->pin_count) {
2151 DRM_DEBUG("can not change the cache level of pinned objects\n");
2155 if (obj->gtt_space) {
2156 ret = i915_gem_object_finish_gpu(obj);
2160 i915_gem_object_finish_gtt(obj);
2162 /* Before SandyBridge, you could not use tiling or fence
2163 * registers with snooped memory, so relinquish any fences
2164 * currently pointing to our region in the aperture.
2166 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2167 ret = i915_gem_object_put_fence(obj);
2172 if (obj->has_global_gtt_mapping)
2173 i915_gem_gtt_bind_object(obj, cache_level);
2174 if (obj->has_aliasing_ppgtt_mapping)
2175 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2179 if (cache_level == I915_CACHE_NONE) {
2180 u32 old_read_domains, old_write_domain;
2182 /* If we're coming from LLC cached, then we haven't
2183 * actually been tracking whether the data is in the
2184 * CPU cache or not, since we only allow one bit set
2185 * in obj->write_domain and have been skipping the clflushes.
2186 * Just set it to the CPU cache for now.
2188 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2189 ("obj %p in CPU write domain", obj));
2190 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2191 ("obj %p in CPU read domain", obj));
2193 old_read_domains = obj->base.read_domains;
2194 old_write_domain = obj->base.write_domain;
2196 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2197 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2201 obj->cache_level = cache_level;
2206 * Prepare buffer for display plane (scanout, cursors, etc).
2207 * Can be called from an uninterruptible phase (modesetting) and allows
2208 * any flushes to be pipelined (for pageflips).
2211 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2213 struct intel_ring_buffer *pipelined)
2215 u32 old_read_domains, old_write_domain;
2218 ret = i915_gem_object_flush_gpu_write_domain(obj);
2222 if (pipelined != obj->ring) {
2223 ret = i915_gem_object_sync(obj, pipelined);
2228 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2232 ret = i915_gem_object_pin(obj, alignment, true);
2236 i915_gem_object_flush_cpu_write_domain(obj);
2238 old_write_domain = obj->base.write_domain;
2239 old_read_domains = obj->base.read_domains;
2241 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
2242 ("obj %p in GTT write domain", obj));
2243 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2249 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2253 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2256 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2257 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2262 ret = i915_gem_object_wait_rendering(obj);
2266 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2272 * Moves a single object to the CPU read, and possibly write domain.
2274 * This function returns when the move is complete, including waiting on
2278 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2280 uint32_t old_write_domain, old_read_domains;
2283 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2286 ret = i915_gem_object_flush_gpu_write_domain(obj);
2290 ret = i915_gem_object_wait_rendering(obj);
2294 i915_gem_object_flush_gtt_write_domain(obj);
2296 old_write_domain = obj->base.write_domain;
2297 old_read_domains = obj->base.read_domains;
2299 /* Flush the CPU cache if it's still invalid. */
2300 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2301 i915_gem_clflush_object(obj);
2303 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2306 /* It should now be out of any other write domains, and we can update
2307 * the domain values for our changes.
2309 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2311 /* If we're writing through the CPU, then the GPU read domains will
2312 * need to be invalidated at next use.
2315 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2316 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2322 /* Throttle our rendering by waiting until the ring has completed our requests
2323 * emitted over 20 msec ago.
2325 * Note that if we were to use the current jiffies each time around the loop,
2326 * we wouldn't escape the function with any frames outstanding if the time to
2327 * render a frame was over 20ms.
2329 * This should get us reasonable parallelism between CPU and GPU but also
2330 * relatively low latency when blocking on a particular request to finish.
2333 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct drm_i915_file_private *file_priv = file->driver_priv;
2337 unsigned long recent_enough = ticks - (20 * hz / 1000);
2338 struct drm_i915_gem_request *request;
2339 struct intel_ring_buffer *ring = NULL;
2343 if (atomic_read(&dev_priv->mm.wedged))
2346 spin_lock(&file_priv->mm.lock);
2347 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2348 if (time_after_eq(request->emitted_jiffies, recent_enough))
2351 ring = request->ring;
2352 seqno = request->seqno;
2354 spin_unlock(&file_priv->mm.lock);
2359 ret = __wait_seqno(ring, seqno, true, NULL);
2362 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
2368 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
2369 bool map_and_fenceable)
2371 struct drm_device *dev;
2372 struct drm_i915_private *dev_priv;
2375 dev = obj->base.dev;
2376 dev_priv = dev->dev_private;
2378 KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
2381 if (obj->gtt_space != NULL) {
2382 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
2383 (map_and_fenceable && !obj->map_and_fenceable)) {
2384 DRM_DEBUG("bo is already pinned with incorrect alignment:"
2385 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
2386 " obj->map_and_fenceable=%d\n",
2387 obj->gtt_offset, alignment,
2389 obj->map_and_fenceable);
2390 ret = i915_gem_object_unbind(obj);
2396 if (obj->gtt_space == NULL) {
2397 ret = i915_gem_object_bind_to_gtt(obj, alignment,
2403 if (obj->pin_count++ == 0 && !obj->active)
2404 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2405 obj->pin_mappable |= map_and_fenceable;
2410 WARN_ON(i915_verify_lists(dev));
2416 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
2418 struct drm_device *dev;
2419 drm_i915_private_t *dev_priv;
2421 dev = obj->base.dev;
2422 dev_priv = dev->dev_private;
2427 WARN_ON(i915_verify_lists(dev));
2430 KASSERT(obj->pin_count != 0, ("zero pin count"));
2431 KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
2433 if (--obj->pin_count == 0) {
2435 list_move_tail(&obj->mm_list,
2436 &dev_priv->mm.inactive_list);
2437 obj->pin_mappable = false;
2442 WARN_ON(i915_verify_lists(dev));
2447 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2448 struct drm_file *file)
2450 struct drm_i915_gem_pin *args;
2451 struct drm_i915_gem_object *obj;
2452 struct drm_gem_object *gobj;
2457 ret = i915_mutex_lock_interruptible(dev);
2461 gobj = drm_gem_object_lookup(dev, file, args->handle);
2466 obj = to_intel_bo(gobj);
2468 if (obj->madv != I915_MADV_WILLNEED) {
2469 DRM_ERROR("Attempting to pin a purgeable buffer\n");
2474 if (obj->pin_filp != NULL && obj->pin_filp != file) {
2475 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2481 obj->user_pin_count++;
2482 obj->pin_filp = file;
2483 if (obj->user_pin_count == 1) {
2484 ret = i915_gem_object_pin(obj, args->alignment, true);
2489 /* XXX - flush the CPU caches for pinned objects
2490 * as the X server doesn't manage domains yet
2492 i915_gem_object_flush_cpu_write_domain(obj);
2493 args->offset = obj->gtt_offset;
2495 drm_gem_object_unreference(&obj->base);
2502 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2503 struct drm_file *file)
2505 struct drm_i915_gem_pin *args;
2506 struct drm_i915_gem_object *obj;
2510 ret = i915_mutex_lock_interruptible(dev);
2514 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2515 if (&obj->base == NULL) {
2520 if (obj->pin_filp != file) {
2521 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2526 obj->user_pin_count--;
2527 if (obj->user_pin_count == 0) {
2528 obj->pin_filp = NULL;
2529 i915_gem_object_unpin(obj);
2533 drm_gem_object_unreference(&obj->base);
2540 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2541 struct drm_file *file)
2543 struct drm_i915_gem_busy *args;
2544 struct drm_i915_gem_object *obj;
2545 struct drm_i915_gem_request *request;
2550 ret = i915_mutex_lock_interruptible(dev);
2554 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2555 if (&obj->base == NULL) {
2560 args->busy = obj->active;
2562 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2563 ret = i915_gem_flush_ring(obj->ring,
2564 0, obj->base.write_domain);
2565 } else if (obj->ring->outstanding_lazy_request ==
2566 obj->last_rendering_seqno) {
2567 request = kmalloc(sizeof(*request), DRM_I915_GEM,
2569 ret = i915_add_request(obj->ring, NULL, request);
2571 drm_free(request, DRM_I915_GEM);
2574 i915_gem_retire_requests_ring(obj->ring);
2575 args->busy = obj->active;
2578 drm_gem_object_unreference(&obj->base);
2585 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2586 struct drm_file *file_priv)
2589 return (i915_gem_ring_throttle(dev, file_priv));
2593 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2594 struct drm_file *file_priv)
2596 struct drm_i915_gem_madvise *args = data;
2597 struct drm_i915_gem_object *obj;
2600 switch (args->madv) {
2601 case I915_MADV_DONTNEED:
2602 case I915_MADV_WILLNEED:
2608 ret = i915_mutex_lock_interruptible(dev);
2612 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
2613 if (&obj->base == NULL) {
2618 if (obj->pin_count) {
2623 if (obj->madv != __I915_MADV_PURGED)
2624 obj->madv = args->madv;
2626 /* if the object is no longer attached, discard its backing storage */
2627 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
2628 i915_gem_object_truncate(obj);
2630 args->retained = obj->madv != __I915_MADV_PURGED;
2633 drm_gem_object_unreference(&obj->base);
2639 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2642 struct drm_i915_private *dev_priv;
2643 struct drm_i915_gem_object *obj;
2645 dev_priv = dev->dev_private;
2647 obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
2649 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
2650 drm_free(obj, DRM_I915_GEM);
2654 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2655 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2658 obj->cache_level = I915_CACHE_LLC;
2660 obj->cache_level = I915_CACHE_NONE;
2661 obj->base.driver_private = NULL;
2662 obj->fence_reg = I915_FENCE_REG_NONE;
2663 INIT_LIST_HEAD(&obj->mm_list);
2664 INIT_LIST_HEAD(&obj->gtt_list);
2665 INIT_LIST_HEAD(&obj->ring_list);
2666 INIT_LIST_HEAD(&obj->exec_list);
2667 INIT_LIST_HEAD(&obj->gpu_write_list);
2668 obj->madv = I915_MADV_WILLNEED;
2669 /* Avoid an unnecessary call to unbind on the first bind. */
2670 obj->map_and_fenceable = true;
2672 i915_gem_info_add_obj(dev_priv, size);
2677 int i915_gem_init_object(struct drm_gem_object *obj)
2680 kprintf("i915_gem_init_object called\n");
2685 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
2687 struct drm_device *dev;
2688 drm_i915_private_t *dev_priv;
2691 dev = obj->base.dev;
2692 dev_priv = dev->dev_private;
2694 ret = i915_gem_object_unbind(obj);
2695 if (ret == -ERESTART) {
2696 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
2700 drm_gem_free_mmap_offset(&obj->base);
2701 drm_gem_object_release(&obj->base);
2702 i915_gem_info_remove_obj(dev_priv, obj->base.size);
2704 drm_free(obj->page_cpu_valid, DRM_I915_GEM);
2705 drm_free(obj->bit_17, DRM_I915_GEM);
2706 drm_free(obj, DRM_I915_GEM);
2710 i915_gem_free_object(struct drm_gem_object *gem_obj)
2712 struct drm_i915_gem_object *obj;
2713 struct drm_device *dev;
2715 obj = to_intel_bo(gem_obj);
2716 dev = obj->base.dev;
2718 while (obj->pin_count > 0)
2719 i915_gem_object_unpin(obj);
2721 if (obj->phys_obj != NULL)
2722 i915_gem_detach_phys_object(dev, obj);
2724 i915_gem_free_object_tail(obj);
2728 i915_gem_do_init(struct drm_device *dev, unsigned long start,
2729 unsigned long mappable_end, unsigned long end)
2731 drm_i915_private_t *dev_priv;
2732 unsigned long mappable;
2735 dev_priv = dev->dev_private;
2736 mappable = min(end, mappable_end) - start;
2738 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
2740 dev_priv->mm.gtt_start = start;
2741 dev_priv->mm.gtt_mappable_end = mappable_end;
2742 dev_priv->mm.gtt_end = end;
2743 dev_priv->mm.gtt_total = end - start;
2744 dev_priv->mm.mappable_gtt_total = mappable;
2746 /* Take over this portion of the GTT */
2747 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
2748 device_printf(dev->dev,
2749 "taking over the fictitious range 0x%lx-0x%lx\n",
2750 dev->agp->base + start, dev->agp->base + start + mappable);
2751 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
2752 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
2757 i915_gem_idle(struct drm_device *dev)
2759 drm_i915_private_t *dev_priv;
2762 dev_priv = dev->dev_private;
2763 if (dev_priv->mm.suspended)
2766 ret = i915_gpu_idle(dev);
2770 /* Under UMS, be paranoid and evict. */
2771 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
2772 ret = i915_gem_evict_inactive(dev, false);
2777 i915_gem_reset_fences(dev);
2779 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2780 * We need to replace this with a semaphore, or something.
2781 * And not confound mm.suspended!
2783 dev_priv->mm.suspended = 1;
2784 del_timer_sync(&dev_priv->hangcheck_timer);
2786 i915_kernel_lost_context(dev);
2787 i915_gem_cleanup_ringbuffer(dev);
2789 /* Cancel the retire work handler, which should be idle now. */
2790 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2795 void i915_gem_l3_remap(struct drm_device *dev)
2797 drm_i915_private_t *dev_priv = dev->dev_private;
2801 if (!HAS_L3_GPU_CACHE(dev))
2804 if (!dev_priv->l3_parity.remap_info)
2807 misccpctl = I915_READ(GEN7_MISCCPCTL);
2808 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
2809 POSTING_READ(GEN7_MISCCPCTL);
2811 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
2812 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
2813 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
2814 DRM_DEBUG("0x%x was already programmed to %x\n",
2815 GEN7_L3LOG_BASE + i, remap);
2816 if (remap && !dev_priv->l3_parity.remap_info[i/4])
2817 DRM_DEBUG_DRIVER("Clearing remapped register\n");
2818 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
2821 /* Make sure all the writes land before disabling dop clock gating */
2822 POSTING_READ(GEN7_L3LOG_BASE);
2824 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
2828 i915_gem_init_swizzling(struct drm_device *dev)
2830 drm_i915_private_t *dev_priv;
2832 dev_priv = dev->dev_private;
2834 if (INTEL_INFO(dev)->gen < 5 ||
2835 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
2838 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
2839 DISP_TILE_SURFACE_SWIZZLING);
2844 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
2846 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
2848 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
2852 intel_enable_blt(struct drm_device *dev)
2859 /* The blitter was dysfunctional on early prototypes */
2860 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
2861 if (IS_GEN6(dev) && revision < 8) {
2862 DRM_INFO("BLT not supported on this pre-production hardware;"
2863 " graphics performance will be degraded.\n");
2871 i915_gem_init_hw(struct drm_device *dev)
2873 drm_i915_private_t *dev_priv = dev->dev_private;
2876 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
2877 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
2879 i915_gem_l3_remap(dev);
2881 i915_gem_init_swizzling(dev);
2883 ret = intel_init_render_ring_buffer(dev);
2888 ret = intel_init_bsd_ring_buffer(dev);
2890 goto cleanup_render_ring;
2893 if (intel_enable_blt(dev)) {
2894 ret = intel_init_blt_ring_buffer(dev);
2896 goto cleanup_bsd_ring;
2899 dev_priv->next_seqno = 1;
2902 * XXX: There was some w/a described somewhere suggesting loading
2903 * contexts before PPGTT.
2905 #if 0 /* XXX: HW context support */
2906 i915_gem_context_init(dev);
2908 i915_gem_init_ppgtt(dev);
2913 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
2914 cleanup_render_ring:
2915 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
2920 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2922 drm_i915_private_t *dev_priv;
2925 dev_priv = dev->dev_private;
2926 for (i = 0; i < I915_NUM_RINGS; i++)
2927 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
2931 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2932 struct drm_file *file_priv)
2934 drm_i915_private_t *dev_priv = dev->dev_private;
2937 if (drm_core_check_feature(dev, DRIVER_MODESET))
2940 if (atomic_read(&dev_priv->mm.wedged)) {
2941 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2942 atomic_set(&dev_priv->mm.wedged, 0);
2946 dev_priv->mm.suspended = 0;
2948 ret = i915_gem_init_hw(dev);
2954 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
2957 ret = drm_irq_install(dev);
2959 goto cleanup_ringbuffer;
2965 i915_gem_cleanup_ringbuffer(dev);
2966 dev_priv->mm.suspended = 1;
2973 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2974 struct drm_file *file_priv)
2977 if (drm_core_check_feature(dev, DRIVER_MODESET))
2980 drm_irq_uninstall(dev);
2981 return (i915_gem_idle(dev));
2985 i915_gem_lastclose(struct drm_device *dev)
2989 if (drm_core_check_feature(dev, DRIVER_MODESET))
2992 ret = i915_gem_idle(dev);
2994 DRM_ERROR("failed to idle hardware: %d\n", ret);
2998 init_ring_lists(struct intel_ring_buffer *ring)
3001 INIT_LIST_HEAD(&ring->active_list);
3002 INIT_LIST_HEAD(&ring->request_list);
3003 INIT_LIST_HEAD(&ring->gpu_write_list);
3007 i915_gem_load(struct drm_device *dev)
3010 drm_i915_private_t *dev_priv = dev->dev_private;
3012 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3013 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3014 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3015 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3016 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3017 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3018 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3019 for (i = 0; i < I915_NUM_RINGS; i++)
3020 init_ring_lists(&dev_priv->ring[i]);
3021 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3022 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3023 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3024 i915_gem_retire_work_handler);
3025 init_completion(&dev_priv->error_completion);
3027 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3029 I915_WRITE(MI_ARB_STATE,
3030 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3033 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3035 /* Old X drivers will take 0-2 for front, back, depth buffers */
3036 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3037 dev_priv->fence_reg_start = 3;
3039 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3040 dev_priv->num_fence_regs = 16;
3042 dev_priv->num_fence_regs = 8;
3044 /* Initialize fence registers to zero */
3045 i915_gem_reset_fences(dev);
3047 i915_gem_detect_bit_6_swizzle(dev);
3049 dev_priv->mm.interruptible = true;
3051 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
3052 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
3056 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3058 drm_i915_private_t *dev_priv;
3059 struct drm_i915_gem_phys_object *phys_obj;
3062 dev_priv = dev->dev_private;
3063 if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3066 phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3071 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3072 if (phys_obj->handle == NULL) {
3076 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3077 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3079 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3084 drm_free(phys_obj, DRM_I915_GEM);
3089 i915_gem_free_phys_object(struct drm_device *dev, int id)
3091 drm_i915_private_t *dev_priv;
3092 struct drm_i915_gem_phys_object *phys_obj;
3094 dev_priv = dev->dev_private;
3095 if (dev_priv->mm.phys_objs[id - 1] == NULL)
3098 phys_obj = dev_priv->mm.phys_objs[id - 1];
3099 if (phys_obj->cur_obj != NULL)
3100 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3102 drm_pci_free(dev, phys_obj->handle);
3103 drm_free(phys_obj, DRM_I915_GEM);
3104 dev_priv->mm.phys_objs[id - 1] = NULL;
3108 i915_gem_free_all_phys_object(struct drm_device *dev)
3112 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3113 i915_gem_free_phys_object(dev, i);
3117 i915_gem_detach_phys_object(struct drm_device *dev,
3118 struct drm_i915_gem_object *obj)
3125 if (obj->phys_obj == NULL)
3127 vaddr = obj->phys_obj->handle->vaddr;
3129 page_count = obj->base.size / PAGE_SIZE;
3130 VM_OBJECT_LOCK(obj->base.vm_obj);
3131 for (i = 0; i < page_count; i++) {
3132 m = i915_gem_wire_page(obj->base.vm_obj, i);
3136 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3137 sf = sf_buf_alloc(m);
3139 dst = (char *)sf_buf_kva(sf);
3140 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3143 drm_clflush_pages(&m, 1);
3145 VM_OBJECT_LOCK(obj->base.vm_obj);
3146 vm_page_reference(m);
3148 vm_page_busy_wait(m, FALSE, "i915gem");
3149 vm_page_unwire(m, 0);
3151 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3153 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3154 intel_gtt_chipset_flush();
3156 obj->phys_obj->cur_obj = NULL;
3157 obj->phys_obj = NULL;
3161 i915_gem_attach_phys_object(struct drm_device *dev,
3162 struct drm_i915_gem_object *obj,
3166 drm_i915_private_t *dev_priv;
3170 int i, page_count, ret;
3172 if (id > I915_MAX_PHYS_OBJECT)
3175 if (obj->phys_obj != NULL) {
3176 if (obj->phys_obj->id == id)
3178 i915_gem_detach_phys_object(dev, obj);
3181 dev_priv = dev->dev_private;
3182 if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3183 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3185 DRM_ERROR("failed to init phys object %d size: %zu\n",
3186 id, obj->base.size);
3191 /* bind to the object */
3192 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3193 obj->phys_obj->cur_obj = obj;
3195 page_count = obj->base.size / PAGE_SIZE;
3197 VM_OBJECT_LOCK(obj->base.vm_obj);
3199 for (i = 0; i < page_count; i++) {
3200 m = i915_gem_wire_page(obj->base.vm_obj, i);
3205 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3206 sf = sf_buf_alloc(m);
3207 src = (char *)sf_buf_kva(sf);
3208 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3209 memcpy(dst, src, PAGE_SIZE);
3212 VM_OBJECT_LOCK(obj->base.vm_obj);
3214 vm_page_reference(m);
3215 vm_page_busy_wait(m, FALSE, "i915gem");
3216 vm_page_unwire(m, 0);
3218 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3220 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3226 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3227 uint64_t data_ptr, uint64_t offset, uint64_t size,
3228 struct drm_file *file_priv)
3230 char *user_data, *vaddr;
3233 vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3234 user_data = (char *)(uintptr_t)data_ptr;
3236 if (copyin_nofault(user_data, vaddr, size) != 0) {
3237 /* The physical object once assigned is fixed for the lifetime
3238 * of the obj, so we can safely drop the lock and continue
3242 ret = -copyin(user_data, vaddr, size);
3248 intel_gtt_chipset_flush();
3253 i915_gem_release(struct drm_device *dev, struct drm_file *file)
3255 struct drm_i915_file_private *file_priv;
3256 struct drm_i915_gem_request *request;
3258 file_priv = file->driver_priv;
3260 /* Clean up our request list when the client is going away, so that
3261 * later retire_requests won't dereference our soon-to-be-gone
3264 spin_lock(&file_priv->mm.lock);
3265 while (!list_empty(&file_priv->mm.request_list)) {
3266 request = list_first_entry(&file_priv->mm.request_list,
3267 struct drm_i915_gem_request,
3269 list_del(&request->client_list);
3270 request->file_priv = NULL;
3272 spin_unlock(&file_priv->mm.lock);
3276 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
3277 uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
3278 struct drm_file *file)
3285 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
3287 if (obj->gtt_offset != 0 && rw == UIO_READ)
3288 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
3290 do_bit17_swizzling = 0;
3293 vm_obj = obj->base.vm_obj;
3296 VM_OBJECT_LOCK(vm_obj);
3297 vm_object_pip_add(vm_obj, 1);
3299 obj_pi = OFF_TO_IDX(offset);
3300 obj_po = offset & PAGE_MASK;
3302 m = i915_gem_wire_page(vm_obj, obj_pi);
3303 VM_OBJECT_UNLOCK(vm_obj);
3305 sf = sf_buf_alloc(m);
3306 mkva = sf_buf_kva(sf);
3307 length = min(size, PAGE_SIZE - obj_po);
3308 while (length > 0) {
3309 if (do_bit17_swizzling &&
3310 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
3311 cnt = roundup2(obj_po + 1, 64);
3312 cnt = min(cnt - obj_po, length);
3313 swizzled_po = obj_po ^ 64;
3316 swizzled_po = obj_po;
3319 ret = -copyout_nofault(
3320 (char *)mkva + swizzled_po,
3321 (void *)(uintptr_t)data_ptr, cnt);
3323 ret = -copyin_nofault(
3324 (void *)(uintptr_t)data_ptr,
3325 (char *)mkva + swizzled_po, cnt);
3335 VM_OBJECT_LOCK(vm_obj);
3336 if (rw == UIO_WRITE)
3338 vm_page_reference(m);
3339 vm_page_busy_wait(m, FALSE, "i915gem");
3340 vm_page_unwire(m, 1);
3342 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3347 vm_object_pip_wakeup(vm_obj);
3348 VM_OBJECT_UNLOCK(vm_obj);
3354 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
3355 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
3361 * Pass the unaligned physical address and size to pmap_mapdev_attr()
3362 * so it can properly calculate whether an extra page needs to be
3363 * mapped or not to cover the requested range. The function will
3364 * add the page offset into the returned mkva for us.
3366 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
3367 offset, size, PAT_WRITE_COMBINING);
3368 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
3369 pmap_unmapdev(mkva, size);
3374 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
3375 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
3377 struct drm_i915_gem_object *obj;
3379 vm_offset_t start, end;
3384 start = trunc_page(data_ptr);
3385 end = round_page(data_ptr + size);
3386 npages = howmany(end - start, PAGE_SIZE);
3387 ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
3389 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
3390 (vm_offset_t)data_ptr, size,
3391 (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
3397 ret = i915_mutex_lock_interruptible(dev);
3401 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
3402 if (&obj->base == NULL) {
3406 if (offset > obj->base.size || size > obj->base.size - offset) {
3411 if (rw == UIO_READ) {
3412 ret = i915_gem_object_set_cpu_read_domain_range(obj,
3416 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3419 if (obj->phys_obj) {
3420 ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
3422 } else if (obj->gtt_space &&
3423 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
3424 ret = i915_gem_object_pin(obj, 0, true);
3427 ret = i915_gem_object_set_to_gtt_domain(obj, true);
3430 ret = i915_gem_object_put_fence(obj);
3433 ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
3436 i915_gem_object_unpin(obj);
3438 ret = i915_gem_object_set_to_cpu_domain(obj, true);
3441 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3446 drm_gem_object_unreference(&obj->base);
3450 vm_page_unhold_pages(ma, npages);
3452 drm_free(ma, DRM_I915_GEM);
3457 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
3458 vm_ooffset_t foff, struct ucred *cred, u_short *color)
3461 *color = 0; /* XXXKIB */
3468 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
3471 struct drm_gem_object *gem_obj;
3472 struct drm_i915_gem_object *obj;
3473 struct drm_device *dev;
3474 drm_i915_private_t *dev_priv;
3479 gem_obj = vm_obj->handle;
3480 obj = to_intel_bo(gem_obj);
3481 dev = obj->base.dev;
3482 dev_priv = dev->dev_private;
3484 write = (prot & VM_PROT_WRITE) != 0;
3488 vm_object_pip_add(vm_obj, 1);
3491 * Remove the placeholder page inserted by vm_fault() from the
3492 * object before dropping the object lock. If
3493 * i915_gem_release_mmap() is active in parallel on this gem
3494 * object, then it owns the drm device sx and might find the
3495 * placeholder already. Then, since the page is busy,
3496 * i915_gem_release_mmap() sleeps waiting for the busy state
3497 * of the page cleared. We will be not able to acquire drm
3498 * device lock until i915_gem_release_mmap() is able to make a
3501 if (*mres != NULL) {
3503 vm_page_remove(oldm);
3508 VM_OBJECT_UNLOCK(vm_obj);
3514 ret = i915_mutex_lock_interruptible(dev);
3523 * Since the object lock was dropped, other thread might have
3524 * faulted on the same GTT address and instantiated the
3525 * mapping for the page. Recheck.
3527 VM_OBJECT_LOCK(vm_obj);
3528 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
3530 if ((m->flags & PG_BUSY) != 0) {
3533 vm_page_sleep(m, "915pee");
3539 VM_OBJECT_UNLOCK(vm_obj);
3541 /* Now bind it into the GTT if needed */
3542 if (!obj->map_and_fenceable) {
3543 ret = i915_gem_object_unbind(obj);
3549 if (!obj->gtt_space) {
3550 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
3556 ret = i915_gem_object_set_to_gtt_domain(obj, write);
3563 if (obj->tiling_mode == I915_TILING_NONE)
3564 ret = i915_gem_object_put_fence(obj);
3566 ret = i915_gem_object_get_fence(obj, NULL);
3572 if (i915_gem_object_is_inactive(obj))
3573 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3575 obj->fault_mappable = true;
3576 VM_OBJECT_LOCK(vm_obj);
3577 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
3584 KASSERT((m->flags & PG_FICTITIOUS) != 0,
3585 ("not fictitious %p", m));
3586 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
3588 if ((m->flags & PG_BUSY) != 0) {
3591 vm_page_sleep(m, "915pbs");
3595 m->valid = VM_PAGE_BITS_ALL;
3596 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
3599 vm_page_busy_try(m, false);
3605 vm_object_pip_wakeup(vm_obj);
3606 return (VM_PAGER_OK);
3611 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
3612 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
3613 goto unlocked_vmobj;
3615 VM_OBJECT_LOCK(vm_obj);
3616 vm_object_pip_wakeup(vm_obj);
3617 return (VM_PAGER_ERROR);
3621 i915_gem_pager_dtor(void *handle)
3623 struct drm_gem_object *obj;
3624 struct drm_device *dev;
3630 drm_gem_free_mmap_offset(obj);
3631 i915_gem_release_mmap(to_intel_bo(obj));
3632 drm_gem_object_unreference(obj);
3636 struct cdev_pager_ops i915_gem_pager_ops = {
3637 .cdev_pg_fault = i915_gem_pager_fault,
3638 .cdev_pg_ctor = i915_gem_pager_ctor,
3639 .cdev_pg_dtor = i915_gem_pager_dtor
3643 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3644 uint64_t offset, uint64_t size)
3646 uint32_t old_read_domains;
3649 if (offset == 0 && size == obj->base.size)
3650 return (i915_gem_object_set_to_cpu_domain(obj, 0));
3652 ret = i915_gem_object_flush_gpu_write_domain(obj);
3655 ret = i915_gem_object_wait_rendering(obj);
3659 i915_gem_object_flush_gtt_write_domain(obj);
3661 if (obj->page_cpu_valid == NULL &&
3662 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3665 if (obj->page_cpu_valid == NULL) {
3666 obj->page_cpu_valid = kmalloc(obj->base.size / PAGE_SIZE,
3667 DRM_I915_GEM, M_WAITOK | M_ZERO);
3668 } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3669 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3671 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3673 if (obj->page_cpu_valid[i])
3675 drm_clflush_pages(obj->pages + i, 1);
3676 obj->page_cpu_valid[i] = 1;
3679 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
3680 ("In gpu write domain"));
3682 old_read_domains = obj->base.read_domains;
3683 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3688 #define GEM_PARANOID_CHECK_GTT 0
3689 #if GEM_PARANOID_CHECK_GTT
3691 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
3694 struct drm_i915_private *dev_priv;
3696 unsigned long start, end;
3700 dev_priv = dev->dev_private;
3701 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
3702 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
3703 for (i = start; i < end; i++) {
3704 pa = intel_gtt_read_pte_paddr(i);
3705 for (j = 0; j < page_count; j++) {
3706 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
3707 panic("Page %p in GTT pte index %d pte %x",
3708 ma[i], i, intel_gtt_read_pte(i));
3716 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
3717 uint32_t flush_domains)
3719 struct drm_i915_gem_object *obj, *next;
3720 uint32_t old_write_domain;
3722 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
3724 if (obj->base.write_domain & flush_domains) {
3725 old_write_domain = obj->base.write_domain;
3726 obj->base.write_domain = 0;
3727 list_del_init(&obj->gpu_write_list);
3728 i915_gem_object_move_to_active(obj, ring,
3729 i915_gem_next_request_seqno(ring));
3734 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
3737 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
3742 VM_OBJECT_LOCK_ASSERT_OWNED(object);
3743 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
3744 if (m->valid != VM_PAGE_BITS_ALL) {
3745 if (vm_pager_has_page(object, pindex)) {
3746 rv = vm_pager_get_page(object, &m, 1);
3747 m = vm_page_lookup(object, pindex);
3750 if (rv != VM_PAGER_OK) {
3755 pmap_zero_page(VM_PAGE_TO_PHYS(m));
3756 m->valid = VM_PAGE_BITS_ALL;
3762 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
3767 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
3768 uint32_t flush_domains)
3772 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
3775 ret = ring->flush(ring, invalidate_domains, flush_domains);
3779 if (flush_domains & I915_GEM_GPU_DOMAINS)
3780 i915_gem_process_flushing_list(ring, flush_domains);
3785 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
3787 if (ring->outstanding_lazy_request == 0)
3788 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
3790 return ring->outstanding_lazy_request;
3794 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3796 drm_i915_private_t *dev_priv = dev->dev_private;
3797 uint32_t fence_reg = reg - dev_priv->fence_regs;
3799 switch (INTEL_INFO(dev)->gen) {
3802 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3806 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3810 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3813 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3815 I915_WRITE(fence_reg, 0);
3819 list_del_init(®->lru_list);
3821 reg->setup_seqno = 0;
3826 i915_gpu_is_active(struct drm_device *dev)
3828 drm_i915_private_t *dev_priv;
3830 dev_priv = dev->dev_private;
3831 return (!list_empty(&dev_priv->mm.flushing_list) ||
3832 !list_empty(&dev_priv->mm.active_list));
3836 i915_gem_lowmem(void *arg)
3838 struct drm_device *dev;
3839 struct drm_i915_private *dev_priv;
3840 struct drm_i915_gem_object *obj, *next;
3841 int cnt, cnt_fail, cnt_total;
3844 dev_priv = dev->dev_private;
3846 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3850 /* first scan for clean buffers */
3851 i915_gem_retire_requests(dev);
3853 cnt_total = cnt_fail = cnt = 0;
3855 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3857 if (i915_gem_object_is_purgeable(obj)) {
3858 if (i915_gem_object_unbind(obj) != 0)
3864 /* second pass, evict/count anything still on the inactive list */
3865 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3867 if (i915_gem_object_unbind(obj) == 0)
3873 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3875 * We are desperate for pages, so as a last resort, wait
3876 * for the GPU to finish and discard whatever we can.
3877 * This has a dramatic impact to reduce the number of
3878 * OOM-killer events whilst running the GPU aggressively.
3880 if (i915_gpu_idle(dev) == 0)
3887 i915_gem_unload(struct drm_device *dev)
3889 struct drm_i915_private *dev_priv;
3891 dev_priv = dev->dev_private;
3892 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);