2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/rv770.c 254885 2013-08-25 19:37:15Z dumbbell $
33 #include "radeon_asic.h"
34 #include <uapi_drm/radeon_drm.h>
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
42 static void rv770_gpu_init(struct radeon_device *rdev);
43 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45 #define PCIE_BUS_CLK 10000
46 #define TCLK (PCIE_BUS_CLK / 10)
49 * rv770_get_xclk - get the xclk
51 * @rdev: radeon_device pointer
53 * Returns the reference clock used by the gfx engine
56 u32 rv770_get_xclk(struct radeon_device *rdev)
58 u32 reference_clock = rdev->clock.spll.reference_freq;
59 u32 tmp = RREG32(CG_CLKPIN_CNTL);
61 if (tmp & MUX_TCLK_TO_XCLK)
64 if (tmp & XTALIN_DIVIDE)
65 return reference_clock / 4;
67 return reference_clock;
70 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
72 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
73 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
76 /* Lock the graphics update lock */
77 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
78 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
80 /* update the scanout addresses */
81 if (radeon_crtc->crtc_id) {
82 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
83 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
85 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
86 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
88 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
90 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
93 /* Wait for update_pending to go high. */
94 for (i = 0; i < rdev->usec_timeout; i++) {
95 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
99 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
101 /* Unlock the lock, so double-buffering can take place inside vblank */
102 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
103 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
105 /* Return current update_pending status: */
106 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
109 /* get temperature in millidegrees */
110 int rv770_get_temp(struct radeon_device *rdev)
112 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
118 else if (temp & 0x200)
120 else if (temp & 0x100) {
121 actual_temp = temp & 0x1ff;
122 actual_temp |= ~0x1ff;
124 actual_temp = temp & 0xff;
126 return (actual_temp * 1000) / 2;
129 void rv770_pm_misc(struct radeon_device *rdev)
131 int req_ps_idx = rdev->pm.requested_power_state_index;
132 int req_cm_idx = rdev->pm.requested_clock_mode_index;
133 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
134 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
136 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
137 /* 0xff01 is a flag rather then an actual voltage */
138 if (voltage->voltage == 0xff01)
140 if (voltage->voltage != rdev->pm.current_vddc) {
141 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
142 rdev->pm.current_vddc = voltage->voltage;
143 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
151 static int rv770_pcie_gart_enable(struct radeon_device *rdev)
156 if (rdev->gart.robj == NULL) {
157 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
160 r = radeon_gart_table_vram_pin(rdev);
163 radeon_gart_restore(rdev);
165 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
166 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
167 EFFECTIVE_L2_QUEUE_SIZE(7));
168 WREG32(VM_L2_CNTL2, 0);
169 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
170 /* Setup TLB control */
171 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
172 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
173 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
174 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
175 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
176 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
177 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
178 if (rdev->family == CHIP_RV740)
179 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
180 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
181 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
182 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
183 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
184 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
185 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
186 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
187 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
188 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
189 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
190 (u32)(rdev->dummy_page.addr >> 12));
191 for (i = 1; i < 7; i++)
192 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
194 r600_pcie_gart_tlb_flush(rdev);
195 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
196 (unsigned)(rdev->mc.gtt_size >> 20),
197 (unsigned long long)rdev->gart.table_addr);
198 rdev->gart.ready = true;
202 static void rv770_pcie_gart_disable(struct radeon_device *rdev)
207 /* Disable all tables */
208 for (i = 0; i < 7; i++)
209 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
212 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
213 EFFECTIVE_L2_QUEUE_SIZE(7));
214 WREG32(VM_L2_CNTL2, 0);
215 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
216 /* Setup TLB control */
217 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
218 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
219 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
220 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
221 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
222 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
223 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
224 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
225 radeon_gart_table_vram_unpin(rdev);
228 static void rv770_pcie_gart_fini(struct radeon_device *rdev)
230 radeon_gart_fini(rdev);
231 rv770_pcie_gart_disable(rdev);
232 radeon_gart_table_vram_free(rdev);
236 static void rv770_agp_enable(struct radeon_device *rdev)
242 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
243 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
244 EFFECTIVE_L2_QUEUE_SIZE(7));
245 WREG32(VM_L2_CNTL2, 0);
246 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
247 /* Setup TLB control */
248 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
249 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
250 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
251 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
252 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
253 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
254 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
255 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
256 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
257 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
258 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
259 for (i = 0; i < 7; i++)
260 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
263 static void rv770_mc_program(struct radeon_device *rdev)
265 struct rv515_mc_save save;
270 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
271 WREG32((0x2c14 + j), 0x00000000);
272 WREG32((0x2c18 + j), 0x00000000);
273 WREG32((0x2c1c + j), 0x00000000);
274 WREG32((0x2c20 + j), 0x00000000);
275 WREG32((0x2c24 + j), 0x00000000);
277 /* r7xx hw bug. Read from HDP_DEBUG1 rather
278 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
280 tmp = RREG32(HDP_DEBUG1);
282 rv515_mc_stop(rdev, &save);
283 if (r600_mc_wait_for_idle(rdev)) {
284 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
286 /* Lockout access through VGA aperture*/
287 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
288 /* Update configuration */
289 if (rdev->flags & RADEON_IS_AGP) {
290 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
291 /* VRAM before AGP */
292 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
293 rdev->mc.vram_start >> 12);
294 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
295 rdev->mc.gtt_end >> 12);
298 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
299 rdev->mc.gtt_start >> 12);
300 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
301 rdev->mc.vram_end >> 12);
304 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
305 rdev->mc.vram_start >> 12);
306 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
307 rdev->mc.vram_end >> 12);
309 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
310 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
311 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
312 WREG32(MC_VM_FB_LOCATION, tmp);
313 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
314 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
315 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
316 if (rdev->flags & RADEON_IS_AGP) {
317 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
318 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
319 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
321 WREG32(MC_VM_AGP_BASE, 0);
322 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
323 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
325 if (r600_mc_wait_for_idle(rdev)) {
326 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
328 rv515_mc_resume(rdev, &save);
329 /* we need to own VRAM, so turn off the VGA renderer here
330 * to stop it overwriting our objects */
331 rv515_vga_render_disable(rdev);
338 void r700_cp_stop(struct radeon_device *rdev)
340 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
341 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
342 WREG32(SCRATCH_UMSK, 0);
343 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
346 static int rv770_cp_load_microcode(struct radeon_device *rdev)
348 const __be32 *fw_data;
351 if (!rdev->me_fw || !rdev->pfp_fw)
359 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
362 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
363 RREG32(GRBM_SOFT_RESET);
365 WREG32(GRBM_SOFT_RESET, 0);
367 fw_data = (const __be32 *)rdev->pfp_fw->data;
368 WREG32(CP_PFP_UCODE_ADDR, 0);
369 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
370 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
371 WREG32(CP_PFP_UCODE_ADDR, 0);
373 fw_data = (const __be32 *)rdev->me_fw->data;
374 WREG32(CP_ME_RAM_WADDR, 0);
375 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
376 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
378 WREG32(CP_PFP_UCODE_ADDR, 0);
379 WREG32(CP_ME_RAM_WADDR, 0);
380 WREG32(CP_ME_RAM_RADDR, 0);
384 void r700_cp_fini(struct radeon_device *rdev)
386 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
388 radeon_ring_fini(rdev, ring);
389 radeon_scratch_free(rdev, ring->rptr_save_reg);
395 static void rv770_gpu_init(struct radeon_device *rdev)
397 int i, j, num_qd_pipes;
402 u32 num_gs_verts_per_thread;
404 u32 gs_prim_buffer_depth = 0;
405 u32 sq_ms_fifo_sizes;
407 u32 sq_thread_resource_mgmt;
408 u32 hdp_host_path_cntl;
409 u32 sq_dyn_gpr_size_simd_ab_0;
410 u32 gb_tiling_config = 0;
411 u32 cc_rb_backend_disable = 0;
412 u32 cc_gc_shader_pipe_config = 0;
415 u32 inactive_pipes, shader_pipe_config;
416 u32 disabled_rb_mask;
417 unsigned active_number;
419 /* setup chip specs */
420 rdev->config.rv770.tiling_group_size = 256;
421 switch (rdev->family) {
423 rdev->config.rv770.max_pipes = 4;
424 rdev->config.rv770.max_tile_pipes = 8;
425 rdev->config.rv770.max_simds = 10;
426 rdev->config.rv770.max_backends = 4;
427 rdev->config.rv770.max_gprs = 256;
428 rdev->config.rv770.max_threads = 248;
429 rdev->config.rv770.max_stack_entries = 512;
430 rdev->config.rv770.max_hw_contexts = 8;
431 rdev->config.rv770.max_gs_threads = 16 * 2;
432 rdev->config.rv770.sx_max_export_size = 128;
433 rdev->config.rv770.sx_max_export_pos_size = 16;
434 rdev->config.rv770.sx_max_export_smx_size = 112;
435 rdev->config.rv770.sq_num_cf_insts = 2;
437 rdev->config.rv770.sx_num_of_sets = 7;
438 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
439 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
440 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
443 rdev->config.rv770.max_pipes = 2;
444 rdev->config.rv770.max_tile_pipes = 4;
445 rdev->config.rv770.max_simds = 8;
446 rdev->config.rv770.max_backends = 2;
447 rdev->config.rv770.max_gprs = 128;
448 rdev->config.rv770.max_threads = 248;
449 rdev->config.rv770.max_stack_entries = 256;
450 rdev->config.rv770.max_hw_contexts = 8;
451 rdev->config.rv770.max_gs_threads = 16 * 2;
452 rdev->config.rv770.sx_max_export_size = 256;
453 rdev->config.rv770.sx_max_export_pos_size = 32;
454 rdev->config.rv770.sx_max_export_smx_size = 224;
455 rdev->config.rv770.sq_num_cf_insts = 2;
457 rdev->config.rv770.sx_num_of_sets = 7;
458 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
459 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
460 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
461 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
462 rdev->config.rv770.sx_max_export_pos_size -= 16;
463 rdev->config.rv770.sx_max_export_smx_size += 16;
467 rdev->config.rv770.max_pipes = 2;
468 rdev->config.rv770.max_tile_pipes = 2;
469 rdev->config.rv770.max_simds = 2;
470 rdev->config.rv770.max_backends = 1;
471 rdev->config.rv770.max_gprs = 256;
472 rdev->config.rv770.max_threads = 192;
473 rdev->config.rv770.max_stack_entries = 256;
474 rdev->config.rv770.max_hw_contexts = 4;
475 rdev->config.rv770.max_gs_threads = 8 * 2;
476 rdev->config.rv770.sx_max_export_size = 128;
477 rdev->config.rv770.sx_max_export_pos_size = 16;
478 rdev->config.rv770.sx_max_export_smx_size = 112;
479 rdev->config.rv770.sq_num_cf_insts = 1;
481 rdev->config.rv770.sx_num_of_sets = 7;
482 rdev->config.rv770.sc_prim_fifo_size = 0x40;
483 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
484 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
487 rdev->config.rv770.max_pipes = 4;
488 rdev->config.rv770.max_tile_pipes = 4;
489 rdev->config.rv770.max_simds = 8;
490 rdev->config.rv770.max_backends = 4;
491 rdev->config.rv770.max_gprs = 256;
492 rdev->config.rv770.max_threads = 248;
493 rdev->config.rv770.max_stack_entries = 512;
494 rdev->config.rv770.max_hw_contexts = 8;
495 rdev->config.rv770.max_gs_threads = 16 * 2;
496 rdev->config.rv770.sx_max_export_size = 256;
497 rdev->config.rv770.sx_max_export_pos_size = 32;
498 rdev->config.rv770.sx_max_export_smx_size = 224;
499 rdev->config.rv770.sq_num_cf_insts = 2;
501 rdev->config.rv770.sx_num_of_sets = 7;
502 rdev->config.rv770.sc_prim_fifo_size = 0x100;
503 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
504 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
506 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
507 rdev->config.rv770.sx_max_export_pos_size -= 16;
508 rdev->config.rv770.sx_max_export_smx_size += 16;
517 for (i = 0; i < 32; i++) {
518 WREG32((0x2c14 + j), 0x00000000);
519 WREG32((0x2c18 + j), 0x00000000);
520 WREG32((0x2c1c + j), 0x00000000);
521 WREG32((0x2c20 + j), 0x00000000);
522 WREG32((0x2c24 + j), 0x00000000);
526 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
528 /* setup tiling, simd, pipe config */
529 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
531 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
532 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
533 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
534 if (!(inactive_pipes & tmp)) {
539 if (active_number == 1) {
540 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
542 WREG32(SPI_CONFIG_CNTL, 0);
545 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
546 tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
547 if (tmp < rdev->config.rv770.max_backends) {
548 rdev->config.rv770.max_backends = tmp;
551 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
552 tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
553 if (tmp < rdev->config.rv770.max_pipes) {
554 rdev->config.rv770.max_pipes = tmp;
556 tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
557 if (tmp < rdev->config.rv770.max_simds) {
558 rdev->config.rv770.max_simds = tmp;
561 switch (rdev->config.rv770.max_tile_pipes) {
564 gb_tiling_config = PIPE_TILING(0);
567 gb_tiling_config = PIPE_TILING(1);
570 gb_tiling_config = PIPE_TILING(2);
573 gb_tiling_config = PIPE_TILING(3);
576 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
578 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
579 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
580 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
581 R7XX_MAX_BACKENDS, disabled_rb_mask);
582 gb_tiling_config |= tmp << 16;
583 rdev->config.rv770.backend_map = tmp;
585 if (rdev->family == CHIP_RV770)
586 gb_tiling_config |= BANK_TILING(1);
588 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
589 gb_tiling_config |= BANK_TILING(1);
591 gb_tiling_config |= BANK_TILING(0);
593 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
594 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
595 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
596 gb_tiling_config |= ROW_TILING(3);
597 gb_tiling_config |= SAMPLE_SPLIT(3);
600 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
602 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
605 gb_tiling_config |= BANK_SWAPS(1);
606 rdev->config.rv770.tile_config = gb_tiling_config;
608 WREG32(GB_TILING_CONFIG, gb_tiling_config);
609 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
610 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
611 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
612 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
614 WREG32(CGTS_SYS_TCC_DISABLE, 0);
615 WREG32(CGTS_TCC_DISABLE, 0);
616 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
617 WREG32(CGTS_USER_TCC_DISABLE, 0);
620 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
621 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
622 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
624 /* set HW defaults for 3D engine */
625 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
626 ROQ_IB2_START(0x2b)));
628 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
630 ta_aux_cntl = RREG32(TA_CNTL_AUX);
631 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
633 sx_debug_1 = RREG32(SX_DEBUG_1);
634 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
635 WREG32(SX_DEBUG_1, sx_debug_1);
637 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
638 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
639 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
640 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
642 if (rdev->family != CHIP_RV740)
643 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
648 if (rdev->family != CHIP_RV770)
649 WREG32(SMX_SAR_CTL0, 0x00003f3f);
651 db_debug3 = RREG32(DB_DEBUG3);
652 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
653 switch (rdev->family) {
656 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
661 db_debug3 |= DB_CLK_OFF_DELAY(2);
664 WREG32(DB_DEBUG3, db_debug3);
666 if (rdev->family != CHIP_RV770) {
667 db_debug4 = RREG32(DB_DEBUG4);
668 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
669 WREG32(DB_DEBUG4, db_debug4);
672 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
673 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
674 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
676 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
677 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
678 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
680 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
682 WREG32(VGT_NUM_INSTANCES, 1);
684 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
686 WREG32(CP_PERFMON_CNTL, 0);
688 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
689 DONE_FIFO_HIWATER(0xe0) |
690 ALU_UPDATE_FIFO_HIWATER(0x8));
691 switch (rdev->family) {
695 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
699 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
702 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
704 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
705 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
707 sq_config = RREG32(SQ_CONFIG);
708 sq_config &= ~(PS_PRIO(3) |
712 sq_config |= (DX9_CONSTS |
719 if (rdev->family == CHIP_RV710)
720 /* no vertex cache */
721 sq_config &= ~VC_ENABLE;
723 WREG32(SQ_CONFIG, sq_config);
725 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
726 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
727 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
729 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
730 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
732 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
733 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
734 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
735 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
736 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
738 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
739 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
741 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
742 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
744 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
745 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
747 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
748 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
749 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
750 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
752 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
753 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
754 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
755 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
756 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
757 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
758 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
759 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
761 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
762 FORCE_EOV_MAX_REZ_CNT(255)));
764 if (rdev->family == CHIP_RV710)
765 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
766 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
768 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
769 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
771 switch (rdev->family) {
775 gs_prim_buffer_depth = 384;
778 gs_prim_buffer_depth = 128;
784 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
785 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
786 /* Max value for this is 256 */
787 if (vgt_gs_per_es > 256)
790 WREG32(VGT_ES_PER_GS, 128);
791 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
792 WREG32(VGT_GS_PER_VS, 2);
794 /* more default values. 2D/3D driver should adjust as needed */
795 WREG32(VGT_GS_VERTEX_REUSE, 16);
796 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
797 WREG32(VGT_STRMOUT_EN, 0);
799 WREG32(PA_SC_MODE_CNTL, 0);
800 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
801 WREG32(PA_SC_AA_CONFIG, 0);
802 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
803 WREG32(PA_SC_LINE_STIPPLE, 0);
804 WREG32(SPI_INPUT_Z, 0);
805 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
806 WREG32(CB_COLOR7_FRAG, 0);
808 /* clear render buffer base addresses */
809 WREG32(CB_COLOR0_BASE, 0);
810 WREG32(CB_COLOR1_BASE, 0);
811 WREG32(CB_COLOR2_BASE, 0);
812 WREG32(CB_COLOR3_BASE, 0);
813 WREG32(CB_COLOR4_BASE, 0);
814 WREG32(CB_COLOR5_BASE, 0);
815 WREG32(CB_COLOR6_BASE, 0);
816 WREG32(CB_COLOR7_BASE, 0);
820 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
821 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
823 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
825 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
827 WREG32(VC_ENHANCE, 0);
830 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
832 u64 size_bf, size_af;
834 if (mc->mc_vram_size > 0xE0000000) {
835 /* leave room for at least 512M GTT */
836 dev_warn(rdev->dev, "limiting VRAM\n");
837 mc->real_vram_size = 0xE0000000;
838 mc->mc_vram_size = 0xE0000000;
840 if (rdev->flags & RADEON_IS_AGP) {
841 size_bf = mc->gtt_start;
842 size_af = 0xFFFFFFFF - mc->gtt_end;
843 if (size_bf > size_af) {
844 if (mc->mc_vram_size > size_bf) {
845 dev_warn(rdev->dev, "limiting VRAM\n");
846 mc->real_vram_size = size_bf;
847 mc->mc_vram_size = size_bf;
849 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
851 if (mc->mc_vram_size > size_af) {
852 dev_warn(rdev->dev, "limiting VRAM\n");
853 mc->real_vram_size = size_af;
854 mc->mc_vram_size = size_af;
856 mc->vram_start = mc->gtt_end + 1;
858 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
859 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n",
860 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
861 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
863 radeon_vram_location(rdev, &rdev->mc, 0);
864 rdev->mc.gtt_base_align = 0;
865 radeon_gtt_location(rdev, mc);
869 static int rv770_mc_init(struct radeon_device *rdev)
872 int chansize, numchan;
874 /* Get VRAM informations */
875 rdev->mc.vram_is_ddr = true;
876 tmp = RREG32(MC_ARB_RAMCFG);
877 if (tmp & CHANSIZE_OVERRIDE) {
879 } else if (tmp & CHANSIZE_MASK) {
884 tmp = RREG32(MC_SHARED_CHMAP);
885 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
900 rdev->mc.vram_width = numchan * chansize;
901 /* Could aper size report 0 ? */
902 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
903 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
904 /* Setup GPU memory space */
905 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
906 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
907 rdev->mc.visible_vram_size = rdev->mc.aper_size;
908 r700_vram_gtt_location(rdev, &rdev->mc);
909 radeon_update_bandwidth_info(rdev);
915 * rv770_copy_dma - copy pages using the DMA engine
917 * @rdev: radeon_device pointer
918 * @src_offset: src GPU address
919 * @dst_offset: dst GPU address
920 * @num_gpu_pages: number of GPU pages to xfer
921 * @fence: radeon fence object
923 * Copy GPU paging using the DMA engine (r7xx).
924 * Used by the radeon ttm implementation to move pages if
925 * registered as the asic copy callback.
927 int rv770_copy_dma(struct radeon_device *rdev,
928 uint64_t src_offset, uint64_t dst_offset,
929 unsigned num_gpu_pages,
930 struct radeon_fence **fence)
932 struct radeon_semaphore *sem = NULL;
933 int ring_index = rdev->asic->copy.dma_ring_index;
934 struct radeon_ring *ring = &rdev->ring[ring_index];
935 u32 size_in_dw, cur_size_in_dw;
939 r = radeon_semaphore_create(rdev, &sem);
941 DRM_ERROR("radeon: moving bo (%d).\n", r);
945 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
946 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
947 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
949 DRM_ERROR("radeon: moving bo (%d).\n", r);
950 radeon_semaphore_free(rdev, &sem, NULL);
954 if (radeon_fence_need_sync(*fence, ring->idx)) {
955 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
957 radeon_fence_note_sync(*fence, ring->idx);
959 radeon_semaphore_free(rdev, &sem, NULL);
962 for (i = 0; i < num_loops; i++) {
963 cur_size_in_dw = size_in_dw;
964 if (cur_size_in_dw > 0xFFFF)
965 cur_size_in_dw = 0xFFFF;
966 size_in_dw -= cur_size_in_dw;
967 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
968 radeon_ring_write(ring, dst_offset & 0xfffffffc);
969 radeon_ring_write(ring, src_offset & 0xfffffffc);
970 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
971 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
972 src_offset += cur_size_in_dw * 4;
973 dst_offset += cur_size_in_dw * 4;
976 r = radeon_fence_emit(rdev, fence, ring->idx);
978 radeon_ring_unlock_undo(rdev, ring);
982 radeon_ring_unlock_commit(rdev, ring);
983 radeon_semaphore_free(rdev, &sem, *fence);
988 static int rv770_startup(struct radeon_device *rdev)
990 struct radeon_ring *ring;
993 /* enable pcie gen2 link */
994 rv770_pcie_gen2_enable(rdev);
996 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
997 r = r600_init_microcode(rdev);
999 DRM_ERROR("Failed to load firmware!\n");
1004 r = r600_vram_scratch_init(rdev);
1008 rv770_mc_program(rdev);
1009 if (rdev->flags & RADEON_IS_AGP) {
1010 rv770_agp_enable(rdev);
1012 r = rv770_pcie_gart_enable(rdev);
1017 rv770_gpu_init(rdev);
1018 r = r600_blit_init(rdev);
1020 r600_blit_fini(rdev);
1021 rdev->asic->copy.copy = NULL;
1022 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1025 /* allocate wb buffer */
1026 r = radeon_wb_init(rdev);
1030 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1032 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1036 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1038 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1043 r = r600_irq_init(rdev);
1045 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1046 radeon_irq_kms_fini(rdev);
1051 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1052 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1053 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
1054 0, 0xfffff, RADEON_CP_PACKET2);
1058 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1059 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1060 DMA_RB_RPTR, DMA_RB_WPTR,
1061 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1065 r = rv770_cp_load_microcode(rdev);
1068 r = r600_cp_resume(rdev);
1072 r = r600_dma_resume(rdev);
1076 r = radeon_ib_pool_init(rdev);
1078 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1082 r = r600_audio_init(rdev);
1084 DRM_ERROR("radeon: audio init failed\n");
1091 int rv770_resume(struct radeon_device *rdev)
1095 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1096 * posting will perform necessary task to bring back GPU into good
1100 atom_asic_init(rdev->mode_info.atom_context);
1102 rdev->accel_working = true;
1103 r = rv770_startup(rdev);
1105 DRM_ERROR("r600 startup failed on resume\n");
1106 rdev->accel_working = false;
1114 int rv770_suspend(struct radeon_device *rdev)
1116 r600_audio_fini(rdev);
1118 r600_dma_stop(rdev);
1119 r600_irq_suspend(rdev);
1120 radeon_wb_disable(rdev);
1121 rv770_pcie_gart_disable(rdev);
1126 /* Plan is to move initialization in that function and use
1127 * helper function so that radeon_device_init pretty much
1128 * do nothing more than calling asic specific function. This
1129 * should also allow to remove a bunch of callback function
1132 int rv770_init(struct radeon_device *rdev)
1137 if (!radeon_get_bios(rdev)) {
1138 if (ASIC_IS_AVIVO(rdev))
1141 /* Must be an ATOMBIOS */
1142 if (!rdev->is_atom_bios) {
1143 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1146 r = radeon_atombios_init(rdev);
1149 /* Post card if necessary */
1150 if (!radeon_card_posted(rdev)) {
1152 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1155 DRM_INFO("GPU not posted. posting now...\n");
1156 atom_asic_init(rdev->mode_info.atom_context);
1158 /* Initialize scratch registers */
1159 r600_scratch_init(rdev);
1160 /* Initialize surface registers */
1161 radeon_surface_init(rdev);
1162 /* Initialize clocks */
1163 radeon_get_clock_info(rdev->ddev);
1165 r = radeon_fence_driver_init(rdev);
1168 /* initialize AGP */
1169 if (rdev->flags & RADEON_IS_AGP) {
1170 r = radeon_agp_init(rdev);
1172 radeon_agp_disable(rdev);
1174 r = rv770_mc_init(rdev);
1177 /* Memory manager */
1178 r = radeon_bo_init(rdev);
1182 r = radeon_irq_kms_init(rdev);
1186 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1187 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1189 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1190 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1192 rdev->ih.ring_obj = NULL;
1193 r600_ih_ring_init(rdev, 64 * 1024);
1195 r = r600_pcie_gart_init(rdev);
1199 rdev->accel_working = true;
1200 r = rv770_startup(rdev);
1202 dev_err(rdev->dev, "disabling GPU acceleration\n");
1204 r600_dma_fini(rdev);
1205 r600_irq_fini(rdev);
1206 radeon_wb_fini(rdev);
1207 radeon_ib_pool_fini(rdev);
1208 radeon_irq_kms_fini(rdev);
1209 rv770_pcie_gart_fini(rdev);
1210 rdev->accel_working = false;
1216 void rv770_fini(struct radeon_device *rdev)
1218 r600_blit_fini(rdev);
1220 r600_dma_fini(rdev);
1221 r600_irq_fini(rdev);
1222 radeon_wb_fini(rdev);
1223 radeon_ib_pool_fini(rdev);
1224 radeon_irq_kms_fini(rdev);
1225 rv770_pcie_gart_fini(rdev);
1226 r600_vram_scratch_fini(rdev);
1227 radeon_gem_fini(rdev);
1228 radeon_fence_driver_fini(rdev);
1229 radeon_agp_fini(rdev);
1230 radeon_bo_fini(rdev);
1231 radeon_atombios_fini(rdev);
1232 r600_fini_microcode(rdev);
1233 drm_free(rdev->bios, M_DRM);
1237 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1239 u32 link_width_cntl, lanes, speed_cntl, tmp;
1244 if (radeon_pcie_gen2 == 0)
1247 if (rdev->flags & RADEON_IS_IGP)
1250 if (!(rdev->flags & RADEON_IS_PCIE))
1253 /* x2 cards have a special sequence */
1254 if (ASIC_IS_X2(rdev))
1257 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
1261 if (!(mask & DRM_PCIE_SPEED_50))
1264 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
1266 /* advertise upconfig capability */
1267 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1268 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1269 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1270 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1271 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1272 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1273 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1274 LC_RECONFIG_ARC_MISSING_ESCAPE);
1275 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1276 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1277 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1279 link_width_cntl |= LC_UPCONFIGURE_DIS;
1280 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1283 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1284 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1285 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1287 tmp = RREG32(0x541c);
1288 WREG32(0x541c, tmp | 0x8);
1289 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1290 link_cntl2 = RREG16(0x4088);
1291 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1293 WREG16(0x4088, link_cntl2);
1294 WREG32(MM_CFGREGS_CNTL, 0);
1296 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1297 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1298 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1300 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1301 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1302 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1304 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1305 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1306 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1308 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1309 speed_cntl |= LC_GEN2_EN_STRAP;
1310 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1313 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1314 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1316 link_width_cntl |= LC_UPCONFIGURE_DIS;
1318 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1319 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);