2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
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32 * $FreeBSD: src/sys/dev/rp/rpreg.h,v 1.4.2.1 2002/06/18 03:11:46 obrien Exp $
36 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD
39 typedef unsigned char Byte_t;
40 typedef unsigned int ByteIO_t;
42 typedef unsigned int Word_t;
43 typedef unsigned int WordIO_t;
45 typedef unsigned long DWord_t;
46 typedef unsigned int DWordIO_t;
48 #define rp_readio(size, ctlp, rid, offset) \
49 (bus_space_read_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset))
50 #define rp_readmultiio(size, ctlp, rid, offset, addr, count) \
51 (bus_space_read_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count))
52 #define rp_writeio(size, ctlp, rid, offset, data) \
53 (bus_space_write_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, data))
54 #define rp_writemultiio(size, ctlp, rid, offset, addr, count) \
55 (bus_space_write_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count))
57 #define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset)
58 #define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset)
59 #define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset)
60 #define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data)
61 #define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data)
62 #define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data)
63 #define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count)
64 #define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count)
65 #define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count)
66 #define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count)
67 #define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count)
68 #define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count)
70 #define rp_readaiop1(ctlp, aiop, offset) \
71 (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
72 #define rp_readaiop2(ctlp, aiop, offset) \
73 (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
74 #define rp_readaiop4(ctlp, aiop, offset) \
75 (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
76 #define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \
77 (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
78 #define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \
79 (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
80 #define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \
81 (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
82 #define rp_writeaiop1(ctlp, aiop, offset, data) \
83 (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
84 #define rp_writeaiop2(ctlp, aiop, offset, data) \
85 (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
86 #define rp_writeaiop4(ctlp, aiop, offset, data) \
87 (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
88 #define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \
89 (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
90 #define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \
91 (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
92 #define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \
93 (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
95 #define rp_readch1(chp, offset) \
96 (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset))
97 #define rp_readch2(chp, offset) \
98 (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset))
99 #define rp_readch4(chp, offset) \
100 (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset))
101 #define rp_readmultich1(chp, offset, addr, count) \
102 (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
103 #define rp_readmultich2(chp, offset, addr, count) \
104 (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
105 #define rp_readmultich4(chp, offset, addr, count) \
106 (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
107 #define rp_writech1(chp, offset, data) \
108 (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data))
109 #define rp_writech2(chp, offset, data) \
110 (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data))
111 #define rp_writech4(chp, offset, data) \
112 (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data))
113 #define rp_writemultich1(chp, offset, addr, count) \
114 (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
115 #define rp_writemultich2(chp, offset, addr, count) \
116 (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
117 #define rp_writemultich4(chp, offset, addr, count) \
118 (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
121 * End of OS-specific defines
127 #define AIOP_CTL_SIZE 4
128 #define CHAN_AIOP_SIZE 8
129 #define MAX_PORTS_PER_AIOP 8
130 #define MAX_AIOPS_PER_BOARD 4
131 #define MAX_PORTS_PER_BOARD 32
133 /* Controller ID numbers */
134 #define CTLID_NULL -1 /* no controller exists */
135 #define CTLID_0001 0x0001 /* controller release 1 */
137 /* AIOP ID numbers, identifies AIOP type implementing channel */
138 #define AIOPID_NULL -1 /* no AIOP or channel exists */
139 #define AIOPID_0001 0x0001 /* AIOP release 1 */
141 #define NULLDEV -1 /* identifies non-existant device */
142 #define NULLCTL -1 /* identifies non-existant controller */
143 #define NULLAIOP -1 /* identifies non-existant AIOP */
144 #define NULLCHAN -1 /* identifies non-existant channel */
146 /************************************************************************
147 Global Register Offsets - Direct Access - Fixed values
148 ************************************************************************/
150 #define _CMD_REG 0x38 /* Command Register 8 Write */
151 #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
152 #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
153 #define _UNUSED 0x3B /* Unused 8 */
154 #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
155 #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
157 /************************************************************************
158 Channel Register Offsets for 1st channel in AIOP - Direct Access
159 ************************************************************************/
160 #define _TD0 0x00 /* Transmit Data 16 Write */
161 #define _RD0 0x00 /* Receive Data 16 Read */
162 #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
163 #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
164 #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
166 /************************************************************************
167 Tx Control Register Offsets - Indexed - External - Fixed
168 ************************************************************************/
169 #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
170 #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
171 #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
172 #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
173 #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
174 #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
176 /************************************************************************
178 ************************************************************************/
179 #define RXFIFO_DATA 0x5f
180 #define RXFIFO_OUT 0x5c
181 #define RXFIFO_EN 0x08
182 #define RXFIFO_DIS 0xa7
184 /************************************************************************
185 Memory Controller Register Offsets - Indexed - External - Fixed
186 ************************************************************************/
187 #define _RX_FIFO 0x000 /* Rx FIFO */
188 #define _TX_FIFO 0x800 /* Tx FIFO */
189 #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
190 #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
191 #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
192 #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
193 #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
194 #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
196 #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
197 #define TXFIFO_SIZE 255 /* size of Tx FIFO */
198 #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
200 /************************************************************************
201 Tx Priority Buffer - Indexed - External - Fixed
202 ************************************************************************/
203 #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
204 #define TXP_SIZE 0x20 /* 32 bytes */
206 /************************************************************************
207 Channel Register Offsets - Indexed - Internal - Fixed
208 ************************************************************************/
210 #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
211 #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
212 #define _BAUD 0xFF4 /* Baud Rate 16 Write */
213 #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
215 #define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */
241 #define STMBREAK 0x08 /* BREAK */
242 #define STMFRAME 0x04 /* framing error */
243 #define STMRCVROVR 0x02 /* receiver over run error */
244 #define STMPARITY 0x01 /* parity error */
245 #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
246 #define STMBREAKH 0x800 /* BREAK */
247 #define STMFRAMEH 0x400 /* framing error */
248 #define STMRCVROVRH 0x200 /* receiver over run error */
249 #define STMPARITYH 0x100 /* parity error */
250 #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
252 #define CTS_ACT 0x20 /* CTS input asserted */
253 #define DSR_ACT 0x10 /* DSR input asserted */
254 #define CD_ACT 0x08 /* CD input asserted */
255 #define TXFIFOMT 0x04 /* Tx FIFO is empty */
256 #define TXSHRMT 0x02 /* Tx shift register is empty */
257 #define RDA 0x01 /* Rx data available */
258 #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
260 #define STATMODE 0x8000 /* status mode enable bit */
261 #define RXFOVERFL 0x2000 /* receive FIFO overflow */
262 #define RX2MATCH 0x1000 /* receive compare byte 2 match */
263 #define RX1MATCH 0x0800 /* receive compare byte 1 match */
264 #define RXBREAK 0x0400 /* received BREAK */
265 #define RXFRAME 0x0200 /* received framing error */
266 #define RXPARITY 0x0100 /* received parity error */
267 #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
269 #define CTSFC_EN 0x80 /* CTS flow control enable bit */
270 #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
271 #define TXINT_EN 0x10 /* transmit interrupt enable */
272 #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
273 #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
274 #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
275 #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
277 #define SETBREAK 0x10 /* send break condition (must clear) */
278 #define LOCALLOOP 0x08 /* local loopback set for test */
279 #define SET_DTR 0x04 /* assert DTR */
280 #define SET_RTS 0x02 /* assert RTS */
281 #define TX_ENABLE 0x01 /* enable transmitter */
283 #define RTSFC_EN 0x40 /* RTS flow control enable */
284 #define RXPROC_EN 0x20 /* receive processor enable */
285 #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
286 #define TRIG_1 0x08 /* trigger level 1 char */
287 #define TRIG_1_2 0x10 /* trigger level 1/2 */
288 #define TRIG_7_8 0x18 /* trigger level 7/8 */
289 #define TRIG_MASK 0x18 /* trigger level mask */
290 #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
291 #define RXINT_EN 0x02 /* Rx interrupt enable */
292 #define MCINT_EN 0x01 /* modem change interrupt enable */
294 #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
295 #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
296 #define SRC_INT 0x08 /* special receive condition interrupt */
297 #define DELTA_CD 0x04 /* CD change interrupt */
298 #define DELTA_CTS 0x02 /* CTS change interrupt */
299 #define DELTA_DSR 0x01 /* DSR change interrupt */
301 #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
302 #define IGN2_EN 0x08 /* ignore byte 2 enable */
303 #define IGN1_EN 0x04 /* ignore byte 1 enable */
304 #define COMP2_EN 0x02 /* compare byte 2 enable */
305 #define COMP1_EN 0x01 /* compare byte 1 enable */
307 #define RESET_ALL 0x80 /* reset AIOP (all channels) */
308 #define TXOVERIDE 0x40 /* Transmit software off override */
309 #define RESETUART 0x20 /* reset channel's UART */
310 #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
311 #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
313 #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
314 #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
315 #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
316 #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
318 #define INTR_EN 0x08 /* allow interrupts to host */
319 #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
321 #define CHAN3_EN 0x08 /* enable AIOP 3 */
322 #define CHAN2_EN 0x04 /* enable AIOP 2 */
323 #define CHAN1_EN 0x02 /* enable AIOP 1 */
324 #define CHAN0_EN 0x01 /* enable AIOP 0 */
325 #define FREQ_DIS 0x00
326 #define FREQ_274HZ 0x60
327 #define FREQ_137HZ 0x50
328 #define FREQ_69HZ 0x40
329 #define FREQ_34HZ 0x30
330 #define FREQ_17HZ 0x20
331 #define FREQ_9HZ 0x10
332 #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
334 #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
337 #define RREGDATASIZE 52
347 struct CONTROLLER_str;
350 /* The types of bus-specific methods */
351 typedef int rp_aiop2rid_t(int, int);
352 typedef int rp_aiop2off_t(int, int);
353 typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *);
355 /* Controller level information structure */
356 struct CONTROLLER_str
360 int AiopID[AIOP_CTL_SIZE];
361 int AiopNumChan[AIOP_CTL_SIZE];
363 /* Device and resource management */
364 device_t dev; /* device */
365 int io_num; /* Number of IO resources */
366 int *io_rid; /* IO resource IDs */
367 struct resource **io; /* IO resources */
369 struct rp_port *rp; /* port */
370 struct tty *tty; /* tty */
372 /* Bus-specific properties */
375 /* Bus-specific methods */
376 rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */
377 rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */
378 rp_ctlmask_t *ctlmask; /* Int status */
380 typedef struct CONTROLLER_str CONTROLLER_T;
381 typedef CONTROLLER_T CONTROLLER_t;
383 /* Channel level information structure */
399 Byte_t R[RREGDATASIZE];
406 Byte_t TxReplace1[4];
407 Byte_t TxReplace2[4];
410 typedef struct CHANNEL_str CHANNEL_T;
411 typedef CHANNEL_T CHANNEL_t;
412 typedef CHANNEL_T * CHANPTR_T;
414 #define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0)
415 #define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0)
416 #define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0)
417 #define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0)
419 /***************************************************************************
421 Purpose: Stop sending a transmit BREAK signal
423 CHANNEL_T *ChP; Ptr to channel structure
425 #define sClrBreak(ChP) \
427 (ChP)->TxControl[3] &= ~SETBREAK; \
428 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
431 /***************************************************************************
433 Purpose: Clr the DTR output
435 CHANNEL_T *ChP; Ptr to channel structure
437 #define sClrDTR(ChP) \
439 (ChP)->TxControl[3] &= ~SET_DTR; \
440 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
443 /***************************************************************************
445 Purpose: Clr the RTS output
447 CHANNEL_T *ChP; Ptr to channel structure
449 #define sClrRTS(ChP) \
451 (ChP)->TxControl[3] &= ~SET_RTS; \
452 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
455 /***************************************************************************
457 Purpose: Clear any existing transmit software flow control off condition
458 Call: sClrTxXOFF(ChP)
459 CHANNEL_T *ChP; Ptr to channel structure
461 #define sClrTxXOFF(ChP) \
463 rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
464 rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \
467 /***************************************************************************
468 Function: sDisCTSFlowCtl
469 Purpose: Disable output flow control using CTS
470 Call: sDisCTSFlowCtl(ChP)
471 CHANNEL_T *ChP; Ptr to channel structure
473 #define sDisCTSFlowCtl(ChP) \
475 (ChP)->TxControl[2] &= ~CTSFC_EN; \
476 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
479 /***************************************************************************
481 Purpose: Disable parity
482 Call: sDisParity(ChP)
483 CHANNEL_T *ChP; Ptr to channel structure
484 Comments: Function sSetParity() can be used in place of functions sEnParity(),
485 sDisParity(), sSetOddParity(), and sSetEvenParity().
487 #define sDisParity(ChP) \
489 (ChP)->TxControl[2] &= ~PARITY_EN; \
490 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
493 /***************************************************************************
495 Purpose: Disable Rx FIFO
496 Call: sDisRxFIFO(ChP)
497 CHANNEL_T *ChP; Ptr to channel structure
499 #define sDisRxFIFO(ChP) \
501 (ChP)->R[0x32] = 0x0a; \
502 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \
505 /***************************************************************************
506 Function: sDisRxStatusMode
507 Purpose: Disable the Rx status mode
508 Call: sDisRxStatusMode(ChP)
509 CHANNEL_T *ChP; Ptr to channel structure
510 Comments: This takes the channel out of the receive status mode. All
511 subsequent reads of receive data using sReadRxWord() will return
514 #define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0)
516 /***************************************************************************
517 Function: sDisTransmit
518 Purpose: Disable transmit
519 Call: sDisTransmit(ChP)
520 CHANNEL_T *ChP; Ptr to channel structure
521 This disables movement of Tx data from the Tx FIFO into the 1 byte
522 Tx buffer. Therefore there could be up to a 2 byte latency
523 between the time sDisTransmit() is called and the transmit buffer
524 and transmit shift register going completely empty.
526 #define sDisTransmit(ChP) \
528 (ChP)->TxControl[3] &= ~TX_ENABLE; \
529 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
532 /***************************************************************************
533 Function: sDisTxSoftFlowCtl
534 Purpose: Disable Tx Software Flow Control
535 Call: sDisTxSoftFlowCtl(ChP)
536 CHANNEL_T *ChP; Ptr to channel structure
538 #define sDisTxSoftFlowCtl(ChP) \
540 (ChP)->R[0x06] = 0x8a; \
541 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x04]); \
544 /***************************************************************************
545 Function: sEnCTSFlowCtl
546 Purpose: Enable output flow control using CTS
547 Call: sEnCTSFlowCtl(ChP)
548 CHANNEL_T *ChP; Ptr to channel structure
550 #define sEnCTSFlowCtl(ChP) \
552 (ChP)->TxControl[2] |= CTSFC_EN; \
553 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
556 /***************************************************************************
558 Purpose: Enable parity
560 CHANNEL_T *ChP; Ptr to channel structure
561 Comments: Function sSetParity() can be used in place of functions sEnParity(),
562 sDisParity(), sSetOddParity(), and sSetEvenParity().
564 Warnings: Before enabling parity odd or even parity should be chosen using
565 functions sSetOddParity() or sSetEvenParity().
567 #define sEnParity(ChP) \
569 (ChP)->TxControl[2] |= PARITY_EN; \
570 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
573 /***************************************************************************
574 Function: sEnRTSFlowCtl
577 #define sEnRTSFlowCtl(ChP) \
579 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
580 (ChP)->TxControl[3] &= ~SET_RTS; \
581 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
582 (ChP)->RxControl[2] |= RTSFC_EN; \
583 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
586 /***************************************************************************
587 Function: sDisRTSFlowCtl
590 #define sDisRTSFlowCtl(ChP) \
592 (ChP)->RxControl[2] &= ~RTSFC_EN; \
593 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
596 /***************************************************************************
598 Purpose: Enable Rx FIFO
600 CHANNEL_T *ChP; Ptr to channel structure
602 #define sEnRxFIFO(ChP) \
604 (ChP)->R[0x32] = 0x08; \
605 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \
608 /***************************************************************************
609 Function: sEnRxProcessor
610 Purpose: Enable the receive processor
611 Call: sEnRxProcessor(ChP)
612 CHANNEL_T *ChP; Ptr to channel structure
613 Comments: This function is used to start the receive processor. When
614 the channel is in the reset state the receive processor is not
615 running. This is done to prevent the receive processor from
616 executing invalid microcode instructions prior to the
617 downloading of the microcode.
619 Warnings: This function must be called after valid microcode has been
620 downloaded to the AIOP, and it must not be called before the
621 microcode has been downloaded.
623 #define sEnRxProcessor(ChP) \
625 (ChP)->RxControl[2] |= RXPROC_EN; \
626 rp_writech2(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
629 /***************************************************************************
630 Function: sEnRxStatusMode
631 Purpose: Enable the Rx status mode
632 Call: sEnRxStatusMode(ChP)
633 CHANNEL_T *ChP; Ptr to channel structure
634 Comments: This places the channel in the receive status mode. All subsequent
635 reads of receive data using sReadRxWord() will return a data byte
636 in the low word and a status byte in the high word.
639 #define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE)
641 /***************************************************************************
642 Function: sEnTransmit
643 Purpose: Enable transmit
644 Call: sEnTransmit(ChP)
645 CHANNEL_T *ChP; Ptr to channel structure
647 #define sEnTransmit(ChP) \
649 (ChP)->TxControl[3] |= TX_ENABLE; \
650 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
653 /***************************************************************************
654 Function: sGetAiopIntStatus
655 Purpose: Get the AIOP interrupt status
656 Call: sGetAiopIntStatus(CtlP,AiopNum)
657 CONTROLLER_T *CtlP; Ptr to controller structure
658 int AiopNum; AIOP number
659 Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
660 represent channels 0 through 7 respectively. If a
661 bit is set that channel is interrupting.
663 #define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN)
665 /***************************************************************************
666 Function: sGetAiopNumChan
667 Purpose: Get the number of channels supported by an AIOP
668 Call: sGetAiopNumChan(CtlP,AiopNum)
669 CONTROLLER_T *CtlP; Ptr to controller structure
670 int AiopNum; AIOP number
671 Return: int: The number of channels supported by the AIOP
673 #define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM]
675 /***************************************************************************
676 Function: sGetChanIntID
677 Purpose: Get a channel's interrupt identification byte
678 Call: sGetChanIntID(ChP)
679 CHANNEL_T *ChP; Ptr to channel structure
680 Return: Byte_t: The channel interrupt ID. Can be any
681 combination of the following flags:
682 RXF_TRIG: Rx FIFO trigger level interrupt
683 TXFIFO_MT: Tx FIFO empty interrupt
684 SRC_INT: Special receive condition interrupt
685 DELTA_CD: CD change interrupt
686 DELTA_CTS: CTS change interrupt
687 DELTA_DSR: DSR change interrupt
689 #define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
691 /***************************************************************************
692 Function: sGetChanNum
693 Purpose: Get the number of a channel within an AIOP
694 Call: sGetChanNum(ChP)
695 CHANNEL_T *ChP; Ptr to channel structure
696 Return: int: Channel number within AIOP, or NULLCHAN if channel does
699 #define sGetChanNum(ChP) (ChP)->ChanNum
701 /***************************************************************************
702 Function: sGetChanStatus
703 Purpose: Get the channel status
704 Call: sGetChanStatus(ChP)
705 CHANNEL_T *ChP; Ptr to channel structure
706 Return: Word_t: The channel status. Can be any combination of
709 CTS_ACT: CTS input asserted
710 DSR_ACT: DSR input asserted
711 CD_ACT: CD input asserted
712 TXFIFOMT: Tx FIFO is empty
713 TXSHRMT: Tx shift register is empty
714 RDA: Rx data available
717 STATMODE: status mode enable bit
718 RXFOVERFL: receive FIFO overflow
719 RX2MATCH: receive compare byte 2 match
720 RX1MATCH: receive compare byte 1 match
721 RXBREAK: received BREAK
722 RXFRAME: received framing error
723 RXPARITY: received parity error
724 Warnings: This function will clear the high byte flags in the Channel
727 #define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP))
729 /***************************************************************************
730 Function: sGetChanStatusLo
731 Purpose: Get the low byte only of the channel status
732 Call: sGetChanStatusLo(ChP)
733 CHANNEL_T *ChP; Ptr to channel structure
734 Return: Byte_t: The channel status low byte. Can be any combination
735 of the following flags:
736 CTS_ACT: CTS input asserted
737 DSR_ACT: DSR input asserted
738 CD_ACT: CD input asserted
739 TXFIFOMT: Tx FIFO is empty
740 TXSHRMT: Tx shift register is empty
741 RDA: Rx data available
743 #define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP))
745 /***************************************************************************
747 Purpose: Get the number of data bytes in the Rx FIFO
749 CHANNEL_T *ChP; Ptr to channel structure
750 Return: int: The number of data bytes in the Rx FIFO.
751 Comments: Byte read of count register is required to obtain Rx count.
754 #define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP))
756 /***************************************************************************
758 Purpose: Get the number of data bytes in the Tx FIFO
760 CHANNEL_T *ChP; Ptr to channel structure
761 Return: Byte_t: The number of data bytes in the Tx FIFO.
762 Comments: Byte read of count register is required to obtain Tx count.
765 #define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP))
767 /*****************************************************************************
768 Function: sGetTxRxDataIO
769 Purpose: Get the offset of a channel's TxRx Data register
770 Call: sGetTxRxDataIO(ChP)
771 CHANNEL_T *ChP; Ptr to channel structure
772 Return: WordIO_t: offset of a channel's TxRx Data register
774 #define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP)
776 /***************************************************************************
777 Function: sInitChanDefaults
778 Purpose: Initialize a channel structure to its default state.
779 Call: sInitChanDefaults(ChP)
780 CHANNEL_T *ChP; Ptr to the channel structure
781 Comments: This function must be called once for every channel structure
782 that exists before any other SSCI calls can be made.
785 #define sInitChanDefaults(ChP) \
787 (ChP)->CtlP = NULL; \
788 (ChP)->AiopNum = NULLAIOP; \
789 (ChP)->ChanID = AIOPID_NULL; \
790 (ChP)->ChanNum = NULLCHAN; \
793 /***************************************************************************
794 Function: sResetAiopByNum
795 Purpose: Reset the AIOP by number
796 Call: sResetAiopByNum(CTLP,AIOPNUM)
797 CONTROLLER_T CTLP; Ptr to controller structure
800 #define sResetAiopByNum(CTLP,AIOPNUM) \
802 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \
803 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \
806 /***************************************************************************
808 Purpose: Send a transmit BREAK signal
809 Call: sSendBreak(ChP)
810 CHANNEL_T *ChP; Ptr to channel structure
812 #define sSendBreak(ChP) \
814 (ChP)->TxControl[3] |= SETBREAK; \
815 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
818 /***************************************************************************
820 Purpose: Set baud rate
821 Call: sSetBaud(ChP,Divisor)
822 CHANNEL_T *ChP; Ptr to channel structure
823 Word_t Divisor; 16 bit baud rate divisor for channel
825 #define sSetBaud(ChP,DIVISOR) \
827 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
828 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
829 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->BaudDiv[0]); \
832 /***************************************************************************
834 Purpose: Set data bits to 7
836 CHANNEL_T *ChP; Ptr to channel structure
838 #define sSetData7(ChP) \
840 (ChP)->TxControl[2] &= ~DATA8BIT; \
841 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
844 /***************************************************************************
846 Purpose: Set data bits to 8
848 CHANNEL_T *ChP; Ptr to channel structure
850 #define sSetData8(ChP) \
852 (ChP)->TxControl[2] |= DATA8BIT; \
853 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
856 /***************************************************************************
858 Purpose: Set the DTR output
860 CHANNEL_T *ChP; Ptr to channel structure
862 #define sSetDTR(ChP) \
864 (ChP)->TxControl[3] |= SET_DTR; \
865 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
868 /***************************************************************************
869 Function: sSetEvenParity
870 Purpose: Set even parity
871 Call: sSetEvenParity(ChP)
872 CHANNEL_T *ChP; Ptr to channel structure
873 Comments: Function sSetParity() can be used in place of functions sEnParity(),
874 sDisParity(), sSetOddParity(), and sSetEvenParity().
876 Warnings: This function has no effect unless parity is enabled with function
879 #define sSetEvenParity(ChP) \
881 (ChP)->TxControl[2] |= EVEN_PAR; \
882 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
885 /***************************************************************************
886 Function: sSetOddParity
887 Purpose: Set odd parity
888 Call: sSetOddParity(ChP)
889 CHANNEL_T *ChP; Ptr to channel structure
890 Comments: Function sSetParity() can be used in place of functions sEnParity(),
891 sDisParity(), sSetOddParity(), and sSetEvenParity().
893 Warnings: This function has no effect unless parity is enabled with function
896 #define sSetOddParity(ChP) \
898 (ChP)->TxControl[2] &= ~EVEN_PAR; \
899 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
902 /***************************************************************************
904 Purpose: Set the RTS output
906 CHANNEL_T *ChP; Ptr to channel structure
908 #define sSetRTS(ChP) \
910 (ChP)->TxControl[3] |= SET_RTS; \
911 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
914 /***************************************************************************
915 Function: sSetRxTrigger
916 Purpose: Set the Rx FIFO trigger level
917 Call: sSetRxProcessor(ChP,Level)
918 CHANNEL_T *ChP; Ptr to channel structure
919 Byte_t Level; Number of characters in Rx FIFO at which the
920 interrupt will be generated. Can be any of the following flags:
923 TRIG_1: 1 character in FIFO
924 TRIG_1_2: FIFO 1/2 full
925 TRIG_7_8: FIFO 7/8 full
926 Comments: An interrupt will be generated when the trigger level is reached
927 only if function sEnInterrupt() has been called with flag
928 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
929 register will be set whenever the trigger level is reached
930 regardless of the setting of RXINT_EN.
933 #define sSetRxTrigger(ChP,LEVEL) \
935 (ChP)->RxControl[2] &= ~TRIG_MASK; \
936 (ChP)->RxControl[2] |= LEVEL; \
937 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
940 /***************************************************************************
942 Purpose: Set stop bits to 1
944 CHANNEL_T *ChP; Ptr to channel structure
946 #define sSetStop1(ChP) \
948 (ChP)->TxControl[2] &= ~STOP2; \
949 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
952 /***************************************************************************
954 Purpose: Set stop bits to 2
956 CHANNEL_T *ChP; Ptr to channel structure
958 #define sSetStop2(ChP) \
960 (ChP)->TxControl[2] |= STOP2; \
961 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
964 /***************************************************************************
965 Function: sStartRxProcessor
966 Purpose: Start a channel's receive processor
967 Call: sStartRxProcessor(ChP)
968 CHANNEL_T *ChP; Ptr to channel structure
969 Comments: This function is used to start a Rx processor after it was
970 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
971 will restart both the Rx processor and software input flow control.
974 #define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0])
976 /***************************************************************************
977 Function: sWriteTxByte
978 Purpose: Write a transmit data byte to a channel.
979 CHANNEL_T *ChP; Ptr to channel structure
980 ByteIO_t io: Channel transmit register I/O address. This can
981 be obtained with sGetTxRxDataIO().
982 Byte_t Data; The transmit data byte.
983 Warnings: This function writes the data byte without checking to see if
984 sMaxTxSize is exceeded in the Tx FIFO.
986 #define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA)
988 int sReadAiopID(CONTROLLER_T *CtlP, int aiop);
989 int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop);
990 int sInitChan( CONTROLLER_T *CtlP,
994 Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
995 void sStopRxProcessor(CHANNEL_T *ChP);
996 void sStopSWInFlowCtl(CHANNEL_T *ChP);
997 void sFlushRxFIFO(CHANNEL_T *ChP);
998 void sFlushTxFIFO(CHANNEL_T *ChP);
999 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1000 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1001 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
1002 int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports);
1003 void rp_releaseresource(CONTROLLER_t *ctlp);
1005 extern Byte_t rp_sBitMapClrTbl[8];
1006 extern Byte_t rp_sBitMapSetTbl[8];