2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
53 * $FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 253497 2013-07-20 13:52:40Z kib $
56 #include <sys/resourcevar.h>
57 #include <sys/sfbuf.h>
60 #include <drm/i915_drm.h>
62 #include "intel_drv.h"
63 #include "intel_ringbuffer.h"
64 #include <linux/completion.h>
65 #include <linux/jiffies.h>
66 #include <linux/time.h>
68 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
70 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
71 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
72 unsigned alignment, bool map_and_fenceable);
74 static int i915_gem_phys_pwrite(struct drm_device *dev,
75 struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
76 uint64_t size, struct drm_file *file_priv);
78 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
80 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
81 uint32_t size, int tiling_mode);
82 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
84 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
85 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
86 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
87 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
88 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
89 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
90 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
91 uint32_t flush_domains);
92 static void i915_gem_clear_fence_reg(struct drm_device *dev,
93 struct drm_i915_fence_reg *reg);
94 static void i915_gem_reset_fences(struct drm_device *dev);
95 static void i915_gem_lowmem(void *arg);
97 static int i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
98 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file);
100 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
101 long i915_gem_wired_pages_cnt;
103 /* some bookkeeping */
104 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
108 dev_priv->mm.object_count++;
109 dev_priv->mm.object_memory += size;
112 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
116 dev_priv->mm.object_count--;
117 dev_priv->mm.object_memory -= size;
121 i915_gem_wait_for_error(struct drm_device *dev)
123 struct drm_i915_private *dev_priv = dev->dev_private;
124 struct completion *x = &dev_priv->error_completion;
127 if (!atomic_read(&dev_priv->mm.wedged))
131 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
132 * userspace. If it takes that long something really bad is going on and
133 * we should simply try to bail out and fail as gracefully as possible.
135 ret = wait_for_completion_interruptible_timeout(x, 10*hz);
137 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
139 } else if (ret < 0) {
143 if (atomic_read(&dev_priv->mm.wedged)) {
144 /* GPU is hung, bump the completion count to account for
145 * the token we just consumed so that we never hit zero and
146 * end up waiting upon a subsequent completion event that
149 spin_lock(&x->wait.lock);
151 spin_unlock(&x->wait.lock);
156 int i915_mutex_lock_interruptible(struct drm_device *dev)
160 ret = i915_gem_wait_for_error(dev);
164 ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
168 WARN_ON(i915_verify_lists(dev));
173 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
175 return (obj->gtt_space && !obj->active && obj->pin_count == 0);
179 i915_gem_init_ioctl(struct drm_device *dev, void *data,
180 struct drm_file *file)
182 struct drm_i915_gem_init *args;
183 drm_i915_private_t *dev_priv;
185 dev_priv = dev->dev_private;
188 if (args->gtt_start >= args->gtt_end ||
189 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
193 * XXXKIB. The second-time initialization should be guarded
196 lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
197 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
198 lockmgr(&dev->dev_lock, LK_RELEASE);
204 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
205 struct drm_file *file)
207 struct drm_i915_private *dev_priv;
208 struct drm_i915_gem_get_aperture *args;
209 struct drm_i915_gem_object *obj;
212 dev_priv = dev->dev_private;
217 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
218 pinned += obj->gtt_space->size;
221 args->aper_size = dev_priv->mm.gtt_total;
222 args->aper_available_size = args->aper_size - pinned;
228 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
231 struct drm_i915_gem_object *obj;
235 size = roundup(size, PAGE_SIZE);
239 obj = i915_gem_alloc_object(dev, size);
244 ret = drm_gem_handle_create(file, &obj->base, &handle);
246 drm_gem_object_release(&obj->base);
247 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
248 drm_free(obj, DRM_I915_GEM);
252 /* drop reference from allocate - handle holds it now */
253 drm_gem_object_unreference(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
264 /* have to work out size/pitch and return them */
265 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
266 args->size = args->pitch * args->height;
267 return (i915_gem_create(file, dev, args->size, &args->handle));
270 int i915_gem_dumb_destroy(struct drm_file *file,
271 struct drm_device *dev,
275 return (drm_gem_handle_delete(file, handle));
279 * Creates a new mm object and returns a handle to it.
282 i915_gem_create_ioctl(struct drm_device *dev, void *data,
283 struct drm_file *file)
285 struct drm_i915_gem_create *args = data;
287 return (i915_gem_create(file, dev, args->size, &args->handle));
290 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
292 drm_i915_private_t *dev_priv;
294 dev_priv = obj->base.dev->dev_private;
295 return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
296 obj->tiling_mode != I915_TILING_NONE);
300 * Reads data from the object referenced by handle.
302 * On error, the contents of *data are undefined.
305 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
306 struct drm_file *file)
308 struct drm_i915_gem_pread *args;
311 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
312 args->offset, UIO_READ, file));
316 * Writes data to the object referenced by handle.
318 * On error, the contents of the buffer that were to be modified are undefined.
321 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
322 struct drm_file *file)
324 struct drm_i915_gem_pwrite *args;
327 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
328 args->offset, UIO_WRITE, file));
332 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
335 if (atomic_read(&dev_priv->mm.wedged)) {
336 struct completion *x = &dev_priv->error_completion;
337 bool recovery_complete;
339 /* Give the error handler a chance to run. */
340 spin_lock(&x->wait.lock);
341 recovery_complete = x->done > 0;
342 spin_unlock(&x->wait.lock);
344 /* Non-interruptible callers can't handle -EAGAIN, hence return
345 * -EIO unconditionally for these. */
349 /* Recovery complete, but still wedged means reset failure. */
350 if (recovery_complete)
360 * Compare seqno against outstanding lazy request. Emit a request if they are
364 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
368 DRM_LOCK_ASSERT(ring->dev);
371 if (seqno == ring->outstanding_lazy_request)
372 ret = i915_add_request(ring, NULL, NULL);
378 * __wait_seqno - wait until execution of seqno has finished
379 * @ring: the ring expected to report seqno
381 * @interruptible: do an interruptible wait (normally yes)
382 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
384 * Returns 0 if the seqno was found within the alloted time. Else returns the
385 * errno with remaining time filled in timeout argument.
387 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
388 bool interruptible, struct timespec *timeout)
390 drm_i915_private_t *dev_priv = ring->dev->dev_private;
391 struct timespec before, now, wait_time={1,0};
392 unsigned long timeout_jiffies;
394 bool wait_forever = true;
397 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
400 if (timeout != NULL) {
401 wait_time = *timeout;
402 wait_forever = false;
405 timeout_jiffies = timespec_to_jiffies(&wait_time);
407 if (WARN_ON(!ring->irq_get(ring)))
410 /* Record current time in case interrupted by signal, or wedged * */
411 getrawmonotonic(&before);
414 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
415 atomic_read(&dev_priv->mm.wedged))
418 end = wait_event_interruptible_timeout(ring->irq_queue,
422 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
425 ret = i915_gem_check_wedge(dev_priv, interruptible);
428 } while (end == 0 && wait_forever);
430 getrawmonotonic(&now);
436 struct timespec sleep_time = timespec_sub(now, before);
437 *timeout = timespec_sub(*timeout, sleep_time);
442 case -EAGAIN: /* Wedged */
443 case -ERESTARTSYS: /* Signal */
445 case 0: /* Timeout */
447 set_normalized_timespec(timeout, 0, 0);
448 return -ETIMEDOUT; /* -ETIME on Linux */
449 default: /* Completed */
450 WARN_ON(end < 0); /* We're not aware of other errors */
456 * Waits for a sequence number to be signaled, and cleans up the
457 * request and object lists appropriately for that event.
460 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
462 drm_i915_private_t *dev_priv = ring->dev->dev_private;
467 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
471 ret = i915_gem_check_olr(ring, seqno);
475 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
481 * Ensures that all rendering to the object has completed and the object is
482 * safe to unbind from the GTT or access from the CPU.
484 static __must_check int
485 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
491 /* This function only exists to support waiting for existing rendering,
492 * not for emitting required flushes.
494 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
496 /* If there is rendering queued on the buffer being evicted, wait for
500 seqno = obj->last_write_seqno;
502 seqno = obj->last_read_seqno;
506 ret = i915_wait_seqno(obj->ring, seqno);
510 /* Manually manage the write flush as we may have not yet retired
513 if (obj->last_write_seqno &&
514 i915_seqno_passed(seqno, obj->last_write_seqno)) {
515 obj->last_write_seqno = 0;
516 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
519 i915_gem_retire_requests_ring(obj->ring);
524 * Ensures that an object will eventually get non-busy by flushing any required
525 * write domains, emitting any outstanding lazy request and retiring and
526 * completed requests.
529 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
534 ret = i915_gem_object_flush_gpu_write_domain(obj);
538 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
542 i915_gem_retire_requests_ring(obj->ring);
549 * Called when user space prepares to use an object with the CPU, either
550 * through the mmap ioctl's mapping or a GTT mapping.
553 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
554 struct drm_file *file)
556 struct drm_i915_gem_set_domain *args;
557 struct drm_i915_gem_object *obj;
558 uint32_t read_domains;
559 uint32_t write_domain;
563 read_domains = args->read_domains;
564 write_domain = args->write_domain;
566 if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
567 (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
568 (write_domain != 0 && read_domains != write_domain))
571 ret = i915_mutex_lock_interruptible(dev);
575 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
576 if (&obj->base == NULL) {
581 if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
582 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
586 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
588 drm_gem_object_unreference(&obj->base);
595 * Called when user space has done writes to this buffer
598 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
599 struct drm_file *file)
601 struct drm_i915_gem_sw_finish *args = data;
602 struct drm_i915_gem_object *obj;
605 ret = i915_mutex_lock_interruptible(dev);
608 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
609 if (&obj->base == NULL) {
613 if (obj->pin_count != 0)
614 i915_gem_object_flush_cpu_write_domain(obj);
615 drm_gem_object_unreference(&obj->base);
622 * Maps the contents of an object, returning the address it is mapped
625 * While the mapping holds a reference on the contents of the object, it doesn't
626 * imply a ref on the object itself.
629 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
630 struct drm_file *file)
632 struct drm_i915_gem_mmap *args;
633 struct drm_gem_object *obj;
642 obj = drm_gem_object_lookup(dev, file, args->handle);
649 map = &p->p_vmspace->vm_map;
650 size = round_page(args->size);
652 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
660 vm_object_hold(obj->vm_obj);
661 vm_object_reference_locked(obj->vm_obj);
662 vm_object_drop(obj->vm_obj);
664 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
665 PAGE_SIZE, /* align */
667 VM_MAPTYPE_NORMAL, /* maptype */
668 VM_PROT_READ | VM_PROT_WRITE, /* prot */
669 VM_PROT_READ | VM_PROT_WRITE, /* max */
670 MAP_SHARED /* cow */);
671 if (rv != KERN_SUCCESS) {
672 vm_object_deallocate(obj->vm_obj);
673 error = -vm_mmap_to_errno(rv);
675 args->addr_ptr = (uint64_t)addr;
679 drm_gem_object_unreference(obj);
684 * i915_gem_release_mmap - remove physical page mappings
685 * @obj: obj in question
687 * Preserve the reservation of the mmapping with the DRM core code, but
688 * relinquish ownership of the pages back to the system.
690 * It is vital that we remove the page mapping if we have mapped a tiled
691 * object through the GTT and then lose the fence register due to
692 * resource pressure. Similarly if the object has been moved out of the
693 * aperture, than pages mapped into userspace must be revoked. Removing the
694 * mapping will then trigger a page fault on the next user access, allowing
695 * fixup by i915_gem_fault().
698 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
704 if (!obj->fault_mappable)
707 devobj = cdev_pager_lookup(obj);
708 if (devobj != NULL) {
709 page_count = OFF_TO_IDX(obj->base.size);
711 VM_OBJECT_LOCK(devobj);
712 for (i = 0; i < page_count; i++) {
713 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
716 cdev_pager_free_page(devobj, m);
718 VM_OBJECT_UNLOCK(devobj);
719 vm_object_deallocate(devobj);
722 obj->fault_mappable = false;
726 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
730 if (INTEL_INFO(dev)->gen >= 4 ||
731 tiling_mode == I915_TILING_NONE)
734 /* Previous chips need a power-of-two fence region when tiling */
735 if (INTEL_INFO(dev)->gen == 3)
736 gtt_size = 1024*1024;
740 while (gtt_size < size)
747 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
748 * @obj: object to check
750 * Return the required GTT alignment for an object, taking into account
751 * potential fence register mapping.
754 i915_gem_get_gtt_alignment(struct drm_device *dev,
760 * Minimum alignment is 4k (GTT page size), but might be greater
761 * if a fence register is needed for the object.
763 if (INTEL_INFO(dev)->gen >= 4 ||
764 tiling_mode == I915_TILING_NONE)
768 * Previous chips need to be aligned to the size of the smallest
769 * fence register that can contain the object.
771 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
775 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
778 * @size: size of the object
779 * @tiling_mode: tiling mode of the object
781 * Return the required GTT alignment for an object, only taking into account
782 * unfenced tiled surface requirements.
785 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
790 if (tiling_mode == I915_TILING_NONE)
794 * Minimum alignment is 4k (GTT page size) for sane hw.
796 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
800 * Previous hardware however needs to be aligned to a power-of-two
801 * tile height. The simplest method for determining this is to reuse
802 * the power-of-tile object size.
804 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
808 i915_gem_mmap_gtt(struct drm_file *file,
809 struct drm_device *dev,
813 struct drm_i915_private *dev_priv;
814 struct drm_i915_gem_object *obj;
817 dev_priv = dev->dev_private;
819 ret = i915_mutex_lock_interruptible(dev);
823 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
824 if (&obj->base == NULL) {
829 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
834 if (obj->madv != I915_MADV_WILLNEED) {
835 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
840 ret = drm_gem_create_mmap_offset(&obj->base);
844 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
847 drm_gem_object_unreference(&obj->base);
854 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
856 * @data: GTT mapping ioctl data
857 * @file: GEM object info
859 * Simply returns the fake offset to userspace so it can mmap it.
860 * The mmap call will end up in drm_gem_mmap(), which will set things
861 * up so we can get faults in the handler above.
863 * The fault handler will take care of binding the object into the GTT
864 * (since it may have been evicted to make room for something), allocating
865 * a fence register, and mapping the appropriate aperture address into
869 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
870 struct drm_file *file)
872 struct drm_i915_private *dev_priv;
873 struct drm_i915_gem_mmap_gtt *args = data;
875 dev_priv = dev->dev_private;
877 return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
880 /* Immediately discard the backing storage */
882 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
886 vm_obj = obj->base.vm_obj;
887 VM_OBJECT_LOCK(vm_obj);
888 vm_object_page_remove(vm_obj, 0, 0, false);
889 VM_OBJECT_UNLOCK(vm_obj);
890 obj->madv = __I915_MADV_PURGED;
894 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
896 return obj->madv == I915_MADV_DONTNEED;
899 static inline void vm_page_reference(vm_page_t m)
901 vm_page_flag_set(m, PG_REFERENCED);
905 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
910 BUG_ON(obj->madv == __I915_MADV_PURGED);
912 if (obj->tiling_mode != I915_TILING_NONE)
913 i915_gem_object_save_bit_17_swizzle(obj);
914 if (obj->madv == I915_MADV_DONTNEED)
916 page_count = obj->base.size / PAGE_SIZE;
917 VM_OBJECT_LOCK(obj->base.vm_obj);
918 #if GEM_PARANOID_CHECK_GTT
919 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
921 for (i = 0; i < page_count; i++) {
925 if (obj->madv == I915_MADV_WILLNEED)
926 vm_page_reference(m);
927 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
928 vm_page_unwire(obj->pages[i], 1);
929 vm_page_wakeup(obj->pages[i]);
930 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
932 VM_OBJECT_UNLOCK(obj->base.vm_obj);
934 drm_free(obj->pages, DRM_I915_GEM);
939 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
942 struct drm_device *dev;
945 int page_count, i, j;
948 KASSERT(obj->pages == NULL, ("Obj already has pages"));
949 page_count = obj->base.size / PAGE_SIZE;
950 obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
952 vm_obj = obj->base.vm_obj;
953 VM_OBJECT_LOCK(vm_obj);
954 for (i = 0; i < page_count; i++) {
955 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
958 VM_OBJECT_UNLOCK(vm_obj);
959 if (i915_gem_object_needs_bit17_swizzle(obj))
960 i915_gem_object_do_bit_17_swizzle(obj);
964 for (j = 0; j < i; j++) {
966 vm_page_busy_wait(m, FALSE, "i915gem");
967 vm_page_unwire(m, 0);
969 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
971 VM_OBJECT_UNLOCK(vm_obj);
972 drm_free(obj->pages, DRM_I915_GEM);
978 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
979 struct intel_ring_buffer *ring,
982 struct drm_device *dev = obj->base.dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
985 BUG_ON(ring == NULL);
988 /* Add a reference if we're newly entering the active list. */
990 drm_gem_object_reference(&obj->base);
994 /* Move from whatever list we were on to the tail of execution. */
995 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
996 list_move_tail(&obj->ring_list, &ring->active_list);
998 obj->last_read_seqno = seqno;
1000 if (obj->fenced_gpu_access) {
1001 obj->last_fenced_seqno = seqno;
1003 /* Bump MRU to take account of the delayed flush */
1004 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1005 struct drm_i915_fence_reg *reg;
1007 reg = &dev_priv->fence_regs[obj->fence_reg];
1008 list_move_tail(®->lru_list,
1009 &dev_priv->mm.fence_list);
1015 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1017 list_del_init(&obj->ring_list);
1018 obj->last_read_seqno = 0;
1019 obj->last_write_seqno = 0;
1020 obj->last_fenced_seqno = 0;
1024 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1026 struct drm_device *dev = obj->base.dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1029 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1031 BUG_ON(!list_empty(&obj->gpu_write_list));
1032 BUG_ON(!obj->active);
1035 i915_gem_object_move_off_active(obj);
1036 obj->fenced_gpu_access = false;
1039 drm_gem_object_unreference(&obj->base);
1041 WARN_ON(i915_verify_lists(dev));
1045 i915_gem_get_seqno(struct drm_device *dev)
1047 drm_i915_private_t *dev_priv = dev->dev_private;
1048 u32 seqno = dev_priv->next_seqno;
1050 /* reserve 0 for non-seqno */
1051 if (++dev_priv->next_seqno == 0)
1052 dev_priv->next_seqno = 1;
1058 i915_add_request(struct intel_ring_buffer *ring,
1059 struct drm_file *file,
1060 struct drm_i915_gem_request *request)
1062 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1064 u32 request_ring_position;
1069 * Emit any outstanding flushes - execbuf can fail to emit the flush
1070 * after having emitted the batchbuffer command. Hence we need to fix
1071 * things up similar to emitting the lazy request. The difference here
1072 * is that the flush _must_ happen before the next request, no matter
1075 if (ring->gpu_caches_dirty) {
1076 ret = i915_gem_flush_ring(ring, 0, I915_GEM_GPU_DOMAINS);
1080 ring->gpu_caches_dirty = false;
1083 if (request == NULL) {
1084 request = kmalloc(sizeof(*request), DRM_I915_GEM,
1086 if (request == NULL)
1090 seqno = i915_gem_next_request_seqno(ring);
1092 /* Record the position of the start of the request so that
1093 * should we detect the updated seqno part-way through the
1094 * GPU processing the request, we never over-estimate the
1095 * position of the head.
1097 request_ring_position = intel_ring_get_tail(ring);
1099 ret = ring->add_request(ring, &seqno);
1101 kfree(request, DRM_I915_GEM);
1105 request->seqno = seqno;
1106 request->ring = ring;
1107 request->tail = request_ring_position;
1108 request->emitted_jiffies = jiffies;
1109 was_empty = list_empty(&ring->request_list);
1110 list_add_tail(&request->list, &ring->request_list);
1111 request->file_priv = NULL;
1114 struct drm_i915_file_private *file_priv = file->driver_priv;
1116 spin_lock(&file_priv->mm.lock);
1117 request->file_priv = file_priv;
1118 list_add_tail(&request->client_list,
1119 &file_priv->mm.request_list);
1120 spin_unlock(&file_priv->mm.lock);
1123 ring->outstanding_lazy_request = 0;
1125 if (!dev_priv->mm.suspended) {
1126 if (i915_enable_hangcheck) {
1127 mod_timer(&dev_priv->hangcheck_timer,
1128 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1131 queue_delayed_work(dev_priv->wq,
1132 &dev_priv->mm.retire_work,
1133 round_jiffies_up_relative(hz));
1134 intel_mark_busy(dev_priv->dev);
1138 WARN_ON(!list_empty(&ring->gpu_write_list));
1144 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1146 struct drm_i915_file_private *file_priv = request->file_priv;
1151 DRM_LOCK_ASSERT(request->ring->dev);
1153 spin_lock(&file_priv->mm.lock);
1154 if (request->file_priv != NULL) {
1155 list_del(&request->client_list);
1156 request->file_priv = NULL;
1158 spin_unlock(&file_priv->mm.lock);
1162 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1163 struct intel_ring_buffer *ring)
1166 if (ring->dev != NULL)
1167 DRM_LOCK_ASSERT(ring->dev);
1169 while (!list_empty(&ring->request_list)) {
1170 struct drm_i915_gem_request *request;
1172 request = list_first_entry(&ring->request_list,
1173 struct drm_i915_gem_request, list);
1175 list_del(&request->list);
1176 i915_gem_request_remove_from_client(request);
1177 drm_free(request, DRM_I915_GEM);
1180 while (!list_empty(&ring->active_list)) {
1181 struct drm_i915_gem_object *obj;
1183 obj = list_first_entry(&ring->active_list,
1184 struct drm_i915_gem_object, ring_list);
1186 obj->base.write_domain = 0;
1187 list_del_init(&obj->gpu_write_list);
1188 i915_gem_object_move_to_inactive(obj);
1193 i915_gem_reset_fences(struct drm_device *dev)
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1198 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1199 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1200 struct drm_i915_gem_object *obj = reg->obj;
1205 if (obj->tiling_mode)
1206 i915_gem_release_mmap(obj);
1208 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1209 reg->obj->fenced_gpu_access = false;
1210 reg->obj->last_fenced_seqno = 0;
1211 i915_gem_clear_fence_reg(dev, reg);
1215 void i915_gem_reset(struct drm_device *dev)
1217 struct drm_i915_private *dev_priv = dev->dev_private;
1218 struct drm_i915_gem_object *obj;
1221 for (i = 0; i < I915_NUM_RINGS; i++)
1222 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1224 /* Remove anything from the flushing lists. The GPU cache is likely
1225 * to be lost on reset along with the data, so simply move the
1226 * lost bo to the inactive list.
1228 while (!list_empty(&dev_priv->mm.flushing_list)) {
1229 obj = list_first_entry(&dev_priv->mm.flushing_list,
1230 struct drm_i915_gem_object,
1233 obj->base.write_domain = 0;
1234 list_del_init(&obj->gpu_write_list);
1235 i915_gem_object_move_to_inactive(obj);
1238 /* Move everything out of the GPU domains to ensure we do any
1239 * necessary invalidation upon reuse.
1241 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
1242 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1245 /* The fence registers are invalidated so clear them out */
1246 i915_gem_reset_fences(dev);
1250 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1252 struct drm_device *dev = obj->base.dev;
1253 drm_i915_private_t *dev_priv = dev->dev_private;
1255 KASSERT(obj->active, ("Object not active"));
1256 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1258 i915_gem_object_move_off_active(obj);
1262 * This function clears the request list as sequence numbers are passed.
1265 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1270 if (list_empty(&ring->request_list))
1273 WARN_ON(i915_verify_lists(ring->dev));
1275 seqno = ring->get_seqno(ring, true);
1277 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1278 if (seqno >= ring->sync_seqno[i])
1279 ring->sync_seqno[i] = 0;
1281 while (!list_empty(&ring->request_list)) {
1282 struct drm_i915_gem_request *request;
1284 request = list_first_entry(&ring->request_list,
1285 struct drm_i915_gem_request,
1288 if (!i915_seqno_passed(seqno, request->seqno))
1291 /* We know the GPU must have read the request to have
1292 * sent us the seqno + interrupt, so use the position
1293 * of tail of the request to update the last known position
1296 ring->last_retired_head = request->tail;
1298 list_del(&request->list);
1299 i915_gem_request_remove_from_client(request);
1300 kfree(request, DRM_I915_GEM);
1303 /* Move any buffers on the active list that are no longer referenced
1304 * by the ringbuffer to the flushing/inactive lists as appropriate.
1306 while (!list_empty(&ring->active_list)) {
1307 struct drm_i915_gem_object *obj;
1309 obj = list_first_entry(&ring->active_list,
1310 struct drm_i915_gem_object,
1313 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1316 if (obj->base.write_domain != 0)
1317 i915_gem_object_move_to_flushing(obj);
1319 i915_gem_object_move_to_inactive(obj);
1322 if (unlikely(ring->trace_irq_seqno &&
1323 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1324 ring->irq_put(ring);
1325 ring->trace_irq_seqno = 0;
1331 i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
1334 i915_gem_retire_requests(struct drm_device *dev)
1336 drm_i915_private_t *dev_priv = dev->dev_private;
1337 struct drm_i915_gem_object *obj, *next;
1340 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1341 list_for_each_entry_safe(obj, next,
1342 &dev_priv->mm.deferred_free_list, mm_list)
1343 i915_gem_free_object_tail(obj);
1346 for (i = 0; i < I915_NUM_RINGS; i++)
1347 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1351 i915_gem_retire_work_handler(struct work_struct *work)
1353 drm_i915_private_t *dev_priv;
1354 struct drm_device *dev;
1355 struct intel_ring_buffer *ring;
1359 dev_priv = container_of(work, drm_i915_private_t,
1360 mm.retire_work.work);
1361 dev = dev_priv->dev;
1363 /* Come back later if the device is busy... */
1364 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
1365 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1366 round_jiffies_up_relative(hz));
1370 i915_gem_retire_requests(dev);
1372 /* Send a periodic flush down the ring so we don't hold onto GEM
1373 * objects indefinitely.
1376 for_each_ring(ring, dev_priv, i) {
1377 if (ring->gpu_caches_dirty)
1378 i915_add_request(ring, NULL, NULL);
1380 idle &= list_empty(&ring->request_list);
1383 if (!dev_priv->mm.suspended && !idle)
1384 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1385 round_jiffies_up_relative(hz));
1387 intel_mark_idle(dev);
1393 * i915_gem_object_sync - sync an object to a ring.
1395 * @obj: object which may be in use on another ring.
1396 * @to: ring we wish to use the object on. May be NULL.
1398 * This code is meant to abstract object synchronization with the GPU.
1399 * Calling with NULL implies synchronizing the object with the CPU
1400 * rather than a particular GPU ring.
1402 * Returns 0 if successful, else propagates up the lower layer error.
1405 i915_gem_object_sync(struct drm_i915_gem_object *obj,
1406 struct intel_ring_buffer *to)
1408 struct intel_ring_buffer *from = obj->ring;
1412 if (from == NULL || to == from)
1415 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
1416 return i915_gem_object_wait_rendering(obj, false);
1418 idx = intel_ring_sync_index(from, to);
1420 seqno = obj->last_read_seqno;
1421 if (seqno <= from->sync_seqno[idx])
1424 ret = i915_gem_check_olr(obj->ring, seqno);
1428 ret = to->sync_to(to, from, seqno);
1430 from->sync_seqno[idx] = seqno;
1435 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1437 u32 old_write_domain, old_read_domains;
1439 /* Act a barrier for all accesses through the GTT */
1442 /* Force a pagefault for domain tracking on next user access */
1443 i915_gem_release_mmap(obj);
1445 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
1448 old_read_domains = obj->base.read_domains;
1449 old_write_domain = obj->base.write_domain;
1451 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
1452 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
1457 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
1459 drm_i915_private_t *dev_priv;
1462 dev_priv = obj->base.dev->dev_private;
1464 if (obj->gtt_space == NULL)
1466 if (obj->pin_count != 0) {
1467 DRM_ERROR("Attempting to unbind pinned buffer\n");
1471 ret = i915_gem_object_finish_gpu(obj);
1472 if (ret == -ERESTART || ret == -EINTR)
1475 i915_gem_object_finish_gtt(obj);
1478 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1479 if (ret == -ERESTART || ret == -EINTR)
1482 i915_gem_clflush_object(obj);
1483 obj->base.read_domains = obj->base.write_domain =
1484 I915_GEM_DOMAIN_CPU;
1487 ret = i915_gem_object_put_fence(obj);
1488 if (ret == -ERESTART)
1491 i915_gem_gtt_unbind_object(obj);
1492 if (obj->has_aliasing_ppgtt_mapping) {
1493 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
1494 obj->has_aliasing_ppgtt_mapping = 0;
1496 i915_gem_object_put_pages_gtt(obj);
1498 list_del_init(&obj->gtt_list);
1499 list_del_init(&obj->mm_list);
1500 obj->map_and_fenceable = true;
1502 drm_mm_put_block(obj->gtt_space);
1503 obj->gtt_space = NULL;
1504 obj->gtt_offset = 0;
1506 if (i915_gem_object_is_purgeable(obj))
1507 i915_gem_object_truncate(obj);
1512 int i915_gpu_idle(struct drm_device *dev)
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct intel_ring_buffer *ring;
1518 /* Flush everything onto the inactive list. */
1519 for_each_ring(ring, dev_priv, i) {
1520 ret = intel_ring_idle(ring);
1528 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj)
1530 struct drm_device *dev = obj->base.dev;
1531 drm_i915_private_t *dev_priv = dev->dev_private;
1532 u32 size = obj->gtt_space->size;
1533 int regnum = obj->fence_reg;
1536 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1538 val |= obj->gtt_offset & 0xfffff000;
1539 val |= (uint64_t)((obj->stride / 128) - 1) <<
1540 SANDYBRIDGE_FENCE_PITCH_SHIFT;
1542 if (obj->tiling_mode == I915_TILING_Y)
1543 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1544 val |= I965_FENCE_REG_VALID;
1546 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
1551 static int i965_write_fence_reg(struct drm_i915_gem_object *obj)
1553 struct drm_device *dev = obj->base.dev;
1554 drm_i915_private_t *dev_priv = dev->dev_private;
1555 u32 size = obj->gtt_space->size;
1556 int regnum = obj->fence_reg;
1559 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1561 val |= obj->gtt_offset & 0xfffff000;
1562 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1563 if (obj->tiling_mode == I915_TILING_Y)
1564 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1565 val |= I965_FENCE_REG_VALID;
1567 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
1572 static int i915_write_fence_reg(struct drm_i915_gem_object *obj)
1574 struct drm_device *dev = obj->base.dev;
1575 drm_i915_private_t *dev_priv = dev->dev_private;
1576 u32 size = obj->gtt_space->size;
1577 u32 fence_reg, val, pitch_val;
1580 if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
1581 (size & -size) != size ||
1582 (obj->gtt_offset & (size - 1)),
1583 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
1584 obj->gtt_offset, obj->map_and_fenceable, size))
1587 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1592 /* Note: pitch better be a power of two tile widths */
1593 pitch_val = obj->stride / tile_width;
1594 pitch_val = ffs(pitch_val) - 1;
1596 val = obj->gtt_offset;
1597 if (obj->tiling_mode == I915_TILING_Y)
1598 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1599 val |= I915_FENCE_SIZE_BITS(size);
1600 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1601 val |= I830_FENCE_REG_VALID;
1603 fence_reg = obj->fence_reg;
1605 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
1607 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
1609 I915_WRITE(fence_reg, val);
1614 static int i830_write_fence_reg(struct drm_i915_gem_object *obj)
1616 struct drm_device *dev = obj->base.dev;
1617 drm_i915_private_t *dev_priv = dev->dev_private;
1618 u32 size = obj->gtt_space->size;
1619 int regnum = obj->fence_reg;
1623 if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
1624 (size & -size) != size ||
1625 (obj->gtt_offset & (size - 1)),
1626 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
1627 obj->gtt_offset, size))
1630 pitch_val = obj->stride / 128;
1631 pitch_val = ffs(pitch_val) - 1;
1633 val = obj->gtt_offset;
1634 if (obj->tiling_mode == I915_TILING_Y)
1635 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1636 val |= I830_FENCE_SIZE_BITS(size);
1637 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1638 val |= I830_FENCE_REG_VALID;
1640 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
1646 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
1650 if (obj->fenced_gpu_access) {
1651 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1652 ret = i915_gem_flush_ring(obj->ring,
1653 0, obj->base.write_domain);
1658 obj->fenced_gpu_access = false;
1661 if (obj->last_fenced_seqno) {
1662 ret = i915_wait_seqno(obj->ring,
1663 obj->last_fenced_seqno);
1667 obj->last_fenced_seqno = 0;
1670 /* Ensure that all CPU reads are completed before installing a fence
1671 * and all writes before removing the fence.
1673 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
1680 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
1684 if (obj->tiling_mode)
1685 i915_gem_release_mmap(obj);
1687 ret = i915_gem_object_flush_fence(obj);
1691 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1692 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1694 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count);
1695 i915_gem_clear_fence_reg(obj->base.dev,
1696 &dev_priv->fence_regs[obj->fence_reg]);
1698 obj->fence_reg = I915_FENCE_REG_NONE;
1704 static struct drm_i915_fence_reg *
1705 i915_find_fence_reg(struct drm_device *dev)
1707 struct drm_i915_private *dev_priv = dev->dev_private;
1708 struct drm_i915_fence_reg *reg, *avail;
1711 /* First try to find a free reg */
1713 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1714 reg = &dev_priv->fence_regs[i];
1718 if (!reg->pin_count)
1725 /* None available, try to steal one or wait for a user to finish */
1726 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
1737 * i915_gem_object_get_fence - set up fencing for an object
1738 * @obj: object to map through a fence reg
1740 * When mapping objects through the GTT, userspace wants to be able to write
1741 * to them without having to worry about swizzling if the object is tiled.
1742 * This function walks the fence regs looking for a free one for @obj,
1743 * stealing one if it can't find any.
1745 * It then sets up the reg based on the object's properties: address, pitch
1746 * and tiling format.
1748 * For an untiled surface, this removes any existing fence.
1751 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
1753 struct drm_device *dev = obj->base.dev;
1754 struct drm_i915_private *dev_priv = dev->dev_private;
1755 struct drm_i915_fence_reg *reg;
1758 if (obj->tiling_mode == I915_TILING_NONE)
1759 return i915_gem_object_put_fence(obj);
1761 /* Just update our place in the LRU if our fence is getting reused. */
1762 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1763 reg = &dev_priv->fence_regs[obj->fence_reg];
1764 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1766 if (obj->tiling_changed) {
1767 ret = i915_gem_object_flush_fence(obj);
1777 reg = i915_find_fence_reg(dev);
1781 ret = i915_gem_object_flush_fence(obj);
1786 struct drm_i915_gem_object *old = reg->obj;
1788 drm_gem_object_reference(&old->base);
1790 if (old->tiling_mode)
1791 i915_gem_release_mmap(old);
1793 ret = i915_gem_object_flush_fence(old);
1795 drm_gem_object_unreference(&old->base);
1799 old->fence_reg = I915_FENCE_REG_NONE;
1800 old->last_fenced_seqno = 0;
1802 drm_gem_object_unreference(&old->base);
1806 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1807 obj->fence_reg = reg - dev_priv->fence_regs;
1810 obj->tiling_changed = false;
1811 switch (INTEL_INFO(dev)->gen) {
1814 ret = sandybridge_write_fence_reg(obj);
1818 ret = i965_write_fence_reg(obj);
1821 ret = i915_write_fence_reg(obj);
1824 ret = i830_write_fence_reg(obj);
1832 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1833 unsigned alignment, bool map_and_fenceable)
1835 struct drm_device *dev;
1836 struct drm_i915_private *dev_priv;
1837 struct drm_mm_node *free_space;
1838 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1839 bool mappable, fenceable;
1842 dev = obj->base.dev;
1843 dev_priv = dev->dev_private;
1845 if (obj->madv != I915_MADV_WILLNEED) {
1846 DRM_ERROR("Attempting to bind a purgeable object\n");
1850 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1852 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1854 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1855 obj->base.size, obj->tiling_mode);
1857 alignment = map_and_fenceable ? fence_alignment :
1859 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
1860 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1864 size = map_and_fenceable ? fence_size : obj->base.size;
1866 /* If the object is bigger than the entire aperture, reject it early
1867 * before evicting everything in a vain attempt to find space.
1869 if (obj->base.size > (map_and_fenceable ?
1870 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
1872 "Attempting to bind an object larger than the aperture\n");
1877 if (map_and_fenceable)
1878 free_space = drm_mm_search_free_in_range(
1879 &dev_priv->mm.gtt_space, size, alignment, 0,
1880 dev_priv->mm.gtt_mappable_end, 0);
1882 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1883 size, alignment, 0);
1884 if (free_space != NULL) {
1886 if (map_and_fenceable)
1887 obj->gtt_space = drm_mm_get_block_range_generic(
1888 free_space, size, alignment, color, 0,
1889 dev_priv->mm.gtt_mappable_end, 1);
1891 obj->gtt_space = drm_mm_get_block_generic(free_space,
1892 size, alignment, color, 1);
1894 if (obj->gtt_space == NULL) {
1895 ret = i915_gem_evict_something(dev, size, alignment,
1903 * NOTE: i915_gem_object_get_pages_gtt() cannot
1904 * return ENOMEM, since we used VM_ALLOC_RETRY.
1906 ret = i915_gem_object_get_pages_gtt(obj, 0);
1908 drm_mm_put_block(obj->gtt_space);
1909 obj->gtt_space = NULL;
1913 i915_gem_gtt_bind_object(obj, obj->cache_level);
1915 i915_gem_object_put_pages_gtt(obj);
1916 drm_mm_put_block(obj->gtt_space);
1917 obj->gtt_space = NULL;
1918 if (i915_gem_evict_everything(dev))
1923 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
1924 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1926 obj->gtt_offset = obj->gtt_space->start;
1929 obj->gtt_space->size == fence_size &&
1930 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
1933 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
1934 obj->map_and_fenceable = mappable && fenceable;
1940 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1943 /* If we don't have a page list set up, then we're not pinned
1944 * to GPU, and we can ignore the cache flush because it'll happen
1945 * again at bind time.
1947 if (obj->pages == NULL)
1950 /* If the GPU is snooping the contents of the CPU cache,
1951 * we do not need to manually clear the CPU cache lines. However,
1952 * the caches are only snooped when the render cache is
1953 * flushed/invalidated. As we always have to emit invalidations
1954 * and flushes when moving into and out of the RENDER domain, correct
1955 * snooping behaviour occurs naturally as the result of our domain
1958 if (obj->cache_level != I915_CACHE_NONE)
1961 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1964 /** Flushes the GTT write domain for the object if it's dirty. */
1966 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1968 uint32_t old_write_domain;
1970 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1973 /* No actual flushing is required for the GTT write domain. Writes
1974 * to it immediately go to main memory as far as we know, so there's
1975 * no chipset flush. It also doesn't land in render cache.
1977 * However, we do have to enforce the order so that all writes through
1978 * the GTT land before any writes to the device, such as updates to
1983 old_write_domain = obj->base.write_domain;
1984 obj->base.write_domain = 0;
1987 /** Flushes the CPU write domain for the object if it's dirty. */
1989 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1991 uint32_t old_write_domain;
1993 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1996 i915_gem_clflush_object(obj);
1997 intel_gtt_chipset_flush();
1998 old_write_domain = obj->base.write_domain;
1999 obj->base.write_domain = 0;
2003 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2006 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2008 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
2012 * Moves a single object to the GTT read, and possibly write domain.
2014 * This function returns when the move is complete, including waiting on
2018 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2020 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2021 uint32_t old_write_domain, old_read_domains;
2024 /* Not valid to be called on unbound objects. */
2025 if (obj->gtt_space == NULL)
2028 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2031 ret = i915_gem_object_flush_gpu_write_domain(obj);
2035 ret = i915_gem_object_wait_rendering(obj, !write);
2039 i915_gem_object_flush_cpu_write_domain(obj);
2041 old_write_domain = obj->base.write_domain;
2042 old_read_domains = obj->base.read_domains;
2044 /* It should now be out of any other write domains, and we can update
2045 * the domain values for our changes.
2047 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2048 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2050 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2051 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2055 /* And bump the LRU for this access */
2056 if (i915_gem_object_is_inactive(obj))
2057 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2062 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2063 enum i915_cache_level cache_level)
2065 struct drm_device *dev = obj->base.dev;
2066 drm_i915_private_t *dev_priv = dev->dev_private;
2069 if (obj->cache_level == cache_level)
2072 if (obj->pin_count) {
2073 DRM_DEBUG("can not change the cache level of pinned objects\n");
2077 if (obj->gtt_space) {
2078 ret = i915_gem_object_finish_gpu(obj);
2082 i915_gem_object_finish_gtt(obj);
2084 /* Before SandyBridge, you could not use tiling or fence
2085 * registers with snooped memory, so relinquish any fences
2086 * currently pointing to our region in the aperture.
2088 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2089 ret = i915_gem_object_put_fence(obj);
2094 if (obj->has_global_gtt_mapping)
2095 i915_gem_gtt_bind_object(obj, cache_level);
2096 if (obj->has_aliasing_ppgtt_mapping)
2097 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2101 if (cache_level == I915_CACHE_NONE) {
2102 u32 old_read_domains, old_write_domain;
2104 /* If we're coming from LLC cached, then we haven't
2105 * actually been tracking whether the data is in the
2106 * CPU cache or not, since we only allow one bit set
2107 * in obj->write_domain and have been skipping the clflushes.
2108 * Just set it to the CPU cache for now.
2110 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2111 ("obj %p in CPU write domain", obj));
2112 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2113 ("obj %p in CPU read domain", obj));
2115 old_read_domains = obj->base.read_domains;
2116 old_write_domain = obj->base.write_domain;
2118 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2119 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2123 obj->cache_level = cache_level;
2128 * Prepare buffer for display plane (scanout, cursors, etc).
2129 * Can be called from an uninterruptible phase (modesetting) and allows
2130 * any flushes to be pipelined (for pageflips).
2133 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2135 struct intel_ring_buffer *pipelined)
2137 u32 old_read_domains, old_write_domain;
2140 ret = i915_gem_object_flush_gpu_write_domain(obj);
2144 if (pipelined != obj->ring) {
2145 ret = i915_gem_object_sync(obj, pipelined);
2150 /* The display engine is not coherent with the LLC cache on gen6. As
2151 * a result, we make sure that the pinning that is about to occur is
2152 * done with uncached PTEs. This is lowest common denominator for all
2155 * However for gen6+, we could do better by using the GFDT bit instead
2156 * of uncaching, which would allow us to flush all the LLC-cached data
2157 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2159 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2163 /* As the user may map the buffer once pinned in the display plane
2164 * (e.g. libkms for the bootup splash), we have to ensure that we
2165 * always use map_and_fenceable for all scanout buffers.
2167 ret = i915_gem_object_pin(obj, alignment, true);
2171 i915_gem_object_flush_cpu_write_domain(obj);
2173 old_write_domain = obj->base.write_domain;
2174 old_read_domains = obj->base.read_domains;
2176 /* It should now be out of any other write domains, and we can update
2177 * the domain values for our changes.
2179 obj->base.write_domain = 0;
2180 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2186 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2190 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2193 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2194 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2199 ret = i915_gem_object_wait_rendering(obj, false);
2203 /* Ensure that we invalidate the GPU's caches and TLBs. */
2204 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2209 * Moves a single object to the CPU read, and possibly write domain.
2211 * This function returns when the move is complete, including waiting on
2215 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2217 uint32_t old_write_domain, old_read_domains;
2220 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2223 ret = i915_gem_object_flush_gpu_write_domain(obj);
2227 ret = i915_gem_object_wait_rendering(obj, !write);
2231 i915_gem_object_flush_gtt_write_domain(obj);
2233 old_write_domain = obj->base.write_domain;
2234 old_read_domains = obj->base.read_domains;
2236 /* Flush the CPU cache if it's still invalid. */
2237 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2238 i915_gem_clflush_object(obj);
2240 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2243 /* It should now be out of any other write domains, and we can update
2244 * the domain values for our changes.
2246 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2248 /* If we're writing through the CPU, then the GPU read domains will
2249 * need to be invalidated at next use.
2252 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2253 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2259 /* Throttle our rendering by waiting until the ring has completed our requests
2260 * emitted over 20 msec ago.
2262 * Note that if we were to use the current jiffies each time around the loop,
2263 * we wouldn't escape the function with any frames outstanding if the time to
2264 * render a frame was over 20ms.
2266 * This should get us reasonable parallelism between CPU and GPU but also
2267 * relatively low latency when blocking on a particular request to finish.
2270 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2272 struct drm_i915_private *dev_priv = dev->dev_private;
2273 struct drm_i915_file_private *file_priv = file->driver_priv;
2274 unsigned long recent_enough = ticks - (20 * hz / 1000);
2275 struct drm_i915_gem_request *request;
2276 struct intel_ring_buffer *ring = NULL;
2280 if (atomic_read(&dev_priv->mm.wedged))
2283 spin_lock(&file_priv->mm.lock);
2284 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2285 if (time_after_eq(request->emitted_jiffies, recent_enough))
2288 ring = request->ring;
2289 seqno = request->seqno;
2291 spin_unlock(&file_priv->mm.lock);
2296 ret = __wait_seqno(ring, seqno, true, NULL);
2299 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
2305 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
2306 bool map_and_fenceable)
2308 struct drm_device *dev;
2309 struct drm_i915_private *dev_priv;
2312 dev = obj->base.dev;
2313 dev_priv = dev->dev_private;
2315 KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
2318 if (obj->gtt_space != NULL) {
2319 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
2320 (map_and_fenceable && !obj->map_and_fenceable)) {
2321 DRM_DEBUG("bo is already pinned with incorrect alignment:"
2322 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
2323 " obj->map_and_fenceable=%d\n",
2324 obj->gtt_offset, alignment,
2326 obj->map_and_fenceable);
2327 ret = i915_gem_object_unbind(obj);
2333 if (obj->gtt_space == NULL) {
2334 ret = i915_gem_object_bind_to_gtt(obj, alignment,
2340 if (obj->pin_count++ == 0 && !obj->active)
2341 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2342 obj->pin_mappable |= map_and_fenceable;
2347 WARN_ON(i915_verify_lists(dev));
2353 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
2355 struct drm_device *dev;
2356 drm_i915_private_t *dev_priv;
2358 dev = obj->base.dev;
2359 dev_priv = dev->dev_private;
2364 WARN_ON(i915_verify_lists(dev));
2367 KASSERT(obj->pin_count != 0, ("zero pin count"));
2368 KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
2370 if (--obj->pin_count == 0) {
2372 list_move_tail(&obj->mm_list,
2373 &dev_priv->mm.inactive_list);
2374 obj->pin_mappable = false;
2379 WARN_ON(i915_verify_lists(dev));
2384 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2385 struct drm_file *file)
2387 struct drm_i915_gem_pin *args;
2388 struct drm_i915_gem_object *obj;
2389 struct drm_gem_object *gobj;
2394 ret = i915_mutex_lock_interruptible(dev);
2398 gobj = drm_gem_object_lookup(dev, file, args->handle);
2403 obj = to_intel_bo(gobj);
2405 if (obj->madv != I915_MADV_WILLNEED) {
2406 DRM_ERROR("Attempting to pin a purgeable buffer\n");
2411 if (obj->pin_filp != NULL && obj->pin_filp != file) {
2412 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2418 obj->user_pin_count++;
2419 obj->pin_filp = file;
2420 if (obj->user_pin_count == 1) {
2421 ret = i915_gem_object_pin(obj, args->alignment, true);
2426 /* XXX - flush the CPU caches for pinned objects
2427 * as the X server doesn't manage domains yet
2429 i915_gem_object_flush_cpu_write_domain(obj);
2430 args->offset = obj->gtt_offset;
2432 drm_gem_object_unreference(&obj->base);
2439 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2440 struct drm_file *file)
2442 struct drm_i915_gem_pin *args;
2443 struct drm_i915_gem_object *obj;
2447 ret = i915_mutex_lock_interruptible(dev);
2451 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2452 if (&obj->base == NULL) {
2457 if (obj->pin_filp != file) {
2458 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2463 obj->user_pin_count--;
2464 if (obj->user_pin_count == 0) {
2465 obj->pin_filp = NULL;
2466 i915_gem_object_unpin(obj);
2470 drm_gem_object_unreference(&obj->base);
2477 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2478 struct drm_file *file)
2480 struct drm_i915_gem_busy *args = data;
2481 struct drm_i915_gem_object *obj;
2484 ret = i915_mutex_lock_interruptible(dev);
2488 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2489 if (&obj->base == NULL) {
2494 /* Count all active objects as busy, even if they are currently not used
2495 * by the gpu. Users of this interface expect objects to eventually
2496 * become non-busy without any further actions, therefore emit any
2497 * necessary flushes here.
2499 ret = i915_gem_object_flush_active(obj);
2501 args->busy = obj->active;
2503 args->busy |= intel_ring_flag(obj->ring) << 17;
2506 drm_gem_object_unreference(&obj->base);
2513 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2514 struct drm_file *file_priv)
2517 return (i915_gem_ring_throttle(dev, file_priv));
2521 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2522 struct drm_file *file_priv)
2524 struct drm_i915_gem_madvise *args = data;
2525 struct drm_i915_gem_object *obj;
2528 switch (args->madv) {
2529 case I915_MADV_DONTNEED:
2530 case I915_MADV_WILLNEED:
2536 ret = i915_mutex_lock_interruptible(dev);
2540 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
2541 if (&obj->base == NULL) {
2546 if (obj->pin_count) {
2551 if (obj->madv != __I915_MADV_PURGED)
2552 obj->madv = args->madv;
2554 /* if the object is no longer attached, discard its backing storage */
2555 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
2556 i915_gem_object_truncate(obj);
2558 args->retained = obj->madv != __I915_MADV_PURGED;
2561 drm_gem_object_unreference(&obj->base);
2567 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2570 struct drm_i915_private *dev_priv;
2571 struct drm_i915_gem_object *obj;
2573 dev_priv = dev->dev_private;
2575 obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
2577 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
2578 drm_free(obj, DRM_I915_GEM);
2582 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2583 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2586 obj->cache_level = I915_CACHE_LLC;
2588 obj->cache_level = I915_CACHE_NONE;
2589 obj->base.driver_private = NULL;
2590 obj->fence_reg = I915_FENCE_REG_NONE;
2591 INIT_LIST_HEAD(&obj->mm_list);
2592 INIT_LIST_HEAD(&obj->gtt_list);
2593 INIT_LIST_HEAD(&obj->ring_list);
2594 INIT_LIST_HEAD(&obj->exec_list);
2595 INIT_LIST_HEAD(&obj->gpu_write_list);
2596 obj->madv = I915_MADV_WILLNEED;
2597 /* Avoid an unnecessary call to unbind on the first bind. */
2598 obj->map_and_fenceable = true;
2600 i915_gem_info_add_obj(dev_priv, size);
2605 int i915_gem_init_object(struct drm_gem_object *obj)
2608 kprintf("i915_gem_init_object called\n");
2613 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
2615 struct drm_device *dev;
2616 drm_i915_private_t *dev_priv;
2619 dev = obj->base.dev;
2620 dev_priv = dev->dev_private;
2622 ret = i915_gem_object_unbind(obj);
2623 if (ret == -ERESTART) {
2624 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
2628 drm_gem_free_mmap_offset(&obj->base);
2629 drm_gem_object_release(&obj->base);
2630 i915_gem_info_remove_obj(dev_priv, obj->base.size);
2632 drm_free(obj->bit_17, DRM_I915_GEM);
2633 drm_free(obj, DRM_I915_GEM);
2637 i915_gem_free_object(struct drm_gem_object *gem_obj)
2639 struct drm_i915_gem_object *obj;
2640 struct drm_device *dev;
2642 obj = to_intel_bo(gem_obj);
2643 dev = obj->base.dev;
2645 while (obj->pin_count > 0)
2646 i915_gem_object_unpin(obj);
2648 if (obj->phys_obj != NULL)
2649 i915_gem_detach_phys_object(dev, obj);
2651 i915_gem_free_object_tail(obj);
2655 i915_gem_do_init(struct drm_device *dev, unsigned long start,
2656 unsigned long mappable_end, unsigned long end)
2658 drm_i915_private_t *dev_priv;
2659 unsigned long mappable;
2662 dev_priv = dev->dev_private;
2663 mappable = min(end, mappable_end) - start;
2665 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
2667 dev_priv->mm.gtt_start = start;
2668 dev_priv->mm.gtt_mappable_end = mappable_end;
2669 dev_priv->mm.gtt_end = end;
2670 dev_priv->mm.gtt_total = end - start;
2671 dev_priv->mm.mappable_gtt_total = mappable;
2673 /* Take over this portion of the GTT */
2674 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
2675 device_printf(dev->dev,
2676 "taking over the fictitious range 0x%lx-0x%lx\n",
2677 dev->agp->base + start, dev->agp->base + start + mappable);
2678 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
2679 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
2684 i915_gem_idle(struct drm_device *dev)
2686 drm_i915_private_t *dev_priv;
2689 dev_priv = dev->dev_private;
2690 if (dev_priv->mm.suspended)
2693 ret = i915_gpu_idle(dev);
2697 /* Under UMS, be paranoid and evict. */
2698 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2699 i915_gem_evict_everything(dev);
2701 i915_gem_reset_fences(dev);
2703 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2704 * We need to replace this with a semaphore, or something.
2705 * And not confound mm.suspended!
2707 dev_priv->mm.suspended = 1;
2708 del_timer_sync(&dev_priv->hangcheck_timer);
2710 i915_kernel_lost_context(dev);
2711 i915_gem_cleanup_ringbuffer(dev);
2713 /* Cancel the retire work handler, which should be idle now. */
2714 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2719 void i915_gem_l3_remap(struct drm_device *dev)
2721 drm_i915_private_t *dev_priv = dev->dev_private;
2725 if (!HAS_L3_GPU_CACHE(dev))
2728 if (!dev_priv->l3_parity.remap_info)
2731 misccpctl = I915_READ(GEN7_MISCCPCTL);
2732 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
2733 POSTING_READ(GEN7_MISCCPCTL);
2735 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
2736 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
2737 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
2738 DRM_DEBUG("0x%x was already programmed to %x\n",
2739 GEN7_L3LOG_BASE + i, remap);
2740 if (remap && !dev_priv->l3_parity.remap_info[i/4])
2741 DRM_DEBUG_DRIVER("Clearing remapped register\n");
2742 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
2745 /* Make sure all the writes land before disabling dop clock gating */
2746 POSTING_READ(GEN7_L3LOG_BASE);
2748 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
2752 i915_gem_init_swizzling(struct drm_device *dev)
2754 drm_i915_private_t *dev_priv;
2756 dev_priv = dev->dev_private;
2758 if (INTEL_INFO(dev)->gen < 5 ||
2759 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
2762 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
2763 DISP_TILE_SURFACE_SWIZZLING);
2768 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
2770 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
2772 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
2776 intel_enable_blt(struct drm_device *dev)
2783 /* The blitter was dysfunctional on early prototypes */
2784 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
2785 if (IS_GEN6(dev) && revision < 8) {
2786 DRM_INFO("BLT not supported on this pre-production hardware;"
2787 " graphics performance will be degraded.\n");
2795 i915_gem_init_hw(struct drm_device *dev)
2797 drm_i915_private_t *dev_priv = dev->dev_private;
2800 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
2801 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
2803 i915_gem_l3_remap(dev);
2805 i915_gem_init_swizzling(dev);
2807 ret = intel_init_render_ring_buffer(dev);
2812 ret = intel_init_bsd_ring_buffer(dev);
2814 goto cleanup_render_ring;
2817 if (intel_enable_blt(dev)) {
2818 ret = intel_init_blt_ring_buffer(dev);
2820 goto cleanup_bsd_ring;
2823 dev_priv->next_seqno = 1;
2826 * XXX: There was some w/a described somewhere suggesting loading
2827 * contexts before PPGTT.
2829 #if 0 /* XXX: HW context support */
2830 i915_gem_context_init(dev);
2832 i915_gem_init_ppgtt(dev);
2837 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
2838 cleanup_render_ring:
2839 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
2844 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2846 drm_i915_private_t *dev_priv;
2849 dev_priv = dev->dev_private;
2850 for (i = 0; i < I915_NUM_RINGS; i++)
2851 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
2855 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2856 struct drm_file *file_priv)
2858 drm_i915_private_t *dev_priv = dev->dev_private;
2861 if (drm_core_check_feature(dev, DRIVER_MODESET))
2864 if (atomic_read(&dev_priv->mm.wedged)) {
2865 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2866 atomic_set(&dev_priv->mm.wedged, 0);
2870 dev_priv->mm.suspended = 0;
2872 ret = i915_gem_init_hw(dev);
2878 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
2881 ret = drm_irq_install(dev);
2883 goto cleanup_ringbuffer;
2889 i915_gem_cleanup_ringbuffer(dev);
2890 dev_priv->mm.suspended = 1;
2897 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2898 struct drm_file *file_priv)
2901 if (drm_core_check_feature(dev, DRIVER_MODESET))
2904 drm_irq_uninstall(dev);
2905 return (i915_gem_idle(dev));
2909 i915_gem_lastclose(struct drm_device *dev)
2913 if (drm_core_check_feature(dev, DRIVER_MODESET))
2916 ret = i915_gem_idle(dev);
2918 DRM_ERROR("failed to idle hardware: %d\n", ret);
2922 init_ring_lists(struct intel_ring_buffer *ring)
2925 INIT_LIST_HEAD(&ring->active_list);
2926 INIT_LIST_HEAD(&ring->request_list);
2927 INIT_LIST_HEAD(&ring->gpu_write_list);
2931 i915_gem_load(struct drm_device *dev)
2934 drm_i915_private_t *dev_priv = dev->dev_private;
2936 INIT_LIST_HEAD(&dev_priv->mm.active_list);
2937 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2938 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2939 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
2940 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2941 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
2942 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
2943 for (i = 0; i < I915_NUM_RINGS; i++)
2944 init_ring_lists(&dev_priv->ring[i]);
2945 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
2946 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
2947 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2948 i915_gem_retire_work_handler);
2949 init_completion(&dev_priv->error_completion);
2951 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
2953 I915_WRITE(MI_ARB_STATE,
2954 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
2957 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
2959 /* Old X drivers will take 0-2 for front, back, depth buffers */
2960 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2961 dev_priv->fence_reg_start = 3;
2963 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2964 dev_priv->num_fence_regs = 16;
2966 dev_priv->num_fence_regs = 8;
2968 /* Initialize fence registers to zero */
2969 i915_gem_reset_fences(dev);
2971 i915_gem_detect_bit_6_swizzle(dev);
2973 dev_priv->mm.interruptible = true;
2975 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
2976 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
2980 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
2982 drm_i915_private_t *dev_priv;
2983 struct drm_i915_gem_phys_object *phys_obj;
2986 dev_priv = dev->dev_private;
2987 if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
2990 phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
2995 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
2996 if (phys_obj->handle == NULL) {
3000 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3001 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3003 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3008 drm_free(phys_obj, DRM_I915_GEM);
3013 i915_gem_free_phys_object(struct drm_device *dev, int id)
3015 drm_i915_private_t *dev_priv;
3016 struct drm_i915_gem_phys_object *phys_obj;
3018 dev_priv = dev->dev_private;
3019 if (dev_priv->mm.phys_objs[id - 1] == NULL)
3022 phys_obj = dev_priv->mm.phys_objs[id - 1];
3023 if (phys_obj->cur_obj != NULL)
3024 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3026 drm_pci_free(dev, phys_obj->handle);
3027 drm_free(phys_obj, DRM_I915_GEM);
3028 dev_priv->mm.phys_objs[id - 1] = NULL;
3032 i915_gem_free_all_phys_object(struct drm_device *dev)
3036 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3037 i915_gem_free_phys_object(dev, i);
3041 i915_gem_detach_phys_object(struct drm_device *dev,
3042 struct drm_i915_gem_object *obj)
3049 if (obj->phys_obj == NULL)
3051 vaddr = obj->phys_obj->handle->vaddr;
3053 page_count = obj->base.size / PAGE_SIZE;
3054 VM_OBJECT_LOCK(obj->base.vm_obj);
3055 for (i = 0; i < page_count; i++) {
3056 m = i915_gem_wire_page(obj->base.vm_obj, i);
3060 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3061 sf = sf_buf_alloc(m);
3063 dst = (char *)sf_buf_kva(sf);
3064 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3067 drm_clflush_pages(&m, 1);
3069 VM_OBJECT_LOCK(obj->base.vm_obj);
3070 vm_page_reference(m);
3072 vm_page_busy_wait(m, FALSE, "i915gem");
3073 vm_page_unwire(m, 0);
3075 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3077 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3078 intel_gtt_chipset_flush();
3080 obj->phys_obj->cur_obj = NULL;
3081 obj->phys_obj = NULL;
3085 i915_gem_attach_phys_object(struct drm_device *dev,
3086 struct drm_i915_gem_object *obj,
3090 drm_i915_private_t *dev_priv;
3094 int i, page_count, ret;
3096 if (id > I915_MAX_PHYS_OBJECT)
3099 if (obj->phys_obj != NULL) {
3100 if (obj->phys_obj->id == id)
3102 i915_gem_detach_phys_object(dev, obj);
3105 dev_priv = dev->dev_private;
3106 if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3107 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3109 DRM_ERROR("failed to init phys object %d size: %zu\n",
3110 id, obj->base.size);
3115 /* bind to the object */
3116 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3117 obj->phys_obj->cur_obj = obj;
3119 page_count = obj->base.size / PAGE_SIZE;
3121 VM_OBJECT_LOCK(obj->base.vm_obj);
3123 for (i = 0; i < page_count; i++) {
3124 m = i915_gem_wire_page(obj->base.vm_obj, i);
3129 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3130 sf = sf_buf_alloc(m);
3131 src = (char *)sf_buf_kva(sf);
3132 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3133 memcpy(dst, src, PAGE_SIZE);
3136 VM_OBJECT_LOCK(obj->base.vm_obj);
3138 vm_page_reference(m);
3139 vm_page_busy_wait(m, FALSE, "i915gem");
3140 vm_page_unwire(m, 0);
3142 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3144 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3150 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3151 uint64_t data_ptr, uint64_t offset, uint64_t size,
3152 struct drm_file *file_priv)
3154 char *user_data, *vaddr;
3157 vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3158 user_data = (char *)(uintptr_t)data_ptr;
3160 if (copyin_nofault(user_data, vaddr, size) != 0) {
3161 /* The physical object once assigned is fixed for the lifetime
3162 * of the obj, so we can safely drop the lock and continue
3166 ret = -copyin(user_data, vaddr, size);
3172 intel_gtt_chipset_flush();
3177 i915_gem_release(struct drm_device *dev, struct drm_file *file)
3179 struct drm_i915_file_private *file_priv;
3180 struct drm_i915_gem_request *request;
3182 file_priv = file->driver_priv;
3184 /* Clean up our request list when the client is going away, so that
3185 * later retire_requests won't dereference our soon-to-be-gone
3188 spin_lock(&file_priv->mm.lock);
3189 while (!list_empty(&file_priv->mm.request_list)) {
3190 request = list_first_entry(&file_priv->mm.request_list,
3191 struct drm_i915_gem_request,
3193 list_del(&request->client_list);
3194 request->file_priv = NULL;
3196 spin_unlock(&file_priv->mm.lock);
3200 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
3201 uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
3202 struct drm_file *file)
3209 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
3211 if (obj->gtt_offset != 0 && rw == UIO_READ)
3212 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
3214 do_bit17_swizzling = 0;
3217 vm_obj = obj->base.vm_obj;
3220 VM_OBJECT_LOCK(vm_obj);
3221 vm_object_pip_add(vm_obj, 1);
3223 obj_pi = OFF_TO_IDX(offset);
3224 obj_po = offset & PAGE_MASK;
3226 m = i915_gem_wire_page(vm_obj, obj_pi);
3227 VM_OBJECT_UNLOCK(vm_obj);
3229 sf = sf_buf_alloc(m);
3230 mkva = sf_buf_kva(sf);
3231 length = min(size, PAGE_SIZE - obj_po);
3232 while (length > 0) {
3233 if (do_bit17_swizzling &&
3234 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
3235 cnt = roundup2(obj_po + 1, 64);
3236 cnt = min(cnt - obj_po, length);
3237 swizzled_po = obj_po ^ 64;
3240 swizzled_po = obj_po;
3243 ret = -copyout_nofault(
3244 (char *)mkva + swizzled_po,
3245 (void *)(uintptr_t)data_ptr, cnt);
3247 ret = -copyin_nofault(
3248 (void *)(uintptr_t)data_ptr,
3249 (char *)mkva + swizzled_po, cnt);
3259 VM_OBJECT_LOCK(vm_obj);
3260 if (rw == UIO_WRITE)
3262 vm_page_reference(m);
3263 vm_page_busy_wait(m, FALSE, "i915gem");
3264 vm_page_unwire(m, 1);
3266 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3271 vm_object_pip_wakeup(vm_obj);
3272 VM_OBJECT_UNLOCK(vm_obj);
3278 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
3279 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
3285 * Pass the unaligned physical address and size to pmap_mapdev_attr()
3286 * so it can properly calculate whether an extra page needs to be
3287 * mapped or not to cover the requested range. The function will
3288 * add the page offset into the returned mkva for us.
3290 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
3291 offset, size, PAT_WRITE_COMBINING);
3292 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
3293 pmap_unmapdev(mkva, size);
3298 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
3299 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
3301 struct drm_i915_gem_object *obj;
3303 vm_offset_t start, end;
3308 start = trunc_page(data_ptr);
3309 end = round_page(data_ptr + size);
3310 npages = howmany(end - start, PAGE_SIZE);
3311 ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
3313 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
3314 (vm_offset_t)data_ptr, size,
3315 (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
3321 ret = i915_mutex_lock_interruptible(dev);
3325 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
3326 if (&obj->base == NULL) {
3330 if (offset > obj->base.size || size > obj->base.size - offset) {
3335 if (rw == UIO_READ) {
3336 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3339 if (obj->phys_obj) {
3340 ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
3342 } else if (obj->gtt_space &&
3343 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
3344 ret = i915_gem_object_pin(obj, 0, true);
3347 ret = i915_gem_object_set_to_gtt_domain(obj, true);
3350 ret = i915_gem_object_put_fence(obj);
3353 ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
3356 i915_gem_object_unpin(obj);
3358 ret = i915_gem_object_set_to_cpu_domain(obj, true);
3361 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3366 drm_gem_object_unreference(&obj->base);
3370 vm_page_unhold_pages(ma, npages);
3372 drm_free(ma, DRM_I915_GEM);
3377 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
3378 vm_ooffset_t foff, struct ucred *cred, u_short *color)
3381 *color = 0; /* XXXKIB */
3388 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
3391 struct drm_gem_object *gem_obj;
3392 struct drm_i915_gem_object *obj;
3393 struct drm_device *dev;
3394 drm_i915_private_t *dev_priv;
3399 gem_obj = vm_obj->handle;
3400 obj = to_intel_bo(gem_obj);
3401 dev = obj->base.dev;
3402 dev_priv = dev->dev_private;
3404 write = (prot & VM_PROT_WRITE) != 0;
3408 vm_object_pip_add(vm_obj, 1);
3411 * Remove the placeholder page inserted by vm_fault() from the
3412 * object before dropping the object lock. If
3413 * i915_gem_release_mmap() is active in parallel on this gem
3414 * object, then it owns the drm device sx and might find the
3415 * placeholder already. Then, since the page is busy,
3416 * i915_gem_release_mmap() sleeps waiting for the busy state
3417 * of the page cleared. We will be not able to acquire drm
3418 * device lock until i915_gem_release_mmap() is able to make a
3421 if (*mres != NULL) {
3423 vm_page_remove(oldm);
3428 VM_OBJECT_UNLOCK(vm_obj);
3434 ret = i915_mutex_lock_interruptible(dev);
3443 * Since the object lock was dropped, other thread might have
3444 * faulted on the same GTT address and instantiated the
3445 * mapping for the page. Recheck.
3447 VM_OBJECT_LOCK(vm_obj);
3448 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
3450 if ((m->flags & PG_BUSY) != 0) {
3453 vm_page_sleep(m, "915pee");
3459 VM_OBJECT_UNLOCK(vm_obj);
3461 /* Now bind it into the GTT if needed */
3462 if (!obj->map_and_fenceable) {
3463 ret = i915_gem_object_unbind(obj);
3469 if (!obj->gtt_space) {
3470 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
3476 ret = i915_gem_object_set_to_gtt_domain(obj, write);
3483 if (obj->tiling_mode == I915_TILING_NONE)
3484 ret = i915_gem_object_put_fence(obj);
3486 ret = i915_gem_object_get_fence(obj);
3492 if (i915_gem_object_is_inactive(obj))
3493 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3495 obj->fault_mappable = true;
3496 VM_OBJECT_LOCK(vm_obj);
3497 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
3504 KASSERT((m->flags & PG_FICTITIOUS) != 0,
3505 ("not fictitious %p", m));
3506 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
3508 if ((m->flags & PG_BUSY) != 0) {
3511 vm_page_sleep(m, "915pbs");
3515 m->valid = VM_PAGE_BITS_ALL;
3516 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
3519 vm_page_busy_try(m, false);
3525 vm_object_pip_wakeup(vm_obj);
3526 return (VM_PAGER_OK);
3531 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
3532 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
3533 goto unlocked_vmobj;
3535 VM_OBJECT_LOCK(vm_obj);
3536 vm_object_pip_wakeup(vm_obj);
3537 return (VM_PAGER_ERROR);
3541 i915_gem_pager_dtor(void *handle)
3543 struct drm_gem_object *obj;
3544 struct drm_device *dev;
3550 drm_gem_free_mmap_offset(obj);
3551 i915_gem_release_mmap(to_intel_bo(obj));
3552 drm_gem_object_unreference(obj);
3556 struct cdev_pager_ops i915_gem_pager_ops = {
3557 .cdev_pg_fault = i915_gem_pager_fault,
3558 .cdev_pg_ctor = i915_gem_pager_ctor,
3559 .cdev_pg_dtor = i915_gem_pager_dtor
3562 #define GEM_PARANOID_CHECK_GTT 0
3563 #if GEM_PARANOID_CHECK_GTT
3565 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
3568 struct drm_i915_private *dev_priv;
3570 unsigned long start, end;
3574 dev_priv = dev->dev_private;
3575 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
3576 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
3577 for (i = start; i < end; i++) {
3578 pa = intel_gtt_read_pte_paddr(i);
3579 for (j = 0; j < page_count; j++) {
3580 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
3581 panic("Page %p in GTT pte index %d pte %x",
3582 ma[i], i, intel_gtt_read_pte(i));
3590 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
3591 uint32_t flush_domains)
3593 struct drm_i915_gem_object *obj, *next;
3594 uint32_t old_write_domain;
3596 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
3598 if (obj->base.write_domain & flush_domains) {
3599 old_write_domain = obj->base.write_domain;
3600 obj->base.write_domain = 0;
3601 list_del_init(&obj->gpu_write_list);
3602 i915_gem_object_move_to_active(obj, ring,
3603 i915_gem_next_request_seqno(ring));
3608 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
3611 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
3616 VM_OBJECT_LOCK_ASSERT_OWNED(object);
3617 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
3618 if (m->valid != VM_PAGE_BITS_ALL) {
3619 if (vm_pager_has_page(object, pindex)) {
3620 rv = vm_pager_get_page(object, &m, 1);
3621 m = vm_page_lookup(object, pindex);
3624 if (rv != VM_PAGER_OK) {
3629 pmap_zero_page(VM_PAGE_TO_PHYS(m));
3630 m->valid = VM_PAGE_BITS_ALL;
3636 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
3641 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
3642 uint32_t flush_domains)
3646 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
3649 ret = ring->flush(ring, invalidate_domains, flush_domains);
3653 if (flush_domains & I915_GEM_GPU_DOMAINS)
3654 i915_gem_process_flushing_list(ring, flush_domains);
3659 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
3661 if (ring->outstanding_lazy_request == 0)
3662 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
3664 return ring->outstanding_lazy_request;
3668 * i915_gem_clear_fence_reg - clear out fence register info
3669 * @obj: object to clear
3671 * Zeroes out the fence register itself and clears out the associated
3672 * data structures in dev_priv and obj.
3675 i915_gem_clear_fence_reg(struct drm_device *dev,
3676 struct drm_i915_fence_reg *reg)
3678 drm_i915_private_t *dev_priv = dev->dev_private;
3679 uint32_t fence_reg = reg - dev_priv->fence_regs;
3681 switch (INTEL_INFO(dev)->gen) {
3684 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3688 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3692 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3695 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3697 I915_WRITE(fence_reg, 0);
3701 list_del_init(®->lru_list);
3707 i915_gpu_is_active(struct drm_device *dev)
3709 drm_i915_private_t *dev_priv;
3711 dev_priv = dev->dev_private;
3712 return (!list_empty(&dev_priv->mm.flushing_list) ||
3713 !list_empty(&dev_priv->mm.active_list));
3717 i915_gem_lowmem(void *arg)
3719 struct drm_device *dev;
3720 struct drm_i915_private *dev_priv;
3721 struct drm_i915_gem_object *obj, *next;
3722 int cnt, cnt_fail, cnt_total;
3725 dev_priv = dev->dev_private;
3727 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3731 /* first scan for clean buffers */
3732 i915_gem_retire_requests(dev);
3734 cnt_total = cnt_fail = cnt = 0;
3736 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3738 if (i915_gem_object_is_purgeable(obj)) {
3739 if (i915_gem_object_unbind(obj) != 0)
3745 /* second pass, evict/count anything still on the inactive list */
3746 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3748 if (i915_gem_object_unbind(obj) == 0)
3754 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3756 * We are desperate for pages, so as a last resort, wait
3757 * for the GPU to finish and discard whatever we can.
3758 * This has a dramatic impact to reduce the number of
3759 * OOM-killer events whilst running the GPU aggressively.
3761 if (i915_gpu_idle(dev) == 0)
3768 i915_gem_unload(struct drm_device *dev)
3770 struct drm_i915_private *dev_priv;
3772 dev_priv = dev->dev_private;
3773 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);