2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
59 #include <drm/i915_drm.h>
61 #include "intel_drv.h"
62 #include <linux/shmem_fs.h>
63 #include <linux/completion.h>
64 #include <linux/highmem.h>
65 #include <linux/jiffies.h>
66 #include <linux/time.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
70 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
72 bool map_and_fenceable,
74 static int i915_gem_phys_pwrite(struct drm_device *dev,
75 struct drm_i915_gem_object *obj,
76 struct drm_i915_gem_pwrite *args,
77 struct drm_file *file);
79 static void i915_gem_write_fence(struct drm_device *dev, int reg,
80 struct drm_i915_gem_object *obj);
81 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
82 struct drm_i915_fence_reg *fence,
85 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
87 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
88 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
90 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
93 i915_gem_release_mmap(obj);
95 /* As we do not have an associated fence register, we will force
96 * a tiling change if we ever need to acquire one.
98 obj->fence_dirty = false;
99 obj->fence_reg = I915_FENCE_REG_NONE;
102 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
103 static void i915_gem_lowmem(void *arg);
105 /* some bookkeeping */
106 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
109 dev_priv->mm.object_count++;
110 dev_priv->mm.object_memory += size;
113 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
116 dev_priv->mm.object_count--;
117 dev_priv->mm.object_memory -= size;
121 i915_gem_wait_for_error(struct i915_gpu_error *error)
125 #define EXIT_COND (!i915_reset_in_progress(error) || \
126 i915_terminally_wedged(error))
131 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
132 * userspace. If it takes that long something really bad is going on and
133 * we should simply try to bail out and fail as gracefully as possible.
135 ret = wait_event_interruptible_timeout(error->reset_queue,
139 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
141 } else if (ret < 0) {
149 int i915_mutex_lock_interruptible(struct drm_device *dev)
151 struct drm_i915_private *dev_priv = dev->dev_private;
154 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
158 ret = lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
162 WARN_ON(i915_verify_lists(dev));
167 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
173 i915_gem_init_ioctl(struct drm_device *dev, void *data,
174 struct drm_file *file)
176 struct drm_i915_gem_init *args = data;
178 if (drm_core_check_feature(dev, DRIVER_MODESET))
181 if (args->gtt_start >= args->gtt_end ||
182 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
185 /* GEM with user mode setting was never supported on ilk and later. */
186 if (INTEL_INFO(dev)->gen >= 5)
189 mutex_lock(&dev->struct_mutex);
190 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
192 mutex_unlock(&dev->struct_mutex);
198 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
199 struct drm_file *file)
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct drm_i915_gem_get_aperture *args = data;
203 struct drm_i915_gem_object *obj;
207 mutex_lock(&dev->struct_mutex);
208 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
210 pinned += obj->gtt_space->size;
211 mutex_unlock(&dev->struct_mutex);
213 args->aper_size = dev_priv->gtt.total;
214 args->aper_available_size = args->aper_size - pinned;
219 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 i915_gem_create(struct drm_file *file,
226 struct drm_device *dev,
230 struct drm_i915_gem_object *obj;
234 size = roundup(size, PAGE_SIZE);
238 /* Allocate the new object */
239 obj = i915_gem_alloc_object(dev, size);
244 ret = drm_gem_handle_create(file, &obj->base, &handle);
246 drm_gem_object_release(&obj->base);
247 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
248 drm_free(obj, M_DRM);
252 /* drop reference from allocate - handle holds it now */
253 drm_gem_object_unreference(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
264 /* have to work out size/pitch and return them */
265 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
266 args->size = args->pitch * args->height;
267 return i915_gem_create(file, dev,
268 args->size, &args->handle);
271 int i915_gem_dumb_destroy(struct drm_file *file,
272 struct drm_device *dev,
276 return drm_gem_handle_delete(file, handle);
280 * Creates a new mm object and returns a handle to it.
283 i915_gem_create_ioctl(struct drm_device *dev, void *data,
284 struct drm_file *file)
286 struct drm_i915_gem_create *args = data;
288 return i915_gem_create(file, dev,
289 args->size, &args->handle);
292 static inline void vm_page_reference(vm_page_t m)
294 vm_page_flag_set(m, PG_REFERENCED);
298 i915_gem_shmem_pread(struct drm_device *dev,
299 struct drm_i915_gem_object *obj,
300 struct drm_i915_gem_pread *args,
301 struct drm_file *file)
308 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
310 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
313 vm_obj = obj->base.vm_obj;
316 VM_OBJECT_LOCK(vm_obj);
317 vm_object_pip_add(vm_obj, 1);
318 while (args->size > 0) {
319 obj_pi = OFF_TO_IDX(args->offset);
320 obj_po = args->offset & PAGE_MASK;
322 m = shmem_read_mapping_page(vm_obj, obj_pi);
323 VM_OBJECT_UNLOCK(vm_obj);
325 sf = sf_buf_alloc(m);
326 mkva = sf_buf_kva(sf);
327 length = min(args->size, PAGE_SIZE - obj_po);
329 if (do_bit17_swizzling &&
330 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
331 cnt = roundup2(obj_po + 1, 64);
332 cnt = min(cnt - obj_po, length);
333 swizzled_po = obj_po ^ 64;
336 swizzled_po = obj_po;
338 ret = -copyout_nofault(
339 (char *)mkva + swizzled_po,
340 (void *)(uintptr_t)args->data_ptr, cnt);
343 args->data_ptr += cnt;
350 VM_OBJECT_LOCK(vm_obj);
351 vm_page_reference(m);
352 vm_page_busy_wait(m, FALSE, "i915gem");
353 vm_page_unwire(m, 1);
359 vm_object_pip_wakeup(vm_obj);
360 VM_OBJECT_UNLOCK(vm_obj);
366 * Reads data from the object referenced by handle.
368 * On error, the contents of *data are undefined.
371 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
372 struct drm_file *file)
374 struct drm_i915_gem_pread *args = data;
375 struct drm_i915_gem_object *obj;
381 ret = i915_mutex_lock_interruptible(dev);
385 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
386 if (&obj->base == NULL) {
391 /* Bounds check source. */
392 if (args->offset > obj->base.size ||
393 args->size > obj->base.size - args->offset) {
398 ret = i915_gem_shmem_pread(dev, obj, args, file);
400 drm_gem_object_unreference(&obj->base);
402 mutex_unlock(&dev->struct_mutex);
407 /* This is the fast write path which cannot handle
408 * page faults in the source data
412 fast_user_write(struct io_mapping *mapping,
413 loff_t page_base, int page_offset,
414 char __user *user_data,
417 void __iomem *vaddr_atomic;
419 unsigned long unwritten;
421 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
422 /* We can use the cpu mem copy function because this is X86. */
423 vaddr = (void __force*)vaddr_atomic + page_offset;
424 unwritten = __copy_from_user_inatomic_nocache(vaddr,
426 io_mapping_unmap_atomic(vaddr_atomic);
431 * This is the fast pwrite path, where we copy the data directly from the
432 * user into the GTT, uncached.
435 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
436 struct drm_i915_gem_object *obj,
437 struct drm_i915_gem_pwrite *args,
438 struct drm_file *file)
440 drm_i915_private_t *dev_priv = dev->dev_private;
442 loff_t offset, page_base;
443 char __user *user_data;
444 int page_offset, page_length, ret;
446 ret = i915_gem_object_pin(obj, 0, true, true);
450 ret = i915_gem_object_set_to_gtt_domain(obj, true);
454 ret = i915_gem_object_put_fence(obj);
458 user_data = to_user_ptr(args->data_ptr);
461 offset = obj->gtt_offset + args->offset;
464 /* Operation in this page
466 * page_base = page offset within aperture
467 * page_offset = offset within page
468 * page_length = bytes to copy for this page
470 page_base = offset & PAGE_MASK;
471 page_offset = offset_in_page(offset);
472 page_length = remain;
473 if ((page_offset + remain) > PAGE_SIZE)
474 page_length = PAGE_SIZE - page_offset;
476 /* If we get a fault while copying data, then (presumably) our
477 * source page isn't available. Return the error and we'll
478 * retry in the slow path.
480 if (fast_user_write(dev_priv->gtt.mappable, page_base,
481 page_offset, user_data, page_length)) {
486 remain -= page_length;
487 user_data += page_length;
488 offset += page_length;
492 i915_gem_object_unpin(obj);
499 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
500 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
506 * Pass the unaligned physical address and size to pmap_mapdev_attr()
507 * so it can properly calculate whether an extra page needs to be
508 * mapped or not to cover the requested range. The function will
509 * add the page offset into the returned mkva for us.
511 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
512 offset, size, PAT_WRITE_COMBINING);
513 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
514 pmap_unmapdev(mkva, size);
519 i915_gem_shmem_pwrite(struct drm_device *dev,
520 struct drm_i915_gem_object *obj,
521 struct drm_i915_gem_pwrite *args,
522 struct drm_file *file)
529 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
531 do_bit17_swizzling = 0;
534 vm_obj = obj->base.vm_obj;
537 VM_OBJECT_LOCK(vm_obj);
538 vm_object_pip_add(vm_obj, 1);
539 while (args->size > 0) {
540 obj_pi = OFF_TO_IDX(args->offset);
541 obj_po = args->offset & PAGE_MASK;
543 m = shmem_read_mapping_page(vm_obj, obj_pi);
544 VM_OBJECT_UNLOCK(vm_obj);
546 sf = sf_buf_alloc(m);
547 mkva = sf_buf_kva(sf);
548 length = min(args->size, PAGE_SIZE - obj_po);
550 if (do_bit17_swizzling &&
551 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
552 cnt = roundup2(obj_po + 1, 64);
553 cnt = min(cnt - obj_po, length);
554 swizzled_po = obj_po ^ 64;
557 swizzled_po = obj_po;
559 ret = -copyin_nofault(
560 (void *)(uintptr_t)args->data_ptr,
561 (char *)mkva + swizzled_po, cnt);
564 args->data_ptr += cnt;
571 VM_OBJECT_LOCK(vm_obj);
573 vm_page_reference(m);
574 vm_page_busy_wait(m, FALSE, "i915gem");
575 vm_page_unwire(m, 1);
581 vm_object_pip_wakeup(vm_obj);
582 VM_OBJECT_UNLOCK(vm_obj);
588 * Writes data to the object referenced by handle.
590 * On error, the contents of the buffer that were to be modified are undefined.
593 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
594 struct drm_file *file)
596 struct drm_i915_gem_pwrite *args = data;
597 struct drm_i915_gem_object *obj;
599 vm_offset_t start, end;
605 start = trunc_page(args->data_ptr);
606 end = round_page(args->data_ptr + args->size);
607 npages = howmany(end - start, PAGE_SIZE);
608 ma = kmalloc(npages * sizeof(vm_page_t), M_DRM, M_WAITOK |
610 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
611 (vm_offset_t)args->data_ptr, args->size,
612 VM_PROT_READ, ma, npages);
618 ret = i915_mutex_lock_interruptible(dev);
622 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
623 if (&obj->base == NULL) {
628 /* Bounds check destination. */
629 if (args->offset > obj->base.size ||
630 args->size > obj->base.size - args->offset) {
636 ret = i915_gem_phys_pwrite(dev, obj, args, file);
637 } else if (obj->gtt_space &&
638 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
639 ret = i915_gem_object_pin(obj, 0, true, false);
642 ret = i915_gem_object_set_to_gtt_domain(obj, true);
645 ret = i915_gem_object_put_fence(obj);
648 ret = i915_gem_gtt_write(dev, obj, args->data_ptr, args->size,
651 i915_gem_object_unpin(obj);
653 ret = i915_gem_object_set_to_cpu_domain(obj, true);
656 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
659 drm_gem_object_unreference(&obj->base);
661 mutex_unlock(&dev->struct_mutex);
663 vm_page_unhold_pages(ma, npages);
670 i915_gem_check_wedge(struct i915_gpu_error *error,
673 if (i915_reset_in_progress(error)) {
674 /* Non-interruptible callers can't handle -EAGAIN, hence return
675 * -EIO unconditionally for these. */
679 /* Recovery complete, but the reset failed ... */
680 if (i915_terminally_wedged(error))
690 * Compare seqno against outstanding lazy request. Emit a request if they are
694 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
698 DRM_LOCK_ASSERT(ring->dev);
701 if (seqno == ring->outstanding_lazy_request)
702 ret = i915_add_request(ring, NULL);
708 * __wait_seqno - wait until execution of seqno has finished
709 * @ring: the ring expected to report seqno
711 * @reset_counter: reset sequence associated with the given seqno
712 * @interruptible: do an interruptible wait (normally yes)
713 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
715 * Note: It is of utmost importance that the passed in seqno and reset_counter
716 * values have been read by the caller in an smp safe manner. Where read-side
717 * locks are involved, it is sufficient to read the reset_counter before
718 * unlocking the lock that protects the seqno. For lockless tricks, the
719 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
722 * Returns 0 if the seqno was found within the alloted time. Else returns the
723 * errno with remaining time filled in timeout argument.
725 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
726 unsigned reset_counter,
727 bool interruptible, struct timespec *timeout)
729 drm_i915_private_t *dev_priv = ring->dev->dev_private;
730 struct timespec before, now, wait_time={1,0};
731 unsigned long timeout_jiffies;
733 bool wait_forever = true;
736 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
739 if (timeout != NULL) {
740 wait_time = *timeout;
741 wait_forever = false;
744 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
746 if (WARN_ON(!ring->irq_get(ring)))
749 /* Record current time in case interrupted by signal, or wedged * */
750 getrawmonotonic(&before);
753 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
754 i915_reset_in_progress(&dev_priv->gpu_error) || \
755 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
758 end = wait_event_interruptible_timeout(ring->irq_queue,
762 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
765 /* We need to check whether any gpu reset happened in between
766 * the caller grabbing the seqno and now ... */
767 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
770 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
772 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
775 } while (end == 0 && wait_forever);
777 getrawmonotonic(&now);
783 struct timespec sleep_time = timespec_sub(now, before);
784 *timeout = timespec_sub(*timeout, sleep_time);
785 if (!timespec_valid(timeout)) /* i.e. negative time remains */
786 set_normalized_timespec(timeout, 0, 0);
791 case -EAGAIN: /* Wedged */
792 case -ERESTARTSYS: /* Signal */
794 case 0: /* Timeout */
795 return -ETIMEDOUT; /* -ETIME on Linux */
796 default: /* Completed */
797 WARN_ON(end < 0); /* We're not aware of other errors */
803 * Waits for a sequence number to be signaled, and cleans up the
804 * request and object lists appropriately for that event.
807 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
809 struct drm_device *dev = ring->dev;
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 bool interruptible = dev_priv->mm.interruptible;
814 DRM_LOCK_ASSERT(dev);
817 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
821 ret = i915_gem_check_olr(ring, seqno);
825 return __wait_seqno(ring, seqno,
826 atomic_read(&dev_priv->gpu_error.reset_counter),
827 interruptible, NULL);
831 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
832 struct intel_ring_buffer *ring)
834 i915_gem_retire_requests_ring(ring);
836 /* Manually manage the write flush as we may have not yet
837 * retired the buffer.
839 * Note that the last_write_seqno is always the earlier of
840 * the two (read/write) seqno, so if we haved successfully waited,
841 * we know we have passed the last write.
843 obj->last_write_seqno = 0;
844 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
850 * Ensures that all rendering to the object has completed and the object is
851 * safe to unbind from the GTT or access from the CPU.
853 static __must_check int
854 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
857 struct intel_ring_buffer *ring = obj->ring;
861 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
865 ret = i915_wait_seqno(ring, seqno);
869 return i915_gem_object_wait_rendering__tail(obj, ring);
872 /* A nonblocking variant of the above wait. This is a highly dangerous routine
873 * as the object state may change during this call.
875 static __must_check int
876 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
879 struct drm_device *dev = obj->base.dev;
880 struct drm_i915_private *dev_priv = dev->dev_private;
881 struct intel_ring_buffer *ring = obj->ring;
882 unsigned reset_counter;
886 DRM_LOCK_ASSERT(dev);
887 BUG_ON(!dev_priv->mm.interruptible);
889 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
893 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
897 ret = i915_gem_check_olr(ring, seqno);
901 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
902 mutex_unlock(&dev->struct_mutex);
903 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
904 mutex_lock(&dev->struct_mutex);
908 return i915_gem_object_wait_rendering__tail(obj, ring);
912 * Called when user space prepares to use an object with the CPU, either
913 * through the mmap ioctl's mapping or a GTT mapping.
916 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
917 struct drm_file *file)
919 struct drm_i915_gem_set_domain *args = data;
920 struct drm_i915_gem_object *obj;
921 uint32_t read_domains = args->read_domains;
922 uint32_t write_domain = args->write_domain;
925 /* Only handle setting domains to types used by the CPU. */
926 if (write_domain & I915_GEM_GPU_DOMAINS)
929 if (read_domains & I915_GEM_GPU_DOMAINS)
932 /* Having something in the write domain implies it's in the read
933 * domain, and only that read domain. Enforce that in the request.
935 if (write_domain != 0 && read_domains != write_domain)
938 ret = i915_mutex_lock_interruptible(dev);
942 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
943 if (&obj->base == NULL) {
948 /* Try to flush the object off the GPU without holding the lock.
949 * We will repeat the flush holding the lock in the normal manner
950 * to catch cases where we are gazumped.
952 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
956 if (read_domains & I915_GEM_DOMAIN_GTT) {
957 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
959 /* Silently promote "you're not bound, there was nothing to do"
960 * to success, since the client was just asking us to
961 * make sure everything was done.
966 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
970 drm_gem_object_unreference(&obj->base);
972 mutex_unlock(&dev->struct_mutex);
977 * Called when user space has done writes to this buffer
980 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file)
983 struct drm_i915_gem_sw_finish *args = data;
984 struct drm_i915_gem_object *obj;
987 ret = i915_mutex_lock_interruptible(dev);
990 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
991 if (&obj->base == NULL) {
996 /* Pinned buffers may be scanout, so flush the cache */
998 i915_gem_object_flush_cpu_write_domain(obj);
1000 drm_gem_object_unreference(&obj->base);
1002 mutex_unlock(&dev->struct_mutex);
1007 * Maps the contents of an object, returning the address it is mapped
1010 * While the mapping holds a reference on the contents of the object, it doesn't
1011 * imply a ref on the object itself.
1014 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1015 struct drm_file *file)
1017 struct drm_i915_gem_mmap *args = data;
1018 struct drm_gem_object *obj;
1019 struct proc *p = curproc;
1020 vm_map_t map = &p->p_vmspace->vm_map;
1025 obj = drm_gem_object_lookup(dev, file, args->handle);
1029 if (args->size == 0)
1032 size = round_page(args->size);
1033 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1039 vm_object_hold(obj->vm_obj);
1040 vm_object_reference_locked(obj->vm_obj);
1041 vm_object_drop(obj->vm_obj);
1042 rv = vm_map_find(map, obj->vm_obj, NULL,
1043 args->offset, &addr, args->size,
1044 PAGE_SIZE, /* align */
1046 VM_MAPTYPE_NORMAL, /* maptype */
1047 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1048 VM_PROT_READ | VM_PROT_WRITE, /* max */
1049 MAP_SHARED /* cow */);
1050 if (rv != KERN_SUCCESS) {
1051 vm_object_deallocate(obj->vm_obj);
1052 error = -vm_mmap_to_errno(rv);
1054 args->addr_ptr = (uint64_t)addr;
1057 drm_gem_object_unreference(obj);
1062 * i915_gem_fault - fault a page into the GTT
1063 * vma: VMA in question
1066 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1067 * from userspace. The fault handler takes care of binding the object to
1068 * the GTT (if needed), allocating and programming a fence register (again,
1069 * only if needed based on whether the old reg is still valid or the object
1070 * is tiled) and inserting a new PTE into the faulting process.
1072 * Note that the faulting process may involve evicting existing objects
1073 * from the GTT and/or fence registers to make room. So performance may
1074 * suffer if the GTT working set is large or there are few fence registers
1078 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1080 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1081 struct drm_device *dev = obj->base.dev;
1082 drm_i915_private_t *dev_priv = dev->dev_private;
1083 pgoff_t page_offset;
1086 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1088 /* We don't use vmf->pgoff since that has the fake offset */
1089 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1092 ret = i915_mutex_lock_interruptible(dev);
1096 trace_i915_gem_object_fault(obj, page_offset, true, write);
1098 /* Access to snoopable pages through the GTT is incoherent. */
1099 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1104 /* Now bind it into the GTT if needed */
1105 ret = i915_gem_object_pin(obj, 0, true, false);
1109 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1113 ret = i915_gem_object_get_fence(obj);
1117 obj->fault_mappable = true;
1119 pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1122 /* Finally, remap it using the new GTT offset */
1123 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1125 i915_gem_object_unpin(obj);
1127 mutex_unlock(&dev->struct_mutex);
1131 /* If this -EIO is due to a gpu hang, give the reset code a
1132 * chance to clean up the mess. Otherwise return the proper
1134 if (i915_terminally_wedged(&dev_priv->gpu_error))
1135 return VM_FAULT_SIGBUS;
1137 /* Give the error handler a chance to run and move the
1138 * objects off the GPU active list. Next time we service the
1139 * fault, we should be able to transition the page into the
1140 * GTT without touching the GPU (and so avoid further
1141 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1142 * with coherency, just lost writes.
1150 * EBUSY is ok: this just means that another thread
1151 * already did the job.
1153 return VM_FAULT_NOPAGE;
1155 return VM_FAULT_OOM;
1157 return VM_FAULT_SIGBUS;
1159 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1160 return VM_FAULT_SIGBUS;
1166 * i915_gem_release_mmap - remove physical page mappings
1167 * @obj: obj in question
1169 * Preserve the reservation of the mmapping with the DRM core code, but
1170 * relinquish ownership of the pages back to the system.
1172 * It is vital that we remove the page mapping if we have mapped a tiled
1173 * object through the GTT and then lose the fence register due to
1174 * resource pressure. Similarly if the object has been moved out of the
1175 * aperture, than pages mapped into userspace must be revoked. Removing the
1176 * mapping will then trigger a page fault on the next user access, allowing
1177 * fixup by i915_gem_fault().
1180 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1186 if (!obj->fault_mappable)
1189 devobj = cdev_pager_lookup(obj);
1190 if (devobj != NULL) {
1191 page_count = OFF_TO_IDX(obj->base.size);
1193 VM_OBJECT_LOCK(devobj);
1194 for (i = 0; i < page_count; i++) {
1195 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1198 cdev_pager_free_page(devobj, m);
1200 VM_OBJECT_UNLOCK(devobj);
1201 vm_object_deallocate(devobj);
1204 obj->fault_mappable = false;
1208 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1212 if (INTEL_INFO(dev)->gen >= 4 ||
1213 tiling_mode == I915_TILING_NONE)
1216 /* Previous chips need a power-of-two fence region when tiling */
1217 if (INTEL_INFO(dev)->gen == 3)
1218 gtt_size = 1024*1024;
1220 gtt_size = 512*1024;
1222 while (gtt_size < size)
1229 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1230 * @obj: object to check
1232 * Return the required GTT alignment for an object, taking into account
1233 * potential fence register mapping.
1236 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1237 int tiling_mode, bool fenced)
1241 * Minimum alignment is 4k (GTT page size), but might be greater
1242 * if a fence register is needed for the object.
1244 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1245 tiling_mode == I915_TILING_NONE)
1249 * Previous chips need to be aligned to the size of the smallest
1250 * fence register that can contain the object.
1252 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1256 i915_gem_mmap_gtt(struct drm_file *file,
1257 struct drm_device *dev,
1261 struct drm_i915_private *dev_priv = dev->dev_private;
1262 struct drm_i915_gem_object *obj;
1265 ret = i915_mutex_lock_interruptible(dev);
1269 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1270 if (&obj->base == NULL) {
1275 if (obj->base.size > dev_priv->gtt.mappable_end) {
1280 if (obj->madv != I915_MADV_WILLNEED) {
1281 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1286 ret = drm_gem_create_mmap_offset(&obj->base);
1290 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1291 DRM_GEM_MAPPING_KEY;
1293 drm_gem_object_unreference(&obj->base);
1295 mutex_unlock(&dev->struct_mutex);
1300 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1302 * @data: GTT mapping ioctl data
1303 * @file: GEM object info
1305 * Simply returns the fake offset to userspace so it can mmap it.
1306 * The mmap call will end up in drm_gem_mmap(), which will set things
1307 * up so we can get faults in the handler above.
1309 * The fault handler will take care of binding the object into the GTT
1310 * (since it may have been evicted to make room for something), allocating
1311 * a fence register, and mapping the appropriate aperture address into
1315 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1316 struct drm_file *file)
1318 struct drm_i915_gem_mmap_gtt *args = data;
1320 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1323 /* Immediately discard the backing storage */
1325 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1329 vm_obj = obj->base.vm_obj;
1330 VM_OBJECT_LOCK(vm_obj);
1331 vm_object_page_remove(vm_obj, 0, 0, false);
1332 VM_OBJECT_UNLOCK(vm_obj);
1333 obj->madv = __I915_MADV_PURGED;
1337 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1339 return obj->madv == I915_MADV_DONTNEED;
1343 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1348 BUG_ON(obj->madv == __I915_MADV_PURGED);
1350 if (obj->tiling_mode != I915_TILING_NONE)
1351 i915_gem_object_save_bit_17_swizzle(obj);
1352 if (obj->madv == I915_MADV_DONTNEED)
1354 page_count = obj->base.size / PAGE_SIZE;
1355 VM_OBJECT_LOCK(obj->base.vm_obj);
1356 #if GEM_PARANOID_CHECK_GTT
1357 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
1359 for (i = 0; i < page_count; i++) {
1363 if (obj->madv == I915_MADV_WILLNEED)
1364 vm_page_reference(m);
1365 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
1366 vm_page_unwire(obj->pages[i], 1);
1367 vm_page_wakeup(obj->pages[i]);
1369 VM_OBJECT_UNLOCK(obj->base.vm_obj);
1371 drm_free(obj->pages, M_DRM);
1376 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1378 const struct drm_i915_gem_object_ops *ops = obj->ops;
1380 if (obj->pages == NULL)
1383 BUG_ON(obj->gtt_space);
1385 if (obj->pages_pin_count)
1388 /* ->put_pages might need to allocate memory for the bit17 swizzle
1389 * array, hence protect them from being reaped by removing them from gtt
1391 list_del(&obj->global_list);
1393 ops->put_pages(obj);
1396 if (i915_gem_object_is_purgeable(obj))
1397 i915_gem_object_truncate(obj);
1403 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1405 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1406 struct drm_device *dev;
1408 int page_count, i, j;
1409 struct vm_page *page;
1411 dev = obj->base.dev;
1412 KASSERT(obj->pages == NULL, ("Obj already has pages"));
1413 page_count = obj->base.size / PAGE_SIZE;
1414 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
1417 vm_obj = obj->base.vm_obj;
1418 VM_OBJECT_LOCK(vm_obj);
1420 for (i = 0; i < page_count; i++) {
1421 page = shmem_read_mapping_page(vm_obj, i);
1423 i915_gem_purge(dev_priv, page_count);
1427 obj->pages[i] = page;
1430 VM_OBJECT_UNLOCK(vm_obj);
1431 if (i915_gem_object_needs_bit17_swizzle(obj))
1432 i915_gem_object_do_bit_17_swizzle(obj);
1437 for (j = 0; j < i; j++) {
1438 page = obj->pages[j];
1439 vm_page_busy_wait(page, FALSE, "i915gem");
1440 vm_page_unwire(page, 0);
1441 vm_page_wakeup(page);
1443 VM_OBJECT_UNLOCK(vm_obj);
1444 drm_free(obj->pages, M_DRM);
1449 /* Ensure that the associated pages are gathered from the backing storage
1450 * and pinned into our object. i915_gem_object_get_pages() may be called
1451 * multiple times before they are released by a single call to
1452 * i915_gem_object_put_pages() - once the pages are no longer referenced
1453 * either as a result of memory pressure (reaping pages under the shrinker)
1454 * or as the object is itself released.
1457 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1459 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1460 const struct drm_i915_gem_object_ops *ops = obj->ops;
1466 if (obj->madv != I915_MADV_WILLNEED) {
1467 DRM_ERROR("Attempting to obtain a purgeable object\n");
1471 BUG_ON(obj->pages_pin_count);
1473 ret = ops->get_pages(obj);
1477 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1482 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1483 struct intel_ring_buffer *ring)
1485 struct drm_device *dev = obj->base.dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 u32 seqno = intel_ring_get_seqno(ring);
1489 BUG_ON(ring == NULL);
1490 if (obj->ring != ring && obj->last_write_seqno) {
1491 /* Keep the seqno relative to the current ring */
1492 obj->last_write_seqno = seqno;
1496 /* Add a reference if we're newly entering the active list. */
1498 drm_gem_object_reference(&obj->base);
1502 /* Move from whatever list we were on to the tail of execution. */
1503 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1504 list_move_tail(&obj->ring_list, &ring->active_list);
1506 obj->last_read_seqno = seqno;
1508 if (obj->fenced_gpu_access) {
1509 obj->last_fenced_seqno = seqno;
1511 /* Bump MRU to take account of the delayed flush */
1512 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1513 struct drm_i915_fence_reg *reg;
1515 reg = &dev_priv->fence_regs[obj->fence_reg];
1516 list_move_tail(®->lru_list,
1517 &dev_priv->mm.fence_list);
1523 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1525 struct drm_device *dev = obj->base.dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1528 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1529 BUG_ON(!obj->active);
1531 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1533 list_del_init(&obj->ring_list);
1536 obj->last_read_seqno = 0;
1537 obj->last_write_seqno = 0;
1538 obj->base.write_domain = 0;
1540 obj->last_fenced_seqno = 0;
1541 obj->fenced_gpu_access = false;
1544 drm_gem_object_unreference(&obj->base);
1546 WARN_ON(i915_verify_lists(dev));
1550 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553 struct intel_ring_buffer *ring;
1556 /* Carefully retire all requests without writing to the rings */
1557 for_each_ring(ring, dev_priv, i) {
1558 ret = intel_ring_idle(ring);
1562 i915_gem_retire_requests(dev);
1564 /* Finally reset hw state */
1565 for_each_ring(ring, dev_priv, i) {
1566 intel_ring_init_seqno(ring, seqno);
1568 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1569 ring->sync_seqno[j] = 0;
1575 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1583 /* HWS page needs to be set less than what we
1584 * will inject to ring
1586 ret = i915_gem_init_seqno(dev, seqno - 1);
1590 /* Carefully set the last_seqno value so that wrap
1591 * detection still works
1593 dev_priv->next_seqno = seqno;
1594 dev_priv->last_seqno = seqno - 1;
1595 if (dev_priv->last_seqno == 0)
1596 dev_priv->last_seqno--;
1602 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1606 /* reserve 0 for non-seqno */
1607 if (dev_priv->next_seqno == 0) {
1608 int ret = i915_gem_init_seqno(dev, 0);
1612 dev_priv->next_seqno = 1;
1615 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
1619 int __i915_add_request(struct intel_ring_buffer *ring,
1620 struct drm_file *file,
1621 struct drm_i915_gem_object *obj,
1624 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1625 struct drm_i915_gem_request *request;
1626 u32 request_ring_position, request_start;
1630 request_start = intel_ring_get_tail(ring);
1632 * Emit any outstanding flushes - execbuf can fail to emit the flush
1633 * after having emitted the batchbuffer command. Hence we need to fix
1634 * things up similar to emitting the lazy request. The difference here
1635 * is that the flush _must_ happen before the next request, no matter
1638 ret = intel_ring_flush_all_caches(ring);
1642 request = kmalloc(sizeof(*request), M_DRM, M_WAITOK);
1643 if (request == NULL)
1647 /* Record the position of the start of the request so that
1648 * should we detect the updated seqno part-way through the
1649 * GPU processing the request, we never over-estimate the
1650 * position of the head.
1652 request_ring_position = intel_ring_get_tail(ring);
1654 ret = ring->add_request(ring);
1660 request->seqno = intel_ring_get_seqno(ring);
1661 request->ring = ring;
1662 request->head = request_start;
1663 request->tail = request_ring_position;
1664 request->ctx = ring->last_context;
1665 request->batch_obj = obj;
1667 /* Whilst this request exists, batch_obj will be on the
1668 * active_list, and so will hold the active reference. Only when this
1669 * request is retired will the the batch_obj be moved onto the
1670 * inactive_list and lose its active reference. Hence we do not need
1671 * to explicitly hold another reference here.
1675 i915_gem_context_reference(request->ctx);
1677 request->emitted_jiffies = jiffies;
1678 was_empty = list_empty(&ring->request_list);
1679 list_add_tail(&request->list, &ring->request_list);
1680 request->file_priv = NULL;
1683 struct drm_i915_file_private *file_priv = file->driver_priv;
1685 spin_lock(&file_priv->mm.lock);
1686 request->file_priv = file_priv;
1687 list_add_tail(&request->client_list,
1688 &file_priv->mm.request_list);
1689 spin_unlock(&file_priv->mm.lock);
1692 ring->outstanding_lazy_request = 0;
1694 if (!dev_priv->mm.suspended) {
1695 if (i915_enable_hangcheck) {
1696 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
1697 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1700 queue_delayed_work(dev_priv->wq,
1701 &dev_priv->mm.retire_work,
1702 round_jiffies_up_relative(hz));
1703 intel_mark_busy(dev_priv->dev);
1708 *out_seqno = request->seqno;
1713 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1715 struct drm_i915_file_private *file_priv = request->file_priv;
1720 spin_lock(&file_priv->mm.lock);
1721 if (request->file_priv) {
1722 list_del(&request->client_list);
1723 request->file_priv = NULL;
1725 spin_unlock(&file_priv->mm.lock);
1728 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
1730 if (acthd >= obj->gtt_offset &&
1731 acthd < obj->gtt_offset + obj->base.size)
1737 static bool i915_head_inside_request(const u32 acthd_unmasked,
1738 const u32 request_start,
1739 const u32 request_end)
1741 const u32 acthd = acthd_unmasked & HEAD_ADDR;
1743 if (request_start < request_end) {
1744 if (acthd >= request_start && acthd < request_end)
1746 } else if (request_start > request_end) {
1747 if (acthd >= request_start || acthd < request_end)
1754 static bool i915_request_guilty(struct drm_i915_gem_request *request,
1755 const u32 acthd, bool *inside)
1757 /* There is a possibility that unmasked head address
1758 * pointing inside the ring, matches the batch_obj address range.
1759 * However this is extremely unlikely.
1762 if (request->batch_obj) {
1763 if (i915_head_inside_object(acthd, request->batch_obj)) {
1769 if (i915_head_inside_request(acthd, request->head, request->tail)) {
1777 static void i915_set_reset_status(struct intel_ring_buffer *ring,
1778 struct drm_i915_gem_request *request,
1781 struct i915_ctx_hang_stats *hs = NULL;
1782 bool inside, guilty;
1784 /* Innocent until proven guilty */
1787 if (ring->hangcheck.action != wait &&
1788 i915_request_guilty(request, acthd, &inside)) {
1789 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
1791 inside ? "inside" : "flushing",
1792 request->batch_obj ?
1793 request->batch_obj->gtt_offset : 0,
1794 request->ctx ? request->ctx->id : 0,
1800 /* If contexts are disabled or this is the default context, use
1801 * file_priv->reset_state
1803 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
1804 hs = &request->ctx->hang_stats;
1805 else if (request->file_priv)
1806 hs = &request->file_priv->hang_stats;
1812 hs->batch_pending++;
1816 static void i915_gem_free_request(struct drm_i915_gem_request *request)
1818 list_del(&request->list);
1819 i915_gem_request_remove_from_client(request);
1822 i915_gem_context_unreference(request->ctx);
1827 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1828 struct intel_ring_buffer *ring)
1830 u32 completed_seqno;
1833 acthd = intel_ring_get_active_head(ring);
1834 completed_seqno = ring->get_seqno(ring, false);
1836 while (!list_empty(&ring->request_list)) {
1837 struct drm_i915_gem_request *request;
1839 request = list_first_entry(&ring->request_list,
1840 struct drm_i915_gem_request,
1843 if (request->seqno > completed_seqno)
1844 i915_set_reset_status(ring, request, acthd);
1846 i915_gem_free_request(request);
1849 while (!list_empty(&ring->active_list)) {
1850 struct drm_i915_gem_object *obj;
1852 obj = list_first_entry(&ring->active_list,
1853 struct drm_i915_gem_object,
1856 i915_gem_object_move_to_inactive(obj);
1860 void i915_gem_restore_fences(struct drm_device *dev)
1862 struct drm_i915_private *dev_priv = dev->dev_private;
1865 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1866 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1869 * Commit delayed tiling changes if we have an object still
1870 * attached to the fence, otherwise just clear the fence.
1873 i915_gem_object_update_fence(reg->obj, reg,
1874 reg->obj->tiling_mode);
1876 i915_gem_write_fence(dev, i, NULL);
1881 void i915_gem_reset(struct drm_device *dev)
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct drm_i915_gem_object *obj;
1885 struct intel_ring_buffer *ring;
1888 for_each_ring(ring, dev_priv, i)
1889 i915_gem_reset_ring_lists(dev_priv, ring);
1891 /* Move everything out of the GPU domains to ensure we do any
1892 * necessary invalidation upon reuse.
1894 list_for_each_entry(obj,
1895 &dev_priv->mm.inactive_list,
1898 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1901 i915_gem_restore_fences(dev);
1905 * This function clears the request list as sequence numbers are passed.
1908 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1912 if (list_empty(&ring->request_list))
1915 WARN_ON(i915_verify_lists(ring->dev));
1917 seqno = ring->get_seqno(ring, true);
1919 while (!list_empty(&ring->request_list)) {
1920 struct drm_i915_gem_request *request;
1922 request = list_first_entry(&ring->request_list,
1923 struct drm_i915_gem_request,
1926 if (!i915_seqno_passed(seqno, request->seqno))
1929 /* We know the GPU must have read the request to have
1930 * sent us the seqno + interrupt, so use the position
1931 * of tail of the request to update the last known position
1934 ring->last_retired_head = request->tail;
1936 i915_gem_free_request(request);
1939 /* Move any buffers on the active list that are no longer referenced
1940 * by the ringbuffer to the flushing/inactive lists as appropriate.
1942 while (!list_empty(&ring->active_list)) {
1943 struct drm_i915_gem_object *obj;
1945 obj = list_first_entry(&ring->active_list,
1946 struct drm_i915_gem_object,
1949 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1952 i915_gem_object_move_to_inactive(obj);
1955 if (unlikely(ring->trace_irq_seqno &&
1956 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1957 ring->irq_put(ring);
1958 ring->trace_irq_seqno = 0;
1964 i915_gem_retire_requests(struct drm_device *dev)
1966 drm_i915_private_t *dev_priv = dev->dev_private;
1967 struct intel_ring_buffer *ring;
1970 for_each_ring(ring, dev_priv, i)
1971 i915_gem_retire_requests_ring(ring);
1975 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1976 bool purgeable_only)
1978 struct drm_i915_gem_object *obj, *next;
1981 list_for_each_entry_safe(obj, next,
1982 &dev_priv->mm.unbound_list,
1985 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1986 i915_gem_object_put_pages(obj) == 0) {
1987 count += obj->base.size >> PAGE_SHIFT;
1988 if (count >= target)
1994 list_for_each_entry_safe(obj, next,
1995 &dev_priv->mm.inactive_list,
1998 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1999 i915_gem_object_unbind(obj) == 0 &&
2000 i915_gem_object_put_pages(obj) == 0) {
2001 count += obj->base.size >> PAGE_SHIFT;
2002 if (count >= target)
2012 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2014 return __i915_gem_shrink(dev_priv, target, true);
2018 i915_gem_retire_work_handler(struct work_struct *work)
2020 drm_i915_private_t *dev_priv;
2021 struct drm_device *dev;
2022 struct intel_ring_buffer *ring;
2026 dev_priv = container_of(work, drm_i915_private_t,
2027 mm.retire_work.work);
2028 dev = dev_priv->dev;
2030 /* Come back later if the device is busy... */
2031 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT)) {
2032 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2033 round_jiffies_up_relative(hz));
2037 i915_gem_retire_requests(dev);
2039 /* Send a periodic flush down the ring so we don't hold onto GEM
2040 * objects indefinitely.
2043 for_each_ring(ring, dev_priv, i) {
2044 if (ring->gpu_caches_dirty)
2045 i915_add_request(ring, NULL);
2047 idle &= list_empty(&ring->request_list);
2050 if (!dev_priv->mm.suspended && !idle)
2051 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2052 round_jiffies_up_relative(hz));
2054 intel_mark_idle(dev);
2056 mutex_unlock(&dev->struct_mutex);
2059 * Ensures that an object will eventually get non-busy by flushing any required
2060 * write domains, emitting any outstanding lazy request and retiring and
2061 * completed requests.
2064 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2069 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2073 i915_gem_retire_requests_ring(obj->ring);
2080 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2081 * @DRM_IOCTL_ARGS: standard ioctl arguments
2083 * Returns 0 if successful, else an error is returned with the remaining time in
2084 * the timeout parameter.
2085 * -ETIME: object is still busy after timeout
2086 * -ERESTARTSYS: signal interrupted the wait
2087 * -ENONENT: object doesn't exist
2088 * Also possible, but rare:
2089 * -EAGAIN: GPU wedged
2091 * -ENODEV: Internal IRQ fail
2092 * -E?: The add request failed
2094 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2095 * non-zero timeout parameter the wait ioctl will wait for the given number of
2096 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2097 * without holding struct_mutex the object may become re-busied before this
2098 * function completes. A similar but shorter * race condition exists in the busy
2102 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2104 drm_i915_private_t *dev_priv = dev->dev_private;
2105 struct drm_i915_gem_wait *args = data;
2106 struct drm_i915_gem_object *obj;
2107 struct intel_ring_buffer *ring = NULL;
2108 struct timespec timeout_stack, *timeout = NULL;
2109 unsigned reset_counter;
2113 if (args->timeout_ns >= 0) {
2114 timeout_stack = ns_to_timespec(args->timeout_ns);
2115 timeout = &timeout_stack;
2118 ret = i915_mutex_lock_interruptible(dev);
2122 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2123 if (&obj->base == NULL) {
2124 mutex_unlock(&dev->struct_mutex);
2128 /* Need to make sure the object gets inactive eventually. */
2129 ret = i915_gem_object_flush_active(obj);
2134 seqno = obj->last_read_seqno;
2141 /* Do this after OLR check to make sure we make forward progress polling
2142 * on this IOCTL with a 0 timeout (like busy ioctl)
2144 if (!args->timeout_ns) {
2149 drm_gem_object_unreference(&obj->base);
2150 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2151 mutex_unlock(&dev->struct_mutex);
2153 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2155 args->timeout_ns = timespec_to_ns(timeout);
2159 drm_gem_object_unreference(&obj->base);
2160 mutex_unlock(&dev->struct_mutex);
2165 * i915_gem_object_sync - sync an object to a ring.
2167 * @obj: object which may be in use on another ring.
2168 * @to: ring we wish to use the object on. May be NULL.
2170 * This code is meant to abstract object synchronization with the GPU.
2171 * Calling with NULL implies synchronizing the object with the CPU
2172 * rather than a particular GPU ring.
2174 * Returns 0 if successful, else propagates up the lower layer error.
2177 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2178 struct intel_ring_buffer *to)
2180 struct intel_ring_buffer *from = obj->ring;
2184 if (from == NULL || to == from)
2187 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2188 return i915_gem_object_wait_rendering(obj, false);
2190 idx = intel_ring_sync_index(from, to);
2192 seqno = obj->last_read_seqno;
2193 if (seqno <= from->sync_seqno[idx])
2196 ret = i915_gem_check_olr(obj->ring, seqno);
2200 ret = to->sync_to(to, from, seqno);
2202 /* We use last_read_seqno because sync_to()
2203 * might have just caused seqno wrap under
2206 from->sync_seqno[idx] = obj->last_read_seqno;
2211 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2213 u32 old_write_domain, old_read_domains;
2215 /* Force a pagefault for domain tracking on next user access */
2216 i915_gem_release_mmap(obj);
2218 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2221 /* Wait for any direct GTT access to complete */
2224 old_read_domains = obj->base.read_domains;
2225 old_write_domain = obj->base.write_domain;
2227 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2228 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2233 * Unbinds an object from the GTT aperture.
2236 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2238 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2241 if (obj->gtt_space == NULL)
2247 BUG_ON(obj->pages == NULL);
2249 ret = i915_gem_object_finish_gpu(obj);
2252 /* Continue on if we fail due to EIO, the GPU is hung so we
2253 * should be safe and we need to cleanup or else we might
2254 * cause memory corruption through use-after-free.
2257 i915_gem_object_finish_gtt(obj);
2259 /* Move the object to the CPU domain to ensure that
2260 * any possible CPU writes while it's not in the GTT
2261 * are flushed when we go to remap it.
2264 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2265 if (ret == -ERESTARTSYS)
2268 /* In the event of a disaster, abandon all caches and
2269 * hope for the best.
2271 i915_gem_clflush_object(obj);
2272 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2275 /* release the fence reg _after_ flushing */
2276 ret = i915_gem_object_put_fence(obj);
2280 if (obj->has_global_gtt_mapping)
2281 i915_gem_gtt_unbind_object(obj);
2282 if (obj->has_aliasing_ppgtt_mapping) {
2283 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2284 obj->has_aliasing_ppgtt_mapping = 0;
2286 i915_gem_gtt_finish_object(obj);
2288 i915_gem_object_put_pages_gtt(obj);
2290 list_del_init(&obj->global_list);
2291 list_del_init(&obj->mm_list);
2292 /* Avoid an unnecessary call to unbind on rebind. */
2293 obj->map_and_fenceable = true;
2295 drm_mm_put_block(obj->gtt_space);
2296 obj->gtt_space = NULL;
2297 obj->gtt_offset = 0;
2299 if (i915_gem_object_is_purgeable(obj))
2300 i915_gem_object_truncate(obj);
2305 int i915_gpu_idle(struct drm_device *dev)
2307 drm_i915_private_t *dev_priv = dev->dev_private;
2308 struct intel_ring_buffer *ring;
2311 /* Flush everything onto the inactive list. */
2312 for_each_ring(ring, dev_priv, i) {
2313 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2317 ret = intel_ring_idle(ring);
2325 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2326 struct drm_i915_gem_object *obj)
2328 drm_i915_private_t *dev_priv = dev->dev_private;
2330 int fence_pitch_shift;
2332 if (INTEL_INFO(dev)->gen >= 6) {
2333 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2334 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2336 fence_reg = FENCE_REG_965_0;
2337 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2340 fence_reg += reg * 8;
2342 /* To w/a incoherency with non-atomic 64-bit register updates,
2343 * we split the 64-bit update into two 32-bit writes. In order
2344 * for a partial fence not to be evaluated between writes, we
2345 * precede the update with write to turn off the fence register,
2346 * and only enable the fence as the last step.
2348 * For extra levels of paranoia, we make sure each step lands
2349 * before applying the next step.
2351 I915_WRITE(fence_reg, 0);
2352 POSTING_READ(fence_reg);
2355 u32 size = obj->gtt_space->size;
2358 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2360 val |= obj->gtt_offset & 0xfffff000;
2361 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2362 if (obj->tiling_mode == I915_TILING_Y)
2363 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2364 val |= I965_FENCE_REG_VALID;
2366 I915_WRITE(fence_reg + 4, val >> 32);
2367 POSTING_READ(fence_reg + 4);
2369 I915_WRITE(fence_reg + 0, val);
2370 POSTING_READ(fence_reg);
2372 I915_WRITE(fence_reg + 4, 0);
2373 POSTING_READ(fence_reg + 4);
2377 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2378 struct drm_i915_gem_object *obj)
2380 drm_i915_private_t *dev_priv = dev->dev_private;
2384 u32 size = obj->gtt_space->size;
2388 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2389 (size & -size) != size ||
2390 (obj->gtt_offset & (size - 1)),
2391 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2392 obj->gtt_offset, obj->map_and_fenceable, size);
2394 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2399 /* Note: pitch better be a power of two tile widths */
2400 pitch_val = obj->stride / tile_width;
2401 pitch_val = ffs(pitch_val) - 1;
2403 val = obj->gtt_offset;
2404 if (obj->tiling_mode == I915_TILING_Y)
2405 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2406 val |= I915_FENCE_SIZE_BITS(size);
2407 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2408 val |= I830_FENCE_REG_VALID;
2413 reg = FENCE_REG_830_0 + reg * 4;
2415 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2417 I915_WRITE(reg, val);
2421 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2422 struct drm_i915_gem_object *obj)
2424 drm_i915_private_t *dev_priv = dev->dev_private;
2428 u32 size = obj->gtt_space->size;
2431 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2432 (size & -size) != size ||
2433 (obj->gtt_offset & (size - 1)),
2434 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2435 obj->gtt_offset, size);
2437 pitch_val = obj->stride / 128;
2438 pitch_val = ffs(pitch_val) - 1;
2440 val = obj->gtt_offset;
2441 if (obj->tiling_mode == I915_TILING_Y)
2442 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2443 val |= I830_FENCE_SIZE_BITS(size);
2444 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2445 val |= I830_FENCE_REG_VALID;
2449 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2450 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2453 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2455 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2458 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2459 struct drm_i915_gem_object *obj)
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2463 /* Ensure that all CPU reads are completed before installing a fence
2464 * and all writes before removing the fence.
2466 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2469 WARN(obj && (!obj->stride || !obj->tiling_mode),
2470 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2471 obj->stride, obj->tiling_mode);
2473 switch (INTEL_INFO(dev)->gen) {
2477 case 4: i965_write_fence_reg(dev, reg, obj); break;
2478 case 3: i915_write_fence_reg(dev, reg, obj); break;
2479 case 2: i830_write_fence_reg(dev, reg, obj); break;
2483 /* And similarly be paranoid that no direct access to this region
2484 * is reordered to before the fence is installed.
2486 if (i915_gem_object_needs_mb(obj))
2490 static inline int fence_number(struct drm_i915_private *dev_priv,
2491 struct drm_i915_fence_reg *fence)
2493 return fence - dev_priv->fence_regs;
2496 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2497 struct drm_i915_fence_reg *fence,
2500 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2501 int reg = fence_number(dev_priv, fence);
2503 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2506 obj->fence_reg = reg;
2508 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2510 obj->fence_reg = I915_FENCE_REG_NONE;
2512 list_del_init(&fence->lru_list);
2514 obj->fence_dirty = false;
2518 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2520 if (obj->last_fenced_seqno) {
2521 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2525 obj->last_fenced_seqno = 0;
2528 obj->fenced_gpu_access = false;
2533 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2535 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2536 struct drm_i915_fence_reg *fence;
2539 ret = i915_gem_object_wait_fence(obj);
2543 if (obj->fence_reg == I915_FENCE_REG_NONE)
2546 fence = &dev_priv->fence_regs[obj->fence_reg];
2548 i915_gem_object_fence_lost(obj);
2549 i915_gem_object_update_fence(obj, fence, false);
2554 static struct drm_i915_fence_reg *
2555 i915_find_fence_reg(struct drm_device *dev)
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct drm_i915_fence_reg *reg, *avail;
2561 /* First try to find a free reg */
2563 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2564 reg = &dev_priv->fence_regs[i];
2568 if (!reg->pin_count)
2575 /* None available, try to steal one or wait for a user to finish */
2576 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2587 * i915_gem_object_get_fence - set up fencing for an object
2588 * @obj: object to map through a fence reg
2590 * When mapping objects through the GTT, userspace wants to be able to write
2591 * to them without having to worry about swizzling if the object is tiled.
2592 * This function walks the fence regs looking for a free one for @obj,
2593 * stealing one if it can't find any.
2595 * It then sets up the reg based on the object's properties: address, pitch
2596 * and tiling format.
2598 * For an untiled surface, this removes any existing fence.
2601 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2603 struct drm_device *dev = obj->base.dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 bool enable = obj->tiling_mode != I915_TILING_NONE;
2606 struct drm_i915_fence_reg *reg;
2609 /* Have we updated the tiling parameters upon the object and so
2610 * will need to serialise the write to the associated fence register?
2612 if (obj->fence_dirty) {
2613 ret = i915_gem_object_wait_fence(obj);
2618 /* Just update our place in the LRU if our fence is getting reused. */
2619 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2620 reg = &dev_priv->fence_regs[obj->fence_reg];
2621 if (!obj->fence_dirty) {
2622 list_move_tail(®->lru_list,
2623 &dev_priv->mm.fence_list);
2626 } else if (enable) {
2627 reg = i915_find_fence_reg(dev);
2632 struct drm_i915_gem_object *old = reg->obj;
2634 ret = i915_gem_object_wait_fence(old);
2638 i915_gem_object_fence_lost(old);
2643 i915_gem_object_update_fence(obj, reg, enable);
2648 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2649 struct drm_mm_node *gtt_space,
2650 unsigned long cache_level)
2652 struct drm_mm_node *other;
2654 /* On non-LLC machines we have to be careful when putting differing
2655 * types of snoopable memory together to avoid the prefetcher
2656 * crossing memory domains and dying.
2661 if (gtt_space == NULL)
2664 if (list_empty(>t_space->node_list))
2667 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2668 if (other->allocated && !other->hole_follows && other->color != cache_level)
2671 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2672 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2678 static void i915_gem_verify_gtt(struct drm_device *dev)
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 struct drm_i915_gem_object *obj;
2685 list_for_each_entry(obj, &dev_priv->mm.global_list, global_list) {
2686 if (obj->gtt_space == NULL) {
2687 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2692 if (obj->cache_level != obj->gtt_space->color) {
2693 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2694 obj->gtt_space->start,
2695 obj->gtt_space->start + obj->gtt_space->size,
2697 obj->gtt_space->color);
2702 if (!i915_gem_valid_gtt_space(dev,
2704 obj->cache_level)) {
2705 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2706 obj->gtt_space->start,
2707 obj->gtt_space->start + obj->gtt_space->size,
2719 * Finds free space in the GTT aperture and binds the object there.
2722 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2724 bool map_and_fenceable,
2727 struct drm_device *dev = obj->base.dev;
2728 drm_i915_private_t *dev_priv = dev->dev_private;
2729 struct drm_mm_node *node;
2730 u32 size, fence_size, fence_alignment, unfenced_alignment;
2731 bool mappable, fenceable;
2732 size_t gtt_max = map_and_fenceable ?
2733 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
2736 fence_size = i915_gem_get_gtt_size(dev,
2739 fence_alignment = i915_gem_get_gtt_alignment(dev,
2741 obj->tiling_mode, true);
2742 unfenced_alignment =
2743 i915_gem_get_gtt_alignment(dev,
2745 obj->tiling_mode, false);
2748 alignment = map_and_fenceable ? fence_alignment :
2750 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2751 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2755 size = map_and_fenceable ? fence_size : obj->base.size;
2757 /* If the object is bigger than the entire aperture, reject it early
2758 * before evicting everything in a vain attempt to find space.
2760 if (obj->base.size > gtt_max) {
2761 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
2763 map_and_fenceable ? "mappable" : "total",
2769 if (map_and_fenceable)
2770 node = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2771 size, alignment, obj->cache_level,
2772 0, dev_priv->gtt.mappable_end,
2775 node = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2776 size, alignment, obj->cache_level,
2779 if (map_and_fenceable)
2781 drm_mm_get_block_range_generic(node,
2782 size, alignment, obj->cache_level,
2783 0, dev_priv->gtt.mappable_end,
2787 drm_mm_get_block_generic(node,
2788 size, alignment, obj->cache_level,
2791 if (obj->gtt_space == NULL) {
2792 ret = i915_gem_evict_something(dev, size, alignment,
2803 * NOTE: i915_gem_object_get_pages_gtt() cannot
2804 * return ENOMEM, since we used VM_ALLOC_RETRY.
2806 ret = i915_gem_object_get_pages_gtt(obj);
2808 drm_mm_put_block(obj->gtt_space);
2809 obj->gtt_space = NULL;
2813 i915_gem_gtt_bind_object(obj, obj->cache_level);
2815 i915_gem_object_put_pages_gtt(obj);
2816 drm_mm_put_block(obj->gtt_space);
2817 obj->gtt_space = NULL;
2818 if (i915_gem_evict_everything(dev))
2823 list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
2824 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2826 obj->gtt_offset = obj->gtt_space->start;
2829 obj->gtt_space->size == fence_size &&
2830 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2833 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
2835 obj->map_and_fenceable = mappable && fenceable;
2837 trace_i915_gem_object_bind(obj, map_and_fenceable);
2838 i915_gem_verify_gtt(dev);
2843 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2846 /* If we don't have a page list set up, then we're not pinned
2847 * to GPU, and we can ignore the cache flush because it'll happen
2848 * again at bind time.
2850 if (obj->pages == NULL)
2854 * Stolen memory is always coherent with the GPU as it is explicitly
2855 * marked as wc by the system, or the system is cache-coherent.
2860 /* If the GPU is snooping the contents of the CPU cache,
2861 * we do not need to manually clear the CPU cache lines. However,
2862 * the caches are only snooped when the render cache is
2863 * flushed/invalidated. As we always have to emit invalidations
2864 * and flushes when moving into and out of the RENDER domain, correct
2865 * snooping behaviour occurs naturally as the result of our domain
2868 if (obj->cache_level != I915_CACHE_NONE)
2871 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2874 /** Flushes the GTT write domain for the object if it's dirty. */
2876 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2878 uint32_t old_write_domain;
2880 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2883 /* No actual flushing is required for the GTT write domain. Writes
2884 * to it immediately go to main memory as far as we know, so there's
2885 * no chipset flush. It also doesn't land in render cache.
2887 * However, we do have to enforce the order so that all writes through
2888 * the GTT land before any writes to the device, such as updates to
2893 old_write_domain = obj->base.write_domain;
2894 obj->base.write_domain = 0;
2897 /** Flushes the CPU write domain for the object if it's dirty. */
2899 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2901 uint32_t old_write_domain;
2903 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2906 i915_gem_clflush_object(obj);
2907 i915_gem_chipset_flush(obj->base.dev);
2908 old_write_domain = obj->base.write_domain;
2909 obj->base.write_domain = 0;
2913 * Moves a single object to the GTT read, and possibly write domain.
2915 * This function returns when the move is complete, including waiting on
2919 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2921 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2922 uint32_t old_write_domain, old_read_domains;
2925 /* Not valid to be called on unbound objects. */
2926 if (obj->gtt_space == NULL)
2929 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2932 ret = i915_gem_object_wait_rendering(obj, !write);
2936 i915_gem_object_flush_cpu_write_domain(obj);
2938 /* Serialise direct access to this object with the barriers for
2939 * coherent writes from the GPU, by effectively invalidating the
2940 * GTT domain upon first access.
2942 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2945 old_write_domain = obj->base.write_domain;
2946 old_read_domains = obj->base.read_domains;
2948 /* It should now be out of any other write domains, and we can update
2949 * the domain values for our changes.
2951 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2952 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2954 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2955 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2959 /* And bump the LRU for this access */
2960 if (i915_gem_object_is_inactive(obj))
2961 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2966 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2967 enum i915_cache_level cache_level)
2969 struct drm_device *dev = obj->base.dev;
2970 drm_i915_private_t *dev_priv = dev->dev_private;
2973 if (obj->cache_level == cache_level)
2976 if (obj->pin_count) {
2977 DRM_DEBUG("can not change the cache level of pinned objects\n");
2981 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
2982 ret = i915_gem_object_unbind(obj);
2987 if (obj->gtt_space) {
2988 ret = i915_gem_object_finish_gpu(obj);
2992 i915_gem_object_finish_gtt(obj);
2994 /* Before SandyBridge, you could not use tiling or fence
2995 * registers with snooped memory, so relinquish any fences
2996 * currently pointing to our region in the aperture.
2998 if (INTEL_INFO(dev)->gen < 6) {
2999 ret = i915_gem_object_put_fence(obj);
3004 if (obj->has_global_gtt_mapping)
3005 i915_gem_gtt_bind_object(obj, cache_level);
3006 if (obj->has_aliasing_ppgtt_mapping)
3007 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3010 obj->gtt_space->color = cache_level;
3013 if (cache_level == I915_CACHE_NONE) {
3014 u32 old_read_domains, old_write_domain;
3016 /* If we're coming from LLC cached, then we haven't
3017 * actually been tracking whether the data is in the
3018 * CPU cache or not, since we only allow one bit set
3019 * in obj->write_domain and have been skipping the clflushes.
3020 * Just set it to the CPU cache for now.
3022 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3023 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3025 old_read_domains = obj->base.read_domains;
3026 old_write_domain = obj->base.write_domain;
3028 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3029 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3033 obj->cache_level = cache_level;
3034 i915_gem_verify_gtt(dev);
3038 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3039 struct drm_file *file)
3041 struct drm_i915_gem_caching *args = data;
3042 struct drm_i915_gem_object *obj;
3045 ret = i915_mutex_lock_interruptible(dev);
3049 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3050 if (&obj->base == NULL) {
3055 args->caching = obj->cache_level != I915_CACHE_NONE;
3057 drm_gem_object_unreference(&obj->base);
3059 mutex_unlock(&dev->struct_mutex);
3063 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3064 struct drm_file *file)
3066 struct drm_i915_gem_caching *args = data;
3067 struct drm_i915_gem_object *obj;
3068 enum i915_cache_level level;
3071 switch (args->caching) {
3072 case I915_CACHING_NONE:
3073 level = I915_CACHE_NONE;
3075 case I915_CACHING_CACHED:
3076 level = I915_CACHE_LLC;
3082 ret = i915_mutex_lock_interruptible(dev);
3086 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3087 if (&obj->base == NULL) {
3092 ret = i915_gem_object_set_cache_level(obj, level);
3094 drm_gem_object_unreference(&obj->base);
3096 mutex_unlock(&dev->struct_mutex);
3101 * Prepare buffer for display plane (scanout, cursors, etc).
3102 * Can be called from an uninterruptible phase (modesetting) and allows
3103 * any flushes to be pipelined (for pageflips).
3106 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3108 struct intel_ring_buffer *pipelined)
3110 u32 old_read_domains, old_write_domain;
3113 if (pipelined != obj->ring) {
3114 ret = i915_gem_object_sync(obj, pipelined);
3119 /* The display engine is not coherent with the LLC cache on gen6. As
3120 * a result, we make sure that the pinning that is about to occur is
3121 * done with uncached PTEs. This is lowest common denominator for all
3124 * However for gen6+, we could do better by using the GFDT bit instead
3125 * of uncaching, which would allow us to flush all the LLC-cached data
3126 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3128 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3132 /* As the user may map the buffer once pinned in the display plane
3133 * (e.g. libkms for the bootup splash), we have to ensure that we
3134 * always use map_and_fenceable for all scanout buffers.
3136 ret = i915_gem_object_pin(obj, alignment, true, false);
3140 i915_gem_object_flush_cpu_write_domain(obj);
3142 old_write_domain = obj->base.write_domain;
3143 old_read_domains = obj->base.read_domains;
3145 /* It should now be out of any other write domains, and we can update
3146 * the domain values for our changes.
3148 obj->base.write_domain = 0;
3149 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3155 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3159 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3162 ret = i915_gem_object_wait_rendering(obj, false);
3166 /* Ensure that we invalidate the GPU's caches and TLBs. */
3167 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3172 * Moves a single object to the CPU read, and possibly write domain.
3174 * This function returns when the move is complete, including waiting on
3178 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3180 uint32_t old_write_domain, old_read_domains;
3183 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3186 ret = i915_gem_object_wait_rendering(obj, !write);
3190 i915_gem_object_flush_gtt_write_domain(obj);
3192 old_write_domain = obj->base.write_domain;
3193 old_read_domains = obj->base.read_domains;
3195 /* Flush the CPU cache if it's still invalid. */
3196 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3197 i915_gem_clflush_object(obj);
3199 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3202 /* It should now be out of any other write domains, and we can update
3203 * the domain values for our changes.
3205 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3207 /* If we're writing through the CPU, then the GPU read domains will
3208 * need to be invalidated at next use.
3211 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3212 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3218 /* Throttle our rendering by waiting until the ring has completed our requests
3219 * emitted over 20 msec ago.
3221 * Note that if we were to use the current jiffies each time around the loop,
3222 * we wouldn't escape the function with any frames outstanding if the time to
3223 * render a frame was over 20ms.
3225 * This should get us reasonable parallelism between CPU and GPU but also
3226 * relatively low latency when blocking on a particular request to finish.
3229 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 struct drm_i915_file_private *file_priv = file->driver_priv;
3233 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3234 struct drm_i915_gem_request *request;
3235 struct intel_ring_buffer *ring = NULL;
3236 unsigned reset_counter;
3240 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3244 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3248 spin_lock(&file_priv->mm.lock);
3249 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3250 if (time_after_eq(request->emitted_jiffies, recent_enough))
3253 ring = request->ring;
3254 seqno = request->seqno;
3256 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3257 spin_unlock(&file_priv->mm.lock);
3262 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3264 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3270 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3272 bool map_and_fenceable,
3277 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3280 if (obj->gtt_space != NULL) {
3281 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3282 (map_and_fenceable && !obj->map_and_fenceable)) {
3283 WARN(obj->pin_count,
3284 "bo is already pinned with incorrect alignment:"
3285 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3286 " obj->map_and_fenceable=%d\n",
3287 obj->gtt_offset, alignment,
3289 obj->map_and_fenceable);
3290 ret = i915_gem_object_unbind(obj);
3296 if (obj->gtt_space == NULL) {
3297 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3299 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3305 if (!dev_priv->mm.aliasing_ppgtt)
3306 i915_gem_gtt_bind_object(obj, obj->cache_level);
3309 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3310 i915_gem_gtt_bind_object(obj, obj->cache_level);
3313 obj->pin_mappable |= map_and_fenceable;
3319 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3321 BUG_ON(obj->pin_count == 0);
3322 BUG_ON(obj->gtt_space == NULL);
3324 if (--obj->pin_count == 0)
3325 obj->pin_mappable = false;
3329 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3330 struct drm_file *file)
3332 struct drm_i915_gem_pin *args = data;
3333 struct drm_i915_gem_object *obj;
3336 ret = i915_mutex_lock_interruptible(dev);
3340 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3341 if (&obj->base == NULL) {
3346 if (obj->madv != I915_MADV_WILLNEED) {
3347 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3352 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3353 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3359 if (obj->user_pin_count == 0) {
3360 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3365 obj->user_pin_count++;
3366 obj->pin_filp = file;
3368 /* XXX - flush the CPU caches for pinned objects
3369 * as the X server doesn't manage domains yet
3371 i915_gem_object_flush_cpu_write_domain(obj);
3372 args->offset = obj->gtt_offset;
3374 drm_gem_object_unreference(&obj->base);
3376 mutex_unlock(&dev->struct_mutex);
3381 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3382 struct drm_file *file)
3384 struct drm_i915_gem_pin *args = data;
3385 struct drm_i915_gem_object *obj;
3388 ret = i915_mutex_lock_interruptible(dev);
3392 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3393 if (&obj->base == NULL) {
3398 if (obj->pin_filp != file) {
3399 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3404 obj->user_pin_count--;
3405 if (obj->user_pin_count == 0) {
3406 obj->pin_filp = NULL;
3407 i915_gem_object_unpin(obj);
3411 drm_gem_object_unreference(&obj->base);
3413 mutex_unlock(&dev->struct_mutex);
3418 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3419 struct drm_file *file)
3421 struct drm_i915_gem_busy *args = data;
3422 struct drm_i915_gem_object *obj;
3425 ret = i915_mutex_lock_interruptible(dev);
3429 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3430 if (&obj->base == NULL) {
3435 /* Count all active objects as busy, even if they are currently not used
3436 * by the gpu. Users of this interface expect objects to eventually
3437 * become non-busy without any further actions, therefore emit any
3438 * necessary flushes here.
3440 ret = i915_gem_object_flush_active(obj);
3442 args->busy = obj->active;
3444 args->busy |= intel_ring_flag(obj->ring) << 16;
3447 drm_gem_object_unreference(&obj->base);
3449 mutex_unlock(&dev->struct_mutex);
3454 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3455 struct drm_file *file_priv)
3457 return i915_gem_ring_throttle(dev, file_priv);
3461 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3462 struct drm_file *file_priv)
3464 struct drm_i915_gem_madvise *args = data;
3465 struct drm_i915_gem_object *obj;
3468 switch (args->madv) {
3469 case I915_MADV_DONTNEED:
3470 case I915_MADV_WILLNEED:
3476 ret = i915_mutex_lock_interruptible(dev);
3480 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3481 if (&obj->base == NULL) {
3486 if (obj->pin_count) {
3491 if (obj->madv != __I915_MADV_PURGED)
3492 obj->madv = args->madv;
3494 /* if the object is no longer attached, discard its backing storage */
3495 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3496 i915_gem_object_truncate(obj);
3498 args->retained = obj->madv != __I915_MADV_PURGED;
3501 drm_gem_object_unreference(&obj->base);
3503 mutex_unlock(&dev->struct_mutex);
3507 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3508 const struct drm_i915_gem_object_ops *ops)
3510 INIT_LIST_HEAD(&obj->mm_list);
3511 INIT_LIST_HEAD(&obj->global_list);
3512 INIT_LIST_HEAD(&obj->ring_list);
3513 INIT_LIST_HEAD(&obj->exec_list);
3517 obj->fence_reg = I915_FENCE_REG_NONE;
3518 obj->madv = I915_MADV_WILLNEED;
3519 /* Avoid an unnecessary call to unbind on the first bind. */
3520 obj->map_and_fenceable = true;
3522 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3525 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3526 .get_pages = i915_gem_object_get_pages_gtt,
3527 .put_pages = i915_gem_object_put_pages_gtt,
3530 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3533 struct drm_i915_gem_object *obj;
3535 struct address_space *mapping;
3539 obj = kmalloc(sizeof(*obj), M_DRM, M_WAITOK | M_ZERO);
3543 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3549 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3550 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3551 /* 965gm cannot relocate objects above 4GiB. */
3552 mask &= ~__GFP_HIGHMEM;
3553 mask |= __GFP_DMA32;
3556 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3557 mapping_set_gfp_mask(mapping, mask);
3560 i915_gem_object_init(obj, &i915_gem_object_ops);
3562 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3563 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3566 /* On some devices, we can have the GPU use the LLC (the CPU
3567 * cache) for about a 10% performance improvement
3568 * compared to uncached. Graphics requests other than
3569 * display scanout are coherent with the CPU in
3570 * accessing this cache. This means in this mode we
3571 * don't need to clflush on the CPU side, and on the
3572 * GPU side we only need to flush internal caches to
3573 * get data visible to the CPU.
3575 * However, we maintain the display planes as UC, and so
3576 * need to rebind when first used as such.
3578 obj->cache_level = I915_CACHE_LLC;
3580 obj->cache_level = I915_CACHE_NONE;
3585 int i915_gem_init_object(struct drm_gem_object *obj)
3592 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3594 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3595 struct drm_device *dev = obj->base.dev;
3596 drm_i915_private_t *dev_priv = dev->dev_private;
3599 i915_gem_detach_phys_object(dev, obj);
3602 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3603 bool was_interruptible;
3605 was_interruptible = dev_priv->mm.interruptible;
3606 dev_priv->mm.interruptible = false;
3608 WARN_ON(i915_gem_object_unbind(obj));
3610 dev_priv->mm.interruptible = was_interruptible;
3613 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3614 * before progressing. */
3616 i915_gem_object_unpin_pages(obj);
3618 if (WARN_ON(obj->pages_pin_count))
3619 obj->pages_pin_count = 0;
3620 i915_gem_object_put_pages(obj);
3621 drm_gem_free_mmap_offset(&obj->base);
3625 drm_gem_object_release(&obj->base);
3626 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3629 i915_gem_object_free(obj);
3633 i915_gem_idle(struct drm_device *dev)
3635 drm_i915_private_t *dev_priv = dev->dev_private;
3638 mutex_lock(&dev->struct_mutex);
3640 if (dev_priv->mm.suspended) {
3641 mutex_unlock(&dev->struct_mutex);
3645 ret = i915_gpu_idle(dev);
3647 mutex_unlock(&dev->struct_mutex);
3650 i915_gem_retire_requests(dev);
3652 /* Under UMS, be paranoid and evict. */
3653 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3654 i915_gem_evict_everything(dev);
3656 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3657 * We need to replace this with a semaphore, or something.
3658 * And not confound mm.suspended!
3660 dev_priv->mm.suspended = 1;
3661 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
3663 i915_kernel_lost_context(dev);
3664 i915_gem_cleanup_ringbuffer(dev);
3666 mutex_unlock(&dev->struct_mutex);
3668 /* Cancel the retire work handler, which should be idle now. */
3669 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3674 void i915_gem_l3_remap(struct drm_device *dev)
3676 drm_i915_private_t *dev_priv = dev->dev_private;
3680 if (!HAS_L3_GPU_CACHE(dev))
3683 if (!dev_priv->l3_parity.remap_info)
3686 misccpctl = I915_READ(GEN7_MISCCPCTL);
3687 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3688 POSTING_READ(GEN7_MISCCPCTL);
3690 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3691 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3692 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3693 DRM_DEBUG("0x%x was already programmed to %x\n",
3694 GEN7_L3LOG_BASE + i, remap);
3695 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3696 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3697 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3700 /* Make sure all the writes land before disabling dop clock gating */
3701 POSTING_READ(GEN7_L3LOG_BASE);
3703 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3706 void i915_gem_init_swizzling(struct drm_device *dev)
3708 drm_i915_private_t *dev_priv = dev->dev_private;
3710 if (INTEL_INFO(dev)->gen < 5 ||
3711 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3714 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3715 DISP_TILE_SURFACE_SWIZZLING);
3720 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3722 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3723 else if (IS_GEN7(dev))
3724 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3730 intel_enable_blt(struct drm_device *dev)
3737 /* The blitter was dysfunctional on early prototypes */
3738 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
3739 if (IS_GEN6(dev) && revision < 8) {
3740 DRM_INFO("BLT not supported on this pre-production hardware;"
3741 " graphics performance will be degraded.\n");
3748 static int i915_gem_init_rings(struct drm_device *dev)
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3753 ret = intel_init_render_ring_buffer(dev);
3758 ret = intel_init_bsd_ring_buffer(dev);
3760 goto cleanup_render_ring;
3763 if (intel_enable_blt(dev)) {
3764 ret = intel_init_blt_ring_buffer(dev);
3766 goto cleanup_bsd_ring;
3769 if (HAS_VEBOX(dev)) {
3770 ret = intel_init_vebox_ring_buffer(dev);
3772 goto cleanup_blt_ring;
3776 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
3778 goto cleanup_vebox_ring;
3783 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
3785 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
3787 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3788 cleanup_render_ring:
3789 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3795 i915_gem_init_hw(struct drm_device *dev)
3797 drm_i915_private_t *dev_priv = dev->dev_private;
3801 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3805 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3806 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3808 if (HAS_PCH_NOP(dev)) {
3809 u32 temp = I915_READ(GEN7_MSG_CTL);
3810 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
3811 I915_WRITE(GEN7_MSG_CTL, temp);
3814 i915_gem_l3_remap(dev);
3816 i915_gem_init_swizzling(dev);
3818 ret = i915_gem_init_rings(dev);
3823 * XXX: There was some w/a described somewhere suggesting loading
3824 * contexts before PPGTT.
3826 i915_gem_context_init(dev);
3827 if (dev_priv->mm.aliasing_ppgtt) {
3828 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
3830 i915_gem_cleanup_aliasing_ppgtt(dev);
3831 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
3838 int i915_gem_init(struct drm_device *dev)
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3843 mutex_lock(&dev->struct_mutex);
3845 if (IS_VALLEYVIEW(dev)) {
3846 /* VLVA0 (potential hack), BIOS isn't actually waking us */
3847 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
3848 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
3849 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
3852 i915_gem_init_global_gtt(dev);
3854 ret = i915_gem_init_hw(dev);
3855 mutex_unlock(&dev->struct_mutex);
3857 i915_gem_cleanup_aliasing_ppgtt(dev);
3861 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3862 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3863 dev_priv->dri1.allow_batchbuffer = 1;
3868 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3870 drm_i915_private_t *dev_priv = dev->dev_private;
3871 struct intel_ring_buffer *ring;
3874 for_each_ring(ring, dev_priv, i)
3875 intel_cleanup_ring_buffer(ring);
3879 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3880 struct drm_file *file_priv)
3882 drm_i915_private_t *dev_priv = dev->dev_private;
3885 if (drm_core_check_feature(dev, DRIVER_MODESET))
3888 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
3889 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3890 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
3893 mutex_lock(&dev->struct_mutex);
3894 dev_priv->mm.suspended = 0;
3896 ret = i915_gem_init_hw(dev);
3898 mutex_unlock(&dev->struct_mutex);
3902 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
3903 mutex_unlock(&dev->struct_mutex);
3905 ret = drm_irq_install(dev);
3907 goto cleanup_ringbuffer;
3912 mutex_lock(&dev->struct_mutex);
3913 i915_gem_cleanup_ringbuffer(dev);
3914 dev_priv->mm.suspended = 1;
3915 mutex_unlock(&dev->struct_mutex);
3921 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3922 struct drm_file *file_priv)
3924 if (drm_core_check_feature(dev, DRIVER_MODESET))
3927 drm_irq_uninstall(dev);
3928 return i915_gem_idle(dev);
3932 i915_gem_lastclose(struct drm_device *dev)
3936 if (drm_core_check_feature(dev, DRIVER_MODESET))
3939 ret = i915_gem_idle(dev);
3941 DRM_ERROR("failed to idle hardware: %d\n", ret);
3945 init_ring_lists(struct intel_ring_buffer *ring)
3947 INIT_LIST_HEAD(&ring->active_list);
3948 INIT_LIST_HEAD(&ring->request_list);
3952 i915_gem_load(struct drm_device *dev)
3955 drm_i915_private_t *dev_priv = dev->dev_private;
3957 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3958 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3959 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
3960 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
3961 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3962 for (i = 0; i < I915_NUM_RINGS; i++)
3963 init_ring_lists(&dev_priv->ring[i]);
3964 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3965 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3966 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3967 i915_gem_retire_work_handler);
3968 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
3970 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3972 I915_WRITE(MI_ARB_STATE,
3973 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3976 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3978 /* Old X drivers will take 0-2 for front, back, depth buffers */
3979 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3980 dev_priv->fence_reg_start = 3;
3982 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
3983 dev_priv->num_fence_regs = 32;
3984 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3985 dev_priv->num_fence_regs = 16;
3987 dev_priv->num_fence_regs = 8;
3989 /* Initialize fence registers to zero */
3990 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3991 i915_gem_restore_fences(dev);
3993 i915_gem_detect_bit_6_swizzle(dev);
3994 init_waitqueue_head(&dev_priv->pending_flip_queue);
3996 dev_priv->mm.interruptible = true;
3999 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4000 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4001 register_shrinker(&dev_priv->mm.inactive_shrinker);
4003 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4004 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
4009 * Create a physically contiguous memory object for this object
4010 * e.g. for cursor + overlay regs
4012 static int i915_gem_init_phys_object(struct drm_device *dev,
4013 int id, int size, int align)
4015 drm_i915_private_t *dev_priv = dev->dev_private;
4016 struct drm_i915_gem_phys_object *phys_obj;
4019 if (dev_priv->mm.phys_objs[id - 1] || !size)
4022 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4028 phys_obj->handle = drm_pci_alloc(dev, size, align);
4029 if (!phys_obj->handle) {
4033 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4034 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4036 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4041 drm_free(phys_obj, M_DRM);
4045 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4047 drm_i915_private_t *dev_priv = dev->dev_private;
4048 struct drm_i915_gem_phys_object *phys_obj;
4050 if (!dev_priv->mm.phys_objs[id - 1])
4053 phys_obj = dev_priv->mm.phys_objs[id - 1];
4054 if (phys_obj->cur_obj) {
4055 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4058 drm_pci_free(dev, phys_obj->handle);
4059 drm_free(phys_obj, M_DRM);
4060 dev_priv->mm.phys_objs[id - 1] = NULL;
4063 void i915_gem_free_all_phys_object(struct drm_device *dev)
4067 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4068 i915_gem_free_phys_object(dev, i);
4071 void i915_gem_detach_phys_object(struct drm_device *dev,
4072 struct drm_i915_gem_object *obj)
4074 struct vm_object *mapping = obj->base.vm_obj;
4081 vaddr = obj->phys_obj->handle->vaddr;
4083 page_count = obj->base.size / PAGE_SIZE;
4084 VM_OBJECT_LOCK(obj->base.vm_obj);
4085 for (i = 0; i < page_count; i++) {
4086 struct vm_page *page = shmem_read_mapping_page(mapping, i);
4087 if (!IS_ERR(page)) {
4088 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4089 char *dst = kmap_atomic(page);
4090 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4093 drm_clflush_pages(&page, 1);
4096 set_page_dirty(page);
4097 mark_page_accessed(page);
4098 page_cache_release(page);
4100 VM_OBJECT_LOCK(obj->base.vm_obj);
4101 vm_page_reference(page);
4102 vm_page_dirty(page);
4103 vm_page_busy_wait(page, FALSE, "i915gem");
4104 vm_page_unwire(page, 0);
4105 vm_page_wakeup(page);
4108 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4109 intel_gtt_chipset_flush();
4111 obj->phys_obj->cur_obj = NULL;
4112 obj->phys_obj = NULL;
4116 i915_gem_attach_phys_object(struct drm_device *dev,
4117 struct drm_i915_gem_object *obj,
4121 struct vm_object *mapping = obj->base.vm_obj;
4122 drm_i915_private_t *dev_priv = dev->dev_private;
4127 if (id > I915_MAX_PHYS_OBJECT)
4130 if (obj->phys_obj) {
4131 if (obj->phys_obj->id == id)
4133 i915_gem_detach_phys_object(dev, obj);
4136 /* create a new object */
4137 if (!dev_priv->mm.phys_objs[id - 1]) {
4138 ret = i915_gem_init_phys_object(dev, id,
4139 obj->base.size, align);
4141 DRM_ERROR("failed to init phys object %d size: %zu\n",
4142 id, obj->base.size);
4147 /* bind to the object */
4148 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4149 obj->phys_obj->cur_obj = obj;
4151 page_count = obj->base.size / PAGE_SIZE;
4153 VM_OBJECT_LOCK(obj->base.vm_obj);
4154 for (i = 0; i < page_count; i++) {
4155 struct vm_page *page;
4158 page = shmem_read_mapping_page(mapping, i);
4159 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4161 return PTR_ERR(page);
4163 src = kmap_atomic(page);
4164 dst = (char*)obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4165 memcpy(dst, src, PAGE_SIZE);
4169 mark_page_accessed(page);
4170 page_cache_release(page);
4172 VM_OBJECT_LOCK(obj->base.vm_obj);
4173 vm_page_reference(page);
4174 vm_page_busy_wait(page, FALSE, "i915gem");
4175 vm_page_unwire(page, 0);
4176 vm_page_wakeup(page);
4178 VM_OBJECT_UNLOCK(obj->base.vm_obj);
4184 i915_gem_phys_pwrite(struct drm_device *dev,
4185 struct drm_i915_gem_object *obj,
4186 struct drm_i915_gem_pwrite *args,
4187 struct drm_file *file_priv)
4189 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4190 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4192 if (copyin_nofault(user_data, vaddr, args->size) != 0) {
4193 unsigned long unwritten;
4195 /* The physical object once assigned is fixed for the lifetime
4196 * of the obj, so we can safely drop the lock and continue
4199 mutex_unlock(&dev->struct_mutex);
4200 unwritten = copy_from_user(vaddr, user_data, args->size);
4201 mutex_lock(&dev->struct_mutex);
4206 i915_gem_chipset_flush(dev);
4210 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4212 struct drm_i915_file_private *file_priv = file->driver_priv;
4214 /* Clean up our request list when the client is going away, so that
4215 * later retire_requests won't dereference our soon-to-be-gone
4218 spin_lock(&file_priv->mm.lock);
4219 while (!list_empty(&file_priv->mm.request_list)) {
4220 struct drm_i915_gem_request *request;
4222 request = list_first_entry(&file_priv->mm.request_list,
4223 struct drm_i915_gem_request,
4225 list_del(&request->client_list);
4226 request->file_priv = NULL;
4228 spin_unlock(&file_priv->mm.lock);
4232 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
4233 vm_ooffset_t foff, struct ucred *cred, u_short *color)
4236 *color = 0; /* XXXKIB */
4243 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
4246 struct drm_gem_object *gem_obj;
4247 struct drm_i915_gem_object *obj;
4248 struct drm_device *dev;
4249 drm_i915_private_t *dev_priv;
4254 gem_obj = vm_obj->handle;
4255 obj = to_intel_bo(gem_obj);
4256 dev = obj->base.dev;
4257 dev_priv = dev->dev_private;
4259 write = (prot & VM_PROT_WRITE) != 0;
4263 vm_object_pip_add(vm_obj, 1);
4266 * Remove the placeholder page inserted by vm_fault() from the
4267 * object before dropping the object lock. If
4268 * i915_gem_release_mmap() is active in parallel on this gem
4269 * object, then it owns the drm device sx and might find the
4270 * placeholder already. Then, since the page is busy,
4271 * i915_gem_release_mmap() sleeps waiting for the busy state
4272 * of the page cleared. We will be not able to acquire drm
4273 * device lock until i915_gem_release_mmap() is able to make a
4276 if (*mres != NULL) {
4278 vm_page_remove(oldm);
4283 VM_OBJECT_UNLOCK(vm_obj);
4289 ret = i915_mutex_lock_interruptible(dev);
4295 mutex_lock(&dev->struct_mutex);
4298 * Since the object lock was dropped, other thread might have
4299 * faulted on the same GTT address and instantiated the
4300 * mapping for the page. Recheck.
4302 VM_OBJECT_LOCK(vm_obj);
4303 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
4305 if ((m->flags & PG_BUSY) != 0) {
4306 mutex_unlock(&dev->struct_mutex);
4308 vm_page_sleep(m, "915pee");
4314 VM_OBJECT_UNLOCK(vm_obj);
4316 /* Access to snoopable pages through the GTT is incoherent. */
4317 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
4322 /* Now bind it into the GTT if needed */
4323 if (!obj->map_and_fenceable) {
4324 ret = i915_gem_object_unbind(obj);
4330 if (!obj->gtt_space) {
4331 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
4337 ret = i915_gem_object_set_to_gtt_domain(obj, write);
4344 if (obj->tiling_mode == I915_TILING_NONE)
4345 ret = i915_gem_object_put_fence(obj);
4347 ret = i915_gem_object_get_fence(obj);
4353 if (i915_gem_object_is_inactive(obj))
4354 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
4356 obj->fault_mappable = true;
4357 VM_OBJECT_LOCK(vm_obj);
4358 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
4365 KASSERT((m->flags & PG_FICTITIOUS) != 0,
4366 ("not fictitious %p", m));
4367 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
4369 if ((m->flags & PG_BUSY) != 0) {
4370 mutex_unlock(&dev->struct_mutex);
4372 vm_page_sleep(m, "915pbs");
4376 m->valid = VM_PAGE_BITS_ALL;
4377 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
4380 vm_page_busy_try(m, false);
4382 mutex_unlock(&dev->struct_mutex);
4386 vm_object_pip_wakeup(vm_obj);
4387 return (VM_PAGER_OK);
4390 mutex_unlock(&dev->struct_mutex);
4392 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
4393 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
4394 goto unlocked_vmobj;
4396 VM_OBJECT_LOCK(vm_obj);
4397 vm_object_pip_wakeup(vm_obj);
4398 return (VM_PAGER_ERROR);
4402 i915_gem_pager_dtor(void *handle)
4404 struct drm_gem_object *obj;
4405 struct drm_device *dev;
4410 mutex_lock(&dev->struct_mutex);
4411 drm_gem_free_mmap_offset(obj);
4412 i915_gem_release_mmap(to_intel_bo(obj));
4413 drm_gem_object_unreference(obj);
4414 mutex_unlock(&dev->struct_mutex);
4417 struct cdev_pager_ops i915_gem_pager_ops = {
4418 .cdev_pg_fault = i915_gem_pager_fault,
4419 .cdev_pg_ctor = i915_gem_pager_ctor,
4420 .cdev_pg_dtor = i915_gem_pager_dtor
4423 #define GEM_PARANOID_CHECK_GTT 0
4424 #if GEM_PARANOID_CHECK_GTT
4426 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
4429 struct drm_i915_private *dev_priv;
4431 unsigned long start, end;
4435 dev_priv = dev->dev_private;
4436 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
4437 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
4438 for (i = start; i < end; i++) {
4439 pa = intel_gtt_read_pte_paddr(i);
4440 for (j = 0; j < page_count; j++) {
4441 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
4442 panic("Page %p in GTT pte index %d pte %x",
4443 ma[i], i, intel_gtt_read_pte(i));
4447 obj->fence_dirty = false;
4452 i915_gpu_is_active(struct drm_device *dev)
4454 drm_i915_private_t *dev_priv = dev->dev_private;
4456 return !list_empty(&dev_priv->mm.active_list);
4460 i915_gem_lowmem(void *arg)
4462 struct drm_device *dev;
4463 struct drm_i915_private *dev_priv;
4464 struct drm_i915_gem_object *obj, *next;
4465 int cnt, cnt_fail, cnt_total;
4468 dev_priv = dev->dev_private;
4470 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT))
4474 /* first scan for clean buffers */
4475 i915_gem_retire_requests(dev);
4477 cnt_total = cnt_fail = cnt = 0;
4479 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4481 if (i915_gem_object_is_purgeable(obj)) {
4482 if (i915_gem_object_unbind(obj) != 0)
4488 /* second pass, evict/count anything still on the inactive list */
4489 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4491 if (i915_gem_object_unbind(obj) == 0)
4497 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
4499 * We are desperate for pages, so as a last resort, wait
4500 * for the GPU to finish and discard whatever we can.
4501 * This has a dramatic impact to reduce the number of
4502 * OOM-killer events whilst running the GPU aggressively.
4504 if (i915_gpu_idle(dev) == 0)
4507 mutex_unlock(&dev->struct_mutex);