2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon_asic.h"
29 #include "cypress_dpm.h"
31 #include <linux/seq_file.h>
33 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
34 #define SUMO_MINIMUM_ENGINE_CLOCK 800
35 #define BOOST_DPM_LEVEL 7
37 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
56 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
75 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
77 static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
79 struct sumo_ps *ps = rps->ps_priv;
84 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
86 struct sumo_power_info *pi = rdev->pm.dpm.priv;
91 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
94 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
96 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
97 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
98 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
99 RREG32(GB_ADDR_CONFIG);
103 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
104 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
106 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
111 local0 = RREG32(CG_CGTT_LOCAL_0);
112 local1 = RREG32(CG_CGTT_LOCAL_1);
115 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
116 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
118 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
119 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
123 static void sumo_program_git(struct radeon_device *rdev)
126 u32 xclk = radeon_get_xclk(rdev);
128 r600_calculate_u_and_p(SUMO_GICST_DFLT,
131 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
134 static void sumo_program_grsd(struct radeon_device *rdev)
137 u32 xclk = radeon_get_xclk(rdev);
138 u32 grs = 256 * 25 / 100;
140 r600_calculate_u_and_p(1, xclk, 14, &p, &u);
142 WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
145 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
147 sumo_program_git(rdev);
148 sumo_program_grsd(rdev);
151 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
153 u32 rcu_pwr_gating_cntl;
157 u32 xclk = radeon_get_xclk(rdev);
159 if (rdev->family == CHIP_PALM) {
164 p_p = 50 + 1000/200 + 6 * 32;
173 WREG32(CG_SCRATCH2, 0x01B60A17);
175 r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
178 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
179 ~(PGP_MASK | PGU_MASK));
181 r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
184 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
185 ~(PGP_MASK | PGU_MASK));
187 if (rdev->family == CHIP_PALM) {
188 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
189 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
191 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
192 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
195 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
196 rcu_pwr_gating_cntl &=
197 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
198 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
199 if (rdev->family == CHIP_PALM) {
200 rcu_pwr_gating_cntl &= ~PCP_MASK;
201 rcu_pwr_gating_cntl |= PCP(0x77);
203 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
205 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
206 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
207 rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
208 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
210 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
211 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
212 rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
213 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
215 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
216 rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
217 rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
218 WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
220 if (rdev->family == CHIP_PALM)
221 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
223 sumo_smu_pg_init(rdev);
225 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
226 rcu_pwr_gating_cntl &=
227 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
228 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
229 if (rdev->family == CHIP_PALM) {
230 rcu_pwr_gating_cntl &= ~PCP_MASK;
231 rcu_pwr_gating_cntl |= PCP(0x77);
233 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
235 if (rdev->family == CHIP_PALM) {
236 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
237 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
238 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
239 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
241 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
242 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
243 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
244 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
247 sumo_smu_pg_init(rdev);
249 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
250 rcu_pwr_gating_cntl &=
251 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
252 rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
254 if (rdev->family == CHIP_PALM) {
255 rcu_pwr_gating_cntl |= PCV(4);
256 rcu_pwr_gating_cntl &= ~PCP_MASK;
257 rcu_pwr_gating_cntl |= PCP(0x77);
259 rcu_pwr_gating_cntl |= PCV(11);
260 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
262 if (rdev->family == CHIP_PALM) {
263 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
264 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
265 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
266 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
268 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
269 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
270 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
271 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
274 sumo_smu_pg_init(rdev);
277 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
280 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
282 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
283 RREG32(GB_ADDR_CONFIG);
287 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
289 struct sumo_power_info *pi = sumo_get_pi(rdev);
291 if (pi->enable_gfx_clock_gating)
292 sumo_gfx_clockgating_initialize(rdev);
293 if (pi->enable_gfx_power_gating)
294 sumo_gfx_powergating_initialize(rdev);
295 if (pi->enable_mg_clock_gating)
296 sumo_mg_clockgating_enable(rdev, true);
297 if (pi->enable_gfx_clock_gating)
298 sumo_gfx_clockgating_enable(rdev, true);
299 if (pi->enable_gfx_power_gating)
300 sumo_gfx_powergating_enable(rdev, true);
305 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
307 struct sumo_power_info *pi = sumo_get_pi(rdev);
309 if (pi->enable_gfx_clock_gating)
310 sumo_gfx_clockgating_enable(rdev, false);
311 if (pi->enable_gfx_power_gating)
312 sumo_gfx_powergating_enable(rdev, false);
313 if (pi->enable_mg_clock_gating)
314 sumo_mg_clockgating_enable(rdev, false);
317 static void sumo_calculate_bsp(struct radeon_device *rdev,
320 struct sumo_power_info *pi = sumo_get_pi(rdev);
321 u32 xclk = radeon_get_xclk(rdev);
323 pi->pasi = 65535 * 100 / high_clk;
324 pi->asi = 65535 * 100 / high_clk;
326 r600_calculate_u_and_p(pi->asi,
327 xclk, 16, &pi->bsp, &pi->bsu);
329 r600_calculate_u_and_p(pi->pasi,
330 xclk, 16, &pi->pbsp, &pi->pbsu);
332 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
333 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
336 static void sumo_init_bsp(struct radeon_device *rdev)
338 struct sumo_power_info *pi = sumo_get_pi(rdev);
340 WREG32(CG_BSP_0, pi->psp);
344 static void sumo_program_bsp(struct radeon_device *rdev,
345 struct radeon_ps *rps)
347 struct sumo_power_info *pi = sumo_get_pi(rdev);
348 struct sumo_ps *ps = sumo_get_ps(rps);
350 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
352 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
353 highest_engine_clock = pi->boost_pl.sclk;
355 sumo_calculate_bsp(rdev, highest_engine_clock);
357 for (i = 0; i < ps->num_levels - 1; i++)
358 WREG32(CG_BSP_0 + (i * 4), pi->dsp);
360 WREG32(CG_BSP_0 + (i * 4), pi->psp);
362 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
363 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
366 static void sumo_write_at(struct radeon_device *rdev,
367 u32 index, u32 value)
370 WREG32(CG_AT_0, value);
372 WREG32(CG_AT_1, value);
374 WREG32(CG_AT_2, value);
376 WREG32(CG_AT_3, value);
378 WREG32(CG_AT_4, value);
380 WREG32(CG_AT_5, value);
382 WREG32(CG_AT_6, value);
384 WREG32(CG_AT_7, value);
387 static void sumo_program_at(struct radeon_device *rdev,
388 struct radeon_ps *rps)
390 struct sumo_power_info *pi = sumo_get_pi(rdev);
391 struct sumo_ps *ps = sumo_get_ps(rps);
396 u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
397 u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
411 for (i = 0; i < ps->num_levels; i++) {
412 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
414 m_a = asi * ps->levels[i].sclk / 100;
416 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
418 sumo_write_at(rdev, i, a_t);
421 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
424 m_a = asi * pi->boost_pl.sclk / 100;
426 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
427 CG_L(m_a * l[ps->num_levels - 1] / 100);
429 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
433 static void sumo_program_tp(struct radeon_device *rdev)
436 enum r600_td td = R600_TD_DFLT;
438 for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
439 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
440 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
443 if (td == R600_TD_AUTO)
444 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
446 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
448 if (td == R600_TD_UP)
449 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
451 if (td == R600_TD_DOWN)
452 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
455 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
460 void sumo_clear_vc(struct radeon_device *rdev)
465 void sumo_program_sstp(struct radeon_device *rdev)
468 u32 xclk = radeon_get_xclk(rdev);
470 r600_calculate_u_and_p(SUMO_SST_DFLT,
473 WREG32(CG_SSP, SSTU(u) | SST(p));
476 static void sumo_set_divider_value(struct radeon_device *rdev,
477 u32 index, u32 divider)
479 u32 reg_index = index / 4;
480 u32 field_index = index % 4;
482 if (field_index == 0)
483 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
484 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
485 else if (field_index == 1)
486 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
487 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
488 else if (field_index == 2)
489 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
490 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
491 else if (field_index == 3)
492 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
493 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
496 static void sumo_set_ds_dividers(struct radeon_device *rdev,
497 u32 index, u32 divider)
499 struct sumo_power_info *pi = sumo_get_pi(rdev);
501 if (pi->enable_sclk_ds) {
502 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
504 dpm_ctrl &= ~(0x7 << (index * 3));
505 dpm_ctrl |= (divider << (index * 3));
506 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
510 static void sumo_set_ss_dividers(struct radeon_device *rdev,
511 u32 index, u32 divider)
513 struct sumo_power_info *pi = sumo_get_pi(rdev);
515 if (pi->enable_sclk_ds) {
516 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
518 dpm_ctrl &= ~(0x7 << (index * 3));
519 dpm_ctrl |= (divider << (index * 3));
520 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
524 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
526 u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
528 voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
529 voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
530 WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
533 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
535 struct sumo_power_info *pi = sumo_get_pi(rdev);
537 u32 cg_sclk_dpm_ctrl_3;
539 if (pi->driver_nbps_policy_disable)
542 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
543 cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
544 cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
546 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
549 static void sumo_program_power_level(struct radeon_device *rdev,
550 struct sumo_pl *pl, u32 index)
552 struct sumo_power_info *pi = sumo_get_pi(rdev);
554 struct atom_clock_dividers dividers;
555 u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
557 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
558 pl->sclk, false, ÷rs);
562 sumo_set_divider_value(rdev, index, dividers.post_div);
564 sumo_set_vid(rdev, index, pl->vddc_index);
566 if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
568 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
570 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
571 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
574 WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
577 sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
579 if (pi->enable_boost)
580 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
583 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
585 u32 reg_index = index / 4;
586 u32 field_index = index % 4;
588 if (field_index == 0)
589 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
590 enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
591 else if (field_index == 1)
592 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
593 enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
594 else if (field_index == 2)
595 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
596 enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
597 else if (field_index == 3)
598 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
599 enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
602 static bool sumo_dpm_enabled(struct radeon_device *rdev)
604 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
610 static void sumo_start_dpm(struct radeon_device *rdev)
612 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
615 static void sumo_stop_dpm(struct radeon_device *rdev)
617 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
620 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
623 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
625 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
628 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
632 sumo_set_forced_mode(rdev, true);
633 for (i = 0; i < rdev->usec_timeout; i++) {
634 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
640 static void sumo_wait_for_level_0(struct radeon_device *rdev)
644 for (i = 0; i < rdev->usec_timeout; i++) {
645 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
649 for (i = 0; i < rdev->usec_timeout; i++) {
650 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
656 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
658 sumo_set_forced_mode(rdev, false);
661 static void sumo_enable_power_level_0(struct radeon_device *rdev)
663 sumo_power_level_enable(rdev, 0, true);
666 static void sumo_patch_boost_state(struct radeon_device *rdev,
667 struct radeon_ps *rps)
669 struct sumo_power_info *pi = sumo_get_pi(rdev);
670 struct sumo_ps *new_ps = sumo_get_ps(rps);
672 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
673 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
674 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
675 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
676 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
680 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
681 struct radeon_ps *new_rps,
682 struct radeon_ps *old_rps)
684 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
685 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
690 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
692 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
694 if (nbps1_old == 1 && nbps1_new == 0)
695 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
698 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
699 struct radeon_ps *new_rps,
700 struct radeon_ps *old_rps)
702 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
703 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
708 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
710 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
712 if (nbps1_old == 0 && nbps1_new == 1)
713 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
716 static void sumo_enable_boost(struct radeon_device *rdev,
717 struct radeon_ps *rps,
720 struct sumo_ps *new_ps = sumo_get_ps(rps);
723 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
724 sumo_boost_state_enable(rdev, true);
726 sumo_boost_state_enable(rdev, false);
729 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
731 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
734 static void sumo_set_forced_level_0(struct radeon_device *rdev)
736 sumo_set_forced_level(rdev, 0);
739 static void sumo_program_wl(struct radeon_device *rdev,
740 struct radeon_ps *rps)
742 struct sumo_ps *new_ps = sumo_get_ps(rps);
743 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
745 dpm_ctrl4 &= 0xFFFFFF00;
746 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
748 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
749 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
751 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
754 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
755 struct radeon_ps *new_rps,
756 struct radeon_ps *old_rps)
758 struct sumo_power_info *pi = sumo_get_pi(rdev);
759 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
760 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
762 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
764 for (i = 0; i < new_ps->num_levels; i++) {
765 sumo_program_power_level(rdev, &new_ps->levels[i], i);
766 sumo_power_level_enable(rdev, i, true);
769 for (i = new_ps->num_levels; i < n_current_state_levels; i++)
770 sumo_power_level_enable(rdev, i, false);
772 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
773 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
776 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
778 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
781 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
783 WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
786 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
788 struct sumo_power_info *pi = sumo_get_pi(rdev);
789 struct atom_clock_dividers dividers;
792 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
798 WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
799 WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
802 static void sumo_program_bootup_state(struct radeon_device *rdev)
804 struct sumo_power_info *pi = sumo_get_pi(rdev);
805 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
808 sumo_program_power_level(rdev, &pi->boot_pl, 0);
810 dpm_ctrl4 &= 0xFFFFFF00;
811 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
813 for (i = 1; i < 8; i++)
814 sumo_power_level_enable(rdev, i, false);
817 static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
818 struct radeon_ps *new_rps,
819 struct radeon_ps *old_rps)
821 struct sumo_power_info *pi = sumo_get_pi(rdev);
823 if (pi->enable_gfx_power_gating) {
824 sumo_gfx_powergating_enable(rdev, false);
827 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
829 if (pi->enable_gfx_power_gating) {
830 if (!pi->disable_gfx_power_gating_in_uvd ||
831 !r600_is_uvd_state(new_rps->class, new_rps->class2))
832 sumo_gfx_powergating_enable(rdev, true);
836 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
837 struct radeon_ps *new_rps,
838 struct radeon_ps *old_rps)
840 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
841 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
843 if ((new_rps->vclk == old_rps->vclk) &&
844 (new_rps->dclk == old_rps->dclk))
847 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
848 current_ps->levels[current_ps->num_levels - 1].sclk)
851 sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
854 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
855 struct radeon_ps *new_rps,
856 struct radeon_ps *old_rps)
858 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
859 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
861 if ((new_rps->vclk == old_rps->vclk) &&
862 (new_rps->dclk == old_rps->dclk))
865 if (new_ps->levels[new_ps->num_levels - 1].sclk <
866 current_ps->levels[current_ps->num_levels - 1].sclk)
869 sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
872 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
874 /* This bit selects who handles display phy powergating.
875 * Clear the bit to let atom handle it.
876 * Set it to let the driver handle it.
877 * For now we just let atom handle it.
880 u32 v = RREG32(DOUT_SCRATCH3);
887 WREG32(DOUT_SCRATCH3, v);
891 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
894 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
895 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
898 deep_sleep_cntl &= ~R_DIS;
899 deep_sleep_cntl &= ~HS_MASK;
900 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
902 deep_sleep_cntl2 |= LB_UFP_EN;
903 deep_sleep_cntl2 &= INOUT_C_MASK;
904 deep_sleep_cntl2 |= INOUT_C(0xf);
906 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
907 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
909 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
912 static void sumo_program_bootup_at(struct radeon_device *rdev)
914 WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
915 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
918 static void sumo_reset_am(struct radeon_device *rdev)
920 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
923 static void sumo_start_am(struct radeon_device *rdev)
925 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
928 static void sumo_program_ttp(struct radeon_device *rdev)
930 u32 xclk = radeon_get_xclk(rdev);
932 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
934 r600_calculate_u_and_p(1000,
937 cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
938 cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
940 WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
943 static void sumo_program_ttt(struct radeon_device *rdev)
945 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
946 struct sumo_power_info *pi = sumo_get_pi(rdev);
948 cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
949 cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
951 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
955 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
958 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
959 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
961 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
962 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
966 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
968 WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
969 ~CNB_THERMTHRO_MASK_SCLK);
972 static void sumo_program_dc_hto(struct radeon_device *rdev)
974 u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
976 u32 xclk = radeon_get_xclk(rdev);
978 r600_calculate_u_and_p(100000,
981 cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
982 cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
984 WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
987 static void sumo_force_nbp_state(struct radeon_device *rdev,
988 struct radeon_ps *rps)
990 struct sumo_power_info *pi = sumo_get_pi(rdev);
991 struct sumo_ps *new_ps = sumo_get_ps(rps);
993 if (!pi->driver_nbps_policy_disable) {
994 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
995 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
997 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
1001 u32 sumo_get_sleep_divider_from_id(u32 id)
1006 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1010 struct sumo_power_info *pi = sumo_get_pi(rdev);
1013 u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
1014 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
1019 if (!pi->enable_sclk_ds)
1022 for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1023 temp = sclk / sumo_get_sleep_divider_from_id(i);
1025 if (temp >= min || i == 0)
1031 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1034 struct sumo_power_info *pi = sumo_get_pi(rdev);
1037 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1038 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1039 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1042 return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1045 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1047 struct sumo_ps *current_ps)
1049 struct sumo_power_info *pi = sumo_get_pi(rdev);
1050 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1053 u32 current_index = 0;
1056 current_vddc = current_ps->levels[current_index].vddc_index;
1057 current_sclk = current_ps->levels[current_index].sclk;
1059 current_vddc = pi->boot_pl.vddc_index;
1060 current_sclk = pi->boot_pl.sclk;
1063 ps->levels[0].vddc_index = current_vddc;
1065 if (ps->levels[0].sclk > current_sclk)
1066 ps->levels[0].sclk = current_sclk;
1068 ps->levels[0].ss_divider_index =
1069 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1071 ps->levels[0].ds_divider_index =
1072 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1074 if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1075 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1077 if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1078 if (ps->levels[0].ss_divider_index > 1)
1079 ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1082 if (ps->levels[0].ss_divider_index == 0)
1083 ps->levels[0].ds_divider_index = 0;
1085 if (ps->levels[0].ds_divider_index == 0)
1086 ps->levels[0].ss_divider_index = 0;
1089 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1090 struct radeon_ps *new_rps,
1091 struct radeon_ps *old_rps)
1093 struct sumo_ps *ps = sumo_get_ps(new_rps);
1094 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1095 struct sumo_power_info *pi = sumo_get_pi(rdev);
1096 u32 min_voltage = 0; /* ??? */
1097 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1098 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1101 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1102 return sumo_patch_thermal_state(rdev, ps, current_ps);
1104 if (pi->enable_boost) {
1105 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1106 ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1109 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1110 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1111 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1112 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1114 for (i = 0; i < ps->num_levels; i++) {
1115 if (ps->levels[i].vddc_index < min_voltage)
1116 ps->levels[i].vddc_index = min_voltage;
1118 if (ps->levels[i].sclk < min_sclk)
1119 ps->levels[i].sclk =
1120 sumo_get_valid_engine_clock(rdev, min_sclk);
1122 ps->levels[i].ss_divider_index =
1123 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1125 ps->levels[i].ds_divider_index =
1126 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1128 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1129 ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1131 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1132 if (ps->levels[i].ss_divider_index > 1)
1133 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1136 if (ps->levels[i].ss_divider_index == 0)
1137 ps->levels[i].ds_divider_index = 0;
1139 if (ps->levels[i].ds_divider_index == 0)
1140 ps->levels[i].ss_divider_index = 0;
1142 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1143 ps->levels[i].allow_gnb_slow = 1;
1144 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1145 (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1146 ps->levels[i].allow_gnb_slow = 0;
1147 else if (i == ps->num_levels - 1)
1148 ps->levels[i].allow_gnb_slow = 0;
1150 ps->levels[i].allow_gnb_slow = 1;
1154 static void sumo_cleanup_asic(struct radeon_device *rdev)
1156 sumo_take_smu_control(rdev, false);
1159 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1160 int min_temp, int max_temp)
1162 int low_temp = 0 * 1000;
1163 int high_temp = 255 * 1000;
1165 if (low_temp < min_temp)
1166 low_temp = min_temp;
1167 if (high_temp > max_temp)
1168 high_temp = max_temp;
1169 if (high_temp < low_temp) {
1170 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1174 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1175 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1177 rdev->pm.dpm.thermal.min_temp = low_temp;
1178 rdev->pm.dpm.thermal.max_temp = high_temp;
1183 static void sumo_update_current_ps(struct radeon_device *rdev,
1184 struct radeon_ps *rps)
1186 struct sumo_ps *new_ps = sumo_get_ps(rps);
1187 struct sumo_power_info *pi = sumo_get_pi(rdev);
1189 pi->current_rps = *rps;
1190 pi->current_ps = *new_ps;
1191 pi->current_rps.ps_priv = &pi->current_ps;
1194 static void sumo_update_requested_ps(struct radeon_device *rdev,
1195 struct radeon_ps *rps)
1197 struct sumo_ps *new_ps = sumo_get_ps(rps);
1198 struct sumo_power_info *pi = sumo_get_pi(rdev);
1200 pi->requested_rps = *rps;
1201 pi->requested_ps = *new_ps;
1202 pi->requested_rps.ps_priv = &pi->requested_ps;
1205 int sumo_dpm_enable(struct radeon_device *rdev)
1207 struct sumo_power_info *pi = sumo_get_pi(rdev);
1209 if (sumo_dpm_enabled(rdev))
1212 sumo_program_bootup_state(rdev);
1213 sumo_init_bsp(rdev);
1214 sumo_reset_am(rdev);
1215 sumo_program_tp(rdev);
1216 sumo_program_bootup_at(rdev);
1217 sumo_start_am(rdev);
1218 if (pi->enable_auto_thermal_throttling) {
1219 sumo_program_ttp(rdev);
1220 sumo_program_ttt(rdev);
1222 sumo_program_dc_hto(rdev);
1223 sumo_program_power_level_enter_state(rdev);
1224 sumo_enable_voltage_scaling(rdev, true);
1225 sumo_program_sstp(rdev);
1226 sumo_program_vc(rdev, SUMO_VRC_DFLT);
1227 sumo_override_cnb_thermal_events(rdev);
1228 sumo_start_dpm(rdev);
1229 sumo_wait_for_level_0(rdev);
1230 if (pi->enable_sclk_ds)
1231 sumo_enable_sclk_ds(rdev, true);
1232 if (pi->enable_boost)
1233 sumo_enable_boost_timer(rdev);
1235 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1240 int sumo_dpm_late_enable(struct radeon_device *rdev)
1244 ret = sumo_enable_clock_power_gating(rdev);
1248 if (rdev->irq.installed &&
1249 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1250 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1253 rdev->irq.dpm_thermal = true;
1254 radeon_irq_set(rdev);
1260 void sumo_dpm_disable(struct radeon_device *rdev)
1262 struct sumo_power_info *pi = sumo_get_pi(rdev);
1264 if (!sumo_dpm_enabled(rdev))
1266 sumo_disable_clock_power_gating(rdev);
1267 if (pi->enable_sclk_ds)
1268 sumo_enable_sclk_ds(rdev, false);
1269 sumo_clear_vc(rdev);
1270 sumo_wait_for_level_0(rdev);
1271 sumo_stop_dpm(rdev);
1272 sumo_enable_voltage_scaling(rdev, false);
1274 if (rdev->irq.installed &&
1275 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1276 rdev->irq.dpm_thermal = false;
1277 radeon_irq_set(rdev);
1280 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1283 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1285 struct sumo_power_info *pi = sumo_get_pi(rdev);
1286 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1287 struct radeon_ps *new_ps = &requested_ps;
1289 sumo_update_requested_ps(rdev, new_ps);
1291 if (pi->enable_dynamic_patch_ps)
1292 sumo_apply_state_adjust_rules(rdev,
1299 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1301 struct sumo_power_info *pi = sumo_get_pi(rdev);
1302 struct radeon_ps *new_ps = &pi->requested_rps;
1303 struct radeon_ps *old_ps = &pi->current_rps;
1306 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1307 if (pi->enable_boost) {
1308 sumo_enable_boost(rdev, new_ps, false);
1309 sumo_patch_boost_state(rdev, new_ps);
1311 if (pi->enable_dpm) {
1312 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1313 sumo_enable_power_level_0(rdev);
1314 sumo_set_forced_level_0(rdev);
1315 sumo_set_forced_mode_enabled(rdev);
1316 sumo_wait_for_level_0(rdev);
1317 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1318 sumo_program_wl(rdev, new_ps);
1319 sumo_program_bsp(rdev, new_ps);
1320 sumo_program_at(rdev, new_ps);
1321 sumo_force_nbp_state(rdev, new_ps);
1322 sumo_set_forced_mode_disabled(rdev);
1323 sumo_set_forced_mode_enabled(rdev);
1324 sumo_set_forced_mode_disabled(rdev);
1325 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1327 if (pi->enable_boost)
1328 sumo_enable_boost(rdev, new_ps, true);
1330 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1335 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1337 struct sumo_power_info *pi = sumo_get_pi(rdev);
1338 struct radeon_ps *new_ps = &pi->requested_rps;
1340 sumo_update_current_ps(rdev, new_ps);
1344 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1346 sumo_program_bootup_state(rdev);
1347 sumo_enable_power_level_0(rdev);
1348 sumo_set_forced_level_0(rdev);
1349 sumo_set_forced_mode_enabled(rdev);
1350 sumo_wait_for_level_0(rdev);
1351 sumo_set_forced_mode_disabled(rdev);
1352 sumo_set_forced_mode_enabled(rdev);
1353 sumo_set_forced_mode_disabled(rdev);
1357 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1359 struct sumo_power_info *pi = sumo_get_pi(rdev);
1361 sumo_initialize_m3_arb(rdev);
1362 pi->fw_version = sumo_get_running_fw_version(rdev);
1363 DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1364 sumo_program_acpi_power_level(rdev);
1365 sumo_enable_acpi_pm(rdev);
1366 sumo_take_smu_control(rdev, true);
1369 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1375 struct _ATOM_POWERPLAY_INFO info;
1376 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1377 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1378 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1379 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1380 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1383 union pplib_clock_info {
1384 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1385 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1386 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1387 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1390 union pplib_power_state {
1391 struct _ATOM_PPLIB_STATE v1;
1392 struct _ATOM_PPLIB_STATE_V2 v2;
1395 static void sumo_patch_boot_state(struct radeon_device *rdev,
1398 struct sumo_power_info *pi = sumo_get_pi(rdev);
1402 ps->levels[0] = pi->boot_pl;
1405 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1406 struct radeon_ps *rps,
1407 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1410 struct sumo_ps *ps = sumo_get_ps(rps);
1412 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1413 rps->class = le16_to_cpu(non_clock_info->usClassification);
1414 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1416 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1417 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1418 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1424 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1425 rdev->pm.dpm.boot_ps = rps;
1426 sumo_patch_boot_state(rdev, ps);
1428 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1429 rdev->pm.dpm.uvd_ps = rps;
1432 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1433 struct radeon_ps *rps, int index,
1434 union pplib_clock_info *clock_info)
1436 struct sumo_power_info *pi = sumo_get_pi(rdev);
1437 struct sumo_ps *ps = sumo_get_ps(rps);
1438 struct sumo_pl *pl = &ps->levels[index];
1441 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1442 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1444 pl->vddc_index = clock_info->sumo.vddcIndex;
1445 pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1447 ps->num_levels = index + 1;
1449 if (pi->enable_sclk_ds) {
1450 pl->ds_divider_index = 5;
1451 pl->ss_divider_index = 4;
1455 static int sumo_parse_power_table(struct radeon_device *rdev)
1457 struct radeon_mode_info *mode_info = &rdev->mode_info;
1458 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1459 union pplib_power_state *power_state;
1460 int i, j, k, non_clock_array_index, clock_array_index;
1461 union pplib_clock_info *clock_info;
1462 struct _StateArray *state_array;
1463 struct _ClockInfoArray *clock_info_array;
1464 struct _NonClockInfoArray *non_clock_info_array;
1465 union power_info *power_info;
1466 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1469 u8 *power_state_offset;
1472 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1473 &frev, &crev, &data_offset))
1475 power_info = (union power_info *)((uint8_t*)mode_info->atom_context->bios + data_offset);
1477 state_array = (struct _StateArray *)
1478 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1479 le16_to_cpu(power_info->pplib.usStateArrayOffset));
1480 clock_info_array = (struct _ClockInfoArray *)
1481 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1482 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1483 non_clock_info_array = (struct _NonClockInfoArray *)
1484 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1485 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1487 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1488 state_array->ucNumEntries, GFP_KERNEL);
1489 if (!rdev->pm.dpm.ps)
1491 power_state_offset = (u8 *)state_array->states;
1492 for (i = 0; i < state_array->ucNumEntries; i++) {
1494 power_state = (union pplib_power_state *)power_state_offset;
1495 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1496 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1497 &non_clock_info_array->nonClockInfo[non_clock_array_index];
1498 if (!rdev->pm.power_state[i].clock_info)
1500 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1502 kfree(rdev->pm.dpm.ps);
1505 rdev->pm.dpm.ps[i].ps_priv = ps;
1507 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1508 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1509 clock_array_index = idx[j];
1510 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1513 clock_info = (union pplib_clock_info *)
1514 ((u8 *)&clock_info_array->clockInfo[0] +
1515 (clock_array_index * clock_info_array->ucEntrySize));
1516 sumo_parse_pplib_clock_info(rdev,
1517 &rdev->pm.dpm.ps[i], k,
1521 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1523 non_clock_info_array->ucEntrySize);
1524 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1526 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1530 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1531 struct sumo_vid_mapping_table *vid_mapping_table,
1536 for (i = 0; i < vid_mapping_table->num_entries; i++) {
1537 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1538 return vid_mapping_table->entries[i].vid_7bit;
1541 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1545 u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,
1546 struct sumo_vid_mapping_table *vid_mapping_table,
1551 for (i = 0; i < vid_mapping_table->num_entries; i++) {
1552 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
1553 return vid_mapping_table->entries[i].vid_2bit;
1556 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
1560 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1563 struct sumo_power_info *pi = sumo_get_pi(rdev);
1564 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1566 if (vid_7bit > 0x7C)
1569 return (15500 - vid_7bit * 125 + 5) / 10;
1572 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1573 struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1574 ATOM_CLK_VOLT_CAPABILITY *table)
1578 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1579 if (table[i].ulMaximumSupportedCLK == 0)
1582 disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1583 table[i].ulMaximumSupportedCLK;
1586 disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1588 if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1589 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1590 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1594 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1595 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1596 ATOM_AVAILABLE_SCLK_LIST *table)
1602 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1603 if (table[i].ulSupportedSCLK > prev_sclk) {
1604 sclk_voltage_mapping_table->entries[n].sclk_frequency =
1605 table[i].ulSupportedSCLK;
1606 sclk_voltage_mapping_table->entries[n].vid_2bit =
1607 table[i].usVoltageIndex;
1608 prev_sclk = table[i].ulSupportedSCLK;
1613 sclk_voltage_mapping_table->num_max_dpm_entries = n;
1616 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1617 struct sumo_vid_mapping_table *vid_mapping_table,
1618 ATOM_AVAILABLE_SCLK_LIST *table)
1622 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1623 if (table[i].ulSupportedSCLK != 0) {
1624 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1625 table[i].usVoltageID;
1626 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1627 table[i].usVoltageIndex;
1631 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1632 if (vid_mapping_table->entries[i].vid_7bit == 0) {
1633 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1634 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1635 vid_mapping_table->entries[i] =
1636 vid_mapping_table->entries[j];
1637 vid_mapping_table->entries[j].vid_7bit = 0;
1642 if (j == SUMO_MAX_NUMBER_VOLTAGES)
1647 vid_mapping_table->num_entries = i;
1651 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1652 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1653 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1654 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1657 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1659 struct sumo_power_info *pi = sumo_get_pi(rdev);
1660 struct radeon_mode_info *mode_info = &rdev->mode_info;
1661 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1662 union igp_info *igp_info;
1667 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1668 &frev, &crev, &data_offset)) {
1669 igp_info = (union igp_info *)((uint8_t*)mode_info->atom_context->bios +
1673 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1676 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1677 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1678 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1679 pi->sys_info.bootup_nb_voltage_index =
1680 le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1681 if (igp_info->info_6.ucHtcTmpLmt == 0)
1682 pi->sys_info.htc_tmp_lmt = 203;
1684 pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1685 if (igp_info->info_6.ucHtcHystLmt == 0)
1686 pi->sys_info.htc_hyst_lmt = 5;
1688 pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1689 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1690 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1692 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1693 pi->sys_info.csr_m3_arb_cntl_default[i] =
1694 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1695 pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1696 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1697 pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1698 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1700 pi->sys_info.sclk_dpm_boost_margin =
1701 le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1702 pi->sys_info.sclk_dpm_throttle_margin =
1703 le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1704 pi->sys_info.sclk_dpm_tdp_limit_pg =
1705 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1706 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1707 pi->sys_info.sclk_dpm_tdp_limit_boost =
1708 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1709 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1710 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1711 if (igp_info->info_6.EnableBoost)
1712 pi->sys_info.enable_boost = true;
1714 pi->sys_info.enable_boost = false;
1715 sumo_construct_display_voltage_mapping_table(rdev,
1716 &pi->sys_info.disp_clk_voltage_mapping_table,
1717 igp_info->info_6.sDISPCLK_Voltage);
1718 sumo_construct_sclk_voltage_mapping_table(rdev,
1719 &pi->sys_info.sclk_voltage_mapping_table,
1720 igp_info->info_6.sAvail_SCLK);
1721 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1722 igp_info->info_6.sAvail_SCLK);
1728 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1730 struct sumo_power_info *pi = sumo_get_pi(rdev);
1732 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1733 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1734 pi->boot_pl.ds_divider_index = 0;
1735 pi->boot_pl.ss_divider_index = 0;
1736 pi->boot_pl.allow_gnb_slow = 1;
1737 pi->acpi_pl = pi->boot_pl;
1738 pi->current_ps.num_levels = 1;
1739 pi->current_ps.levels[0] = pi->boot_pl;
1742 int sumo_dpm_init(struct radeon_device *rdev)
1744 struct sumo_power_info *pi;
1745 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1748 pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1751 rdev->pm.dpm.priv = pi;
1753 pi->driver_nbps_policy_disable = false;
1754 if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1755 pi->disable_gfx_power_gating_in_uvd = true;
1757 pi->disable_gfx_power_gating_in_uvd = false;
1758 pi->enable_alt_vddnb = true;
1759 pi->enable_sclk_ds = true;
1760 pi->enable_dynamic_m3_arbiter = false;
1761 pi->enable_dynamic_patch_ps = true;
1762 /* Some PALM chips don't seem to properly ungate gfx when UVD is in use;
1763 * for now just disable gfx PG.
1765 if (rdev->family == CHIP_PALM)
1766 pi->enable_gfx_power_gating = false;
1768 pi->enable_gfx_power_gating = true;
1769 pi->enable_gfx_clock_gating = true;
1770 pi->enable_mg_clock_gating = true;
1771 pi->enable_auto_thermal_throttling = true;
1773 ret = sumo_parse_sys_info_table(rdev);
1777 sumo_construct_boot_and_acpi_state(rdev);
1779 ret = r600_get_platform_caps(rdev);
1783 ret = sumo_parse_power_table(rdev);
1787 pi->pasi = CYPRESS_HASI_DFLT;
1788 pi->asi = RV770_ASI_DFLT;
1789 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1790 pi->enable_boost = pi->sys_info.enable_boost;
1791 pi->enable_dpm = true;
1796 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1797 struct radeon_ps *rps)
1800 struct sumo_ps *ps = sumo_get_ps(rps);
1802 r600_dpm_print_class_info(rps->class, rps->class2);
1803 r600_dpm_print_cap_info(rps->caps);
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1805 for (i = 0; i < ps->num_levels; i++) {
1806 struct sumo_pl *pl = &ps->levels[i];
1807 printk("\t\tpower level %d sclk: %u vddc: %u\n",
1809 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1811 r600_dpm_print_ps_status(rdev, rps);
1814 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1817 struct sumo_power_info *pi = sumo_get_pi(rdev);
1818 struct radeon_ps *rps = &pi->current_rps;
1819 struct sumo_ps *ps = sumo_get_ps(rps);
1822 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1825 if (current_index == BOOST_DPM_LEVEL) {
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1828 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
1829 current_index, pl->sclk,
1830 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1831 } else if (current_index >= ps->num_levels) {
1832 seq_printf(m, "invalid dpm profile %d\n", current_index);
1834 pl = &ps->levels[current_index];
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1836 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
1837 current_index, pl->sclk,
1838 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1842 void sumo_dpm_fini(struct radeon_device *rdev)
1846 sumo_cleanup_asic(rdev); /* ??? */
1848 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1849 kfree(rdev->pm.dpm.ps[i].ps_priv);
1851 kfree(rdev->pm.dpm.ps);
1852 kfree(rdev->pm.dpm.priv);
1855 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1857 struct sumo_power_info *pi = sumo_get_pi(rdev);
1858 struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1861 return requested_state->levels[0].sclk;
1863 return requested_state->levels[requested_state->num_levels - 1].sclk;
1866 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1868 struct sumo_power_info *pi = sumo_get_pi(rdev);
1870 return pi->sys_info.bootup_uma_clk;
1873 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
1874 enum radeon_dpm_forced_level level)
1876 struct sumo_power_info *pi = sumo_get_pi(rdev);
1877 struct radeon_ps *rps = &pi->current_rps;
1878 struct sumo_ps *ps = sumo_get_ps(rps);
1881 if (ps->num_levels <= 1)
1884 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1885 if (pi->enable_boost)
1886 sumo_enable_boost(rdev, rps, false);
1887 sumo_power_level_enable(rdev, ps->num_levels - 1, true);
1888 sumo_set_forced_level(rdev, ps->num_levels - 1);
1889 sumo_set_forced_mode_enabled(rdev);
1890 for (i = 0; i < ps->num_levels - 1; i++) {
1891 sumo_power_level_enable(rdev, i, false);
1893 sumo_set_forced_mode(rdev, false);
1894 sumo_set_forced_mode_enabled(rdev);
1895 sumo_set_forced_mode(rdev, false);
1896 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1897 if (pi->enable_boost)
1898 sumo_enable_boost(rdev, rps, false);
1899 sumo_power_level_enable(rdev, 0, true);
1900 sumo_set_forced_level(rdev, 0);
1901 sumo_set_forced_mode_enabled(rdev);
1902 for (i = 1; i < ps->num_levels; i++) {
1903 sumo_power_level_enable(rdev, i, false);
1905 sumo_set_forced_mode(rdev, false);
1906 sumo_set_forced_mode_enabled(rdev);
1907 sumo_set_forced_mode(rdev, false);
1909 for (i = 0; i < ps->num_levels; i++) {
1910 sumo_power_level_enable(rdev, i, true);
1912 if (pi->enable_boost)
1913 sumo_enable_boost(rdev, rps, true);
1916 rdev->pm.dpm.forced_level = level;