2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
28 * $DragonFly: src/sys/dev/agp/agp_i810.c,v 1.19 2008/10/03 08:56:58 hasso Exp $
32 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
33 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
46 #include <bus/pci/pcivar.h>
47 #include <bus/pci/pcireg.h>
52 #include <vm/vm_object.h>
53 #include <vm/vm_page.h>
54 #include <vm/vm_pageout.h>
57 #include <machine/md_var.h>
59 #define bus_read_1(r, o) \
60 bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
61 #define bus_read_4(r, o) \
62 bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
63 #define bus_write_4(r, o, v) \
64 bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
66 MALLOC_DECLARE(M_AGP);
69 CHIP_I810, /* i810/i815 */
70 CHIP_I830, /* 830M/845G */
71 CHIP_I855, /* 852GM/855GM/865G */
72 CHIP_I915, /* 915G/915GM */
74 CHIP_G33, /* G33/Q33/Q35 */
75 CHIP_IGD, /* G33 like IGD */
76 CHIP_G4X, /* G45/Q45 */
79 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
80 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
81 * start of the stolen memory, and should only be accessed by the OS through
82 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
83 * is registers, second 512KB is GATT.
85 static struct resource_spec agp_i810_res_spec[] = {
86 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
90 static struct resource_spec agp_i915_res_spec[] = {
91 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
92 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
96 static struct resource_spec agp_i965_res_spec[] = {
97 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
101 struct agp_i810_softc {
102 struct agp_softc agp;
103 u_int32_t initial_aperture; /* aperture size at startup */
104 struct agp_gatt *gatt;
105 int chiptype; /* i810-like or i830 */
106 u_int32_t dcache_size; /* i810 only */
107 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
108 device_t bdev; /* bridge device */
110 void *argb_cursor; /* contigmalloc area for ARGB cursor */
112 struct resource_spec * sc_res_spec;
113 struct resource *sc_res[2];
116 /* For adding new devices, devid is the id of the graphics controller
117 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
118 * second head should never be added. The bridge_offset is the offset to
119 * subtract from devid to get the id of the hostb that the device is on.
121 static const struct agp_i810_match {
126 } agp_i810_matches[] = {
127 {0x71218086, CHIP_I810, 0x00010000,
128 "Intel 82810 (i810 GMCH) SVGA controller"},
129 {0x71238086, CHIP_I810, 0x00010000,
130 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
131 {0x71258086, CHIP_I810, 0x00010000,
132 "Intel 82810E (i810E GMCH) SVGA controller"},
133 {0x11328086, CHIP_I810, 0x00020000,
134 "Intel 82815 (i815 GMCH) SVGA controller"},
135 {0x35778086, CHIP_I830, 0x00020000,
136 "Intel 82830M (830M GMCH) SVGA controller"},
137 {0x25628086, CHIP_I830, 0x00020000,
138 "Intel 82845M (845M GMCH) SVGA controller"},
139 {0x35828086, CHIP_I855, 0x00020000,
140 "Intel 82852/855GM SVGA controller"},
141 {0x25728086, CHIP_I855, 0x00020000,
142 "Intel 82865G (865G GMCH) SVGA controller"},
143 {0x25828086, CHIP_I915, 0x00020000,
144 "Intel 82915G (915G GMCH) SVGA controller"},
145 {0x258A8086, CHIP_I915, 0x00020000,
146 "Intel E7221 SVGA controller"},
147 {0x25928086, CHIP_I915, 0x00020000,
148 "Intel 82915GM (915GM GMCH) SVGA controller"},
149 {0x27728086, CHIP_I915, 0x00020000,
150 "Intel 82945G (945G GMCH) SVGA controller"},
151 {0x27A28086, CHIP_I915, 0x00020000,
152 "Intel 82945GM (945GM GMCH) SVGA controller"},
153 {0x27AE8086, CHIP_I915, 0x00020000,
154 "Intel 945GME SVGA controller"},
155 {0x29728086, CHIP_I965, 0x00020000,
156 "Intel 946GZ SVGA controller"},
157 {0x29828086, CHIP_I965, 0x00020000,
158 "Intel G965 SVGA controller"},
159 {0x29928086, CHIP_I965, 0x00020000,
160 "Intel Q965 SVGA controller"},
161 {0x29A28086, CHIP_I965, 0x00020000,
162 "Intel G965 SVGA controller"},
163 {0x29B28086, CHIP_G33, 0x00020000,
164 "Intel Q35 SVGA controller"},
165 {0x29C28086, CHIP_G33, 0x00020000,
166 "Intel G33 SVGA controller"},
167 {0x29D28086, CHIP_G33, 0x00020000,
168 "Intel Q33 SVGA controller"},
169 {0x2A028086, CHIP_I965, 0x00020000,
170 "Intel GM965 SVGA controller"},
171 {0x2A128086, CHIP_I965, 0x00020000,
172 "Intel GME965 SVGA controller"},
173 {0x2A428086, CHIP_G4X, 0x00020000,
174 "Intel GM45 SVGA controller"},
175 {0x2E028086, CHIP_G4X, 0x00020000,
176 "Intel 4 Series SVGA controller"},
177 {0x2E128086, CHIP_G4X, 0x00020000,
178 "Intel Q45 SVGA controller"},
179 {0x2E228086, CHIP_G4X, 0x00020000,
180 "Intel G45 SVGA controller"},
181 {0x2E328086, CHIP_G4X, 0x00020000,
182 "Intel G41 SVGA controller"},
183 {0xA0018086, CHIP_IGD, 0x00010000,
184 "Intel IGD SVGA controller"},
185 {0xA0118086, CHIP_IGD, 0x00010000,
186 "Intel IGD SVGA controller"},
190 static const struct agp_i810_match*
191 agp_i810_match(device_t dev)
195 if (pci_get_class(dev) != PCIC_DISPLAY
196 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
199 devid = pci_get_devid(dev);
200 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
201 if (agp_i810_matches[i].devid == devid)
204 if (agp_i810_matches[i].devid == 0)
207 return &agp_i810_matches[i];
211 * Find bridge device.
214 agp_i810_find_bridge(device_t dev)
216 device_t *children, child;
219 const struct agp_i810_match *match;
221 match = agp_i810_match(dev);
222 devid = match->devid - match->bridge_offset;
224 if (device_get_children(device_get_parent(device_get_parent(dev)),
225 &children, &nchildren))
228 for (i = 0; i < nchildren; i++) {
231 if (pci_get_devid(child) == devid) {
232 kfree(children, M_TEMP);
236 kfree(children, M_TEMP);
241 agp_i810_identify(driver_t *driver, device_t parent)
244 if (device_find_child(parent, "agp", -1) == NULL &&
245 agp_i810_match(parent))
246 device_add_child(parent, "agp", -1);
250 agp_i810_probe(device_t dev)
253 const struct agp_i810_match *match;
257 if (resource_disabled("agp", device_get_unit(dev)))
259 match = agp_i810_match(dev);
263 bdev = agp_i810_find_bridge(dev);
266 kprintf("I810: can't find bridge device\n");
271 * checking whether internal graphics device has been activated.
273 switch (match->chiptype) {
275 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
276 if ((smram & AGP_I810_SMRAM_GMS) ==
277 AGP_I810_SMRAM_GMS_DISABLED) {
279 kprintf("I810: disabled, not probing\n");
285 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
286 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
287 AGP_I830_GCC1_DEV2_DISABLED) {
289 kprintf("I830: disabled, not probing\n");
298 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
299 if ((deven & AGP_I915_DEVEN_D2F0) ==
300 AGP_I915_DEVEN_D2F0_DISABLED) {
302 kprintf("I915: disabled, not probing\n");
309 if (match->devid == 0x35828086) {
310 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
313 "Intel 82855GME (855GME GMCH) SVGA controller");
317 "Intel 82855GM (855GM GMCH) SVGA controller");
321 "Intel 82852GME (852GME GMCH) SVGA controller");
325 "Intel 82852GM (852GM GMCH) SVGA controller");
329 "Intel 8285xM (85xGM GMCH) SVGA controller");
333 device_set_desc(dev, match->name);
336 return BUS_PROBE_DEFAULT;
340 agp_i810_dump_regs(device_t dev)
342 struct agp_i810_softc *sc = device_get_softc(dev);
344 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
345 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
347 switch (sc->chiptype) {
349 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
350 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
353 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
354 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
357 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
358 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
365 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
366 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
367 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
368 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
371 device_printf(dev, "Aperture resource size: %d bytes\n",
372 AGP_GET_APERTURE(dev));
376 agp_i810_attach(device_t dev)
378 struct agp_i810_softc *sc = device_get_softc(dev);
379 struct agp_gatt *gatt;
380 const struct agp_i810_match *match;
383 sc->bdev = agp_i810_find_bridge(dev);
387 match = agp_i810_match(dev);
388 sc->chiptype = match->chiptype;
390 switch (sc->chiptype) {
394 sc->sc_res_spec = agp_i810_res_spec;
395 agp_set_aperture_resource(dev, AGP_APBASE);
400 sc->sc_res_spec = agp_i915_res_spec;
401 agp_set_aperture_resource(dev, AGP_I915_GMADR);
405 sc->sc_res_spec = agp_i965_res_spec;
406 agp_set_aperture_resource(dev, AGP_I915_GMADR);
410 error = agp_generic_attach(dev);
414 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
415 sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X &&
416 ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
418 device_printf(dev, "agp_i810.c does not support physical "
419 "memory above 4GB.\n");
423 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
424 agp_generic_detach(dev);
428 sc->initial_aperture = AGP_GET_APERTURE(dev);
429 if (sc->initial_aperture == 0) {
430 device_printf(dev, "bad initial aperture size, disabling\n");
434 gatt = kmalloc( sizeof(struct agp_gatt), M_AGP, M_INTWAIT);
437 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
439 if ( sc->chiptype == CHIP_I810 ) {
440 /* Some i810s have on-chip memory called dcache */
441 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
442 AGP_I810_DRT_POPULATED)
443 sc->dcache_size = 4 * 1024 * 1024;
447 /* According to the specs the gatt on the i810 must be 64k */
448 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
449 0, ~0, PAGE_SIZE, 0);
450 if (!gatt->ag_virtual) {
452 device_printf(dev, "contiguous allocation failed\n");
453 bus_release_resources(dev, sc->sc_res_spec,
456 agp_generic_detach(dev);
459 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
461 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
463 /* Install the GATT. */
464 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
465 gatt->ag_physical | 1);
466 } else if ( sc->chiptype == CHIP_I830 ) {
467 /* The i830 automatically initializes the 128k gatt on boot. */
468 unsigned int gcc1, pgtblctl;
470 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
471 switch (gcc1 & AGP_I830_GCC1_GMS) {
472 case AGP_I830_GCC1_GMS_STOLEN_512:
473 sc->stolen = (512 - 132) * 1024 / 4096;
475 case AGP_I830_GCC1_GMS_STOLEN_1024:
476 sc->stolen = (1024 - 132) * 1024 / 4096;
478 case AGP_I830_GCC1_GMS_STOLEN_8192:
479 sc->stolen = (8192 - 132) * 1024 / 4096;
483 device_printf(dev, "unknown memory configuration, disabling\n");
484 bus_release_resources(dev, sc->sc_res_spec,
487 agp_generic_detach(dev);
490 if (sc->stolen > 0) {
491 device_printf(dev, "detected %dk stolen memory\n",
494 device_printf(dev, "aperture size is %dM\n",
495 sc->initial_aperture / 1024 / 1024);
497 /* GATT address is already in there, make sure it's enabled */
498 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
500 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
502 gatt->ag_physical = pgtblctl & ~1;
503 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
504 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
505 sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
506 unsigned int gcc1, pgtblctl, stolen, gtt_size;
508 /* Stolen memory is set up at the beginning of the aperture by
509 * the BIOS, consisting of the GATT followed by 4kb for the
512 switch (sc->chiptype) {
520 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
521 AGP_I810_PGTBL_SIZE_MASK) {
522 case AGP_I810_PGTBL_SIZE_128KB:
525 case AGP_I810_PGTBL_SIZE_256KB:
528 case AGP_I810_PGTBL_SIZE_512KB:
531 case AGP_I965_PGTBL_SIZE_1MB:
534 case AGP_I965_PGTBL_SIZE_2MB:
537 case AGP_I965_PGTBL_SIZE_1_5MB:
538 gtt_size = 1024 + 512;
541 device_printf(dev, "Bad PGTBL size\n");
542 bus_release_resources(dev, sc->sc_res_spec,
545 agp_generic_detach(dev);
550 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
551 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
552 case AGP_G33_MGGC_GGMS_SIZE_1M:
555 case AGP_G33_MGGC_GGMS_SIZE_2M:
559 device_printf(dev, "Bad PGTBL size\n");
560 bus_release_resources(dev, sc->sc_res_spec,
563 agp_generic_detach(dev);
572 device_printf(dev, "Bad chiptype\n");
573 bus_release_resources(dev, sc->sc_res_spec,
576 agp_generic_detach(dev);
580 /* GCC1 is called MGGC on i915+ */
581 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
582 switch (gcc1 & AGP_I855_GCC1_GMS) {
583 case AGP_I855_GCC1_GMS_STOLEN_1M:
586 case AGP_I855_GCC1_GMS_STOLEN_4M:
589 case AGP_I855_GCC1_GMS_STOLEN_8M:
592 case AGP_I855_GCC1_GMS_STOLEN_16M:
595 case AGP_I855_GCC1_GMS_STOLEN_32M:
598 case AGP_I915_GCC1_GMS_STOLEN_48M:
599 if (sc->chiptype == CHIP_I915 ||
600 sc->chiptype == CHIP_I965 ||
601 sc->chiptype == CHIP_G33 ||
602 sc->chiptype == CHIP_IGD ||
603 sc->chiptype == CHIP_G4X) {
609 case AGP_I915_GCC1_GMS_STOLEN_64M:
610 if (sc->chiptype == CHIP_I915 ||
611 sc->chiptype == CHIP_I965 ||
612 sc->chiptype == CHIP_G33 ||
613 sc->chiptype == CHIP_IGD ||
614 sc->chiptype == CHIP_G4X) {
620 case AGP_G33_GCC1_GMS_STOLEN_128M:
621 if (sc->chiptype == CHIP_I965 ||
622 sc->chiptype == CHIP_G33 ||
623 sc->chiptype == CHIP_IGD ||
624 sc->chiptype == CHIP_G4X) {
630 case AGP_G33_GCC1_GMS_STOLEN_256M:
631 if (sc->chiptype == CHIP_I965 ||
632 sc->chiptype == CHIP_G33 ||
633 sc->chiptype == CHIP_IGD ||
634 sc->chiptype == CHIP_G4X) {
640 case AGP_G4X_GCC1_GMS_STOLEN_96M:
641 if (sc->chiptype == CHIP_I965 ||
642 sc->chiptype == CHIP_G4X) {
648 case AGP_G4X_GCC1_GMS_STOLEN_160M:
649 if (sc->chiptype == CHIP_I965 ||
650 sc->chiptype == CHIP_G4X) {
656 case AGP_G4X_GCC1_GMS_STOLEN_224M:
657 if (sc->chiptype == CHIP_I965 ||
658 sc->chiptype == CHIP_G4X) {
664 case AGP_G4X_GCC1_GMS_STOLEN_352M:
665 if (sc->chiptype == CHIP_I965 ||
666 sc->chiptype == CHIP_G4X) {
673 device_printf(dev, "unknown memory configuration, "
675 bus_release_resources(dev, sc->sc_res_spec,
678 agp_generic_detach(dev);
684 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
686 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
687 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
689 /* GATT address is already in there, make sure it's enabled */
690 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
692 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
694 gatt->ag_physical = pgtblctl & ~1;
698 agp_i810_dump_regs(dev);
704 agp_i810_detach(device_t dev)
706 struct agp_i810_softc *sc = device_get_softc(dev);
710 /* Clear the GATT base. */
711 if ( sc->chiptype == CHIP_I810 ) {
712 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
714 unsigned int pgtblctl;
715 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
717 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
720 /* Put the aperture back the way it started. */
721 AGP_SET_APERTURE(dev, sc->initial_aperture);
723 if ( sc->chiptype == CHIP_I810 ) {
724 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
726 kfree(sc->gatt, M_AGP);
728 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
735 agp_i810_resume(device_t dev)
737 struct agp_i810_softc *sc;
738 sc = device_get_softc(dev);
740 AGP_SET_APERTURE(dev, sc->initial_aperture);
742 /* Install the GATT. */
743 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
744 sc->gatt->ag_physical | 1);
746 return (bus_generic_resume(dev));
750 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
751 * while returning failure on later chipsets when an actual change is
754 * This whole function is likely bogus, as the kernel would probably need to
755 * reconfigure the placement of the AGP aperture if a larger size is requested,
756 * which doesn't happen currently.
759 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
761 struct agp_i810_softc *sc = device_get_softc(dev);
762 u_int16_t miscc, gcc1;
764 switch (sc->chiptype) {
767 * Double check for sanity.
769 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
770 device_printf(dev, "bad aperture size %d\n", aperture);
774 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
775 miscc &= ~AGP_I810_MISCC_WINSIZE;
776 if (aperture == 32 * 1024 * 1024)
777 miscc |= AGP_I810_MISCC_WINSIZE_32;
779 miscc |= AGP_I810_MISCC_WINSIZE_64;
781 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
784 if (aperture != 64 * 1024 * 1024 &&
785 aperture != 128 * 1024 * 1024) {
786 device_printf(dev, "bad aperture size %d\n", aperture);
789 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
790 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
791 if (aperture == 64 * 1024 * 1024)
792 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
794 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
796 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
804 return agp_generic_set_aperture(dev, aperture);
811 * Writes a GTT entry mapping the page at the given offset from the beginning
812 * of the aperture to the given physical address.
815 agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
818 struct agp_i810_softc *sc = device_get_softc(dev);
821 pte = (u_int32_t)physical | 1;
822 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
823 sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
824 pte |= (physical & 0x0000000f00000000ull) >> 28;
826 /* If we do actually have memory above 4GB on an older system,
827 * crash cleanly rather than scribble on system memory,
828 * so we know we need to fix it.
830 KASSERT((pte & 0x0000000f00000000ull) == 0,
831 (">4GB physical address in agp"));
834 switch (sc->chiptype) {
838 bus_write_4(sc->sc_res[0],
839 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
844 bus_write_4(sc->sc_res[1],
845 (offset >> AGP_PAGE_SHIFT) * 4, pte);
848 bus_write_4(sc->sc_res[0],
849 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
852 bus_write_4(sc->sc_res[0],
853 (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
859 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
861 struct agp_i810_softc *sc = device_get_softc(dev);
863 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
864 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
868 if ( sc->chiptype != CHIP_I810 ) {
869 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
870 device_printf(dev, "trying to bind into stolen memory");
875 agp_i810_write_gtt_entry(dev, offset, physical, 1);
881 agp_i810_unbind_page(device_t dev, int offset)
883 struct agp_i810_softc *sc = device_get_softc(dev);
885 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
888 if ( sc->chiptype != CHIP_I810 ) {
889 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
890 device_printf(dev, "trying to unbind from stolen memory");
895 agp_i810_write_gtt_entry(dev, offset, 0, 0);
901 * Writing via memory mapped registers already flushes all TLBs.
904 agp_i810_flush_tlb(device_t dev)
909 agp_i810_enable(device_t dev, u_int32_t mode)
915 static struct agp_memory *
916 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
918 struct agp_i810_softc *sc = device_get_softc(dev);
919 struct agp_memory *mem;
921 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
924 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
929 * Mapping local DRAM into GATT.
931 if ( sc->chiptype != CHIP_I810 )
933 if (size != sc->dcache_size)
935 } else if (type == 2) {
937 * Type 2 is the contiguous physical memory type, that hands
938 * back a physical address. This is used for cursors on i810.
939 * Hand back as many single pages with physical as the user
940 * wants, but only allow one larger allocation (ARGB cursor)
943 if (size != AGP_PAGE_SIZE) {
944 if (sc->argb_cursor != NULL)
947 /* Allocate memory for ARGB cursor, if we can. */
948 sc->argb_cursor = contigmalloc(size, M_AGP,
949 0, 0, ~0, PAGE_SIZE, 0);
950 if (sc->argb_cursor == NULL)
955 mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
956 mem->am_id = sc->agp.as_nextid++;
959 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
960 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
961 atop(round_page(size)));
966 if (size == AGP_PAGE_SIZE) {
968 * Allocate and wire down the page now so that we can
969 * get its physical address.
973 m = vm_page_grab(mem->am_obj, 0,
974 VM_ALLOC_NORMAL|VM_ALLOC_ZERO|VM_ALLOC_RETRY);
975 if ((m->flags & PG_ZERO) == 0)
976 vm_page_zero_fill(m);
978 mem->am_physical = VM_PAGE_TO_PHYS(m);
981 /* Our allocation is already nicely wired down for us.
982 * Just grab the physical address.
984 mem->am_physical = vtophys(sc->argb_cursor);
987 mem->am_physical = 0;
991 mem->am_is_bound = 0;
992 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
993 sc->agp.as_allocated += size;
999 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
1001 struct agp_i810_softc *sc = device_get_softc(dev);
1003 if (mem->am_is_bound)
1006 if (mem->am_type == 2) {
1007 if (mem->am_size == AGP_PAGE_SIZE) {
1009 * Unwire the page which we wired in alloc_memory.
1011 vm_page_t m = vm_page_lookup(mem->am_obj, 0);
1012 vm_page_unwire(m, 0);
1014 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1015 sc->argb_cursor = NULL;
1019 sc->agp.as_allocated -= mem->am_size;
1020 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1022 vm_object_deallocate(mem->am_obj);
1028 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1031 struct agp_i810_softc *sc = device_get_softc(dev);
1034 /* Do some sanity checks first. */
1035 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1036 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1037 device_printf(dev, "binding memory at bad offset %#x\n",
1042 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1043 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1044 if (mem->am_is_bound) {
1045 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1048 /* The memory's already wired down, just stick it in the GTT. */
1049 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1050 agp_i810_write_gtt_entry(dev, offset + i,
1051 mem->am_physical + i, 1);
1054 mem->am_offset = offset;
1055 mem->am_is_bound = 1;
1056 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1060 if (mem->am_type != 1)
1061 return agp_generic_bind_memory(dev, mem, offset);
1063 if ( sc->chiptype != CHIP_I810 )
1066 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1067 bus_write_4(sc->sc_res[0],
1068 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1075 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1077 struct agp_i810_softc *sc = device_get_softc(dev);
1080 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1081 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1082 if (!mem->am_is_bound) {
1083 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1087 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1088 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1092 mem->am_is_bound = 0;
1093 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1097 if (mem->am_type != 1)
1098 return agp_generic_unbind_memory(dev, mem);
1100 if ( sc->chiptype != CHIP_I810 )
1103 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1104 bus_write_4(sc->sc_res[0],
1105 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1111 static device_method_t agp_i810_methods[] = {
1112 /* Device interface */
1113 DEVMETHOD(device_identify, agp_i810_identify),
1114 DEVMETHOD(device_probe, agp_i810_probe),
1115 DEVMETHOD(device_attach, agp_i810_attach),
1116 DEVMETHOD(device_detach, agp_i810_detach),
1117 DEVMETHOD(device_suspend, bus_generic_suspend),
1118 DEVMETHOD(device_resume, agp_i810_resume),
1121 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
1122 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
1123 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1124 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1125 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1126 DEVMETHOD(agp_enable, agp_i810_enable),
1127 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1128 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1129 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1130 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1135 static driver_t agp_i810_driver = {
1138 sizeof(struct agp_i810_softc),
1141 static devclass_t agp_devclass;
1143 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
1144 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1145 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);