2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
51 #include "opt_msgbuf.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysproto.h>
57 #include <sys/signalvar.h>
58 #include <sys/kernel.h>
59 #include <sys/linker.h>
60 #include <sys/malloc.h>
64 #include <sys/reboot.h>
66 #include <sys/msgbuf.h>
67 #include <sys/sysent.h>
68 #include <sys/sysctl.h>
69 #include <sys/vmmeter.h>
71 #include <sys/usched.h>
74 #include <sys/ctype.h>
75 #include <sys/serialize.h>
76 #include <sys/systimer.h>
79 #include <vm/vm_param.h>
81 #include <vm/vm_kern.h>
82 #include <vm/vm_object.h>
83 #include <vm/vm_page.h>
84 #include <vm/vm_map.h>
85 #include <vm/vm_pager.h>
86 #include <vm/vm_extern.h>
88 #include <sys/thread2.h>
89 #include <sys/mplock2.h>
90 #include <sys/mutex2.h>
98 #include <machine/cpu.h>
99 #include <machine/clock.h>
100 #include <machine/specialreg.h>
102 #include <machine/bootinfo.h>
104 #include <machine/md_var.h>
105 #include <machine/metadata.h>
106 #include <machine/pc/bios.h>
107 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
108 #include <machine/globaldata.h> /* CPU_prvspace */
109 #include <machine/smp.h>
111 #include <machine/perfmon.h>
113 #include <machine/cputypes.h>
114 #include <machine/intr_machdep.h>
117 #include <bus/isa/isa_device.h>
119 #include <machine_base/isa/isa_intr.h>
120 #include <bus/isa/rtc.h>
121 #include <sys/random.h>
122 #include <sys/ptrace.h>
123 #include <machine/sigframe.h>
125 #include <sys/machintr.h>
126 #include <machine_base/icu/icu_abi.h>
127 #include <machine_base/icu/elcr_var.h>
128 #include <machine_base/apic/lapic.h>
129 #include <machine_base/apic/ioapic.h>
130 #include <machine_base/apic/ioapic_abi.h>
131 #include <machine/mptable.h>
133 #define PHYSMAP_ENTRIES 10
135 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
137 extern void printcpuinfo(void); /* XXX header file */
138 extern void identify_cpu(void);
140 extern void finishidentcpu(void);
142 extern void panicifcpuunsupported(void);
144 static void cpu_startup(void *);
145 static void pic_finish(void *);
146 static void cpu_finish(void *);
148 #ifndef CPU_DISABLE_SSE
149 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
150 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
151 #endif /* CPU_DISABLE_SSE */
153 extern void ffs_rawread_setup(void);
154 #endif /* DIRECTIO */
155 static void init_locks(void);
157 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
158 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
159 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
162 extern vm_offset_t ksym_start, ksym_end;
165 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
167 int _udatasel, _ucodesel, _ucode32sel;
169 int64_t tsc_offsets[MAXCPU];
171 int cpu_mwait_halt; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
173 #if defined(SWTCH_OPTIM_STATS)
174 extern int swtch_optim_stats;
175 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
176 CTLFLAG_RD, &swtch_optim_stats, 0, "");
177 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
178 CTLFLAG_RD, &tlb_flush_count, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
181 CTLFLAG_RW, &cpu_mwait_halt, 0, "");
183 #define CPU_MWAIT_C3 3
184 #define CPU_MWAIT_CX_MAX 8
186 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
187 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
189 SYSCTL_NODE(_machdep, 0, mwait, CTLFLAG_RW, 0, "MWAIT features");
190 SYSCTL_NODE(_machdep_mwait, 0, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
192 struct cpu_mwait_cx {
195 struct sysctl_ctx_list sysctl_ctx;
196 struct sysctl_oid *sysctl_tree;
198 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
199 static char cpu_mwait_cx_supported[256];
201 static int cpu_mwait_hints_cnt;
202 static int *cpu_mwait_hints;
204 static int cpu_mwait_deep_hints_cnt;
205 static int *cpu_mwait_deep_hints;
207 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
208 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
210 static struct lwkt_serialize cpu_mwait_cx_slize = LWKT_SERIALIZE_INITIALIZER;
211 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *);
212 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
213 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
215 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
216 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
217 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
218 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
222 u_long ebda_addr = 0;
224 int imcr_present = 0;
226 int naps = 0; /* # of Applications processors */
229 struct mtx dt_lock; /* lock for GDT and LDT */
232 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
234 u_long pmem = ctob(physmem);
236 int error = sysctl_handle_long(oidp, &pmem, 0, req);
240 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
241 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
244 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
246 int error = sysctl_handle_int(oidp, 0,
247 ctob(physmem - vmstats.v_wire_count), req);
251 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
252 0, 0, sysctl_hw_usermem, "IU", "");
255 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
257 int error = sysctl_handle_int(oidp, 0,
258 x86_64_btop(avail_end - avail_start), req);
262 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
263 0, 0, sysctl_hw_availpages, "I", "");
269 * The number of PHYSMAP entries must be one less than the number of
270 * PHYSSEG entries because the PHYSMAP entry that spans the largest
271 * physical address that is accessible by ISA DMA is split into two
274 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
276 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
277 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
279 /* must be 2 less so 0 0 can signal end of chunks */
280 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
281 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
283 static vm_offset_t buffer_sva, buffer_eva;
284 vm_offset_t clean_sva, clean_eva;
285 static vm_offset_t pager_sva, pager_eva;
286 static struct trapframe proc0_tf;
289 cpu_startup(void *dummy)
293 vm_offset_t firstaddr;
296 * Good {morning,afternoon,evening,night}.
298 kprintf("%s", version);
301 panicifcpuunsupported();
305 kprintf("real memory = %ju (%ju MB)\n",
307 (intmax_t)Realmem / 1024 / 1024);
309 * Display any holes after the first chunk of extended memory.
314 kprintf("Physical memory chunk(s):\n");
315 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
316 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
318 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
319 (intmax_t)phys_avail[indx],
320 (intmax_t)phys_avail[indx + 1] - 1,
322 (intmax_t)(size1 / PAGE_SIZE));
327 * Allocate space for system data structures.
328 * The first available kernel virtual address is in "v".
329 * As pages of kernel virtual memory are allocated, "v" is incremented.
330 * As pages of memory are allocated and cleared,
331 * "firstaddr" is incremented.
332 * An index into the kernel page table corresponding to the
333 * virtual memory address maintained in "v" is kept in "mapaddr".
337 * Make two passes. The first pass calculates how much memory is
338 * needed and allocates it. The second pass assigns virtual
339 * addresses to the various data structures.
343 v = (caddr_t)firstaddr;
345 #define valloc(name, type, num) \
346 (name) = (type *)v; v = (caddr_t)((name)+(num))
347 #define valloclim(name, type, num, lim) \
348 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
351 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
352 * For the first 64MB of ram nominally allocate sufficient buffers to
353 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
354 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
355 * the buffer cache we limit the eventual kva reservation to
358 * factor represents the 1/4 x ram conversion.
361 long factor = 4 * BKVASIZE / 1024;
362 long kbytes = physmem * (PAGE_SIZE / 1024);
366 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
368 nbuf += (kbytes - 65536) * 2 / (factor * 5);
369 if (maxbcache && nbuf > maxbcache / BKVASIZE)
370 nbuf = maxbcache / BKVASIZE;
374 * Do not allow the buffer_map to be more then 1/2 the size of the
377 if (nbuf > (virtual_end - virtual_start +
378 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
379 nbuf = (virtual_end - virtual_start +
380 virtual2_end - virtual2_start) / (BKVASIZE * 2);
381 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
385 * Do not allow the buffer_map to use more than 50% of available
386 * physical-equivalent memory. Since the VM pages which back
387 * individual buffers are typically wired, having too many bufs
388 * can prevent the system from paging properly.
390 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
391 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
392 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
396 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
397 * the valloc space which is just the virtual_end - virtual_start
398 * section. We use valloc() to allocate the buf header array.
400 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
401 nbuf = (virtual_end - virtual_start) /
402 sizeof(struct buf) / 2;
403 kprintf("Warning: nbufs capped at %ld due to valloc "
404 "considerations", nbuf);
407 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
409 if (nswbuf < NSWBUF_MIN)
416 valloc(swbuf, struct buf, nswbuf);
417 valloc(buf, struct buf, nbuf);
420 * End of first pass, size has been calculated so allocate memory
422 if (firstaddr == 0) {
423 size = (vm_size_t)(v - firstaddr);
424 firstaddr = kmem_alloc(&kernel_map, round_page(size));
426 panic("startup: no room for tables");
431 * End of second pass, addresses have been assigned
433 * nbuf is an int, make sure we don't overflow the field.
435 * On 64-bit systems we always reserve maximal allocations for
436 * buffer cache buffers and there are no fragmentation issues,
437 * so the KVA segment does not have to be excessively oversized.
439 if ((vm_size_t)(v - firstaddr) != size)
440 panic("startup: table size inconsistency");
442 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
443 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
444 (nswbuf * MAXPHYS) + pager_map_size);
445 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
446 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
447 buffer_map.system_map = 1;
448 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
449 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
450 pager_map.system_map = 1;
452 #if defined(USERCONFIG)
454 cninit(); /* the preferred console may have changed */
457 kprintf("avail memory = %ju (%ju MB)\n",
458 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
459 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
464 cpu_finish(void *dummy __unused)
470 if ((cpu_feature2 & CPUID2_MON) &&
471 (cpu_mwait_feature & CPUID_MWAIT_EXT)) {
475 sbuf_new(&sb, cpu_mwait_cx_supported,
476 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
478 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
479 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
482 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
484 sysctl_ctx_init(&cx->sysctl_ctx);
485 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
486 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
487 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
488 if (cx->sysctl_tree == NULL)
491 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
492 SYSCTL_ADD_INT(&cx->sysctl_ctx,
493 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
494 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
497 for (sub = 0; sub < cx->subcnt; ++sub)
498 sbuf_printf(&sb, "C%d/%d ", i, sub);
506 for (i = 0; i < CPU_MWAIT_C3; ++i)
507 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
508 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
512 for (i = 0; i < CPU_MWAIT_C3; ++i) {
515 subcnt = cpu_mwait_cx_info[i].subcnt;
516 for (j = 0; j < subcnt; ++j) {
517 KASSERT(hint_idx < cpu_mwait_hints_cnt,
518 ("invalid mwait hint index %d", hint_idx));
519 cpu_mwait_hints[hint_idx] =
520 MWAIT_EAX_HINT(i, j);
524 KASSERT(hint_idx == cpu_mwait_hints_cnt,
525 ("mwait hint count %d != index %d",
526 cpu_mwait_hints_cnt, hint_idx));
529 kprintf("MWAIT hints:\n");
530 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
531 int hint = cpu_mwait_hints[i];
533 kprintf(" C%d/%d hint 0x%04x\n",
534 MWAIT_EAX_TO_CX(hint),
535 MWAIT_EAX_TO_CX_SUB(hint), hint);
542 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i)
543 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
544 cpu_mwait_deep_hints =
545 kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
549 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
552 subcnt = cpu_mwait_cx_info[i].subcnt;
553 for (j = 0; j < subcnt; ++j) {
554 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
555 ("invalid mwait deep hint index %d",
557 cpu_mwait_deep_hints[hint_idx] =
558 MWAIT_EAX_HINT(i, j);
562 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
563 ("mwait deep hint count %d != index %d",
564 cpu_mwait_deep_hints_cnt, hint_idx));
567 kprintf("MWAIT deep hints:\n");
568 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
569 int hint = cpu_mwait_deep_hints[i];
571 kprintf(" C%d/%d hint 0x%04x\n",
572 MWAIT_EAX_TO_CX(hint),
573 MWAIT_EAX_TO_CX_SUB(hint), hint);
580 pic_finish(void *dummy __unused)
582 /* Log ELCR information */
585 /* Log MPTABLE information */
586 mptable_pci_int_dump();
589 MachIntrABI.finalize();
593 * Send an interrupt to process.
595 * Stack is set up to allow sigcode stored
596 * at top to call routine, followed by kcall
597 * to sigreturn routine below. After sigreturn
598 * resets the signal mask, the stack, and the
599 * frame pointer, it returns to the user
603 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
605 struct lwp *lp = curthread->td_lwp;
606 struct proc *p = lp->lwp_proc;
607 struct trapframe *regs;
608 struct sigacts *psp = p->p_sigacts;
609 struct sigframe sf, *sfp;
613 regs = lp->lwp_md.md_regs;
614 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
616 /* Save user context */
617 bzero(&sf, sizeof(struct sigframe));
618 sf.sf_uc.uc_sigmask = *mask;
619 sf.sf_uc.uc_stack = lp->lwp_sigstk;
620 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
621 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
622 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
624 /* Make the size of the saved context visible to userland */
625 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
627 /* Allocate and validate space for the signal handler context. */
628 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
629 SIGISMEMBER(psp->ps_sigonstack, sig)) {
630 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
631 sizeof(struct sigframe));
632 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
634 /* We take red zone into account */
635 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
639 * XXX AVX needs 64-byte alignment but sigframe has other fields and
640 * the embedded ucontext is not at the front, so aligning this won't
641 * help us. Fortunately we bcopy in/out of the sigframe, so the
644 * The problem though is if userland winds up trying to use the
647 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
649 /* Translate the signal is appropriate */
650 if (p->p_sysent->sv_sigtbl) {
651 if (sig <= p->p_sysent->sv_sigsize)
652 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
656 * Build the argument list for the signal handler.
658 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
660 regs->tf_rdi = sig; /* argument 1 */
661 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
663 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
665 * Signal handler installed with SA_SIGINFO.
667 * action(signo, siginfo, ucontext)
669 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
670 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
671 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
673 /* fill siginfo structure */
674 sf.sf_si.si_signo = sig;
675 sf.sf_si.si_code = code;
676 sf.sf_si.si_addr = (void *)regs->tf_addr;
679 * Old FreeBSD-style arguments.
681 * handler (signo, code, [uc], addr)
683 regs->tf_rsi = (register_t)code; /* argument 2 */
684 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
685 sf.sf_ahu.sf_handler = catcher;
689 * If we're a vm86 process, we want to save the segment registers.
690 * We also change eflags to be our emulated eflags, not the actual
694 if (regs->tf_eflags & PSL_VM) {
695 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
696 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
698 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
699 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
700 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
701 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
703 if (vm86->vm86_has_vme == 0)
704 sf.sf_uc.uc_mcontext.mc_eflags =
705 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
706 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
709 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
710 * syscalls made by the signal handler. This just avoids
711 * wasting time for our lazy fixup of such faults. PSL_NT
712 * does nothing in vm86 mode, but vm86 programs can set it
713 * almost legitimately in probes for old cpu types.
715 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
720 * Save the FPU state and reinit the FP unit
722 npxpush(&sf.sf_uc.uc_mcontext);
725 * Copy the sigframe out to the user's stack.
727 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
729 * Something is wrong with the stack pointer.
730 * ...Kill the process.
735 regs->tf_rsp = (register_t)sfp;
736 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
739 * i386 abi specifies that the direction flag must be cleared
742 regs->tf_rflags &= ~(PSL_T|PSL_D);
745 * 64 bit mode has a code and stack selector but
746 * no data or extra selector. %fs and %gs are not
749 regs->tf_cs = _ucodesel;
750 regs->tf_ss = _udatasel;
755 * Sanitize the trapframe for a virtual kernel passing control to a custom
756 * VM context. Remove any items that would otherwise create a privilage
759 * XXX at the moment we allow userland to set the resume flag. Is this a
763 cpu_sanitize_frame(struct trapframe *frame)
765 frame->tf_cs = _ucodesel;
766 frame->tf_ss = _udatasel;
767 /* XXX VM (8086) mode not supported? */
768 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
769 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
775 * Sanitize the tls so loading the descriptor does not blow up
776 * on us. For x86_64 we don't have to do anything.
779 cpu_sanitize_tls(struct savetls *tls)
785 * sigreturn(ucontext_t *sigcntxp)
787 * System call to cleanup state after a signal
788 * has been taken. Reset signal mask and
789 * stack state from context left by sendsig (above).
790 * Return to previous pc and psl as specified by
791 * context left by sendsig. Check carefully to
792 * make sure that the user has not modified the
793 * state to gain improper privileges.
797 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
798 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
801 sys_sigreturn(struct sigreturn_args *uap)
803 struct lwp *lp = curthread->td_lwp;
804 struct trapframe *regs;
812 * We have to copy the information into kernel space so userland
813 * can't modify it while we are sniffing it.
815 regs = lp->lwp_md.md_regs;
816 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
820 rflags = ucp->uc_mcontext.mc_rflags;
822 /* VM (8086) mode not supported */
823 rflags &= ~PSL_VM_UNSUPP;
826 if (eflags & PSL_VM) {
827 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
828 struct vm86_kernel *vm86;
831 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
832 * set up the vm86 area, and we can't enter vm86 mode.
834 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
836 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
837 if (vm86->vm86_inited == 0)
840 /* go back to user mode if both flags are set */
841 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
842 trapsignal(lp, SIGBUS, 0);
844 if (vm86->vm86_has_vme) {
845 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
846 (eflags & VME_USERCHANGE) | PSL_VM;
848 vm86->vm86_eflags = eflags; /* save VIF, VIP */
849 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
850 (eflags & VM_USERCHANGE) | PSL_VM;
852 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
853 tf->tf_eflags = eflags;
854 tf->tf_vm86_ds = tf->tf_ds;
855 tf->tf_vm86_es = tf->tf_es;
856 tf->tf_vm86_fs = tf->tf_fs;
857 tf->tf_vm86_gs = tf->tf_gs;
858 tf->tf_ds = _udatasel;
859 tf->tf_es = _udatasel;
860 tf->tf_fs = _udatasel;
861 tf->tf_gs = _udatasel;
866 * Don't allow users to change privileged or reserved flags.
869 * XXX do allow users to change the privileged flag PSL_RF.
870 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
871 * should sometimes set it there too. tf_eflags is kept in
872 * the signal context during signal handling and there is no
873 * other place to remember it, so the PSL_RF bit may be
874 * corrupted by the signal handler without us knowing.
875 * Corruption of the PSL_RF bit at worst causes one more or
876 * one less debugger trap, so allowing it is fairly harmless.
878 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
879 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
884 * Don't allow users to load a valid privileged %cs. Let the
885 * hardware check for invalid selectors, excess privilege in
886 * other selectors, invalid %eip's and invalid %esp's.
888 cs = ucp->uc_mcontext.mc_cs;
889 if (!CS_SECURE(cs)) {
890 kprintf("sigreturn: cs = 0x%x\n", cs);
891 trapsignal(lp, SIGBUS, T_PROTFLT);
894 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
898 * Restore the FPU state from the frame
901 npxpop(&ucp->uc_mcontext);
903 if (ucp->uc_mcontext.mc_onstack & 1)
904 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
906 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
908 lp->lwp_sigmask = ucp->uc_sigmask;
909 SIG_CANTMASK(lp->lwp_sigmask);
916 * Machine dependent boot() routine
918 * I haven't seen anything to put here yet
919 * Possibly some stuff might be grafted back here from boot()
927 * Shutdown the CPU as much as possible
933 __asm__ __volatile("hlt");
937 * cpu_idle() represents the idle LWKT. You cannot return from this function
938 * (unless you want to blow things up!). Instead we look for runnable threads
939 * and loop or halt as appropriate. Giant is not held on entry to the thread.
941 * The main loop is entered with a critical section held, we must release
942 * the critical section before doing anything else. lwkt_switch() will
943 * check for pending interrupts due to entering and exiting its own
946 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
947 * However, there are cases where the idlethread will be entered with
948 * the possibility that no IPI will occur and in such cases
949 * lwkt_switch() sets TDF_IDLE_NOHLT.
951 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
952 * must occur before it starts using ACPI halt.
954 static int cpu_idle_hlt = 2;
955 static int cpu_idle_hltcnt;
956 static int cpu_idle_spincnt;
957 static u_int cpu_idle_repeat = 750;
958 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
959 &cpu_idle_hlt, 0, "Idle loop HLT enable");
960 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
961 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
962 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
963 &cpu_idle_spincnt, 0, "Idle loop entry spins");
964 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
965 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
968 cpu_idle_default_hook(void)
971 * We must guarentee that hlt is exactly the instruction
974 __asm __volatile("sti; hlt");
977 /* Other subsystems (e.g., ACPI) can hook this later. */
978 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
981 cpu_mwait_cx_hint(struct globaldata *gd)
983 if (cpu_mwait_halt >= 0)
984 return cpu_mwait_halt;
985 panic("not supported yet");
991 globaldata_t gd = mycpu;
992 struct thread *td __debugvar = gd->gd_curthread;
997 KKASSERT(td->td_critcount == 0);
1000 * See if there are any LWKTs ready to go.
1005 * When halting inside a cli we must check for reqflags
1006 * races, particularly [re]schedule requests. Running
1007 * splz() does the job.
1010 * 0 Never halt, just spin
1012 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1013 * This typically eats more power than the
1016 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1017 * use the ACPI halt (default). This is a hybrid
1018 * approach. See machdep.cpu_idle_repeat.
1020 * 3 Always use the ACPI halt. This typically
1021 * eats the least amount of power but the cpu
1022 * will be slow waking up. Slows down e.g.
1023 * compiles and other pipe/event oriented stuff.
1025 * NOTE: Interrupts are enabled and we are not in a critical
1028 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1029 * don't bother capping gd_idle_repeat, it is ok if
1032 ++gd->gd_idle_repeat;
1033 reqflags = gd->gd_reqflags;
1034 quick = (cpu_idle_hlt == 1) ||
1035 (cpu_idle_hlt < 3 &&
1036 gd->gd_idle_repeat < cpu_idle_repeat);
1038 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1039 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1041 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1042 cpu_mwait_cx_hint(gd), 0);
1044 } else if (cpu_idle_hlt) {
1045 __asm __volatile("cli");
1047 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1049 cpu_idle_default_hook();
1053 __asm __volatile("sti");
1057 __asm __volatile("sti");
1064 * This routine is called if a spinlock has been held through the
1065 * exponential backoff period and is seriously contested. On a real cpu
1069 cpu_spinlock_contested(void)
1075 * Clear registers on exec
1078 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1080 struct thread *td = curthread;
1081 struct lwp *lp = td->td_lwp;
1082 struct pcb *pcb = td->td_pcb;
1083 struct trapframe *regs = lp->lwp_md.md_regs;
1085 /* was i386_user_cleanup() in NetBSD */
1089 bzero((char *)regs, sizeof(struct trapframe));
1090 regs->tf_rip = entry;
1091 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1092 regs->tf_rdi = stack; /* argv */
1093 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1094 regs->tf_ss = _udatasel;
1095 regs->tf_cs = _ucodesel;
1096 regs->tf_rbx = ps_strings;
1099 * Reset the hardware debug registers if they were in use.
1100 * They won't have any meaning for the newly exec'd process.
1102 if (pcb->pcb_flags & PCB_DBREGS) {
1108 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1109 if (pcb == td->td_pcb) {
1111 * Clear the debug registers on the running
1112 * CPU, otherwise they will end up affecting
1113 * the next process we switch to.
1117 pcb->pcb_flags &= ~PCB_DBREGS;
1121 * Initialize the math emulator (if any) for the current process.
1122 * Actually, just clear the bit that says that the emulator has
1123 * been initialized. Initialization is delayed until the process
1124 * traps to the emulator (if it is done at all) mainly because
1125 * emulators don't provide an entry point for initialization.
1127 pcb->pcb_flags &= ~FP_SOFTFP;
1130 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1131 * gd_npxthread. Otherwise a preemptive interrupt thread
1132 * may panic in npxdna().
1135 load_cr0(rcr0() | CR0_MP);
1138 * NOTE: The MSR values must be correct so we can return to
1139 * userland. gd_user_fs/gs must be correct so the switch
1140 * code knows what the current MSR values are.
1142 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1143 pcb->pcb_gsbase = 0;
1144 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1145 mdcpu->gd_user_gs = 0;
1146 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1147 wrmsr(MSR_KGSBASE, 0);
1149 /* Initialize the npx (if any) for the current process. */
1150 npxinit(__INITIAL_FPUCW__);
1153 pcb->pcb_ds = _udatasel;
1154 pcb->pcb_es = _udatasel;
1155 pcb->pcb_fs = _udatasel;
1156 pcb->pcb_gs = _udatasel;
1165 cr0 |= CR0_NE; /* Done by npxinit() */
1166 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1167 cr0 |= CR0_WP | CR0_AM;
1173 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1176 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1178 if (!error && req->newptr)
1183 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1184 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1186 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1187 CTLFLAG_RW, &disable_rtc_set, 0, "");
1190 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1191 CTLFLAG_RD, &bootinfo, bootinfo, "");
1194 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1195 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1197 extern u_long bootdev; /* not a cdev_t - encoding is different */
1198 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1199 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1202 * Initialize 386 and configure to run kernel
1206 * Initialize segments & interrupt table
1210 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1211 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1213 union descriptor ldt[NLDT]; /* local descriptor table */
1216 /* table descriptors - used to load tables by cpu */
1217 struct region_descriptor r_gdt;
1218 struct region_descriptor r_idt_arr[MAXCPU];
1220 /* JG proc0paddr is a virtual address */
1223 char proc0paddr_buff[LWKT_THREAD_STACK];
1226 /* software prototypes -- in more palatable form */
1227 struct soft_segment_descriptor gdt_segs[] = {
1228 /* GNULL_SEL 0 Null Descriptor */
1229 { 0x0, /* segment base address */
1231 0, /* segment type */
1232 0, /* segment descriptor priority level */
1233 0, /* segment descriptor present */
1235 0, /* default 32 vs 16 bit size */
1236 0 /* limit granularity (byte/page units)*/ },
1237 /* GCODE_SEL 1 Code Descriptor for kernel */
1238 { 0x0, /* segment base address */
1239 0xfffff, /* length - all address space */
1240 SDT_MEMERA, /* segment type */
1241 SEL_KPL, /* segment descriptor priority level */
1242 1, /* segment descriptor present */
1244 0, /* default 32 vs 16 bit size */
1245 1 /* limit granularity (byte/page units)*/ },
1246 /* GDATA_SEL 2 Data Descriptor for kernel */
1247 { 0x0, /* segment base address */
1248 0xfffff, /* length - all address space */
1249 SDT_MEMRWA, /* segment type */
1250 SEL_KPL, /* segment descriptor priority level */
1251 1, /* segment descriptor present */
1253 0, /* default 32 vs 16 bit size */
1254 1 /* limit granularity (byte/page units)*/ },
1255 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1256 { 0x0, /* segment base address */
1257 0xfffff, /* length - all address space */
1258 SDT_MEMERA, /* segment type */
1259 SEL_UPL, /* segment descriptor priority level */
1260 1, /* segment descriptor present */
1262 1, /* default 32 vs 16 bit size */
1263 1 /* limit granularity (byte/page units)*/ },
1264 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1265 { 0x0, /* segment base address */
1266 0xfffff, /* length - all address space */
1267 SDT_MEMRWA, /* segment type */
1268 SEL_UPL, /* segment descriptor priority level */
1269 1, /* segment descriptor present */
1271 1, /* default 32 vs 16 bit size */
1272 1 /* limit granularity (byte/page units)*/ },
1273 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1274 { 0x0, /* segment base address */
1275 0xfffff, /* length - all address space */
1276 SDT_MEMERA, /* segment type */
1277 SEL_UPL, /* segment descriptor priority level */
1278 1, /* segment descriptor present */
1280 0, /* default 32 vs 16 bit size */
1281 1 /* limit granularity (byte/page units)*/ },
1282 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1284 0x0, /* segment base address */
1285 sizeof(struct x86_64tss)-1,/* length - all address space */
1286 SDT_SYSTSS, /* segment type */
1287 SEL_KPL, /* segment descriptor priority level */
1288 1, /* segment descriptor present */
1290 0, /* unused - default 32 vs 16 bit size */
1291 0 /* limit granularity (byte/page units)*/ },
1292 /* Actually, the TSS is a system descriptor which is double size */
1293 { 0x0, /* segment base address */
1295 0, /* segment type */
1296 0, /* segment descriptor priority level */
1297 0, /* segment descriptor present */
1299 0, /* default 32 vs 16 bit size */
1300 0 /* limit granularity (byte/page units)*/ },
1301 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1302 { 0x0, /* segment base address */
1303 0xfffff, /* length - all address space */
1304 SDT_MEMRWA, /* segment type */
1305 SEL_UPL, /* segment descriptor priority level */
1306 1, /* segment descriptor present */
1308 1, /* default 32 vs 16 bit size */
1309 1 /* limit granularity (byte/page units)*/ },
1313 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1317 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1318 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1320 ip->gd_looffset = (uintptr_t)func;
1321 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1327 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1332 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1334 struct gate_descriptor *ip;
1336 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1338 ip = &idt_arr[cpu][idx];
1339 ip->gd_looffset = (uintptr_t)func;
1340 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1346 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1349 #define IDTVEC(name) __CONCAT(X,name)
1352 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1353 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1354 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1355 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1356 IDTVEC(xmm), IDTVEC(dblfault),
1357 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1359 #ifdef DEBUG_INTERRUPTS
1360 extern inthand_t *Xrsvdary[256];
1364 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1366 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1367 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1368 ssd->ssd_type = sd->sd_type;
1369 ssd->ssd_dpl = sd->sd_dpl;
1370 ssd->ssd_p = sd->sd_p;
1371 ssd->ssd_def32 = sd->sd_def32;
1372 ssd->ssd_gran = sd->sd_gran;
1376 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1379 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1380 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1381 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1382 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1383 sd->sd_type = ssd->ssd_type;
1384 sd->sd_dpl = ssd->ssd_dpl;
1385 sd->sd_p = ssd->ssd_p;
1386 sd->sd_long = ssd->ssd_long;
1387 sd->sd_def32 = ssd->ssd_def32;
1388 sd->sd_gran = ssd->ssd_gran;
1392 ssdtosyssd(struct soft_segment_descriptor *ssd,
1393 struct system_segment_descriptor *sd)
1396 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1397 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1398 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1399 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1400 sd->sd_type = ssd->ssd_type;
1401 sd->sd_dpl = ssd->ssd_dpl;
1402 sd->sd_p = ssd->ssd_p;
1403 sd->sd_gran = ssd->ssd_gran;
1407 * Populate the (physmap) array with base/bound pairs describing the
1408 * available physical memory in the system, then test this memory and
1409 * build the phys_avail array describing the actually-available memory.
1411 * If we cannot accurately determine the physical memory map, then use
1412 * value from the 0xE801 call, and failing that, the RTC.
1414 * Total memory size may be set by the kernel environment variable
1415 * hw.physmem or the compile-time define MAXMEM.
1417 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1418 * of PAGE_SIZE. This also greatly reduces the memory test time
1419 * which would otherwise be excessive on machines with > 8G of ram.
1421 * XXX first should be vm_paddr_t.
1424 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1425 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1428 getmemsize(caddr_t kmdp, u_int64_t first)
1430 int off, physmap_idx, pa_indx, da_indx;
1432 vm_paddr_t physmap[PHYSMAP_SIZE];
1434 vm_paddr_t msgbuf_size;
1435 u_long physmem_tunable;
1437 struct bios_smap *smapbase, *smap, *smapend;
1439 quad_t dcons_addr, dcons_size;
1441 bzero(physmap, sizeof(physmap));
1445 * get memory map from INT 15:E820, kindly supplied by the loader.
1447 * subr_module.c says:
1448 * "Consumer may safely assume that size value precedes data."
1449 * ie: an int32_t immediately precedes smap.
1451 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1452 MODINFO_METADATA | MODINFOMD_SMAP);
1453 if (smapbase == NULL)
1454 panic("No BIOS smap info from loader!");
1456 smapsize = *((u_int32_t *)smapbase - 1);
1457 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1459 for (smap = smapbase; smap < smapend; smap++) {
1460 if (boothowto & RB_VERBOSE)
1461 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1462 smap->type, smap->base, smap->length);
1464 if (smap->type != SMAP_TYPE_MEMORY)
1467 if (smap->length == 0)
1470 for (i = 0; i <= physmap_idx; i += 2) {
1471 if (smap->base < physmap[i + 1]) {
1472 if (boothowto & RB_VERBOSE) {
1473 kprintf("Overlapping or non-monotonic "
1474 "memory region, ignoring "
1480 if (i <= physmap_idx)
1483 Realmem += smap->length;
1485 if (smap->base == physmap[physmap_idx + 1]) {
1486 physmap[physmap_idx + 1] += smap->length;
1491 if (physmap_idx == PHYSMAP_SIZE) {
1492 kprintf("Too many segments in the physical "
1493 "address map, giving up\n");
1496 physmap[physmap_idx] = smap->base;
1497 physmap[physmap_idx + 1] = smap->base + smap->length;
1500 base_memory = physmap[1] / 1024;
1501 /* make hole for AP bootstrap code */
1502 physmap[1] = mp_bootaddress(base_memory);
1504 /* Save EBDA address, if any */
1505 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1509 * Maxmem isn't the "maximum memory", it's one larger than the
1510 * highest page of the physical address space. It should be
1511 * called something like "Maxphyspage". We may adjust this
1512 * based on ``hw.physmem'' and the results of the memory test.
1514 Maxmem = atop(physmap[physmap_idx + 1]);
1517 Maxmem = MAXMEM / 4;
1520 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1521 Maxmem = atop(physmem_tunable);
1524 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1527 if (Maxmem > atop(physmap[physmap_idx + 1]))
1528 Maxmem = atop(physmap[physmap_idx + 1]);
1531 * Blowing out the DMAP will blow up the system.
1533 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1534 kprintf("Limiting Maxmem due to DMAP size\n");
1535 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1538 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1539 (boothowto & RB_VERBOSE)) {
1540 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1544 * Call pmap initialization to make new kernel address space
1548 pmap_bootstrap(&first);
1549 physmap[0] = PAGE_SIZE;
1552 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1555 for (i = j = 0; i <= physmap_idx; i += 2) {
1556 if (physmap[i+1] > ptoa(Maxmem))
1557 physmap[i+1] = ptoa(Maxmem);
1558 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1559 ~PHYSMAP_ALIGN_MASK;
1560 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1562 physmap[j] = physmap[i];
1563 physmap[j+1] = physmap[i+1];
1565 if (physmap[i] < physmap[i+1])
1568 physmap_idx = j - 2;
1571 * Align anything else used in the validation loop.
1573 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1576 * Size up each available chunk of physical memory.
1580 phys_avail[pa_indx++] = physmap[0];
1581 phys_avail[pa_indx] = physmap[0];
1582 dump_avail[da_indx] = physmap[0];
1586 * Get dcons buffer address
1588 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1589 kgetenv_quad("dcons.size", &dcons_size) == 0)
1593 * Validate the physical memory. The physical memory segments
1594 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1597 for (i = 0; i <= physmap_idx; i += 2) {
1600 end = physmap[i + 1];
1602 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1603 int tmp, page_bad, full;
1604 int *ptr = (int *)CADDR1;
1608 * block out kernel memory as not available.
1610 if (pa >= 0x200000 && pa < first)
1614 * block out dcons buffer
1617 && pa >= trunc_page(dcons_addr)
1618 && pa < dcons_addr + dcons_size) {
1625 * map page into kernel: valid, read/write,non-cacheable
1628 kernel_pmap.pmap_bits[PG_V_IDX] |
1629 kernel_pmap.pmap_bits[PG_RW_IDX] |
1630 kernel_pmap.pmap_bits[PG_N_IDX];
1635 * Test for alternating 1's and 0's
1637 *(volatile int *)ptr = 0xaaaaaaaa;
1639 if (*(volatile int *)ptr != 0xaaaaaaaa)
1642 * Test for alternating 0's and 1's
1644 *(volatile int *)ptr = 0x55555555;
1646 if (*(volatile int *)ptr != 0x55555555)
1651 *(volatile int *)ptr = 0xffffffff;
1653 if (*(volatile int *)ptr != 0xffffffff)
1658 *(volatile int *)ptr = 0x0;
1660 if (*(volatile int *)ptr != 0x0)
1663 * Restore original value.
1668 * Adjust array of valid/good pages.
1670 if (page_bad == TRUE)
1673 * If this good page is a continuation of the
1674 * previous set of good pages, then just increase
1675 * the end pointer. Otherwise start a new chunk.
1676 * Note that "end" points one higher than end,
1677 * making the range >= start and < end.
1678 * If we're also doing a speculative memory
1679 * test and we at or past the end, bump up Maxmem
1680 * so that we keep going. The first bad page
1681 * will terminate the loop.
1683 if (phys_avail[pa_indx] == pa) {
1684 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1687 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1689 "Too many holes in the physical address space, giving up\n");
1694 phys_avail[pa_indx++] = pa;
1695 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1697 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1699 if (dump_avail[da_indx] == pa) {
1700 dump_avail[da_indx] += PHYSMAP_ALIGN;
1703 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1707 dump_avail[da_indx++] = pa;
1708 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1719 * The last chunk must contain at least one page plus the message
1720 * buffer to avoid complicating other code (message buffer address
1721 * calculation, etc.).
1723 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1725 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1726 msgbuf_size >= phys_avail[pa_indx]) {
1727 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1728 phys_avail[pa_indx--] = 0;
1729 phys_avail[pa_indx--] = 0;
1732 Maxmem = atop(phys_avail[pa_indx]);
1734 /* Trim off space for the message buffer. */
1735 phys_avail[pa_indx] -= msgbuf_size;
1737 avail_end = phys_avail[pa_indx];
1739 /* Map the message buffer. */
1740 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1741 pmap_kenter((vm_offset_t)msgbufp + off,
1742 phys_avail[pa_indx] + off);
1746 struct machintr_abi MachIntrABI;
1757 * 7 Device Not Available (x87)
1759 * 9 Coprocessor Segment overrun (unsupported, reserved)
1761 * 11 Segment not present
1763 * 13 General Protection
1766 * 16 x87 FP Exception pending
1767 * 17 Alignment Check
1769 * 19 SIMD floating point
1771 * 32-255 INTn/external sources
1774 hammer_time(u_int64_t modulep, u_int64_t physfree)
1777 int gsel_tss, x, cpu;
1779 int metadata_missing, off;
1781 struct mdglobaldata *gd;
1785 * Prevent lowering of the ipl if we call tsleep() early.
1787 gd = &CPU_prvspace[0].mdglobaldata;
1788 bzero(gd, sizeof(*gd));
1791 * Note: on both UP and SMP curthread must be set non-NULL
1792 * early in the boot sequence because the system assumes
1793 * that 'curthread' is never NULL.
1796 gd->mi.gd_curthread = &thread0;
1797 thread0.td_gd = &gd->mi;
1799 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1802 metadata_missing = 0;
1803 if (bootinfo.bi_modulep) {
1804 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1805 preload_bootstrap_relocate(KERNBASE);
1807 metadata_missing = 1;
1809 if (bootinfo.bi_envp)
1810 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1813 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1814 preload_bootstrap_relocate(PTOV_OFFSET);
1815 kmdp = preload_search_by_type("elf kernel");
1817 kmdp = preload_search_by_type("elf64 kernel");
1818 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1819 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1821 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1822 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1825 if (boothowto & RB_VERBOSE)
1829 * Default MachIntrABI to ICU
1831 MachIntrABI = MachIntrABI_ICU;
1834 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1835 * and ncpus_fit_mask remain 0.
1840 /* Init basic tunables, hz etc */
1844 * make gdt memory segments
1846 gdt_segs[GPROC0_SEL].ssd_base =
1847 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1849 gd->mi.gd_prvspace = &CPU_prvspace[0];
1851 for (x = 0; x < NGDT; x++) {
1852 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1853 ssdtosd(&gdt_segs[x], &gdt[x]);
1855 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1856 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1858 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1859 r_gdt.rd_base = (long) gdt;
1862 wrmsr(MSR_FSBASE, 0); /* User value */
1863 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1864 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1866 mi_gdinit(&gd->mi, 0);
1868 proc0paddr = proc0paddr_buff;
1869 mi_proc0init(&gd->mi, proc0paddr);
1870 safepri = TDPRI_MAX;
1872 /* spinlocks and the BGL */
1876 for (x = 0; x < NIDT; x++)
1877 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1878 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1879 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1880 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1881 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1882 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1883 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1884 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1885 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1886 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1887 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1888 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1889 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1890 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1891 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1892 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1893 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1894 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1895 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1896 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1898 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1899 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
1900 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
1903 lidt(&r_idt_arr[0]);
1906 * Initialize the console before we print anything out.
1911 if (metadata_missing)
1912 kprintf("WARNING: loader(8) metadata is missing!\n");
1922 * Initialize IRQ mapping
1925 * SHOULD be after elcr_probe()
1927 MachIntrABI_ICU.initmap();
1928 MachIntrABI_IOAPIC.initmap();
1932 if (boothowto & RB_KDB)
1933 Debugger("Boot flags requested debugger");
1937 finishidentcpu(); /* Final stage of CPU initialization */
1938 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1939 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1941 identify_cpu(); /* Final stage of CPU initialization */
1942 initializecpu(0); /* Initialize CPU registers */
1944 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1945 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
1946 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
1949 * Some of the virtual machines do not work w/ I/O APIC
1950 * enabled. If the user does not explicitly enable or
1951 * disable the I/O APIC (ioapic_enable < 0), then we
1952 * disable I/O APIC on all virtual machines.
1955 * This must be done after identify_cpu(), which sets
1958 if (ioapic_enable < 0) {
1959 if (cpu_feature2 & CPUID2_VMM)
1965 /* make an initial tss so cpu can get interrupt stack on syscall! */
1966 gd->gd_common_tss.tss_rsp0 =
1967 (register_t)(thread0.td_kstack +
1968 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
1969 /* Ensure the stack is aligned to 16 bytes */
1970 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
1972 /* double fault stack */
1973 gd->gd_common_tss.tss_ist1 =
1974 (long)&gd->mi.gd_prvspace->idlestack[
1975 sizeof(gd->mi.gd_prvspace->idlestack)];
1977 /* Set the IO permission bitmap (empty due to tss seg limit) */
1978 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
1980 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1981 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
1982 gd->gd_common_tssd = *gd->gd_tss_gdt;
1985 /* Set up the fast syscall stuff */
1986 msr = rdmsr(MSR_EFER) | EFER_SCE;
1987 wrmsr(MSR_EFER, msr);
1988 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1989 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1990 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1991 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1992 wrmsr(MSR_STAR, msr);
1993 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
1995 getmemsize(kmdp, physfree);
1996 init_param2(physmem);
1998 /* now running on new page tables, configured,and u/iom is accessible */
2000 /* Map the message buffer. */
2002 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2003 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2006 msgbufinit(msgbufp, MSGBUF_SIZE);
2009 /* transfer to user mode */
2011 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2012 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2013 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2019 /* setup proc 0's pcb */
2020 thread0.td_pcb->pcb_flags = 0;
2021 thread0.td_pcb->pcb_cr3 = KPML4phys;
2022 thread0.td_pcb->pcb_ext = NULL;
2023 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2025 /* Location of kernel stack for locore */
2026 return ((u_int64_t)thread0.td_pcb);
2030 * Initialize machine-dependant portions of the global data structure.
2031 * Note that the global data area and cpu0's idlestack in the private
2032 * data space were allocated in locore.
2034 * Note: the idlethread's cpl is 0
2036 * WARNING! Called from early boot, 'mycpu' may not work yet.
2039 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2042 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2044 lwkt_init_thread(&gd->mi.gd_idlethread,
2045 gd->mi.gd_prvspace->idlestack,
2046 sizeof(gd->mi.gd_prvspace->idlestack),
2048 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2049 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2050 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2051 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2055 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2057 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2058 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2061 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2067 globaldata_find(int cpu)
2069 KKASSERT(cpu >= 0 && cpu < ncpus);
2070 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2074 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2076 lp->lwp_md.md_regs->tf_rip = addr;
2081 ptrace_single_step(struct lwp *lp)
2083 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2088 fill_regs(struct lwp *lp, struct reg *regs)
2090 struct trapframe *tp;
2092 if ((tp = lp->lwp_md.md_regs) == NULL)
2094 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2099 set_regs(struct lwp *lp, struct reg *regs)
2101 struct trapframe *tp;
2103 tp = lp->lwp_md.md_regs;
2104 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2105 !CS_SECURE(regs->r_cs))
2107 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2112 #ifndef CPU_DISABLE_SSE
2114 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2116 struct env87 *penv_87 = &sv_87->sv_env;
2117 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2120 /* FPU control/status */
2121 penv_87->en_cw = penv_xmm->en_cw;
2122 penv_87->en_sw = penv_xmm->en_sw;
2123 penv_87->en_tw = penv_xmm->en_tw;
2124 penv_87->en_fip = penv_xmm->en_fip;
2125 penv_87->en_fcs = penv_xmm->en_fcs;
2126 penv_87->en_opcode = penv_xmm->en_opcode;
2127 penv_87->en_foo = penv_xmm->en_foo;
2128 penv_87->en_fos = penv_xmm->en_fos;
2131 for (i = 0; i < 8; ++i)
2132 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2136 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2138 struct env87 *penv_87 = &sv_87->sv_env;
2139 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2142 /* FPU control/status */
2143 penv_xmm->en_cw = penv_87->en_cw;
2144 penv_xmm->en_sw = penv_87->en_sw;
2145 penv_xmm->en_tw = penv_87->en_tw;
2146 penv_xmm->en_fip = penv_87->en_fip;
2147 penv_xmm->en_fcs = penv_87->en_fcs;
2148 penv_xmm->en_opcode = penv_87->en_opcode;
2149 penv_xmm->en_foo = penv_87->en_foo;
2150 penv_xmm->en_fos = penv_87->en_fos;
2153 for (i = 0; i < 8; ++i)
2154 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2156 #endif /* CPU_DISABLE_SSE */
2159 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2161 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2163 #ifndef CPU_DISABLE_SSE
2165 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2166 (struct save87 *)fpregs);
2169 #endif /* CPU_DISABLE_SSE */
2170 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2175 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2177 #ifndef CPU_DISABLE_SSE
2179 set_fpregs_xmm((struct save87 *)fpregs,
2180 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2183 #endif /* CPU_DISABLE_SSE */
2184 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2189 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2194 dbregs->dr[0] = rdr0();
2195 dbregs->dr[1] = rdr1();
2196 dbregs->dr[2] = rdr2();
2197 dbregs->dr[3] = rdr3();
2198 dbregs->dr[4] = rdr4();
2199 dbregs->dr[5] = rdr5();
2200 dbregs->dr[6] = rdr6();
2201 dbregs->dr[7] = rdr7();
2204 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2206 dbregs->dr[0] = pcb->pcb_dr0;
2207 dbregs->dr[1] = pcb->pcb_dr1;
2208 dbregs->dr[2] = pcb->pcb_dr2;
2209 dbregs->dr[3] = pcb->pcb_dr3;
2212 dbregs->dr[6] = pcb->pcb_dr6;
2213 dbregs->dr[7] = pcb->pcb_dr7;
2218 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2221 load_dr0(dbregs->dr[0]);
2222 load_dr1(dbregs->dr[1]);
2223 load_dr2(dbregs->dr[2]);
2224 load_dr3(dbregs->dr[3]);
2225 load_dr4(dbregs->dr[4]);
2226 load_dr5(dbregs->dr[5]);
2227 load_dr6(dbregs->dr[6]);
2228 load_dr7(dbregs->dr[7]);
2231 struct ucred *ucred;
2233 uint64_t mask1, mask2;
2236 * Don't let an illegal value for dr7 get set. Specifically,
2237 * check for undefined settings. Setting these bit patterns
2238 * result in undefined behaviour and can lead to an unexpected
2241 /* JG this loop looks unreadable */
2242 /* Check 4 2-bit fields for invalid patterns.
2243 * These fields are R/Wi, for i = 0..3
2245 /* Is 10 in LENi allowed when running in compatibility mode? */
2246 /* Pattern 10 in R/Wi might be used to indicate
2247 * breakpoint on I/O. Further analysis should be
2248 * carried to decide if it is safe and useful to
2249 * provide access to that capability
2251 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2252 i++, mask1 <<= 4, mask2 <<= 4)
2253 if ((dbregs->dr[7] & mask1) == mask2)
2256 pcb = lp->lwp_thread->td_pcb;
2257 ucred = lp->lwp_proc->p_ucred;
2260 * Don't let a process set a breakpoint that is not within the
2261 * process's address space. If a process could do this, it
2262 * could halt the system by setting a breakpoint in the kernel
2263 * (if ddb was enabled). Thus, we need to check to make sure
2264 * that no breakpoints are being enabled for addresses outside
2265 * process's address space, unless, perhaps, we were called by
2268 * XXX - what about when the watched area of the user's
2269 * address space is written into from within the kernel
2270 * ... wouldn't that still cause a breakpoint to be generated
2271 * from within kernel mode?
2274 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2275 if (dbregs->dr[7] & 0x3) {
2276 /* dr0 is enabled */
2277 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2281 if (dbregs->dr[7] & (0x3<<2)) {
2282 /* dr1 is enabled */
2283 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2287 if (dbregs->dr[7] & (0x3<<4)) {
2288 /* dr2 is enabled */
2289 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2293 if (dbregs->dr[7] & (0x3<<6)) {
2294 /* dr3 is enabled */
2295 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2300 pcb->pcb_dr0 = dbregs->dr[0];
2301 pcb->pcb_dr1 = dbregs->dr[1];
2302 pcb->pcb_dr2 = dbregs->dr[2];
2303 pcb->pcb_dr3 = dbregs->dr[3];
2304 pcb->pcb_dr6 = dbregs->dr[6];
2305 pcb->pcb_dr7 = dbregs->dr[7];
2307 pcb->pcb_flags |= PCB_DBREGS;
2314 * Return > 0 if a hardware breakpoint has been hit, and the
2315 * breakpoint was in user space. Return 0, otherwise.
2318 user_dbreg_trap(void)
2320 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2321 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2322 int nbp; /* number of breakpoints that triggered */
2323 caddr_t addr[4]; /* breakpoint addresses */
2327 if ((dr7 & 0xff) == 0) {
2329 * all GE and LE bits in the dr7 register are zero,
2330 * thus the trap couldn't have been caused by the
2331 * hardware debug registers
2342 * None of the breakpoint bits are set meaning this
2343 * trap was not caused by any of the debug registers
2349 * at least one of the breakpoints were hit, check to see
2350 * which ones and if any of them are user space addresses
2354 addr[nbp++] = (caddr_t)rdr0();
2357 addr[nbp++] = (caddr_t)rdr1();
2360 addr[nbp++] = (caddr_t)rdr2();
2363 addr[nbp++] = (caddr_t)rdr3();
2366 for (i=0; i<nbp; i++) {
2368 (caddr_t)VM_MAX_USER_ADDRESS) {
2370 * addr[i] is in user space
2377 * None of the breakpoints are in user space.
2385 Debugger(const char *msg)
2387 kprintf("Debugger(\"%s\") called.\n", msg);
2394 * Provide inb() and outb() as functions. They are normally only
2395 * available as macros calling inlined functions, thus cannot be
2396 * called inside DDB.
2398 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2404 /* silence compiler warnings */
2406 void outb(u_int, u_char);
2413 * We use %%dx and not %1 here because i/o is done at %dx and not at
2414 * %edx, while gcc generates inferior code (movw instead of movl)
2415 * if we tell it to load (u_short) port.
2417 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2422 outb(u_int port, u_char data)
2426 * Use an unnecessary assignment to help gcc's register allocator.
2427 * This make a large difference for gcc-1.40 and a tiny difference
2428 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2429 * best results. gcc-2.6.0 can't handle this.
2432 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2440 * initialize all the SMP locks
2443 /* critical region when masking or unmasking interupts */
2444 struct spinlock_deprecated imen_spinlock;
2446 /* critical region for old style disable_intr/enable_intr */
2447 struct spinlock_deprecated mpintr_spinlock;
2449 /* critical region around INTR() routines */
2450 struct spinlock_deprecated intr_spinlock;
2452 /* lock region used by kernel profiling */
2453 struct spinlock_deprecated mcount_spinlock;
2455 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2456 struct spinlock_deprecated com_spinlock;
2458 /* lock regions around the clock hardware */
2459 struct spinlock_deprecated clock_spinlock;
2465 * Get the initial mplock with a count of 1 for the BSP.
2466 * This uses a LOGICAL cpu ID, ie BSP == 0.
2468 cpu_get_initial_mplock();
2470 spin_lock_init(&mcount_spinlock);
2471 spin_lock_init(&intr_spinlock);
2472 spin_lock_init(&mpintr_spinlock);
2473 spin_lock_init(&imen_spinlock);
2474 spin_lock_init(&com_spinlock);
2475 spin_lock_init(&clock_spinlock);
2477 /* our token pool needs to work early */
2478 lwkt_token_pool_init();
2482 cpu_mwait_hint_valid(uint32_t hint)
2486 cx_idx = MWAIT_EAX_TO_CX(hint);
2487 if (cx_idx >= CPU_MWAIT_CX_MAX)
2490 sub = MWAIT_EAX_TO_CX_SUB(hint);
2491 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2498 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0)
2500 int error, cx_idx, sub, hint, new_hint;
2501 char name[16], *ptr, *start;
2504 cx_idx = MWAIT_EAX_TO_CX(hint);
2505 sub = MWAIT_EAX_TO_CX_SUB(hint);
2507 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2508 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2509 strlcpy(name, "NONE", sizeof(name));
2510 else if (cx_idx >= CPU_MWAIT_CX_MAX ||
2511 sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2512 strlcpy(name, "INVALID", sizeof(name));
2514 ksnprintf(name, sizeof(name), "C%d/%d", cx_idx, sub);
2516 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2517 if (error != 0 || req->newptr == NULL)
2520 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2521 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2524 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2529 cx_idx = strtol(start, &ptr, 10);
2530 if (ptr == start || *ptr != '/')
2532 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2538 sub = strtol(start, &ptr, 10);
2541 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2544 new_hint = MWAIT_EAX_HINT(cx_idx, sub);
2545 if (hint < CPU_MWAIT_C3 && new_hint >= CPU_MWAIT_C3) {
2546 error = cputimer_intr_powersave_addreq();
2549 } else if (hint >= CPU_MWAIT_C3 && new_hint < CPU_MWAIT_C3) {
2550 cputimer_intr_powersave_remreq();
2558 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
2562 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2563 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2565 lwkt_serialize_exit(&cpu_mwait_cx_slize);
2570 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
2574 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2575 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2577 lwkt_serialize_exit(&cpu_mwait_cx_slize);