2 * Copyright (c) 1999, 2000 Gary Jennejohn. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 *---------------------------------------------------------------------------
33 * i4b_ifpi_pci.c: AVM Fritz!Card PCI hardware driver
34 * --------------------------------------------------
36 * $Id: i4b_ifpi_pci.c,v 1.4 2000/06/02 11:58:56 hm Exp $
38 * $FreeBSD: src/sys/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.6.2.1 2001/08/10 14:08:37 obrien Exp $
39 * $DragonFly: src/sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.6 2004/02/13 17:45:50 joerg Exp $
41 * last edit-date: [Fri Jan 12 17:01:26 2001]
43 *---------------------------------------------------------------------------*/
49 #if (NIFPI > 0) && (NPCI > 0)
51 #include <sys/param.h>
52 #include <sys/kernel.h>
53 #include <sys/systm.h>
56 #include <machine/bus.h>
60 #include <bus/pci/pcireg.h>
61 #include <bus/pci/pcivar.h>
63 #include <sys/socket.h>
66 #include <net/i4b/include/machine/i4b_debug.h>
67 #include <net/i4b/include/machine/i4b_ioctl.h>
68 #include <net/i4b/include/machine/i4b_trace.h>
70 #include "../../include/i4b_global.h"
71 #include "../../include/i4b_mbuf.h"
73 #include "../i4b_l1.h"
74 #include "../isic/i4b_isic.h"
75 #include "../isic/i4b_isac.h"
76 #include "../isic/i4b_hscx.h"
78 #include "i4b_ifpi_ext.h"
80 #define PCI_AVMA1_VID 0x1244
81 #define PCI_AVMA1_DID 0x0a00
84 static void avma1pp_disable(device_t);
86 static void avma1pp_intr(void *);
87 static void hscx_write_reg(int, u_int, u_int, struct l1_softc *);
88 static u_char hscx_read_reg(int, u_int, struct l1_softc *);
89 static u_int hscx_read_reg_int(int, u_int, struct l1_softc *);
90 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
91 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
92 static void avma1pp_hscx_int_handler(struct l1_softc *);
93 static void avma1pp_hscx_intr(int, u_int, struct l1_softc *);
94 static void avma1pp_init_linktab(struct l1_softc *);
95 static void avma1pp_bchannel_setup(int, int, int, int);
96 static void avma1pp_bchannel_start(int, int);
97 static void avma1pp_hscx_init(struct l1_softc *, int, int);
98 static void avma1pp_bchannel_stat(int, int, bchan_statistics_t *);
99 static void avma1pp_set_linktab(int, int, drvr_link_t *);
100 static isdn_link_t * avma1pp_ret_linktab(int, int);
101 static int avma1pp_pci_probe(device_t);
102 static int avma1pp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
103 int avma1pp_attach_avma1pp(device_t);
104 static void ifpi_isac_intr(struct l1_softc *sc);
106 static device_method_t avma1pp_pci_methods[] = {
107 /* Device interface */
108 DEVMETHOD(device_probe, avma1pp_pci_probe),
109 DEVMETHOD(device_attach, avma1pp_attach_avma1pp),
110 DEVMETHOD(device_shutdown, avma1pp_disable),
113 DEVMETHOD(bus_print_child, bus_generic_print_child),
114 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
119 #if 0 /* use what's in l1_softc */
120 /* a minimal softc for the Fritz!Card PCI */
123 bus_space_handle_t avma1pp_bhandle;
124 bus_space_tag_t avma1pp_btag;
125 void *avma1pp_intrhand;
126 struct resource *avma1pp_irq;
127 struct resource *avma1pp_res;
128 /* pointer to ifpi_sc */
129 struct l1_softc *avma1pp_isc;
133 static driver_t avma1pp_pci_driver = {
136 sizeof(struct l1_softc)
139 static devclass_t avma1pp_pci_devclass;
141 DRIVER_MODULE(avma1pp, pci, avma1pp_pci_driver, avma1pp_pci_devclass, 0, 0);
143 /* jump table for multiplex routines */
145 struct i4b_l1mux_func avma1pp_l1mux_func = {
148 ifpi_mph_command_req,
150 ifpi_ph_activate_req,
153 struct l1_softc *ifpi_scp[IFPI_MAXUNIT];
155 /*---------------------------------------------------------------------------*
156 * AVM PCI Fritz!Card special registers
157 *---------------------------------------------------------------------------*/
160 * register offsets from i/o base
162 #define STAT0_OFFSET 0x02
163 #define STAT1_OFFSET 0x03
164 #define ADDR_REG_OFFSET 0x04
165 /*#define MODREG_OFFSET 0x06
166 #define VERREG_OFFSET 0x07*/
168 /* these 2 are used to select an ISAC register set */
169 #define ISAC_LO_REG_OFFSET 0x04
170 #define ISAC_HI_REG_OFFSET 0x06
172 /* offset higher than this goes to the HI register set */
173 #define MAX_LO_REG_OFFSET 0x2f
175 /* mask for the offset */
176 #define ISAC_REGSET_MASK 0x0f
178 /* the offset from the base to the ISAC registers */
179 #define ISAC_REG_OFFSET 0x10
181 /* the offset from the base to the ISAC FIFO */
182 #define ISAC_FIFO 0x02
184 /* not really the HSCX, but sort of */
185 #define HSCX_FIFO 0x00
186 #define HSCX_STAT 0x04
189 * AVM PCI Status Latch 0 read only bits
191 #define ASL_IRQ_ISAC 0x01 /* ISAC interrupt, active low */
192 #define ASL_IRQ_HSCX 0x02 /* HSX interrupt, active low */
193 #define ASL_IRQ_TIMER 0x04 /* Timer interrupt, active low */
194 #define ASL_IRQ_BCHAN ASL_IRQ_HSCX
195 /* actually active LOW */
196 #define ASL_IRQ_Pending (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
199 * AVM Status Latch 0 write only bits
201 #define ASL_RESET_ALL 0x01 /* reset siemens IC's, active 1 */
202 #define ASL_TIMERDISABLE 0x02 /* active high */
203 #define ASL_TIMERRESET 0x04 /* active high */
204 #define ASL_ENABLE_INT 0x08 /* active high */
205 #define ASL_TESTBIT 0x10 /* active high */
208 * AVM Status Latch 1 write only bits
210 #define ASL1_INTSEL 0x0f /* active high */
211 #define ASL1_ENABLE_IOM 0x80 /* active high */
216 #define HSCX_MODE_ITF_FLG 0x01
217 #define HSCX_MODE_TRANS 0x02
218 #define HSCX_MODE_CCR_7 0x04
219 #define HSCX_MODE_CCR_16 0x08
220 #define HSCX_MODE_TESTLOOP 0x80
225 #define HSCX_STAT_RME 0x01
226 #define HSCX_STAT_RDO 0x10
227 #define HSCX_STAT_CRCVFRRAB 0x0E
228 #define HSCX_STAT_CRCVFR 0x06
229 #define HSCX_STAT_RML_MASK 0x3f00
232 * "HSCX" interrupt bits
234 #define HSCX_INT_XPR 0x80
235 #define HSCX_INT_XDU 0x40
236 #define HSCX_INT_RPR 0x20
237 #define HSCX_INT_MASK 0xE0
240 * "HSCX" command bits
242 #define HSCX_CMD_XRS 0x80
243 #define HSCX_CMD_XME 0x01
244 #define HSCX_CMD_RRS 0x20
245 #define HSCX_CMD_XML_MASK 0x3f00
248 * Commands and parameters are sent to the "HSCX" as a long, but the
249 * fields are handled as bytes.
252 * (prot << 16)|(txl << 8)|cmd
255 * prot = protocol to use
256 * txl = transmit length
257 * cmd = the command to be executed
259 * The fields are defined as u_char in struct l1_softc.
261 * Macro to coalesce the byte fields into a u_int
263 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
264 | (sc->avma1pp_prot << 16))
267 * to prevent deactivating the "HSCX" when both channels are active we
268 * define an HSCX_ACTIVE flag which is or'd into the channel's state
269 * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
270 * It is set high to allow room for new flags.
272 #define HSCX_AVMA1PP_ACTIVE 0x1000
274 /*---------------------------------------------------------------------------*
275 * AVM read fifo routines
276 *---------------------------------------------------------------------------*/
279 avma1pp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
281 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
282 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
286 bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, ISAC_FIFO);
287 bus_space_read_multi_1(btag, bhandle, ISAC_REG_OFFSET, buf, size);
289 case ISIC_WHAT_HSCXA:
290 hscx_read_fifo(0, buf, size, sc);
292 case ISIC_WHAT_HSCXB:
293 hscx_read_fifo(1, buf, size, sc);
299 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
303 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
304 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
306 bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
307 ip = (u_int32_t *)buf;
309 /* what if len isn't a multiple of sizeof(int) and buf is */
313 *ip++ = bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET);
318 /*---------------------------------------------------------------------------*
319 * AVM write fifo routines
320 *---------------------------------------------------------------------------*/
322 avma1pp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
324 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
325 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
329 bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, ISAC_FIFO);
330 bus_space_write_multi_1(btag, bhandle, ISAC_REG_OFFSET, (u_int8_t*)buf, size);
332 case ISIC_WHAT_HSCXA:
333 hscx_write_fifo(0, buf, size, sc);
335 case ISIC_WHAT_HSCXB:
336 hscx_write_fifo(1, buf, size, sc);
342 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
346 l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
347 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
348 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
351 sc->avma1pp_cmd &= ~HSCX_CMD_XME;
353 if (Bchan->out_mbuf_cur == NULL)
355 if (Bchan->bprot != BPROT_NONE)
356 sc->avma1pp_cmd |= HSCX_CMD_XME;
358 if (len != sc->sc_bfifolen)
359 sc->avma1pp_txl = len;
361 cnt = 0; /* borrow cnt */
362 AVMA1PPSETCMDLONG(cnt);
363 hscx_write_reg(chan, HSCX_STAT, cnt, sc);
365 ip = (u_int32_t *)buf;
369 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET, *ip);
375 /*---------------------------------------------------------------------------*
376 * AVM write register routines
377 *---------------------------------------------------------------------------*/
380 avma1pp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
383 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
384 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
388 reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
389 #ifdef AVMA1PCI_DEBUG
390 printf("write_reg bank %d off %ld.. ", (int)reg_bank, (long)offs);
392 /* set the register bank */
393 bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
394 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
396 case ISIC_WHAT_HSCXA:
397 hscx_write_reg(0, offs, data, sc);
399 case ISIC_WHAT_HSCXB:
400 hscx_write_reg(1, offs, data, sc);
406 hscx_write_reg(int chan, u_int off, u_int val, struct l1_softc *sc)
408 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
409 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
411 /* point at the correct channel */
412 bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
413 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET + off, val);
416 /*---------------------------------------------------------------------------*
417 * AVM read register routines
418 *---------------------------------------------------------------------------*/
420 avma1pp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
423 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
424 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
428 reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
429 #ifdef AVMA1PCI_DEBUG
430 printf("read_reg bank %d off %ld.. ", (int)reg_bank, (long)offs);
432 /* set the register bank */
433 bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
434 return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
435 (offs & ISAC_REGSET_MASK)));
436 case ISIC_WHAT_HSCXA:
437 return hscx_read_reg(0, offs, sc);
438 case ISIC_WHAT_HSCXB:
439 return hscx_read_reg(1, offs, sc);
445 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
447 return(hscx_read_reg_int(chan, off, sc) & 0xff);
451 * need to be able to return an int because the RBCH is in the 2nd
455 hscx_read_reg_int(int chan, u_int off, struct l1_softc *sc)
457 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
458 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
460 /* point at the correct channel */
461 bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
462 return(bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET + off));
465 /*---------------------------------------------------------------------------*
466 * avma1pp_probe - probe for a card
467 *---------------------------------------------------------------------------*/
469 avma1pp_pci_probe(dev)
474 vid = pci_get_vendor(dev);
475 did = pci_get_device(dev);
477 if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_DID)) {
478 device_set_desc(dev, "AVM Fritz!Card PCI");
485 /*---------------------------------------------------------------------------*
486 * avma1pp_attach_avma1pp - attach Fritz!Card PCI
487 *---------------------------------------------------------------------------*/
489 avma1pp_attach_avma1pp(device_t dev)
497 bus_space_handle_t bhandle;
498 bus_space_tag_t btag;
499 l1_bchan_state_t *chan;
503 vid = pci_get_vendor(dev);
504 did = pci_get_device(dev);
505 sc = device_get_softc(dev);
506 unit = device_get_unit(dev);
507 bzero(sc, sizeof(struct l1_softc));
509 /* probably not really required */
510 if(unit > IFPI_MAXUNIT) {
511 printf("avma1pp%d: Error, unit > IFPI_MAXUNIT!\n", unit);
516 if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_DID)) {
517 printf("avma1pp%d: unknown device!?\n", unit);
523 sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
524 sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
525 &sc->sc_resources.io_rid[0],
526 0, ~0, 1, RF_ACTIVE);
528 if (sc->sc_resources.io_base[0] == NULL) {
529 printf("avma1pp%d: couldn't map IO port\n", unit);
534 bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
535 btag = rman_get_bustag(sc->sc_resources.io_base[0]);
537 /* Allocate interrupt */
538 sc->sc_resources.irq_rid = 0;
539 sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
540 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
542 if (sc->sc_resources.irq == NULL) {
543 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
544 printf("avma1pp%d: couldn't map interrupt\n", unit);
549 error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET, avma1pp_intr, sc, &ih);
552 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
553 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
554 printf("avma1pp%d: couldn't set up irq\n", unit);
560 /* end of new-bus stuff */
562 ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
564 HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
565 HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
567 /* setup access routines */
570 sc->readreg = avma1pp_read_reg;
571 sc->writereg = avma1pp_write_reg;
573 sc->readfifo = avma1pp_read_fifo;
574 sc->writefifo = avma1pp_write_fifo;
576 /* setup card type */
578 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
580 /* setup IOM bus type */
582 sc->sc_bustyp = BUS_TYPE_IOM2;
584 /* set up some other miscellaneous things */
586 sc->sc_bfifolen = HSCX_FIFO_LEN;
589 /* the Linux driver does this to clear any pending ISAC interrupts */
591 v = ISAC_READ(I_STAR);
592 #ifdef AVMA1PCI_DEBUG
593 printf("avma1pp_attach: I_STAR %x...", v);
595 v = ISAC_READ(I_MODE);
596 #ifdef AVMA1PCI_DEBUG
597 printf("avma1pp_attach: I_MODE %x...", v);
599 v = ISAC_READ(I_ADF2);
600 #ifdef AVMA1PCI_DEBUG
601 printf("avma1pp_attach: I_ADF2 %x...", v);
603 v = ISAC_READ(I_ISTA);
604 #ifdef AVMA1PCI_DEBUG
605 printf("avma1pp_attach: I_ISTA %x...", v);
607 if (v & ISAC_ISTA_EXI)
609 v = ISAC_READ(I_EXIR);
610 #ifdef AVMA1PCI_DEBUG
611 printf("avma1pp_attach: I_EXIR %x...", v);
614 v = ISAC_READ(I_CIRR);
615 #ifdef AVMA1PCI_DEBUG
616 printf("avma1pp_attach: I_CIRR %x...", v);
618 ISAC_WRITE(I_MASK, 0xff);
619 /* the Linux driver does this to clear any pending HSCX interrupts */
620 v = hscx_read_reg_int(0, HSCX_STAT, sc);
621 #ifdef AVMA1PCI_DEBUG
622 printf("avma1pp_attach: 0 HSCX_STAT %x...", v);
624 v = hscx_read_reg_int(1, HSCX_STAT, sc);
625 #ifdef AVMA1PCI_DEBUG
626 printf("avma1pp_attach: 1 HSCX_STAT %x\n", v);
629 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
630 DELAY(SEC_DELAY/100); /* 10 ms */
631 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
632 DELAY(SEC_DELAY/100); /* 10 ms */
633 #ifdef AVMA1PCI_DEBUG
634 bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
635 DELAY(SEC_DELAY/100); /* 10 ms */
636 v = bus_space_read_1(btag, bhandle, STAT1_OFFSET);
637 printf("after reset: S1 %#x\n", v);
639 v = bus_space_read_4(btag, bhandle, 0);
640 printf("avma1pp_attach_avma1pp: v %#x\n", v);
643 /* from here to the end would normally be done in isic_pciattach */
645 printf("ifpi%d: ISAC %s (IOM-%c)\n", unit,
646 "2085 Version A1/A2 or 2086/2186 Version 1.1",
647 sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
652 #if defined (__FreeBSD__) && __FreeBSD__ > 4
653 /* Init the channel mutexes */
654 chan = &sc->sc_chan[HSCX_CH_A];
655 mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp_rx", MTX_DEF);
656 mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp_tx", MTX_DEF);
657 chan = &sc->sc_chan[HSCX_CH_B];
658 mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp_rx", MTX_DEF);
659 mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp_tx", MTX_DEF);
662 /* init the "HSCX" */
663 avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
665 avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
667 /* can't use the normal B-Channel stuff */
668 avma1pp_init_linktab(sc);
670 /* set trace level */
672 sc->sc_trace = TRACE_OFF;
674 sc->sc_state = ISAC_IDLE;
686 sc->sc_freeflag2 = 0;
688 #if defined(__DragonFly__) || (defined(__FreeBSD__) && __FreeBSD__ >=3)
689 callout_handle_init(&sc->sc_T3_callout);
690 callout_handle_init(&sc->sc_T4_callout);
693 /* init higher protocol layers */
695 i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp_l1mux_func);
703 * this is the real interrupt routine
706 avma1pp_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
708 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
712 NDBGL1(L1_H_IRQ, "%#x", stat);
714 if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
717 NDBGL1(L1_H_XFRERR, "xmit data underrun");
718 /* abort the transmission */
720 sc->avma1pp_cmd |= HSCX_CMD_XRS;
721 AVMA1PPSETCMDLONG(param);
722 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
723 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
724 AVMA1PPSETCMDLONG(param);
725 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
727 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
729 i4b_Bfreembuf(chan->out_mbuf_head);
730 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
735 * The following is based on examination of the Linux driver.
737 * The logic here is different than with a "real" HSCX; all kinds
738 * of information (interrupt/status bits) are in stat.
739 * HSCX_INT_RPR indicates a receive interrupt
740 * HSCX_STAT_RDO indicates an overrun condition, abort -
741 * otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
742 * HSCX_STAT_RME indicates end-of-frame and apparently any
743 * CRC/framing errors are only reported in this state.
744 * if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
748 if(stat & HSCX_INT_RPR)
752 /* always have to read the FIFO, so use a scratch buffer */
753 u_char scrbuf[HSCX_FIFO_LEN];
755 if(stat & HSCX_STAT_RDO)
758 NDBGL1(L1_H_XFRERR, "receive data overflow");
763 * check whether we're receiving data for an inactive B-channel
764 * and discard it. This appears to happen for telephony when
765 * both B-channels are active and one is deactivated. Since
766 * it is not really possible to deactivate the channel in that
767 * case (the ASIC seems to deactivate _both_ channels), the
768 * "deactivated" channel keeps receiving data which can lead
769 * to exhaustion of mbufs and a kernel panic.
771 * This is a hack, but it's the only solution I can think of
772 * without having the documentation for the ASIC.
775 if (chan->state == HSCX_IDLE)
777 NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
781 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
783 if(fifo_data_len == 0)
784 fifo_data_len = sc->sc_bfifolen;
786 /* ALWAYS read data from HSCX fifo */
788 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
789 chan->rxcount += fifo_data_len;
791 /* all error conditions checked, now decide and take action */
795 if(chan->in_mbuf == NULL)
797 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
798 panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!\n");
799 chan->in_cbptr = chan->in_mbuf->m_data;
803 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
805 /* OK to copy the data */
806 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
807 chan->in_cbptr += fifo_data_len;
808 chan->in_len += fifo_data_len;
810 /* setup mbuf data length */
812 chan->in_mbuf->m_len = chan->in_len;
813 chan->in_mbuf->m_pkthdr.len = chan->in_len;
815 if(sc->sc_trace & TRACE_B_RX)
818 hdr.unit = L0IFPIUNIT(sc->sc_unit);
819 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
821 hdr.count = ++sc->sc_trace_bcount;
823 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
826 if (stat & HSCX_STAT_RME)
828 if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
830 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
833 /* mark buffer ptr as unused */
835 chan->in_mbuf = NULL;
836 chan->in_cbptr = NULL;
842 NDBGL1(L1_H_XFRERR, "CRC/RAB");
843 if (chan->in_mbuf != NULL)
845 i4b_Bfreembuf(chan->in_mbuf);
846 chan->in_mbuf = NULL;
847 chan->in_cbptr = NULL;
852 } /* END enough space in mbuf */
855 if(chan->bprot == BPROT_NONE)
857 /* setup mbuf data length */
859 chan->in_mbuf->m_len = chan->in_len;
860 chan->in_mbuf->m_pkthdr.len = chan->in_len;
862 if(sc->sc_trace & TRACE_B_RX)
865 hdr.unit = L0IFPIUNIT(sc->sc_unit);
866 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
868 hdr.count = ++sc->sc_trace_bcount;
870 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
873 if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
876 /* move rx'd data to rx queue */
878 #if defined (__FreeBSD__) && __FreeBSD__ > 4
879 (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
881 if(!(IF_QFULL(&chan->rx_queue)))
883 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
887 i4b_Bfreembuf(chan->in_mbuf);
890 /* signal upper layer that data are available */
891 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
893 /* alloc new buffer */
895 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
896 panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!\n");
898 /* setup new data ptr */
900 chan->in_cbptr = chan->in_mbuf->m_data;
902 /* OK to copy the data */
903 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
905 chan->in_cbptr += fifo_data_len;
906 chan->in_len = fifo_data_len;
908 chan->rxcount += fifo_data_len;
912 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
913 chan->in_cbptr = chan->in_mbuf->m_data;
917 } /* if(error == 0) */
920 /* land here for RDO */
921 if (chan->in_mbuf != NULL)
923 i4b_Bfreembuf(chan->in_mbuf);
924 chan->in_mbuf = NULL;
925 chan->in_cbptr = NULL;
929 sc->avma1pp_cmd |= HSCX_CMD_RRS;
930 AVMA1PPSETCMDLONG(param);
931 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
932 sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
933 AVMA1PPSETCMDLONG(param);
934 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
939 /* transmit fifo empty, new data can be written to fifo */
941 if(stat & HSCX_INT_XPR)
944 * for a description what is going on here, please have
945 * a look at isic_bchannel_start() in i4b_bchan.c !
948 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
950 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
952 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
954 if(chan->out_mbuf_head == NULL)
956 chan->state &= ~HSCX_TX_ACTIVE;
957 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
961 chan->state |= HSCX_TX_ACTIVE;
962 chan->out_mbuf_cur = chan->out_mbuf_head;
963 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
964 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
966 if(sc->sc_trace & TRACE_B_TX)
969 hdr.unit = L0IFPIUNIT(sc->sc_unit);
970 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
972 hdr.count = ++sc->sc_trace_bcount;
974 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
977 if(chan->bprot == BPROT_NONE)
979 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
989 avma1pp_hscx_fifo(chan, sc);
992 /* call timeout handling routine */
994 if(activity == ACT_RX || activity == ACT_TX)
995 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
999 * this is the main routine which checks each channel and then calls
1000 * the real interrupt routine as appropriate
1003 avma1pp_hscx_int_handler(struct l1_softc *sc)
1007 /* has to be a u_int because the byte count is in the 2nd byte */
1008 stat = hscx_read_reg_int(0, HSCX_STAT, sc);
1009 if (stat & HSCX_INT_MASK)
1010 avma1pp_hscx_intr(0, stat, sc);
1011 stat = hscx_read_reg_int(1, HSCX_STAT, sc);
1012 if (stat & HSCX_INT_MASK)
1013 avma1pp_hscx_intr(1, stat, sc);
1017 avma1pp_disable(device_t dev)
1019 struct l1_softc *sc = device_get_softc(dev);
1020 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1021 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1023 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
1027 avma1pp_intr(void *xsc)
1030 struct l1_softc *sc;
1031 bus_space_handle_t bhandle;
1032 bus_space_tag_t btag;
1035 bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1036 btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1038 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
1039 NDBGL1(L1_H_IRQ, "stat %x", stat);
1040 /* was there an interrupt from this card ? */
1041 if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1043 /* interrupts are low active */
1044 if (!(stat & ASL_IRQ_TIMER))
1045 NDBGL1(L1_H_IRQ, "timer interrupt ???");
1046 if (!(stat & ASL_IRQ_HSCX))
1048 NDBGL1(L1_H_IRQ, "HSCX");
1049 avma1pp_hscx_int_handler(sc);
1051 if (!(stat & ASL_IRQ_ISAC))
1053 NDBGL1(L1_H_IRQ, "ISAC");
1059 avma1pp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1061 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1064 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1065 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1069 /* only deactivate if both channels are idle */
1070 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1071 sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1075 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1076 sc->avma1pp_prot = HSCX_MODE_TRANS;
1077 AVMA1PPSETCMDLONG(param);
1078 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1081 if(chan->bprot == BPROT_RHDLC)
1083 NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1085 /* HDLC Frames, transparent mode 0 */
1086 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1087 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1088 AVMA1PPSETCMDLONG(param);
1089 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1090 sc->avma1pp_cmd = HSCX_CMD_XRS;
1091 AVMA1PPSETCMDLONG(param);
1092 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1093 sc->avma1pp_cmd = 0;
1097 NDBGL1(L1_BCHAN, "BPROT_NONE??");
1099 /* Raw Telephony, extended transparent mode 1 */
1100 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1101 sc->avma1pp_prot = HSCX_MODE_TRANS;
1102 AVMA1PPSETCMDLONG(param);
1103 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1104 sc->avma1pp_cmd = HSCX_CMD_XRS;
1105 AVMA1PPSETCMDLONG(param);
1106 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1107 sc->avma1pp_cmd = 0;
1112 avma1pp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1114 #if defined(__DragonFly__) || defined(__FreeBSD__)
1115 struct l1_softc *sc = ifpi_scp[unit];
1117 struct l1_softc *sc = isic_find_sc(unit);
1119 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1126 chan->state = HSCX_IDLE;
1127 avma1pp_hscx_init(sc, h_chan, activate);
1130 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1131 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1135 chan->unit = sc->sc_unit; /* unit number */
1136 chan->channel = h_chan; /* B channel */
1137 chan->bprot = bprot; /* B channel protocol */
1138 chan->state = HSCX_IDLE; /* B channel state */
1142 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1144 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1146 chan->rxcount = 0; /* reset rx counter */
1148 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1150 chan->in_mbuf = NULL; /* reset mbuf ptr */
1151 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1152 chan->in_len = 0; /* reset mbuf data len */
1154 /* transmitter part */
1156 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1158 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1160 chan->txcount = 0; /* reset tx counter */
1162 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1164 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1165 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1166 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1167 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1172 avma1pp_hscx_init(sc, h_chan, activate);
1173 chan->state |= HSCX_AVMA1PP_ACTIVE;
1180 avma1pp_bchannel_start(int unit, int h_chan)
1182 #if defined(__DragonFly__) || defined(__FreeBSD__)
1183 struct l1_softc *sc = ifpi_scp[unit];
1185 struct l1_softc *sc = isic_find_sc(unit);
1187 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1191 s = SPLI4B(); /* enter critical section */
1192 if(chan->state & HSCX_TX_ACTIVE) /* already running ? */
1195 return; /* yes, leave */
1198 /* get next mbuf from queue */
1200 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1202 if(chan->out_mbuf_head == NULL) /* queue empty ? */
1204 splx(s); /* leave critical section */
1205 return; /* yes, exit */
1208 /* init current mbuf values */
1210 chan->out_mbuf_cur = chan->out_mbuf_head;
1211 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1212 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1214 /* activity indicator for timeout handling */
1216 if(chan->bprot == BPROT_NONE)
1218 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1226 chan->state |= HSCX_TX_ACTIVE; /* we start transmitting */
1228 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
1230 i4b_trace_hdr_t hdr;
1231 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1232 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1234 hdr.count = ++sc->sc_trace_bcount;
1235 MICROTIME(hdr.time);
1236 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1239 avma1pp_hscx_fifo(chan, sc);
1241 /* call timeout handling routine */
1243 if(activity == ACT_RX || activity == ACT_TX)
1244 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1249 /*---------------------------------------------------------------------------*
1250 * return the address of isic drivers linktab
1251 *---------------------------------------------------------------------------*/
1252 static isdn_link_t *
1253 avma1pp_ret_linktab(int unit, int channel)
1255 #if defined(__DragonFly__) || defined(__FreeBSD__)
1256 struct l1_softc *sc = ifpi_scp[unit];
1258 struct l1_softc *sc = isic_find_sc(unit);
1260 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1262 return(&chan->isic_isdn_linktab);
1265 /*---------------------------------------------------------------------------*
1266 * set the driver linktab in the b channel softc
1267 *---------------------------------------------------------------------------*/
1269 avma1pp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1271 #if defined(__DragonFly__) || defined(__FreeBSD__)
1272 struct l1_softc *sc = ifpi_scp[unit];
1274 struct l1_softc *sc = isic_find_sc(unit);
1276 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1278 chan->isic_drvr_linktab = dlt;
1282 /*---------------------------------------------------------------------------*
1283 * initialize our local linktab
1284 *---------------------------------------------------------------------------*/
1286 avma1pp_init_linktab(struct l1_softc *sc)
1288 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1289 isdn_link_t *lt = &chan->isic_isdn_linktab;
1291 /* make sure the hardware driver is known to layer 4 */
1292 /* avoid overwriting if already set */
1293 if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1295 ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp_set_linktab;
1296 ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp_ret_linktab;
1300 lt->unit = sc->sc_unit;
1301 lt->channel = HSCX_CH_A;
1302 lt->bch_config = avma1pp_bchannel_setup;
1303 lt->bch_tx_start = avma1pp_bchannel_start;
1304 lt->bch_stat = avma1pp_bchannel_stat;
1305 lt->tx_queue = &chan->tx_queue;
1307 /* used by non-HDLC data transfers, i.e. telephony drivers */
1308 lt->rx_queue = &chan->rx_queue;
1310 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1311 lt->rx_mbuf = &chan->in_mbuf;
1313 chan = &sc->sc_chan[HSCX_CH_B];
1314 lt = &chan->isic_isdn_linktab;
1316 lt->unit = sc->sc_unit;
1317 lt->channel = HSCX_CH_B;
1318 lt->bch_config = avma1pp_bchannel_setup;
1319 lt->bch_tx_start = avma1pp_bchannel_start;
1320 lt->bch_stat = avma1pp_bchannel_stat;
1321 lt->tx_queue = &chan->tx_queue;
1323 /* used by non-HDLC data transfers, i.e. telephony drivers */
1324 lt->rx_queue = &chan->rx_queue;
1326 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1327 lt->rx_mbuf = &chan->in_mbuf;
1331 * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1334 avma1pp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1336 #if defined(__DragonFly__) || defined(__FreeBSD__)
1337 struct l1_softc *sc = ifpi_scp[unit];
1339 struct l1_softc *sc = isic_find_sc(unit);
1341 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1346 bsp->outbytes = chan->txcount;
1347 bsp->inbytes = chan->rxcount;
1355 /*---------------------------------------------------------------------------*
1356 * fill HSCX fifo with data from the current mbuf
1357 * Put this here until it can go into i4b_hscx.c
1358 *---------------------------------------------------------------------------*/
1360 avma1pp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1366 /* using a scratch buffer simplifies writing to the FIFO */
1367 u_char scrbuf[HSCX_FIFO_LEN];
1372 * fill the HSCX tx fifo with data from the current mbuf. if
1373 * current mbuf holds less data than HSCX fifo length, try to
1374 * get the next mbuf from (a possible) mbuf chain. if there is
1375 * not enough data in a single mbuf or in a chain, then this
1376 * is the last mbuf and we tell the HSCX that it has to send
1377 * CRC and closing flag
1380 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1382 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1385 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1386 chan->out_mbuf_head,
1388 chan->out_mbuf_cur_ptr,
1389 chan->out_mbuf_cur_len,
1394 cmd |= HSCX_CMDR_XTF;
1395 /* collect the data in the scratch buffer */
1396 for (i = 0; i < nextlen; i++)
1397 scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1400 chan->txcount += nextlen;
1402 chan->out_mbuf_cur_ptr += nextlen;
1403 chan->out_mbuf_cur_len -= nextlen;
1405 if(chan->out_mbuf_cur_len == 0)
1407 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1409 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1410 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1412 if(sc->sc_trace & TRACE_B_TX)
1414 i4b_trace_hdr_t hdr;
1415 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1416 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1418 hdr.count = ++sc->sc_trace_bcount;
1419 MICROTIME(hdr.time);
1420 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1425 if (chan->bprot != BPROT_NONE)
1426 cmd |= HSCX_CMDR_XME;
1427 i4b_Bfreembuf(chan->out_mbuf_head);
1428 chan->out_mbuf_head = NULL;
1432 /* write what we have from the scratch buf to the HSCX fifo */
1434 HSCX_WRFIFO(chan->channel, scrbuf, len);
1438 /*---------------------------------------------------------------------------*
1439 * ifpi - ISAC interrupt routine
1440 *---------------------------------------------------------------------------*/
1442 ifpi_isac_intr(struct l1_softc *sc)
1444 u_char isac_irq_stat;
1448 /* get isac irq status */
1449 isac_irq_stat = ISAC_READ(I_ISTA);
1452 ifpi_isac_irq(sc, isac_irq_stat); /* isac handler */
1457 ISAC_WRITE(I_MASK, 0xff);
1461 ISAC_WRITE(I_MASK, ISAC_IMASK);
1464 /*---------------------------------------------------------------------------*
1465 * ifpi_recover - try to recover from irq lockup
1466 *---------------------------------------------------------------------------*/
1468 ifpi_recover(struct l1_softc *sc)
1472 /* get isac irq status */
1474 byte = ISAC_READ(I_ISTA);
1476 NDBGL1(L1_ERROR, " ISAC: ISTA = 0x%x", byte);
1478 if(byte & ISAC_ISTA_EXI)
1479 NDBGL1(L1_ERROR, " ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1481 if(byte & ISAC_ISTA_CISQ)
1483 byte = ISAC_READ(I_CIRR);
1485 NDBGL1(L1_ERROR, " ISAC: CISQ = 0x%x", byte);
1487 if(byte & ISAC_CIRR_SQC)
1488 NDBGL1(L1_ERROR, " ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1491 NDBGL1(L1_ERROR, " ISAC: IMASK = 0x%x", ISAC_IMASK);
1493 ISAC_WRITE(I_MASK, 0xff);
1495 ISAC_WRITE(I_MASK, ISAC_IMASK);
1499 #endif /* NIFPI > 0 */