2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.8 2004/03/14 15:36:50 joerg Exp $
36 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
41 * documentation not available, but ask me nicely.
43 * Written by Bill Paul <william.paul@windriver.com>
48 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
49 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
50 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
51 * are three supported methods for data transfer between host and
52 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
53 * Propulsion Technology (tm) DMA. The latter mechanism is a form
54 * of double buffer DMA where the packet data is copied to a
55 * pre-allocated DMA buffer who's physical address has been loaded
56 * into a table at device initialization time. The rationale is that
57 * the virtual to physical address translation needed for normal
58 * scatter/gather DMA is more expensive than the data copy needed
59 * for double buffering. This may be true in Windows NT and the like,
60 * but it isn't true for us, at least on the x86 arch. This driver
61 * uses the scatter/gather I/O method for both TX and RX.
63 * The LXT1001 only supports TCP/IP checksum offload on receive.
64 * Also, the VLAN tagging is done using a 16-entry table which allows
65 * the chip to perform hardware filtering based on VLAN tags. Sadly,
66 * our vlan support doesn't currently play well with this kind of
70 * - Jeff James at Intel, for arranging to have the LXT1001 manual
71 * released (at long last)
72 * - Beny Chen at D-Link, for actually sending it to me
73 * - Brad Short and Keith Alexis at SMC, for sending me sample
74 * SMC9462SX and SMC9462TX adapters for testing
75 * - Paul Saab at Y!, for not killing me (though it remains to be seen
76 * if in fact he did me much of a favor)
79 #include <sys/param.h>
80 #include <sys/systm.h>
81 #include <sys/sockio.h>
83 #include <sys/malloc.h>
84 #include <sys/kernel.h>
85 #include <sys/socket.h>
88 #include <net/if_arp.h>
89 #include <net/ethernet.h>
90 #include <net/if_dl.h>
91 #include <net/if_media.h>
95 #include <vm/vm.h> /* for vtophys */
96 #include <vm/pmap.h> /* for vtophys */
97 #include <machine/clock.h> /* for DELAY */
98 #include <machine/bus_pio.h>
99 #include <machine/bus_memio.h>
100 #include <machine/bus.h>
101 #include <machine/resource.h>
103 #include <sys/rman.h>
105 #include "../mii_layer/mii.h"
106 #include "../mii_layer/miivar.h"
108 #include <bus/pci/pcireg.h>
109 #include <bus/pci/pcivar.h>
111 #define LGE_USEIOSPACE
113 #include "if_lgereg.h"
115 /* "controller miibus0" required. See GENERIC if you get errors here. */
116 #include "miibus_if.h"
119 * Various supported device vendors/types and their names.
121 static struct lge_type lge_devs[] = {
122 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
126 static int lge_probe (device_t);
127 static int lge_attach (device_t);
128 static int lge_detach (device_t);
130 static int lge_alloc_jumbo_mem (struct lge_softc *);
131 static void lge_free_jumbo_mem (struct lge_softc *);
132 static void *lge_jalloc (struct lge_softc *);
133 static void lge_jfree (caddr_t, u_int);
134 static void lge_jref (caddr_t, u_int);
136 static int lge_newbuf (struct lge_softc *,
137 struct lge_rx_desc *,
139 static int lge_encap (struct lge_softc *,
140 struct mbuf *, u_int32_t *);
141 static void lge_rxeof (struct lge_softc *, int);
142 static void lge_rxeoc (struct lge_softc *);
143 static void lge_txeof (struct lge_softc *);
144 static void lge_intr (void *);
145 static void lge_tick (void *);
146 static void lge_start (struct ifnet *);
147 static int lge_ioctl (struct ifnet *, u_long, caddr_t);
148 static void lge_init (void *);
149 static void lge_stop (struct lge_softc *);
150 static void lge_watchdog (struct ifnet *);
151 static void lge_shutdown (device_t);
152 static int lge_ifmedia_upd (struct ifnet *);
153 static void lge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
155 static void lge_eeprom_getword (struct lge_softc *, int, u_int16_t *);
156 static void lge_read_eeprom (struct lge_softc *, caddr_t, int,
159 static int lge_miibus_readreg (device_t, int, int);
160 static int lge_miibus_writereg (device_t, int, int, int);
161 static void lge_miibus_statchg (device_t);
163 static void lge_setmulti (struct lge_softc *);
164 static u_int32_t lge_crc (struct lge_softc *, caddr_t);
165 static void lge_reset (struct lge_softc *);
166 static int lge_list_rx_init (struct lge_softc *);
167 static int lge_list_tx_init (struct lge_softc *);
169 #ifdef LGE_USEIOSPACE
170 #define LGE_RES SYS_RES_IOPORT
171 #define LGE_RID LGE_PCI_LOIO
173 #define LGE_RES SYS_RES_MEMORY
174 #define LGE_RID LGE_PCI_LOMEM
177 static device_method_t lge_methods[] = {
178 /* Device interface */
179 DEVMETHOD(device_probe, lge_probe),
180 DEVMETHOD(device_attach, lge_attach),
181 DEVMETHOD(device_detach, lge_detach),
182 DEVMETHOD(device_shutdown, lge_shutdown),
185 DEVMETHOD(bus_print_child, bus_generic_print_child),
186 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
189 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
190 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
191 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
196 static driver_t lge_driver = {
199 sizeof(struct lge_softc)
202 static devclass_t lge_devclass;
204 DECLARE_DUMMY_MODULE(if_lge);
205 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
206 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
208 #define LGE_SETBIT(sc, reg, x) \
209 CSR_WRITE_4(sc, reg, \
210 CSR_READ_4(sc, reg) | (x))
212 #define LGE_CLRBIT(sc, reg, x) \
213 CSR_WRITE_4(sc, reg, \
214 CSR_READ_4(sc, reg) & ~(x))
217 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
220 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
223 * Read a word of data stored in the EEPROM at address 'addr.'
225 static void lge_eeprom_getword(sc, addr, dest)
226 struct lge_softc *sc;
233 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
234 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
236 for (i = 0; i < LGE_TIMEOUT; i++)
237 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
240 if (i == LGE_TIMEOUT) {
241 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
245 val = CSR_READ_4(sc, LGE_EEDATA);
248 *dest = (val >> 16) & 0xFFFF;
250 *dest = val & 0xFFFF;
256 * Read a sequence of words from the EEPROM.
258 static void lge_read_eeprom(sc, dest, off, cnt, swap)
259 struct lge_softc *sc;
266 u_int16_t word = 0, *ptr;
268 for (i = 0; i < cnt; i++) {
269 lge_eeprom_getword(sc, off + i, &word);
270 ptr = (u_int16_t *)(dest + (i * 2));
280 static int lge_miibus_readreg(dev, phy, reg)
284 struct lge_softc *sc;
287 sc = device_get_softc(dev);
290 * If we have a non-PCS PHY, pretend that the internal
291 * autoneg stuff at PHY address 0 isn't there so that
292 * the miibus code will find only the GMII PHY.
294 if (sc->lge_pcs == 0 && phy == 0)
297 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
299 for (i = 0; i < LGE_TIMEOUT; i++)
300 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
303 if (i == LGE_TIMEOUT) {
304 printf("lge%d: PHY read timed out\n", sc->lge_unit);
308 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
311 static int lge_miibus_writereg(dev, phy, reg, data)
315 struct lge_softc *sc;
318 sc = device_get_softc(dev);
320 CSR_WRITE_4(sc, LGE_GMIICTL,
321 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
323 for (i = 0; i < LGE_TIMEOUT; i++)
324 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
327 if (i == LGE_TIMEOUT) {
328 printf("lge%d: PHY write timed out\n", sc->lge_unit);
335 static void lge_miibus_statchg(dev)
338 struct lge_softc *sc;
339 struct mii_data *mii;
341 sc = device_get_softc(dev);
342 mii = device_get_softc(sc->lge_miibus);
344 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
345 switch (IFM_SUBTYPE(mii->mii_media_active)) {
348 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
351 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
358 * Choose something, even if it's wrong. Clearing
359 * all the bits will hose autoneg on the internal
362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
366 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
367 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
369 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
375 static u_int32_t lge_crc(sc, addr)
376 struct lge_softc *sc;
379 u_int32_t crc, carry;
383 /* Compute CRC for the address value. */
384 crc = 0xFFFFFFFF; /* initial value */
386 for (i = 0; i < 6; i++) {
388 for (j = 0; j < 8; j++) {
389 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
393 crc = (crc ^ 0x04c11db6) | carry;
398 * return the filter bit position
400 return((crc >> 26) & 0x0000003F);
403 static void lge_setmulti(sc)
404 struct lge_softc *sc;
407 struct ifmultiaddr *ifma;
408 u_int32_t h = 0, hashes[2] = { 0, 0 };
410 ifp = &sc->arpcom.ac_if;
412 /* Make sure multicast hash table is enabled. */
413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
415 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
416 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
417 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
421 /* first, zot all the existing hash bits */
422 CSR_WRITE_4(sc, LGE_MAR0, 0);
423 CSR_WRITE_4(sc, LGE_MAR1, 0);
425 /* now program new ones */
426 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
427 ifma = ifma->ifma_link.le_next) {
428 if (ifma->ifma_addr->sa_family != AF_LINK)
430 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
432 hashes[0] |= (1 << h);
434 hashes[1] |= (1 << (h - 32));
437 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
438 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
443 static void lge_reset(sc)
444 struct lge_softc *sc;
448 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
450 for (i = 0; i < LGE_TIMEOUT; i++) {
451 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
455 if (i == LGE_TIMEOUT)
456 printf("lge%d: reset never completed\n", sc->lge_unit);
458 /* Wait a little while for the chip to get its brains in order. */
465 * Probe for a Level 1 chip. Check the PCI vendor and device
466 * IDs against our list and return a device name if we find a match.
468 static int lge_probe(dev)
475 while(t->lge_name != NULL) {
476 if ((pci_get_vendor(dev) == t->lge_vid) &&
477 (pci_get_device(dev) == t->lge_did)) {
478 device_set_desc(dev, t->lge_name);
488 * Attach the interface. Allocate softc structures, do ifmedia
489 * setup and ethernet/BPF attach.
491 static int lge_attach(dev)
495 u_char eaddr[ETHER_ADDR_LEN];
497 struct lge_softc *sc;
499 int unit, error = 0, rid;
503 sc = device_get_softc(dev);
504 unit = device_get_unit(dev);
505 bzero(sc, sizeof(struct lge_softc));
508 * Handle power management nonsense.
510 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF;
511 if (command == 0x01) {
513 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4);
514 if (command & LGE_PSTATE_MASK) {
515 u_int32_t iobase, membase, irq;
517 /* Save important PCI config data. */
518 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
519 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
520 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
522 /* Reset the power state. */
523 printf("lge%d: chip is in D%d power mode "
524 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK);
525 command &= 0xFFFFFFFC;
526 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4);
528 /* Restore PCI config data. */
529 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
530 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
531 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
536 * Map control/status registers.
538 command = pci_read_config(dev, PCIR_COMMAND, 4);
539 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
540 pci_write_config(dev, PCIR_COMMAND, command, 4);
541 command = pci_read_config(dev, PCIR_COMMAND, 4);
543 #ifdef LGE_USEIOSPACE
544 if (!(command & PCIM_CMD_PORTEN)) {
545 printf("lge%d: failed to enable I/O ports!\n", unit);
550 if (!(command & PCIM_CMD_MEMEN)) {
551 printf("lge%d: failed to enable memory mapping!\n", unit);
558 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
559 0, ~0, 1, RF_ACTIVE);
561 if (sc->lge_res == NULL) {
562 printf("lge%d: couldn't map ports/memory\n", unit);
567 sc->lge_btag = rman_get_bustag(sc->lge_res);
568 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
570 /* Allocate interrupt */
572 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
573 RF_SHAREABLE | RF_ACTIVE);
575 if (sc->lge_irq == NULL) {
576 printf("lge%d: couldn't map interrupt\n", unit);
577 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
582 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
583 lge_intr, sc, &sc->lge_intrhand);
586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
587 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
588 printf("lge%d: couldn't set up irq\n", unit);
592 /* Reset the adapter. */
596 * Get station address from the EEPROM.
598 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
599 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
600 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
603 * A Level 1 chip was detected. Inform the world.
605 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":");
608 callout_handle_init(&sc->lge_stat_ch);
610 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
611 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
613 if (sc->lge_ldata == NULL) {
614 printf("lge%d: no memory for list buffers!\n", unit);
615 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
617 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
621 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
623 /* Try to allocate memory for jumbo buffers. */
624 if (lge_alloc_jumbo_mem(sc)) {
625 printf("lge%d: jumbo buffer allocation failed\n",
627 contigfree(sc->lge_ldata,
628 sizeof(struct lge_list_data), M_DEVBUF);
629 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
630 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
631 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
636 ifp = &sc->arpcom.ac_if;
638 if_initname(ifp, "lge", unit);
639 ifp->if_mtu = ETHERMTU;
640 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
641 ifp->if_ioctl = lge_ioctl;
642 ifp->if_output = ether_output;
643 ifp->if_start = lge_start;
644 ifp->if_watchdog = lge_watchdog;
645 ifp->if_init = lge_init;
646 ifp->if_baudrate = 1000000000;
647 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
648 ifp->if_capabilities = IFCAP_RXCSUM;
649 ifp->if_capenable = ifp->if_capabilities;
651 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
659 if (mii_phy_probe(dev, &sc->lge_miibus,
660 lge_ifmedia_upd, lge_ifmedia_sts)) {
661 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
662 contigfree(sc->lge_ldata,
663 sizeof(struct lge_list_data), M_DEVBUF);
664 lge_free_jumbo_mem(sc);
665 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
666 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
667 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
673 * Call MI attach routine.
675 ether_ifattach(ifp, eaddr);
676 callout_handle_init(&sc->lge_stat_ch);
683 static int lge_detach(dev)
686 struct lge_softc *sc;
692 sc = device_get_softc(dev);
693 ifp = &sc->arpcom.ac_if;
699 bus_generic_detach(dev);
700 device_delete_child(dev, sc->lge_miibus);
702 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
703 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
704 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
706 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
707 lge_free_jumbo_mem(sc);
715 * Initialize the transmit descriptors.
717 static int lge_list_tx_init(sc)
718 struct lge_softc *sc;
720 struct lge_list_data *ld;
721 struct lge_ring_data *cd;
726 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
727 ld->lge_tx_list[i].lge_mbuf = NULL;
728 ld->lge_tx_list[i].lge_ctl = 0;
731 cd->lge_tx_prod = cd->lge_tx_cons = 0;
738 * Initialize the RX descriptors and allocate mbufs for them. Note that
739 * we arralge the descriptors in a closed ring, so that the last descriptor
740 * points back to the first.
742 static int lge_list_rx_init(sc)
743 struct lge_softc *sc;
745 struct lge_list_data *ld;
746 struct lge_ring_data *cd;
752 cd->lge_rx_prod = cd->lge_rx_cons = 0;
754 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
756 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
757 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
759 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
763 /* Clear possible 'rx command queue empty' interrupt. */
764 CSR_READ_4(sc, LGE_ISR);
770 * Initialize an RX descriptor and attach an MBUF cluster.
772 static int lge_newbuf(sc, c, m)
773 struct lge_softc *sc;
774 struct lge_rx_desc *c;
777 struct mbuf *m_new = NULL;
781 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
783 printf("lge%d: no memory for rx list "
784 "-- packet dropped!\n", sc->lge_unit);
788 /* Allocate the jumbo buffer */
789 buf = lge_jalloc(sc);
792 printf("lge%d: jumbo allocation failed "
793 "-- packet dropped!\n", sc->lge_unit);
798 /* Attach the buffer to the mbuf */
799 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
800 m_new->m_flags |= M_EXT;
801 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
802 m_new->m_len = LGE_MCLBYTES;
803 m_new->m_ext.ext_free = lge_jfree;
804 m_new->m_ext.ext_ref = lge_jref;
807 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES;
808 m_new->m_data = m_new->m_ext.ext_buf;
812 * Adjust alignment so packet payload begins on a
813 * longword boundary. Mandatory for Alpha, useful on
816 m_adj(m_new, ETHER_ALIGN);
819 c->lge_fragptr_hi = 0;
820 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
821 c->lge_fraglen = m_new->m_len;
822 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
826 * Put this buffer in the RX command FIFO. To do this,
827 * we just write the physical address of the descriptor
828 * into the RX descriptor address registers. Note that
829 * there are two registers, one high DWORD and one low
830 * DWORD, which lets us specify a 64-bit address if
831 * desired. We only use a 32-bit address for now.
832 * Writing to the low DWORD register is what actually
833 * causes the command to be issued, so we do that
836 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
837 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
842 static int lge_alloc_jumbo_mem(sc)
843 struct lge_softc *sc;
847 struct lge_jpool_entry *entry;
849 /* Grab a big chunk o' storage. */
850 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
851 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
853 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
854 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
858 SLIST_INIT(&sc->lge_jfree_listhead);
859 SLIST_INIT(&sc->lge_jinuse_listhead);
862 * Now divide it up into 9K pieces and save the addresses
865 ptr = sc->lge_cdata.lge_jumbo_buf;
866 for (i = 0; i < LGE_JSLOTS; i++) {
868 aptr = (u_int64_t **)ptr;
869 aptr[0] = (u_int64_t *)sc;
870 ptr += sizeof(u_int64_t);
871 sc->lge_cdata.lge_jslots[i].lge_buf = ptr;
872 sc->lge_cdata.lge_jslots[i].lge_inuse = 0;
874 entry = malloc(sizeof(struct lge_jpool_entry),
877 printf("lge%d: no memory for jumbo "
878 "buffer queue!\n", sc->lge_unit);
882 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
883 entry, jpool_entries);
889 static void lge_free_jumbo_mem(sc)
890 struct lge_softc *sc;
893 struct lge_jpool_entry *entry;
895 for (i = 0; i < LGE_JSLOTS; i++) {
896 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
897 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
898 free(entry, M_DEVBUF);
901 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
907 * Allocate a jumbo buffer.
909 static void *lge_jalloc(sc)
910 struct lge_softc *sc;
912 struct lge_jpool_entry *entry;
914 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
918 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
923 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
924 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
925 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1;
926 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf);
930 * Adjust usage count on a jumbo buffer. In general this doesn't
931 * get used much because our jumbo buffers don't get passed around
932 * a lot, but it's implemented for correctness.
934 static void lge_jref(buf, size)
938 struct lge_softc *sc;
942 /* Extract the softc struct pointer. */
943 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
944 sc = (struct lge_softc *)(aptr[0]);
947 panic("lge_jref: can't find softc pointer!");
949 if (size != LGE_MCLBYTES)
950 panic("lge_jref: adjusting refcount of buf of wrong size!");
952 /* calculate the slot this buffer belongs to */
954 i = ((vm_offset_t)aptr
955 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
957 if ((i < 0) || (i >= LGE_JSLOTS))
958 panic("lge_jref: asked to reference buffer "
959 "that we don't manage!");
960 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
961 panic("lge_jref: buffer already free!");
963 sc->lge_cdata.lge_jslots[i].lge_inuse++;
969 * Release a jumbo buffer.
971 static void lge_jfree(buf, size)
975 struct lge_softc *sc;
978 struct lge_jpool_entry *entry;
980 /* Extract the softc struct pointer. */
981 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
982 sc = (struct lge_softc *)(aptr[0]);
985 panic("lge_jfree: can't find softc pointer!");
987 if (size != LGE_MCLBYTES)
988 panic("lge_jfree: freeing buffer of wrong size!");
990 /* calculate the slot this buffer belongs to */
991 i = ((vm_offset_t)aptr
992 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
994 if ((i < 0) || (i >= LGE_JSLOTS))
995 panic("lge_jfree: asked to free buffer that we don't manage!");
996 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
997 panic("lge_jfree: buffer already free!");
999 sc->lge_cdata.lge_jslots[i].lge_inuse--;
1000 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) {
1001 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
1003 panic("lge_jfree: buffer not in use!");
1005 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead,
1007 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
1008 entry, jpool_entries);
1016 * A frame has been uploaded: pass the resulting mbuf chain up to
1017 * the higher level protocols.
1019 static void lge_rxeof(sc, cnt)
1020 struct lge_softc *sc;
1023 struct ether_header *eh;
1026 struct lge_rx_desc *cur_rx;
1027 int c, i, total_len = 0;
1028 u_int32_t rxsts, rxctl;
1030 ifp = &sc->arpcom.ac_if;
1032 /* Find out how many frames were processed. */
1034 i = sc->lge_cdata.lge_rx_cons;
1038 struct mbuf *m0 = NULL;
1040 cur_rx = &sc->lge_ldata->lge_rx_list[i];
1041 rxctl = cur_rx->lge_ctl;
1042 rxsts = cur_rx->lge_sts;
1043 m = cur_rx->lge_mbuf;
1044 cur_rx->lge_mbuf = NULL;
1045 total_len = LGE_RXBYTES(cur_rx);
1046 LGE_INC(i, LGE_RX_LIST_CNT);
1050 * If an error occurs, update stats, clear the
1051 * status word and leave the mbuf cluster in place:
1052 * it should simply get re-used next time this descriptor
1053 * comes up in the ring.
1055 if (rxctl & LGE_RXCTL_ERRMASK) {
1057 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1061 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
1062 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1063 total_len + ETHER_ALIGN, 0, ifp, NULL);
1064 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1066 printf("lge%d: no receive buffers "
1067 "available -- packet dropped!\n",
1072 m_adj(m0, ETHER_ALIGN);
1075 m->m_pkthdr.rcvif = ifp;
1076 m->m_pkthdr.len = m->m_len = total_len;
1080 eh = mtod(m, struct ether_header *);
1082 /* Remove header from mbuf and pass it on. */
1083 m_adj(m, sizeof(struct ether_header));
1085 /* Do IP checksum checking. */
1086 if (rxsts & LGE_RXSTS_ISIP)
1087 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1088 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1089 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1090 if ((rxsts & LGE_RXSTS_ISTCP &&
1091 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1092 (rxsts & LGE_RXSTS_ISUDP &&
1093 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1094 m->m_pkthdr.csum_flags |=
1095 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1096 m->m_pkthdr.csum_data = 0xffff;
1099 ether_input(ifp, eh, m);
1102 sc->lge_cdata.lge_rx_cons = i;
1108 struct lge_softc *sc;
1112 ifp = &sc->arpcom.ac_if;
1113 ifp->if_flags &= ~IFF_RUNNING;
1119 * A frame was downloaded to the chip. It's safe for us to clean up
1123 static void lge_txeof(sc)
1124 struct lge_softc *sc;
1126 struct lge_tx_desc *cur_tx = NULL;
1128 u_int32_t idx, txdone;
1130 ifp = &sc->arpcom.ac_if;
1132 /* Clear the timeout timer. */
1136 * Go through our tx list and free mbufs for those
1137 * frames that have been transmitted.
1139 idx = sc->lge_cdata.lge_tx_cons;
1140 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1142 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1143 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1146 if (cur_tx->lge_mbuf != NULL) {
1147 m_freem(cur_tx->lge_mbuf);
1148 cur_tx->lge_mbuf = NULL;
1150 cur_tx->lge_ctl = 0;
1153 LGE_INC(idx, LGE_TX_LIST_CNT);
1157 sc->lge_cdata.lge_tx_cons = idx;
1160 ifp->if_flags &= ~IFF_OACTIVE;
1165 static void lge_tick(xsc)
1168 struct lge_softc *sc;
1169 struct mii_data *mii;
1176 ifp = &sc->arpcom.ac_if;
1178 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1179 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1180 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1181 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1183 if (!sc->lge_link) {
1184 mii = device_get_softc(sc->lge_miibus);
1187 if (mii->mii_media_status & IFM_ACTIVE &&
1188 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1190 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1191 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX)
1192 printf("lge%d: gigabit link up\n",
1194 if (ifp->if_snd.ifq_head != NULL)
1199 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1206 static void lge_intr(arg)
1209 struct lge_softc *sc;
1214 ifp = &sc->arpcom.ac_if;
1216 /* Supress unwanted interrupts */
1217 if (!(ifp->if_flags & IFF_UP)) {
1224 * Reading the ISR register clears all interrupts, and
1225 * clears the 'interrupts enabled' bit in the IMR
1228 status = CSR_READ_4(sc, LGE_ISR);
1230 if ((status & LGE_INTRS) == 0)
1233 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1236 if (status & LGE_ISR_RXDMA_DONE)
1237 lge_rxeof(sc, LGE_RX_DMACNT(status));
1239 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1242 if (status & LGE_ISR_PHY_INTR) {
1244 untimeout(lge_tick, sc, sc->lge_stat_ch);
1249 /* Re-enable interrupts. */
1250 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1252 if (ifp->if_snd.ifq_head != NULL)
1259 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1260 * pointers to the fragment pointers.
1262 static int lge_encap(sc, m_head, txidx)
1263 struct lge_softc *sc;
1264 struct mbuf *m_head;
1267 struct lge_frag *f = NULL;
1268 struct lge_tx_desc *cur_tx;
1270 int frag = 0, tot_len = 0;
1273 * Start packing the mbufs in this chain into
1274 * the fragment pointers. Stop when we run out
1275 * of fragments or hit the end of the mbuf chain.
1278 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1281 for (m = m_head; m != NULL; m = m->m_next) {
1282 if (m->m_len != 0) {
1283 tot_len += m->m_len;
1284 f = &cur_tx->lge_frags[frag];
1285 f->lge_fraglen = m->m_len;
1286 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1287 f->lge_fragptr_hi = 0;
1295 cur_tx->lge_mbuf = m_head;
1296 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1297 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1299 /* Queue for transmit */
1300 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1306 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1307 * to the mbuf data regions directly in the transmit lists. We also save a
1308 * copy of the pointers since the transmit list fragment pointers are
1309 * physical addresses.
1312 static void lge_start(ifp)
1315 struct lge_softc *sc;
1316 struct mbuf *m_head = NULL;
1324 idx = sc->lge_cdata.lge_tx_prod;
1326 if (ifp->if_flags & IFF_OACTIVE)
1329 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1330 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1333 IF_DEQUEUE(&ifp->if_snd, m_head);
1337 if (lge_encap(sc, m_head, &idx)) {
1338 IF_PREPEND(&ifp->if_snd, m_head);
1339 ifp->if_flags |= IFF_OACTIVE;
1344 * If there's a BPF listener, bounce a copy of this frame
1348 bpf_mtap(ifp, m_head);
1351 sc->lge_cdata.lge_tx_prod = idx;
1354 * Set a timeout in case the chip goes out to lunch.
1361 static void lge_init(xsc)
1364 struct lge_softc *sc = xsc;
1365 struct ifnet *ifp = &sc->arpcom.ac_if;
1366 struct mii_data *mii;
1369 if (ifp->if_flags & IFF_RUNNING)
1375 * Cancel pending I/O and free all RX/TX buffers.
1380 mii = device_get_softc(sc->lge_miibus);
1382 /* Set MAC address */
1383 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1384 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1386 /* Init circular RX list. */
1387 if (lge_list_rx_init(sc) == ENOBUFS) {
1388 printf("lge%d: initialization failed: no "
1389 "memory for rx buffers\n", sc->lge_unit);
1396 * Init tx descriptors.
1398 lge_list_tx_init(sc);
1400 /* Set initial value for MODE1 register. */
1401 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1402 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1403 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1404 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1406 /* If we want promiscuous mode, set the allframes bit. */
1407 if (ifp->if_flags & IFF_PROMISC) {
1408 CSR_WRITE_4(sc, LGE_MODE1,
1409 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1411 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1415 * Set the capture broadcast bit to capture broadcast frames.
1417 if (ifp->if_flags & IFF_BROADCAST) {
1418 CSR_WRITE_4(sc, LGE_MODE1,
1419 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1421 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1424 /* Packet padding workaround? */
1425 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1427 /* No error frames */
1428 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1430 /* Receive large frames */
1431 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1433 /* Workaround: disable RX/TX flow control */
1434 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1435 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1437 /* Make sure to strip CRC from received frames */
1438 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1440 /* Turn off magic packet mode */
1441 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1443 /* Turn off all VLAN stuff */
1444 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1445 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1447 /* Workarond: FIFO overflow */
1448 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1449 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1452 * Load the multicast filter.
1457 * Enable hardware checksum validation for all received IPv4
1458 * packets, do not reject packets with bad checksums.
1460 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1461 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1462 LGE_MODE2_RX_ERRCSUM);
1465 * Enable the delivery of PHY interrupts based on
1466 * link/speed/duplex status chalges.
1468 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1470 /* Enable receiver and transmitter. */
1471 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1472 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1474 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1475 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1478 * Enable interrupts.
1480 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1481 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1483 lge_ifmedia_upd(ifp);
1485 ifp->if_flags |= IFF_RUNNING;
1486 ifp->if_flags &= ~IFF_OACTIVE;
1490 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1496 * Set media options.
1498 static int lge_ifmedia_upd(ifp)
1501 struct lge_softc *sc;
1502 struct mii_data *mii;
1506 mii = device_get_softc(sc->lge_miibus);
1508 if (mii->mii_instance) {
1509 struct mii_softc *miisc;
1510 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1511 miisc = LIST_NEXT(miisc, mii_list))
1512 mii_phy_reset(miisc);
1520 * Report current media status.
1522 static void lge_ifmedia_sts(ifp, ifmr)
1524 struct ifmediareq *ifmr;
1526 struct lge_softc *sc;
1527 struct mii_data *mii;
1531 mii = device_get_softc(sc->lge_miibus);
1533 ifmr->ifm_active = mii->mii_media_active;
1534 ifmr->ifm_status = mii->mii_media_status;
1539 static int lge_ioctl(ifp, command, data)
1544 struct lge_softc *sc = ifp->if_softc;
1545 struct ifreq *ifr = (struct ifreq *) data;
1546 struct mii_data *mii;
1554 error = ether_ioctl(ifp, command, data);
1557 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1560 ifp->if_mtu = ifr->ifr_mtu;
1563 if (ifp->if_flags & IFF_UP) {
1564 if (ifp->if_flags & IFF_RUNNING &&
1565 ifp->if_flags & IFF_PROMISC &&
1566 !(sc->lge_if_flags & IFF_PROMISC)) {
1567 CSR_WRITE_4(sc, LGE_MODE1,
1568 LGE_MODE1_SETRST_CTL1|
1569 LGE_MODE1_RX_PROMISC);
1570 } else if (ifp->if_flags & IFF_RUNNING &&
1571 !(ifp->if_flags & IFF_PROMISC) &&
1572 sc->lge_if_flags & IFF_PROMISC) {
1573 CSR_WRITE_4(sc, LGE_MODE1,
1574 LGE_MODE1_RX_PROMISC);
1576 ifp->if_flags &= ~IFF_RUNNING;
1580 if (ifp->if_flags & IFF_RUNNING)
1583 sc->lge_if_flags = ifp->if_flags;
1593 mii = device_get_softc(sc->lge_miibus);
1594 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1606 static void lge_watchdog(ifp)
1609 struct lge_softc *sc;
1614 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1618 ifp->if_flags &= ~IFF_RUNNING;
1621 if (ifp->if_snd.ifq_head != NULL)
1628 * Stop the adapter and free any mbufs allocated to the
1631 static void lge_stop(sc)
1632 struct lge_softc *sc;
1637 ifp = &sc->arpcom.ac_if;
1639 untimeout(lge_tick, sc, sc->lge_stat_ch);
1640 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1642 /* Disable receiver and transmitter. */
1643 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1647 * Free data in the RX lists.
1649 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1650 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1651 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1652 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1655 bzero((char *)&sc->lge_ldata->lge_rx_list,
1656 sizeof(sc->lge_ldata->lge_rx_list));
1659 * Free the TX list buffers.
1661 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1662 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1663 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1664 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1668 bzero((char *)&sc->lge_ldata->lge_tx_list,
1669 sizeof(sc->lge_ldata->lge_tx_list));
1671 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1677 * Stop all chip I/O so that the kernel's probe routines don't
1678 * get confused by errant DMAs when rebooting.
1680 static void lge_shutdown(dev)
1683 struct lge_softc *sc;
1685 sc = device_get_softc(dev);