1 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
35 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.26 2005/02/21 18:40:37 joerg Exp $
39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
41 * Permission to use, copy, modify, and distribute this software for any
42 * purpose with or without fee is hereby granted, provided that the above
43 * copyright notice and this permission notice appear in all copies.
45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
55 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
56 * the SK-984x series adapters, both single port and dual port.
58 * The XaQti XMAC II datasheet,
59 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
60 * The SysKonnect GEnesis manual, http://www.syskonnect.com
62 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
63 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
64 * convenience to others until Vitesse corrects this problem:
66 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
68 * Written by Bill Paul <wpaul@ee.columbia.edu>
69 * Department of Electrical Engineering
70 * Columbia University, New York City
74 * The SysKonnect gigabit ethernet adapters consist of two main
75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
77 * components and a PHY while the GEnesis controller provides a PCI
78 * interface with DMA support. Each card may have between 512K and
79 * 2MB of SRAM on board depending on the configuration.
81 * The SysKonnect GEnesis controller can have either one or two XMAC
82 * chips connected to it, allowing single or dual port NIC configurations.
83 * SysKonnect has the distinction of being the only vendor on the market
84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
86 * XMAC registers. This driver takes advantage of these features to allow
87 * both XMACs to operate as independent interfaces.
90 #include <sys/param.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/socket.h>
97 #include <sys/queue.h>
100 #include <net/ifq_var.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
108 #include <vm/vm.h> /* for vtophys */
109 #include <vm/pmap.h> /* for vtophys */
110 #include <machine/clock.h> /* for DELAY */
111 #include <machine/bus_pio.h>
112 #include <machine/bus_memio.h>
113 #include <machine/bus.h>
114 #include <machine/resource.h>
116 #include <sys/rman.h>
118 #include "../mii_layer/mii.h"
119 #include "../mii_layer/miivar.h"
120 #include "../mii_layer/brgphyreg.h"
122 #include <bus/pci/pcireg.h>
123 #include <bus/pci/pcivar.h>
126 #define SK_USEIOSPACE
129 #include "if_skreg.h"
130 #include "xmaciireg.h"
131 #include "yukonreg.h"
133 /* "controller miibus0" required. See GENERIC if you get errors here. */
134 #include "miibus_if.h"
136 static struct sk_type sk_devs[] = {
140 "SysKonnect Gigabit Ethernet (V1.0)"
145 "SysKonnect Gigabit Ethernet (V2.0)"
150 "Marvell Gigabit Ethernet"
155 "3Com 3C940 Gigabit Ethernet"
159 DEVICEID_LINKSYS_EG1032,
160 "Linksys EG1032 Gigabit Ethernet"
164 DEVICEID_DLINK_DGE530T,
165 "D-Link DGE-530T Gigabit Ethernet"
170 static int skc_probe (device_t);
171 static int skc_attach (device_t);
172 static int skc_detach (device_t);
173 static void skc_shutdown (device_t);
174 static int sk_probe (device_t);
175 static int sk_attach (device_t);
176 static int sk_detach (device_t);
177 static void sk_tick (void *);
178 static void sk_intr (void *);
179 static void sk_intr_bcom (struct sk_if_softc *);
180 static void sk_intr_xmac (struct sk_if_softc *);
181 static void sk_intr_yukon (struct sk_if_softc *);
182 static void sk_rxeof (struct sk_if_softc *);
183 static void sk_txeof (struct sk_if_softc *);
184 static int sk_encap (struct sk_if_softc *, struct mbuf *,
186 static void sk_start (struct ifnet *);
187 static int sk_ioctl (struct ifnet *, u_long, caddr_t,
189 static void sk_init (void *);
190 static void sk_init_xmac (struct sk_if_softc *);
191 static void sk_init_yukon (struct sk_if_softc *);
192 static void sk_stop (struct sk_if_softc *);
193 static void sk_watchdog (struct ifnet *);
194 static int sk_ifmedia_upd (struct ifnet *);
195 static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *);
196 static void sk_reset (struct sk_softc *);
197 static int sk_newbuf (struct sk_if_softc *,
198 struct sk_chain *, struct mbuf *);
199 static int sk_alloc_jumbo_mem (struct sk_if_softc *);
200 static void *sk_jalloc (struct sk_if_softc *);
201 static void sk_jfree (caddr_t, u_int);
202 static void sk_jref (caddr_t, u_int);
203 static int sk_init_rx_ring (struct sk_if_softc *);
204 static void sk_init_tx_ring (struct sk_if_softc *);
205 static u_int32_t sk_win_read_4 (struct sk_softc *, int);
206 static u_int16_t sk_win_read_2 (struct sk_softc *, int);
207 static u_int8_t sk_win_read_1 (struct sk_softc *, int);
208 static void sk_win_write_4 (struct sk_softc *, int, u_int32_t);
209 static void sk_win_write_2 (struct sk_softc *, int, u_int32_t);
210 static void sk_win_write_1 (struct sk_softc *, int, u_int32_t);
211 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int);
212 static void sk_vpd_read_res (struct sk_softc *,
213 struct vpd_res *, int);
214 static void sk_vpd_read (struct sk_softc *);
216 static int sk_miibus_readreg (device_t, int, int);
217 static int sk_miibus_writereg (device_t, int, int, int);
218 static void sk_miibus_statchg (device_t);
220 static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int);
221 static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, int);
222 static void sk_xmac_miibus_statchg (struct sk_if_softc *);
224 static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int);
225 static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, int);
226 static void sk_marv_miibus_statchg (struct sk_if_softc *);
228 static u_int32_t xmac_calchash (caddr_t);
229 static u_int32_t gmac_calchash (caddr_t);
230 static void sk_setfilt (struct sk_if_softc *, caddr_t, int);
231 static void sk_setmulti (struct sk_if_softc *);
232 static void sk_setpromisc (struct sk_if_softc *);
235 #define SK_RES SYS_RES_IOPORT
236 #define SK_RID SK_PCI_LOIO
238 #define SK_RES SYS_RES_MEMORY
239 #define SK_RID SK_PCI_LOMEM
243 * Note that we have newbus methods for both the GEnesis controller
244 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
245 * the miibus code is a child of the XMACs. We need to do it this way
246 * so that the miibus drivers can access the PHY registers on the
247 * right PHY. It's not quite what I had in mind, but it's the only
248 * design that achieves the desired effect.
250 static device_method_t skc_methods[] = {
251 /* Device interface */
252 DEVMETHOD(device_probe, skc_probe),
253 DEVMETHOD(device_attach, skc_attach),
254 DEVMETHOD(device_detach, skc_detach),
255 DEVMETHOD(device_shutdown, skc_shutdown),
258 DEVMETHOD(bus_print_child, bus_generic_print_child),
259 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
264 static driver_t skc_driver = {
267 sizeof(struct sk_softc)
270 static devclass_t skc_devclass;
272 static device_method_t sk_methods[] = {
273 /* Device interface */
274 DEVMETHOD(device_probe, sk_probe),
275 DEVMETHOD(device_attach, sk_attach),
276 DEVMETHOD(device_detach, sk_detach),
277 DEVMETHOD(device_shutdown, bus_generic_shutdown),
280 DEVMETHOD(bus_print_child, bus_generic_print_child),
281 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
284 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
285 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
286 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
291 static driver_t sk_driver = {
294 sizeof(struct sk_if_softc)
297 static devclass_t sk_devclass;
299 DECLARE_DUMMY_MODULE(if_sk);
300 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
301 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
302 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
304 #define SK_SETBIT(sc, reg, x) \
305 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
307 #define SK_CLRBIT(sc, reg, x) \
308 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
310 #define SK_WIN_SETBIT_4(sc, reg, x) \
311 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
313 #define SK_WIN_CLRBIT_4(sc, reg, x) \
314 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
316 #define SK_WIN_SETBIT_2(sc, reg, x) \
317 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
319 #define SK_WIN_CLRBIT_2(sc, reg, x) \
320 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
322 static u_int32_t sk_win_read_4(sc, reg)
327 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
328 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
330 return(CSR_READ_4(sc, reg));
334 static u_int16_t sk_win_read_2(sc, reg)
339 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
340 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
342 return(CSR_READ_2(sc, reg));
346 static u_int8_t sk_win_read_1(sc, reg)
351 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
352 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
354 return(CSR_READ_1(sc, reg));
358 static void sk_win_write_4(sc, reg, val)
364 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
365 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
367 CSR_WRITE_4(sc, reg, val);
372 static void sk_win_write_2(sc, reg, val)
378 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
379 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
381 CSR_WRITE_2(sc, reg, val);
386 static void sk_win_write_1(sc, reg, val)
392 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
393 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
395 CSR_WRITE_1(sc, reg, val);
401 * The VPD EEPROM contains Vital Product Data, as suggested in
402 * the PCI 2.1 specification. The VPD data is separared into areas
403 * denoted by resource IDs. The SysKonnect VPD contains an ID string
404 * resource (the name of the adapter), a read-only area resource
405 * containing various key/data fields and a read/write area which
406 * can be used to store asset management information or log messages.
407 * We read the ID string and read-only into buffers attached to
408 * the controller softc structure for later use. At the moment,
409 * we only use the ID string during sk_attach().
411 static u_int8_t sk_vpd_readbyte(sc, addr)
417 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
418 for (i = 0; i < SK_TIMEOUT; i++) {
420 if (sk_win_read_2(sc,
421 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
428 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
431 static void sk_vpd_read_res(sc, res, addr)
439 ptr = (u_int8_t *)res;
440 for (i = 0; i < sizeof(struct vpd_res); i++)
441 ptr[i] = sk_vpd_readbyte(sc, i + addr);
446 static void sk_vpd_read(sc)
452 if (sc->sk_vpd_prodname != NULL)
453 free(sc->sk_vpd_prodname, M_DEVBUF);
454 if (sc->sk_vpd_readonly != NULL)
455 free(sc->sk_vpd_readonly, M_DEVBUF);
456 sc->sk_vpd_prodname = NULL;
457 sc->sk_vpd_readonly = NULL;
459 sk_vpd_read_res(sc, &res, pos);
461 if (res.vr_id != VPD_RES_ID) {
462 printf("skc%d: bad VPD resource id: expected %x got %x\n",
463 sc->sk_unit, VPD_RES_ID, res.vr_id);
468 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
469 for (i = 0; i < res.vr_len; i++)
470 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
471 sc->sk_vpd_prodname[i] = '\0';
474 sk_vpd_read_res(sc, &res, pos);
476 if (res.vr_id != VPD_RES_READ) {
477 printf("skc%d: bad VPD resource id: expected %x got %x\n",
478 sc->sk_unit, VPD_RES_READ, res.vr_id);
483 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
484 for (i = 0; i < res.vr_len + 1; i++)
485 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
490 static int sk_miibus_readreg(dev, phy, reg)
494 struct sk_if_softc *sc_if;
496 sc_if = device_get_softc(dev);
498 switch(sc_if->sk_softc->sk_type) {
500 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
502 return(sk_marv_miibus_readreg(sc_if, phy, reg));
508 static int sk_miibus_writereg(dev, phy, reg, val)
512 struct sk_if_softc *sc_if;
514 sc_if = device_get_softc(dev);
516 switch(sc_if->sk_softc->sk_type) {
518 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
520 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
526 static void sk_miibus_statchg(dev)
529 struct sk_if_softc *sc_if;
531 sc_if = device_get_softc(dev);
533 switch(sc_if->sk_softc->sk_type) {
535 sk_xmac_miibus_statchg(sc_if);
538 sk_marv_miibus_statchg(sc_if);
545 static int sk_xmac_miibus_readreg(sc_if, phy, reg)
546 struct sk_if_softc *sc_if;
551 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
554 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
555 SK_XM_READ_2(sc_if, XM_PHY_DATA);
556 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
557 for (i = 0; i < SK_TIMEOUT; i++) {
559 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
560 XM_MMUCMD_PHYDATARDY)
564 if (i == SK_TIMEOUT) {
565 printf("sk%d: phy failed to come ready\n",
571 return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
574 static int sk_xmac_miibus_writereg(sc_if, phy, reg, val)
575 struct sk_if_softc *sc_if;
580 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
581 for (i = 0; i < SK_TIMEOUT; i++) {
582 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
586 if (i == SK_TIMEOUT) {
587 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
591 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
592 for (i = 0; i < SK_TIMEOUT; i++) {
594 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
599 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
604 static void sk_xmac_miibus_statchg(sc_if)
605 struct sk_if_softc *sc_if;
607 struct mii_data *mii;
609 mii = device_get_softc(sc_if->sk_miibus);
612 * If this is a GMII PHY, manually set the XMAC's
613 * duplex mode accordingly.
615 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
616 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
617 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
619 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
626 static int sk_marv_miibus_readreg(sc_if, phy, reg)
627 struct sk_if_softc *sc_if;
634 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
635 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
639 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
640 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
642 for (i = 0; i < SK_TIMEOUT; i++) {
644 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
645 if (val & YU_SMICR_READ_VALID)
649 if (i == SK_TIMEOUT) {
650 printf("sk%d: phy failed to come ready\n",
655 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
660 static int sk_marv_miibus_writereg(sc_if, phy, reg, val)
661 struct sk_if_softc *sc_if;
666 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
667 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
668 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
670 for (i = 0; i < SK_TIMEOUT; i++) {
672 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
679 static void sk_marv_miibus_statchg(sc_if)
680 struct sk_if_softc *sc_if;
685 #define XMAC_POLY 0xEDB88320
686 #define GMAC_POLY 0x04C11DB7L
689 static u_int32_t xmac_calchash(addr)
692 u_int32_t idx, bit, data, crc;
694 /* Compute CRC for the address value. */
695 crc = 0xFFFFFFFF; /* initial value */
697 for (idx = 0; idx < 6; idx++) {
698 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
699 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? XMAC_POLY : 0);
702 return (~crc & ((1 << HASH_BITS) - 1));
705 static u_int32_t gmac_calchash(addr)
708 u_int32_t idx, bit, crc, tmpData, data;
710 /* Compute CRC for the address value. */
711 crc = 0xFFFFFFFF; /* initial value */
713 for (idx = 0; idx < 6; idx++) {
716 /* Change bit order in byte. */
718 for (bit = 0; bit < 8; bit++) {
720 data |= 1 << (7 - bit);
723 data &= ~(1 << (7 - bit));
730 for (bit = 0; bit < 8; bit++) {
731 if (crc & 0x80000000) {
732 crc = (crc << 1) ^ GMAC_POLY;
739 return (crc & ((1 << HASH_BITS) - 1));
742 static void sk_setfilt(sc_if, addr, slot)
743 struct sk_if_softc *sc_if;
749 base = XM_RXFILT_ENTRY(slot);
751 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
752 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
753 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
758 static void sk_setmulti(sc_if)
759 struct sk_if_softc *sc_if;
761 struct sk_softc *sc = sc_if->sk_softc;
762 struct ifnet *ifp = &sc_if->arpcom.ac_if;
763 u_int32_t hashes[2] = { 0, 0 };
765 struct ifmultiaddr *ifma;
766 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
769 /* First, zot all the existing filters. */
770 switch(sc->sk_type) {
772 for (i = 1; i < XM_RXFILT_MAX; i++)
773 sk_setfilt(sc_if, (caddr_t)&dummy, i);
775 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
776 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
779 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
780 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
781 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
782 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
786 /* Now program new ones. */
787 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
788 hashes[0] = 0xFFFFFFFF;
789 hashes[1] = 0xFFFFFFFF;
792 /* First find the tail of the list. */
793 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
794 ifma = ifma->ifma_link.le_next) {
795 if (ifma->ifma_link.le_next == NULL)
798 /* Now traverse the list backwards. */
799 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
800 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
801 if (ifma->ifma_addr->sa_family != AF_LINK)
804 * Program the first XM_RXFILT_MAX multicast groups
805 * into the perfect filter. For all others,
806 * use the hash table.
808 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
810 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
815 switch(sc->sk_type) {
818 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
820 hashes[0] |= (1 << h);
822 hashes[1] |= (1 << (h - 32));
827 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
829 hashes[0] |= (1 << h);
831 hashes[1] |= (1 << (h - 32));
837 switch(sc->sk_type) {
839 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
840 XM_MODE_RX_USE_PERFECT);
841 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
842 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
845 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
846 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
847 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
848 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
855 static void sk_setpromisc(sc_if)
856 struct sk_if_softc *sc_if;
858 struct sk_softc *sc = sc_if->sk_softc;
859 struct ifnet *ifp = &sc_if->arpcom.ac_if;
861 switch(sc->sk_type) {
863 if (ifp->if_flags & IFF_PROMISC) {
864 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
866 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
870 if (ifp->if_flags & IFF_PROMISC) {
871 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
872 YU_RCR_UFLEN | YU_RCR_MUFLEN);
874 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
875 YU_RCR_UFLEN | YU_RCR_MUFLEN);
883 static int sk_init_rx_ring(sc_if)
884 struct sk_if_softc *sc_if;
886 struct sk_chain_data *cd = &sc_if->sk_cdata;
887 struct sk_ring_data *rd = sc_if->sk_rdata;
890 bzero((char *)rd->sk_rx_ring,
891 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
893 for (i = 0; i < SK_RX_RING_CNT; i++) {
894 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
895 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
897 if (i == (SK_RX_RING_CNT - 1)) {
898 cd->sk_rx_chain[i].sk_next =
900 rd->sk_rx_ring[i].sk_next =
901 vtophys(&rd->sk_rx_ring[0]);
903 cd->sk_rx_chain[i].sk_next =
904 &cd->sk_rx_chain[i + 1];
905 rd->sk_rx_ring[i].sk_next =
906 vtophys(&rd->sk_rx_ring[i + 1]);
910 sc_if->sk_cdata.sk_rx_prod = 0;
911 sc_if->sk_cdata.sk_rx_cons = 0;
916 static void sk_init_tx_ring(sc_if)
917 struct sk_if_softc *sc_if;
919 struct sk_chain_data *cd = &sc_if->sk_cdata;
920 struct sk_ring_data *rd = sc_if->sk_rdata;
923 bzero((char *)sc_if->sk_rdata->sk_tx_ring,
924 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
926 for (i = 0; i < SK_TX_RING_CNT; i++) {
927 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
928 if (i == (SK_TX_RING_CNT - 1)) {
929 cd->sk_tx_chain[i].sk_next =
931 rd->sk_tx_ring[i].sk_next =
932 vtophys(&rd->sk_tx_ring[0]);
934 cd->sk_tx_chain[i].sk_next =
935 &cd->sk_tx_chain[i + 1];
936 rd->sk_tx_ring[i].sk_next =
937 vtophys(&rd->sk_tx_ring[i + 1]);
941 sc_if->sk_cdata.sk_tx_prod = 0;
942 sc_if->sk_cdata.sk_tx_cons = 0;
943 sc_if->sk_cdata.sk_tx_cnt = 0;
948 static int sk_newbuf(sc_if, c, m)
949 struct sk_if_softc *sc_if;
953 struct mbuf *m_new = NULL;
954 struct sk_rx_desc *r;
959 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
963 /* Allocate the jumbo buffer */
964 buf = sk_jalloc(sc_if);
968 printf("sk%d: jumbo allocation failed "
969 "-- packet dropped!\n", sc_if->sk_unit);
974 /* Attach the buffer to the mbuf */
975 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
976 m_new->m_flags |= M_EXT | M_EXT_OLD;
977 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
978 m_new->m_len = SK_MCLBYTES;
979 m_new->m_ext.ext_nfree.old = sk_jfree;
980 m_new->m_ext.ext_nref.old = sk_jref;
983 * We're re-using a previously allocated mbuf;
984 * be sure to re-init pointers and lengths to
988 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES;
989 m_new->m_data = m_new->m_ext.ext_buf;
993 * Adjust alignment so packet payload begins on a
994 * longword boundary. Mandatory for Alpha, useful on
997 m_adj(m_new, ETHER_ALIGN);
1001 r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
1002 r->sk_ctl = m_new->m_len | SK_RXSTAT;
1008 * Allocate jumbo buffer storage. The SysKonnect adapters support
1009 * "jumbograms" (9K frames), although SysKonnect doesn't currently
1010 * use them in their drivers. In order for us to use them, we need
1011 * large 9K receive buffers, however standard mbuf clusters are only
1012 * 2048 bytes in size. Consequently, we need to allocate and manage
1013 * our own jumbo buffer pool. Fortunately, this does not require an
1014 * excessive amount of additional code.
1016 static int sk_alloc_jumbo_mem(sc_if)
1017 struct sk_if_softc *sc_if;
1021 struct sk_jpool_entry *entry;
1023 /* Grab a big chunk o' storage. */
1024 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
1025 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1027 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
1028 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
1032 SLIST_INIT(&sc_if->sk_jfree_listhead);
1033 SLIST_INIT(&sc_if->sk_jinuse_listhead);
1036 * Now divide it up into 9K pieces and save the addresses
1037 * in an array. Note that we play an evil trick here by using
1038 * the first few bytes in the buffer to hold the the address
1039 * of the softc structure for this interface. This is because
1040 * sk_jfree() needs it, but it is called by the mbuf management
1041 * code which will not pass it to us explicitly.
1043 ptr = sc_if->sk_cdata.sk_jumbo_buf;
1044 for (i = 0; i < SK_JSLOTS; i++) {
1046 aptr = (u_int64_t **)ptr;
1047 aptr[0] = (u_int64_t *)sc_if;
1048 ptr += sizeof(u_int64_t);
1049 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr;
1050 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0;
1052 entry = malloc(sizeof(struct sk_jpool_entry),
1053 M_DEVBUF, M_WAITOK);
1054 if (entry == NULL) {
1055 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
1056 sc_if->sk_cdata.sk_jumbo_buf = NULL;
1057 printf("sk%d: no memory for jumbo "
1058 "buffer queue!\n", sc_if->sk_unit);
1062 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1063 entry, jpool_entries);
1070 * Allocate a jumbo buffer.
1072 static void *sk_jalloc(sc_if)
1073 struct sk_if_softc *sc_if;
1075 struct sk_jpool_entry *entry;
1077 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
1079 if (entry == NULL) {
1081 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
1086 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
1087 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
1088 sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1;
1089 return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf);
1093 * Adjust usage count on a jumbo buffer. In general this doesn't
1094 * get used much because our jumbo buffers don't get passed around
1095 * a lot, but it's implemented for correctness.
1097 static void sk_jref(buf, size)
1101 struct sk_if_softc *sc_if;
1105 /* Extract the softc struct pointer. */
1106 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1107 sc_if = (struct sk_if_softc *)(aptr[0]);
1110 panic("sk_jref: can't find softc pointer!");
1112 if (size != SK_MCLBYTES)
1113 panic("sk_jref: adjusting refcount of buf of wrong size!");
1115 /* calculate the slot this buffer belongs to */
1117 i = ((vm_offset_t)aptr
1118 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1120 if ((i < 0) || (i >= SK_JSLOTS))
1121 panic("sk_jref: asked to reference buffer "
1122 "that we don't manage!");
1123 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1124 panic("sk_jref: buffer already free!");
1126 sc_if->sk_cdata.sk_jslots[i].sk_inuse++;
1132 * Release a jumbo buffer.
1134 static void sk_jfree(buf, size)
1138 struct sk_if_softc *sc_if;
1141 struct sk_jpool_entry *entry;
1143 /* Extract the softc struct pointer. */
1144 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1145 sc_if = (struct sk_if_softc *)(aptr[0]);
1148 panic("sk_jfree: can't find softc pointer!");
1150 if (size != SK_MCLBYTES)
1151 panic("sk_jfree: freeing buffer of wrong size!");
1153 /* calculate the slot this buffer belongs to */
1155 i = ((vm_offset_t)aptr
1156 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1158 if ((i < 0) || (i >= SK_JSLOTS))
1159 panic("sk_jfree: asked to free buffer that we don't manage!");
1160 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1161 panic("sk_jfree: buffer already free!");
1163 sc_if->sk_cdata.sk_jslots[i].sk_inuse--;
1164 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) {
1165 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
1167 panic("sk_jfree: buffer not in use!");
1169 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead,
1171 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1172 entry, jpool_entries);
1180 * Set media options.
1182 static int sk_ifmedia_upd(ifp)
1185 struct sk_if_softc *sc_if = ifp->if_softc;
1186 struct mii_data *mii;
1188 mii = device_get_softc(sc_if->sk_miibus);
1196 * Report current media status.
1198 static void sk_ifmedia_sts(ifp, ifmr)
1200 struct ifmediareq *ifmr;
1202 struct sk_if_softc *sc_if;
1203 struct mii_data *mii;
1205 sc_if = ifp->if_softc;
1206 mii = device_get_softc(sc_if->sk_miibus);
1209 ifmr->ifm_active = mii->mii_media_active;
1210 ifmr->ifm_status = mii->mii_media_status;
1215 static int sk_ioctl(ifp, command, data, cr)
1221 struct sk_if_softc *sc_if = ifp->if_softc;
1222 struct ifreq *ifr = (struct ifreq *) data;
1224 struct mii_data *mii;
1231 error = ether_ioctl(ifp, command, data);
1234 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1237 ifp->if_mtu = ifr->ifr_mtu;
1242 if (ifp->if_flags & IFF_UP) {
1243 if (ifp->if_flags & IFF_RUNNING) {
1244 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1246 sk_setpromisc(sc_if);
1252 if (ifp->if_flags & IFF_RUNNING)
1255 sc_if->sk_if_flags = ifp->if_flags;
1265 mii = device_get_softc(sc_if->sk_miibus);
1266 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1279 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1280 * IDs against our list and return a device name if we find a match.
1282 static int skc_probe(dev)
1285 struct sk_softc *sc;
1286 struct sk_type *t = sk_devs;
1288 sc = device_get_softc(dev);
1290 while(t->sk_name != NULL) {
1291 if ((pci_get_vendor(dev) == t->sk_vid) &&
1292 (pci_get_device(dev) == t->sk_did)) {
1293 device_set_desc(dev, t->sk_name);
1303 * Force the GEnesis into reset, then bring it out of reset.
1305 static void sk_reset(sc)
1306 struct sk_softc *sc;
1308 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1309 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1310 if (sc->sk_type == SK_YUKON)
1311 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1314 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1316 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1317 if (sc->sk_type == SK_YUKON)
1318 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1320 if (sc->sk_type == SK_GENESIS) {
1321 /* Configure packet arbiter */
1322 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1323 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1324 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1325 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1326 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1329 /* Enable RAM interface */
1330 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1333 * Configure interrupt moderation. The moderation timer
1334 * defers interrupts specified in the interrupt moderation
1335 * timer mask based on the timeout specified in the interrupt
1336 * moderation timer init register. Each bit in the timer
1337 * register represents 18.825ns, so to specify a timeout in
1338 * microseconds, we have to multiply by 54.
1340 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1341 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1342 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1343 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1348 static int sk_probe(dev)
1351 struct sk_softc *sc;
1353 sc = device_get_softc(device_get_parent(dev));
1356 * Not much to do here. We always know there will be
1357 * at least one XMAC present, and if there are two,
1358 * skc_attach() will create a second device instance
1361 switch (sc->sk_type) {
1363 device_set_desc(dev, "XaQti Corp. XMAC II");
1366 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1374 * Each XMAC chip is attached as a separate logical IP interface.
1375 * Single port cards will have only one logical interface of course.
1377 static int sk_attach(dev)
1380 struct sk_softc *sc;
1381 struct sk_if_softc *sc_if;
1388 sc_if = device_get_softc(dev);
1389 sc = device_get_softc(device_get_parent(dev));
1390 port = *(int *)device_get_ivars(dev);
1391 free(device_get_ivars(dev), M_DEVBUF);
1392 device_set_ivars(dev, NULL);
1393 sc_if->sk_dev = dev;
1394 callout_init(&sc_if->sk_tick_timer);
1396 bzero((char *)sc_if, sizeof(struct sk_if_softc));
1398 sc_if->sk_dev = dev;
1399 sc_if->sk_unit = device_get_unit(dev);
1400 sc_if->sk_port = port;
1401 sc_if->sk_softc = sc;
1402 sc->sk_if[port] = sc_if;
1403 if (port == SK_PORT_A)
1404 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1405 if (port == SK_PORT_B)
1406 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1409 * Get station address for this interface. Note that
1410 * dual port cards actually come with three station
1411 * addresses: one for each port, plus an extra. The
1412 * extra one is used by the SysKonnect driver software
1413 * as a 'virtual' station address for when both ports
1414 * are operating in failover mode. Currently we don't
1415 * use this extra address.
1417 for (i = 0; i < ETHER_ADDR_LEN; i++)
1418 sc_if->arpcom.ac_enaddr[i] =
1419 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1422 * Set up RAM buffer addresses. The NIC will have a certain
1423 * amount of SRAM on it, somewhere between 512K and 2MB. We
1424 * need to divide this up a) between the transmitter and
1425 * receiver and b) between the two XMACs, if this is a
1426 * dual port NIC. Our algotithm is to divide up the memory
1427 * evenly so that everyone gets a fair share.
1429 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1430 u_int32_t chunk, val;
1432 chunk = sc->sk_ramsize / 2;
1433 val = sc->sk_rboff / sizeof(u_int64_t);
1434 sc_if->sk_rx_ramstart = val;
1435 val += (chunk / sizeof(u_int64_t));
1436 sc_if->sk_rx_ramend = val - 1;
1437 sc_if->sk_tx_ramstart = val;
1438 val += (chunk / sizeof(u_int64_t));
1439 sc_if->sk_tx_ramend = val - 1;
1441 u_int32_t chunk, val;
1443 chunk = sc->sk_ramsize / 4;
1444 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1446 sc_if->sk_rx_ramstart = val;
1447 val += (chunk / sizeof(u_int64_t));
1448 sc_if->sk_rx_ramend = val - 1;
1449 sc_if->sk_tx_ramstart = val;
1450 val += (chunk / sizeof(u_int64_t));
1451 sc_if->sk_tx_ramend = val - 1;
1454 /* Read and save PHY type and set PHY address */
1455 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1456 switch(sc_if->sk_phytype) {
1457 case SK_PHYTYPE_XMAC:
1458 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1460 case SK_PHYTYPE_BCOM:
1461 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1463 case SK_PHYTYPE_MARV_COPPER:
1464 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1467 printf("skc%d: unsupported PHY type: %d\n",
1468 sc->sk_unit, sc_if->sk_phytype);
1472 /* Allocate the descriptor queues. */
1473 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1474 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1476 if (sc_if->sk_rdata == NULL) {
1477 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1478 sc->sk_if[port] = NULL;
1482 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1484 /* Try to allocate memory for jumbo buffers. */
1485 if (sk_alloc_jumbo_mem(sc_if)) {
1486 printf("sk%d: jumbo buffer allocation failed\n",
1488 contigfree(sc_if->sk_rdata,
1489 sizeof(struct sk_ring_data), M_DEVBUF);
1490 sc->sk_if[port] = NULL;
1494 ifp = &sc_if->arpcom.ac_if;
1495 ifp->if_softc = sc_if;
1496 if_initname(ifp, "sk", sc_if->sk_unit);
1497 ifp->if_mtu = ETHERMTU;
1498 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1499 ifp->if_ioctl = sk_ioctl;
1500 ifp->if_start = sk_start;
1501 ifp->if_watchdog = sk_watchdog;
1502 ifp->if_init = sk_init;
1503 ifp->if_baudrate = 1000000000;
1504 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1505 ifq_set_ready(&ifp->if_snd);
1510 switch (sc->sk_type) {
1512 sk_init_xmac(sc_if);
1515 sk_init_yukon(sc_if);
1519 if (mii_phy_probe(dev, &sc_if->sk_miibus,
1520 sk_ifmedia_upd, sk_ifmedia_sts)) {
1521 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1522 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1524 contigfree(sc_if->sk_rdata,
1525 sizeof(struct sk_ring_data), M_DEVBUF);
1530 * Call MI attach routine.
1532 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr);
1533 callout_init(&sc_if->sk_tick_timer);
1539 * Attach the interface. Allocate softc structures, do ifmedia
1540 * setup and ethernet/BPF attach.
1542 static int skc_attach(dev)
1547 struct sk_softc *sc;
1548 int unit, error = 0, rid, *port;
1553 sc = device_get_softc(dev);
1554 unit = device_get_unit(dev);
1555 bzero(sc, sizeof(struct sk_softc));
1556 switch (pci_get_device(dev)) {
1557 case DEVICEID_SK_V1:
1558 sc->sk_type = SK_GENESIS;
1560 case DEVICEID_SK_V2:
1561 case DEVICEID_3COM_3C940:
1562 case DEVICEID_LINKSYS_EG1032:
1563 case DEVICEID_DLINK_DGE530T:
1564 sc->sk_type = SK_YUKON;
1569 * Handle power management nonsense.
1571 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1572 if (command == 0x01) {
1573 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1574 if (command & SK_PSTATE_MASK) {
1575 u_int32_t iobase, membase, irq;
1577 /* Save important PCI config data. */
1578 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1579 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1580 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1582 /* Reset the power state. */
1583 printf("skc%d: chip is in D%d power mode "
1584 "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1585 command &= 0xFFFFFFFC;
1586 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1588 /* Restore PCI config data. */
1589 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1590 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1591 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1596 * Map control/status registers.
1598 command = pci_read_config(dev, PCIR_COMMAND, 4);
1599 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1600 pci_write_config(dev, PCIR_COMMAND, command, 4);
1601 command = pci_read_config(dev, PCIR_COMMAND, 4);
1603 #ifdef SK_USEIOSPACE
1604 if (!(command & PCIM_CMD_PORTEN)) {
1605 printf("skc%d: failed to enable I/O ports!\n", unit);
1610 if (!(command & PCIM_CMD_MEMEN)) {
1611 printf("skc%d: failed to enable memory mapping!\n", unit);
1618 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1619 0, ~0, 1, RF_ACTIVE);
1621 if (sc->sk_res == NULL) {
1622 printf("sk%d: couldn't map ports/memory\n", unit);
1627 sc->sk_btag = rman_get_bustag(sc->sk_res);
1628 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1630 /* Allocate interrupt */
1632 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1633 RF_SHAREABLE | RF_ACTIVE);
1635 if (sc->sk_irq == NULL) {
1636 printf("skc%d: couldn't map interrupt\n", unit);
1637 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1642 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1643 sk_intr, sc, &sc->sk_intrhand);
1646 printf("skc%d: couldn't set up irq\n", unit);
1647 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1648 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1652 /* Reset the adapter. */
1657 /* Read and save vital product data from EEPROM. */
1660 skrs = sk_win_read_1(sc, SK_EPROM0);
1661 if (sc->sk_type == SK_GENESIS) {
1662 /* Read and save RAM size and RAMbuffer offset */
1664 case SK_RAMSIZE_512K_64:
1665 sc->sk_ramsize = 0x80000;
1666 sc->sk_rboff = SK_RBOFF_0;
1668 case SK_RAMSIZE_1024K_64:
1669 sc->sk_ramsize = 0x100000;
1670 sc->sk_rboff = SK_RBOFF_80000;
1672 case SK_RAMSIZE_1024K_128:
1673 sc->sk_ramsize = 0x100000;
1674 sc->sk_rboff = SK_RBOFF_0;
1676 case SK_RAMSIZE_2048K_128:
1677 sc->sk_ramsize = 0x200000;
1678 sc->sk_rboff = SK_RBOFF_0;
1681 printf("skc%d: unknown ram size: %d\n",
1682 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1683 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1685 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1690 } else { /* SK_YUKON */
1692 sc->sk_ramsize = 0x20000;
1694 sc->sk_ramsize = skrs * (1<<12);
1696 sc->sk_rboff = SK_RBOFF_0;
1699 /* Read and save physical media type */
1700 switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1701 case SK_PMD_1000BASESX:
1702 sc->sk_pmd = IFM_1000_SX;
1704 case SK_PMD_1000BASELX:
1705 sc->sk_pmd = IFM_1000_LX;
1707 case SK_PMD_1000BASECX:
1708 sc->sk_pmd = IFM_1000_CX;
1710 case SK_PMD_1000BASETX:
1711 sc->sk_pmd = IFM_1000_T;
1714 printf("skc%d: unknown media type: 0x%x\n",
1715 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1716 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1717 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1718 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1723 /* Announce the product name. */
1724 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1725 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1726 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1728 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1730 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1731 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1732 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1734 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1737 /* Turn on the 'driver is loaded' LED. */
1738 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1740 bus_generic_attach(dev);
1747 static int sk_detach(dev)
1750 struct sk_softc *sc;
1751 struct sk_if_softc *sc_if;
1757 sc = device_get_softc(device_get_parent(dev));
1758 sc_if = device_get_softc(dev);
1759 ifp = &sc_if->arpcom.ac_if;
1761 ether_ifdetach(ifp);
1762 bus_generic_detach(dev);
1763 if (sc_if->sk_miibus != NULL)
1764 device_delete_child(dev, sc_if->sk_miibus);
1765 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1766 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1771 static int skc_detach(dev)
1774 struct sk_softc *sc;
1779 sc = device_get_softc(dev);
1781 bus_generic_detach(dev);
1782 if (sc->sk_devs[SK_PORT_A] != NULL)
1783 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1784 if (sc->sk_devs[SK_PORT_B] != NULL)
1785 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1787 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1788 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1789 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1796 static int sk_encap(sc_if, m_head, txidx)
1797 struct sk_if_softc *sc_if;
1798 struct mbuf *m_head;
1801 struct sk_tx_desc *f = NULL;
1803 u_int32_t frag, cur, cnt = 0;
1806 cur = frag = *txidx;
1809 * Start packing the mbufs in this chain into
1810 * the fragment pointers. Stop when we run out
1811 * of fragments or hit the end of the mbuf chain.
1813 for (m = m_head; m != NULL; m = m->m_next) {
1814 if (m->m_len != 0) {
1815 if ((SK_TX_RING_CNT -
1816 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1818 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1819 f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1820 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1822 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1824 f->sk_ctl |= SK_TXCTL_OWN;
1826 SK_INC(frag, SK_TX_RING_CNT);
1834 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1835 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1836 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1837 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1838 sc_if->sk_cdata.sk_tx_cnt += cnt;
1845 static void sk_start(ifp)
1848 struct sk_softc *sc;
1849 struct sk_if_softc *sc_if;
1850 struct mbuf *m_head = NULL;
1853 sc_if = ifp->if_softc;
1854 sc = sc_if->sk_softc;
1856 idx = sc_if->sk_cdata.sk_tx_prod;
1858 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1859 m_head = ifq_poll(&ifp->if_snd);
1864 * Pack the data into the transmit ring. If we
1865 * don't have room, set the OACTIVE flag and wait
1866 * for the NIC to drain the ring.
1868 if (sk_encap(sc_if, m_head, &idx)) {
1869 ifp->if_flags |= IFF_OACTIVE;
1872 m_head = ifq_dequeue(&ifp->if_snd);
1874 BPF_MTAP(ifp, m_head);
1878 sc_if->sk_cdata.sk_tx_prod = idx;
1879 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1881 /* Set a timeout in case the chip goes out to lunch. */
1888 static void sk_watchdog(ifp)
1891 struct sk_if_softc *sc_if;
1893 sc_if = ifp->if_softc;
1895 printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1901 static void skc_shutdown(dev)
1904 struct sk_softc *sc;
1906 sc = device_get_softc(dev);
1908 /* Turn off the 'driver is loaded' LED. */
1909 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1912 * Reset the GEnesis controller. Doing this should also
1913 * assert the resets on the attached XMAC(s).
1920 static void sk_rxeof(sc_if)
1921 struct sk_if_softc *sc_if;
1925 struct sk_chain *cur_rx;
1930 ifp = &sc_if->arpcom.ac_if;
1931 i = sc_if->sk_cdata.sk_rx_prod;
1932 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1934 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1936 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1937 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1938 m = cur_rx->sk_mbuf;
1939 cur_rx->sk_mbuf = NULL;
1940 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1941 SK_INC(i, SK_RX_RING_CNT);
1943 if (rxstat & XM_RXSTAT_ERRFRAME) {
1945 sk_newbuf(sc_if, cur_rx, m);
1950 * Try to allocate a new jumbo buffer. If that
1951 * fails, copy the packet to mbufs and put the
1952 * jumbo buffer back in the ring so it can be
1953 * re-used. If allocating mbufs fails, then we
1954 * have to drop the packet.
1956 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1958 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1959 total_len + ETHER_ALIGN, 0, ifp, NULL);
1960 sk_newbuf(sc_if, cur_rx, m);
1962 printf("sk%d: no receive buffers "
1963 "available -- packet dropped!\n",
1968 m_adj(m0, ETHER_ALIGN);
1971 m->m_pkthdr.rcvif = ifp;
1972 m->m_pkthdr.len = m->m_len = total_len;
1976 (*ifp->if_input)(ifp, m);
1979 sc_if->sk_cdata.sk_rx_prod = i;
1984 static void sk_txeof(sc_if)
1985 struct sk_if_softc *sc_if;
1987 struct sk_tx_desc *cur_tx = NULL;
1991 ifp = &sc_if->arpcom.ac_if;
1994 * Go through our tx ring and free mbufs for those
1995 * frames that have been sent.
1997 idx = sc_if->sk_cdata.sk_tx_cons;
1998 while(idx != sc_if->sk_cdata.sk_tx_prod) {
1999 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
2000 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
2002 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
2004 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
2005 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
2006 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
2008 sc_if->sk_cdata.sk_tx_cnt--;
2009 SK_INC(idx, SK_TX_RING_CNT);
2013 sc_if->sk_cdata.sk_tx_cons = idx;
2016 ifp->if_flags &= ~IFF_OACTIVE;
2021 static void sk_tick(xsc_if)
2024 struct sk_if_softc *sc_if;
2025 struct mii_data *mii;
2030 ifp = &sc_if->arpcom.ac_if;
2031 mii = device_get_softc(sc_if->sk_miibus);
2033 if (!(ifp->if_flags & IFF_UP))
2036 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2037 sk_intr_bcom(sc_if);
2042 * According to SysKonnect, the correct way to verify that
2043 * the link has come back up is to poll bit 0 of the GPIO
2044 * register three times. This pin has the signal from the
2045 * link_sync pin connected to it; if we read the same link
2046 * state 3 times in a row, we know the link is up.
2048 for (i = 0; i < 3; i++) {
2049 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2054 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2058 /* Turn the GP0 interrupt back on. */
2059 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2060 SK_XM_READ_2(sc_if, XM_ISR);
2063 callout_stop(&sc_if->sk_tick_timer);
2068 static void sk_intr_bcom(sc_if)
2069 struct sk_if_softc *sc_if;
2071 struct sk_softc *sc;
2072 struct mii_data *mii;
2076 sc = sc_if->sk_softc;
2077 mii = device_get_softc(sc_if->sk_miibus);
2078 ifp = &sc_if->arpcom.ac_if;
2080 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2083 * Read the PHY interrupt register to make sure
2084 * we clear any pending interrupts.
2086 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2088 if (!(ifp->if_flags & IFF_RUNNING)) {
2089 sk_init_xmac(sc_if);
2093 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2095 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2098 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2100 /* Turn off the link LED. */
2101 SK_IF_WRITE_1(sc_if, 0,
2102 SK_LINKLED1_CTL, SK_LINKLED_OFF);
2104 } else if (status & BRGPHY_ISR_LNK_CHG) {
2105 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2106 BRGPHY_MII_IMR, 0xFF00);
2109 /* Turn on the link LED. */
2110 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2111 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2112 SK_LINKLED_BLINK_OFF);
2116 callout_reset(&sc_if->sk_tick_timer, hz,
2121 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2126 static void sk_intr_xmac(sc_if)
2127 struct sk_if_softc *sc_if;
2129 struct sk_softc *sc;
2131 struct mii_data *mii;
2133 sc = sc_if->sk_softc;
2134 mii = device_get_softc(sc_if->sk_miibus);
2135 status = SK_XM_READ_2(sc_if, XM_ISR);
2138 * Link has gone down. Start MII tick timeout to
2139 * watch for link resync.
2141 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2142 if (status & XM_ISR_GP0_SET) {
2143 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2144 callout_reset(&sc_if->sk_tick_timer, hz,
2148 if (status & XM_ISR_AUTONEG_DONE) {
2149 callout_reset(&sc_if->sk_tick_timer, hz,
2154 if (status & XM_IMR_TX_UNDERRUN)
2155 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2157 if (status & XM_IMR_RX_OVERRUN)
2158 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2160 status = SK_XM_READ_2(sc_if, XM_ISR);
2165 static void sk_intr_yukon(sc_if)
2166 struct sk_if_softc *sc_if;
2170 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2175 static void sk_intr(xsc)
2178 struct sk_softc *sc = xsc;
2179 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL;
2180 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2183 sc_if0 = sc->sk_if[SK_PORT_A];
2184 sc_if1 = sc->sk_if[SK_PORT_B];
2187 ifp0 = &sc_if0->arpcom.ac_if;
2189 ifp1 = &sc_if1->arpcom.ac_if;
2192 status = CSR_READ_4(sc, SK_ISSR);
2193 if (!(status & sc->sk_intrmask))
2196 /* Handle receive interrupts first. */
2197 if (status & SK_ISR_RX1_EOF) {
2199 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2200 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2202 if (status & SK_ISR_RX2_EOF) {
2204 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2205 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2208 /* Then transmit interrupts. */
2209 if (status & SK_ISR_TX1_S_EOF) {
2211 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2212 SK_TXBMU_CLR_IRQ_EOF);
2214 if (status & SK_ISR_TX2_S_EOF) {
2216 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2217 SK_TXBMU_CLR_IRQ_EOF);
2220 /* Then MAC interrupts. */
2221 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
2222 if (sc->sk_type == SK_GENESIS)
2223 sk_intr_xmac(sc_if0);
2225 sk_intr_yukon(sc_if0);
2228 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
2229 if (sc->sk_type == SK_GENESIS)
2230 sk_intr_xmac(sc_if1);
2232 sk_intr_yukon(sc_if0);
2235 if (status & SK_ISR_EXTERNAL_REG) {
2237 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2238 sk_intr_bcom(sc_if0);
2240 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2241 sk_intr_bcom(sc_if1);
2245 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2247 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2249 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd))
2255 static void sk_init_xmac(sc_if)
2256 struct sk_if_softc *sc_if;
2258 struct sk_softc *sc;
2260 struct sk_bcom_hack bhack[] = {
2261 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2262 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2263 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2266 sc = sc_if->sk_softc;
2267 ifp = &sc_if->arpcom.ac_if;
2269 /* Unreset the XMAC. */
2270 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2273 /* Reset the XMAC's internal state. */
2274 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2276 /* Save the XMAC II revision */
2277 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2280 * Perform additional initialization for external PHYs,
2281 * namely for the 1000baseTX cards that use the XMAC's
2284 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2288 /* Take PHY out of reset. */
2289 val = sk_win_read_4(sc, SK_GPIO);
2290 if (sc_if->sk_port == SK_PORT_A)
2291 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2293 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2294 sk_win_write_4(sc, SK_GPIO, val);
2296 /* Enable GMII mode on the XMAC. */
2297 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2299 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2300 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2302 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2303 BRGPHY_MII_IMR, 0xFFF0);
2306 * Early versions of the BCM5400 apparently have
2307 * a bug that requires them to have their reserved
2308 * registers initialized to some magic values. I don't
2309 * know what the numbers do, I'm just the messenger.
2311 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2313 while(bhack[i].reg) {
2314 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2315 bhack[i].reg, bhack[i].val);
2321 /* Set station address */
2322 SK_XM_WRITE_2(sc_if, XM_PAR0,
2323 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2324 SK_XM_WRITE_2(sc_if, XM_PAR1,
2325 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2326 SK_XM_WRITE_2(sc_if, XM_PAR2,
2327 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2328 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2330 if (ifp->if_flags & IFF_BROADCAST) {
2331 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2333 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2336 /* We don't need the FCS appended to the packet. */
2337 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2339 /* We want short frames padded to 60 bytes. */
2340 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2343 * Enable the reception of all error frames. This is is
2344 * a necessary evil due to the design of the XMAC. The
2345 * XMAC's receive FIFO is only 8K in size, however jumbo
2346 * frames can be up to 9000 bytes in length. When bad
2347 * frame filtering is enabled, the XMAC's RX FIFO operates
2348 * in 'store and forward' mode. For this to work, the
2349 * entire frame has to fit into the FIFO, but that means
2350 * that jumbo frames larger than 8192 bytes will be
2351 * truncated. Disabling all bad frame filtering causes
2352 * the RX FIFO to operate in streaming mode, in which
2353 * case the XMAC will start transfering frames out of the
2354 * RX FIFO as soon as the FIFO threshold is reached.
2356 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2357 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2358 XM_MODE_RX_INRANGELEN);
2360 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2361 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2363 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2366 * Bump up the transmit threshold. This helps hold off transmit
2367 * underruns when we're blasting traffic from both ports at once.
2369 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2371 /* Set promiscuous mode */
2372 sk_setpromisc(sc_if);
2374 /* Set multicast filter */
2377 /* Clear and enable interrupts */
2378 SK_XM_READ_2(sc_if, XM_ISR);
2379 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2380 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2382 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2384 /* Configure MAC arbiter */
2385 switch(sc_if->sk_xmac_rev) {
2386 case XM_XMAC_REV_B2:
2387 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2388 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2389 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2390 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2391 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2392 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2393 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2394 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2395 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2397 case XM_XMAC_REV_C1:
2398 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2399 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2400 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2401 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2402 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2403 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2404 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2405 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2406 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2411 sk_win_write_2(sc, SK_MACARB_CTL,
2412 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2419 static void sk_init_yukon(sc_if)
2420 struct sk_if_softc *sc_if;
2424 struct sk_softc *sc;
2428 sc = sc_if->sk_softc;
2429 ifp = &sc_if->arpcom.ac_if;
2431 /* GMAC and GPHY Reset */
2432 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2433 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2435 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2436 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2439 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2440 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2442 switch(sc_if->sk_softc->sk_pmd) {
2445 phy |= SK_GPHY_FIBER;
2450 phy |= SK_GPHY_COPPER;
2454 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2456 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2457 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2458 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2460 /* unused read of the interrupt source register */
2461 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2463 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2465 /* MIB Counter Clear Mode set */
2466 reg |= YU_PAR_MIB_CLR;
2467 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2469 /* MIB Counter Clear Mode clear */
2470 reg &= ~YU_PAR_MIB_CLR;
2471 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2473 /* receive control reg */
2474 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2476 /* transmit parameter register */
2477 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2478 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2480 /* serial mode register */
2481 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2482 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2483 reg |= YU_SMR_MFL_JUMBO;
2484 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2486 /* Setup Yukon's address */
2487 for (i = 0; i < 3; i++) {
2488 /* Write Source Address 1 (unicast filter) */
2489 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2490 sc_if->arpcom.ac_enaddr[i * 2] |
2491 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2494 for (i = 0; i < 3; i++) {
2495 reg = sk_win_read_2(sc_if->sk_softc,
2496 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2497 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2500 /* Set promiscuous mode */
2501 sk_setpromisc(sc_if);
2503 /* Set multicast filter */
2506 /* enable interrupt mask for counter overflows */
2507 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2508 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2509 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2511 /* Configure RX MAC FIFO */
2512 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2513 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2515 /* Configure TX MAC FIFO */
2516 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2517 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2521 * Note that to properly initialize any part of the GEnesis chip,
2522 * you first have to take it out of reset mode.
2524 static void sk_init(xsc)
2527 struct sk_if_softc *sc_if = xsc;
2528 struct sk_softc *sc;
2530 struct mii_data *mii;
2536 ifp = &sc_if->arpcom.ac_if;
2537 sc = sc_if->sk_softc;
2538 mii = device_get_softc(sc_if->sk_miibus);
2540 /* Cancel pending I/O and free all RX/TX buffers. */
2543 if (sc->sk_type == SK_GENESIS) {
2544 /* Configure LINK_SYNC LED */
2545 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2546 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2547 SK_LINKLED_LINKSYNC_ON);
2549 /* Configure RX LED */
2550 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2551 SK_RXLEDCTL_COUNTER_START);
2553 /* Configure TX LED */
2554 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2555 SK_TXLEDCTL_COUNTER_START);
2558 /* Configure I2C registers */
2560 /* Configure XMAC(s) */
2561 switch (sc->sk_type) {
2563 sk_init_xmac(sc_if);
2566 sk_init_yukon(sc_if);
2571 if (sc->sk_type == SK_GENESIS) {
2572 /* Configure MAC FIFOs */
2573 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2574 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2575 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2577 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2578 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2579 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2582 /* Configure transmit arbiter(s) */
2583 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2584 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2586 /* Configure RAMbuffers */
2587 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2588 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2589 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2590 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2591 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2592 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2594 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2595 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2596 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2597 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2598 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2599 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2600 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2602 /* Configure BMUs */
2603 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2604 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2605 vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2606 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2608 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2609 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2610 vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2611 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2613 /* Init descriptors */
2614 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2615 printf("sk%d: initialization failed: no "
2616 "memory for rx buffers\n", sc_if->sk_unit);
2621 sk_init_tx_ring(sc_if);
2623 /* Configure interrupt handling */
2624 CSR_READ_4(sc, SK_ISSR);
2625 if (sc_if->sk_port == SK_PORT_A)
2626 sc->sk_intrmask |= SK_INTRS1;
2628 sc->sk_intrmask |= SK_INTRS2;
2630 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2632 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2635 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2637 switch(sc->sk_type) {
2639 /* Enable XMACs TX and RX state machines */
2640 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2641 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2644 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2645 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2646 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2647 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2650 ifp->if_flags |= IFF_RUNNING;
2651 ifp->if_flags &= ~IFF_OACTIVE;
2658 static void sk_stop(sc_if)
2659 struct sk_if_softc *sc_if;
2662 struct sk_softc *sc;
2665 sc = sc_if->sk_softc;
2666 ifp = &sc_if->arpcom.ac_if;
2668 callout_stop(&sc_if->sk_tick_timer);
2670 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2673 /* Put PHY back into reset. */
2674 val = sk_win_read_4(sc, SK_GPIO);
2675 if (sc_if->sk_port == SK_PORT_A) {
2676 val |= SK_GPIO_DIR0;
2677 val &= ~SK_GPIO_DAT0;
2679 val |= SK_GPIO_DIR2;
2680 val &= ~SK_GPIO_DAT2;
2682 sk_win_write_4(sc, SK_GPIO, val);
2685 /* Turn off various components of this interface. */
2686 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2687 switch (sc->sk_type) {
2689 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2690 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2693 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2694 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2697 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2698 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2699 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2700 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2701 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2702 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2703 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2704 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2705 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2707 /* Disable interrupts */
2708 if (sc_if->sk_port == SK_PORT_A)
2709 sc->sk_intrmask &= ~SK_INTRS1;
2711 sc->sk_intrmask &= ~SK_INTRS2;
2712 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2714 SK_XM_READ_2(sc_if, XM_ISR);
2715 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2717 /* Free RX and TX mbufs still in the queues. */
2718 for (i = 0; i < SK_RX_RING_CNT; i++) {
2719 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2720 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2721 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2725 for (i = 0; i < SK_TX_RING_CNT; i++) {
2726 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2727 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2728 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2732 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);