2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.16 2004/11/10 18:30:13 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
39 * RealTek 8129/8139 PCI NIC driver
41 * Supports several extremely cheap PCI 10/100 adapters based on
42 * the RealTek chipset. Datasheets can be obtained from
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
52 * probably the worst PCI ethernet controller ever made, with the possible
53 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
54 * DMA, but it has a terrible interface that nullifies any performance
55 * gains that bus-master DMA usually offers.
57 * For transmission, the chip offers a series of four TX descriptor
58 * registers. Each transmit frame must be in a contiguous buffer, aligned
59 * on a longword (32-bit) boundary. This means we almost always have to
60 * do mbuf copies in order to transmit a frame, except in the unlikely
61 * case where a) the packet fits into a single mbuf, and b) the packet
62 * is 32-bit aligned within the mbuf's data area. The presence of only
63 * four descriptor registers means that we can never have more than four
64 * packets queued for transmission at any one time.
66 * Reception is not much better. The driver has to allocate a single large
67 * buffer area (up to 64K in size) into which the chip will DMA received
68 * frames. Because we don't know where within this region received packets
69 * will begin or end, we have no choice but to copy data from the buffer
70 * area into mbufs in order to pass the packets up to the higher protocol
73 * It's impossible given this rotten design to really achieve decent
74 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
75 * some equally overmuscled CPU to drive it.
77 * On the bright side, the 8139 does have a built-in PHY, although
78 * rather than using an MDIO serial interface like most other NICs, the
79 * PHY registers are directly accessible through the 8139's register
80 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
83 * The 8129 chip is an older version of the 8139 that uses an external PHY
84 * chip. The 8129 has a serial MDIO interface for accessing the MII where
85 * the 8139 lets you directly access the on-board PHY registers. We need
86 * to select which interface to use depending on the chip type.
89 #include <sys/param.h>
90 #include <sys/endian.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/module.h>
97 #include <sys/socket.h>
100 #include <net/if_arp.h>
101 #include <net/ethernet.h>
102 #include <net/if_dl.h>
103 #include <net/if_media.h>
107 #include <machine/bus_pio.h>
108 #include <machine/bus_memio.h>
109 #include <machine/bus.h>
110 #include <machine/resource.h>
112 #include <sys/rman.h>
114 #include <dev/netif/mii_layer/mii.h>
115 #include <dev/netif/mii_layer/miivar.h>
117 #include <bus/pci/pcireg.h>
118 #include <bus/pci/pcivar.h>
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
131 #define RL_USEIOSPACE
133 #include <dev/netif/rl/if_rlreg.h>
136 * Various supported device vendors/types and their names.
138 static struct rl_type {
143 { RT_VENDORID, RT_DEVICEID_8129,
144 "RealTek 8129 10/100BaseTX" },
145 { RT_VENDORID, RT_DEVICEID_8139,
146 "RealTek 8139 10/100BaseTX" },
147 { RT_VENDORID, RT_DEVICEID_8138,
148 "RealTek 8139 10/100BaseTX CardBus" },
149 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
150 "Accton MPX 5030/5038 10/100BaseTX" },
151 { DELTA_VENDORID, DELTA_DEVICEID_8139,
152 "Delta Electronics 8139 10/100BaseTX" },
153 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
154 "Addtron Technolgy 8139 10/100BaseTX" },
155 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
156 "D-Link DFE-530TX+ 10/100BaseTX" },
157 { DLINK_VENDORID, DLINK_DEVICEID_690TXD,
158 "D-Link DFE-690TX 10/100BaseTX" },
159 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
160 "Nortel Networks 10/100BaseTX" },
161 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
162 "Peppercon AG ROL/F" },
163 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD,
164 "Corega FEther CB-TXD" },
165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD,
166 "Corega FEtherII CB-TXD" },
167 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX,
168 "Planex FNW-3800-TX" },
172 static int rl_probe(device_t);
173 static int rl_attach(device_t);
174 static int rl_detach(device_t);
176 static int rl_encap(struct rl_softc *, struct mbuf * );
178 static void rl_rxeof(struct rl_softc *);
179 static void rl_txeof(struct rl_softc *);
180 static void rl_intr(void *);
181 static void rl_tick(void *);
182 static void rl_start(struct ifnet *);
183 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
184 static void rl_init(void *);
185 static void rl_stop (struct rl_softc *);
186 static void rl_watchdog(struct ifnet *);
187 static int rl_suspend(device_t);
188 static int rl_resume(device_t);
189 static void rl_shutdown(device_t);
190 static int rl_ifmedia_upd(struct ifnet *);
191 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
193 static void rl_eeprom_putbyte(struct rl_softc *, int);
194 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
195 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
196 static void rl_mii_sync(struct rl_softc *);
197 static void rl_mii_send(struct rl_softc *, uint32_t, int);
198 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
199 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
201 static int rl_miibus_readreg(device_t, int, int);
202 static int rl_miibus_writereg(device_t, int, int, int);
203 static void rl_miibus_statchg(device_t);
205 static void rl_setmulti(struct rl_softc *);
206 static void rl_reset(struct rl_softc *);
207 static void rl_list_tx_init(struct rl_softc *);
209 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
210 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
213 #define RL_RES SYS_RES_IOPORT
214 #define RL_RID RL_PCI_LOIO
216 #define RL_RES SYS_RES_MEMORY
217 #define RL_RID RL_PCI_LOMEM
220 static device_method_t rl_methods[] = {
221 /* Device interface */
222 DEVMETHOD(device_probe, rl_probe),
223 DEVMETHOD(device_attach, rl_attach),
224 DEVMETHOD(device_detach, rl_detach),
225 DEVMETHOD(device_suspend, rl_suspend),
226 DEVMETHOD(device_resume, rl_resume),
227 DEVMETHOD(device_shutdown, rl_shutdown),
230 DEVMETHOD(bus_print_child, bus_generic_print_child),
231 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
234 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
235 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
236 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
241 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
242 static devclass_t rl_devclass;
244 DECLARE_DUMMY_MODULE(if_rl);
245 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
246 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
247 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
248 MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
251 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
254 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
257 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
259 struct rl_softc *sc = arg;
261 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
265 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
267 struct rl_softc *sc = arg;
269 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
273 * Send a read command and address to the EEPROM, check for ACK.
276 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
280 d = addr | sc->rl_eecmd_read;
283 * Feed in each bit and strobe the clock.
285 for (i = 0x400; i; i >>= 1) {
287 EE_SET(RL_EE_DATAIN);
289 EE_CLR(RL_EE_DATAIN);
299 * Read a word of data stored in the EEPROM at address 'addr.'
302 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
307 /* Enter EEPROM access mode. */
308 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
311 * Send address of word we want to read.
313 rl_eeprom_putbyte(sc, addr);
315 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
318 * Start reading bits from EEPROM.
320 for (i = 0x8000; i; i >>= 1) {
323 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
329 /* Turn off EEPROM access mode. */
330 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
336 * Read a sequence of words from the EEPROM.
339 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
342 u_int16_t word = 0, *ptr;
344 for (i = 0; i < cnt; i++) {
345 rl_eeprom_getword(sc, off + i, &word);
346 ptr = (u_int16_t *)(dest + (i * 2));
356 * MII access routines are provided for the 8129, which
357 * doesn't have a built-in PHY. For the 8139, we fake things
358 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
359 * direct access PHY registers.
362 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
365 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
368 * Sync the PHYs by setting data bit and strobing the clock 32 times.
371 rl_mii_sync(struct rl_softc *sc)
375 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
377 for (i = 0; i < 32; i++) {
386 * Clock a series of bits through the MII.
389 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
395 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
397 MII_SET(RL_MII_DATAOUT);
399 MII_CLR(RL_MII_DATAOUT);
408 * Read an PHY register through the MII.
411 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
418 * Set up frame for RX.
420 frame->mii_stdelim = RL_MII_STARTDELIM;
421 frame->mii_opcode = RL_MII_READOP;
422 frame->mii_turnaround = 0;
425 CSR_WRITE_2(sc, RL_MII, 0);
435 * Send command/address info.
437 rl_mii_send(sc, frame->mii_stdelim, 2);
438 rl_mii_send(sc, frame->mii_opcode, 2);
439 rl_mii_send(sc, frame->mii_phyaddr, 5);
440 rl_mii_send(sc, frame->mii_regaddr, 5);
443 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
454 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
459 * Now try reading data bits. If the ack failed, we still
460 * need to clock through 16 cycles to keep the PHY(s) in sync.
463 for(i = 0; i < 16; i++) {
470 for (i = 0x8000; i; i >>= 1) {
474 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
475 frame->mii_data |= i;
494 * Write to a PHY register through the MII.
497 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
503 * Set up frame for TX.
506 frame->mii_stdelim = RL_MII_STARTDELIM;
507 frame->mii_opcode = RL_MII_WRITEOP;
508 frame->mii_turnaround = RL_MII_TURNAROUND;
511 * Turn on data output.
517 rl_mii_send(sc, frame->mii_stdelim, 2);
518 rl_mii_send(sc, frame->mii_opcode, 2);
519 rl_mii_send(sc, frame->mii_phyaddr, 5);
520 rl_mii_send(sc, frame->mii_regaddr, 5);
521 rl_mii_send(sc, frame->mii_turnaround, 2);
522 rl_mii_send(sc, frame->mii_data, 16);
541 rl_miibus_readreg(device_t dev, int phy, int reg)
544 struct rl_mii_frame frame;
546 uint16_t rl8139_reg = 0;
548 sc = device_get_softc(dev);
550 if (sc->rl_type == RL_8139) {
551 /* Pretend the internal PHY is only at address 0 */
556 rl8139_reg = RL_BMCR;
559 rl8139_reg = RL_BMSR;
562 rl8139_reg = RL_ANAR;
565 rl8139_reg = RL_ANER;
568 rl8139_reg = RL_LPAR;
575 * Allow the rlphy driver to read the media status
576 * register. If we have a link partner which does not
577 * support NWAY, this is the register which will tell
578 * us the results of parallel detection.
581 rval = CSR_READ_1(sc, RL_MEDIASTAT);
584 device_printf(dev, "bad phy register\n");
587 rval = CSR_READ_2(sc, rl8139_reg);
591 bzero(&frame, sizeof(frame));
593 frame.mii_phyaddr = phy;
594 frame.mii_regaddr = reg;
595 rl_mii_readreg(sc, &frame);
597 return(frame.mii_data);
601 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
604 struct rl_mii_frame frame;
605 u_int16_t rl8139_reg = 0;
607 sc = device_get_softc(dev);
609 if (sc->rl_type == RL_8139) {
610 /* Pretend the internal PHY is only at address 0 */
615 rl8139_reg = RL_BMCR;
618 rl8139_reg = RL_BMSR;
621 rl8139_reg = RL_ANAR;
624 rl8139_reg = RL_ANER;
627 rl8139_reg = RL_LPAR;
633 device_printf(dev, "bad phy register\n");
636 CSR_WRITE_2(sc, rl8139_reg, data);
640 bzero(&frame, sizeof(frame));
642 frame.mii_phyaddr = phy;
643 frame.mii_regaddr = reg;
644 frame.mii_data = data;
646 rl_mii_writereg(sc, &frame);
652 rl_miibus_statchg(device_t dev)
657 * Program the 64-bit multicast hash filter.
660 rl_setmulti(struct rl_softc *sc)
664 uint32_t hashes[2] = { 0, 0 };
665 struct ifmultiaddr *ifma;
669 ifp = &sc->arpcom.ac_if;
671 rxfilt = CSR_READ_4(sc, RL_RXCFG);
673 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
674 rxfilt |= RL_RXCFG_RX_MULTI;
675 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
676 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
677 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
681 /* first, zot all the existing hash bits */
682 CSR_WRITE_4(sc, RL_MAR0, 0);
683 CSR_WRITE_4(sc, RL_MAR4, 0);
685 /* now program new ones */
686 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
687 if (ifma->ifma_addr->sa_family != AF_LINK)
690 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
691 ETHER_ADDR_LEN >> 26);
693 hashes[0] |= (1 << h);
695 hashes[1] |= (1 << (h - 32));
700 rxfilt |= RL_RXCFG_RX_MULTI;
702 rxfilt &= ~RL_RXCFG_RX_MULTI;
704 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
705 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
706 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
710 rl_reset(struct rl_softc *sc)
714 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
716 for (i = 0; i < RL_TIMEOUT; i++) {
718 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
722 device_printf(sc->rl_dev, "reset never completed!\n");
726 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
727 * IDs against our list and return a device name if we find a match.
729 * Return with a value < 0 to give re(4) a change to attach.
732 rl_probe(device_t dev)
735 uint16_t product = pci_get_device(dev);
736 uint16_t vendor = pci_get_vendor(dev);
738 for (t = rl_devs; t->rl_name != NULL; t++) {
739 if (vendor == t->rl_vid && product == t->rl_did) {
740 device_set_desc(dev, t->rl_name);
749 * Attach the interface. Allocate softc structures, do ifmedia
750 * setup and ethernet/BPF attach.
753 rl_attach(device_t dev)
755 uint8_t eaddr[ETHER_ADDR_LEN];
760 int error = 0, rid, i;
762 sc = device_get_softc(dev);
766 * Handle power management nonsense.
769 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
770 uint32_t iobase, membase, irq;
772 /* Save important PCI config data. */
773 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
774 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
775 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
777 /* Reset the power state. */
778 device_printf(dev, "chip is is in D%d power mode "
779 "-- setting to D0\n", pci_get_powerstate(dev));
780 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
782 /* Restore PCI config data. */
783 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
784 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
785 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
789 * Map control/status registers.
791 pci_enable_busmaster(dev);
792 pci_enable_io(dev, RL_RES);
795 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
796 0, ~0, 1, RF_ACTIVE);
798 if (sc->rl_res == NULL) {
799 device_printf(dev, "couldn't map ports/memory\n");
804 sc->rl_btag = rman_get_bustag(sc->rl_res);
805 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
808 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
809 RF_SHAREABLE | RF_ACTIVE);
811 if (sc->rl_irq == NULL) {
812 device_printf(dev, "couldn't map interrupt\n");
817 callout_init(&sc->rl_stat_timer);
819 /* Reset the adapter. */
822 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
823 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
824 if (rl_did != 0x8129)
825 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
828 * Get station address from the EEPROM.
830 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
831 for (i = 0; i < 3; i++) {
832 eaddr[(i * 2) + 0] = as[i] & 0xff;
833 eaddr[(i * 2) + 1] = as[i] >> 8;
837 * Now read the exact device type from the EEPROM to find
838 * out if it's an 8129 or 8139.
840 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
842 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
843 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
844 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 ||
845 rl_did == DLINK_DEVICEID_690TXD ||
846 rl_did == COREGA_DEVICEID_FETHERCBTXD ||
847 rl_did == COREGA_DEVICEID_FETHERIICBTXD ||
848 rl_did == PLANEX_DEVICEID_FNW3800TX)
849 sc->rl_type = RL_8139;
850 else if (rl_did == RT_DEVICEID_8129)
851 sc->rl_type = RL_8129;
853 device_printf(dev, "unknown device ID: %x\n", rl_did);
858 #define RL_NSEG_NEW 32
859 error = bus_dma_tag_create(NULL, /* parent */
860 1, 0, /* alignment, boundary */
861 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
862 BUS_SPACE_MAXADDR, /* highaddr */
863 NULL, NULL, /* filter, filterarg */
864 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
865 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
866 BUS_DMA_ALLOCNOW, /* flags */
870 device_printf(dev, "can't create parent tag\n");
875 * Now allocate a tag for the DMA descriptor lists.
876 * All of our lists are allocated as a contiguous block
879 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
880 1, 0, /* alignment, boundary */
881 BUS_SPACE_MAXADDR, /* lowaddr */
882 BUS_SPACE_MAXADDR, /* highaddr */
883 NULL, NULL, /* filter, filterarg */
884 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */
885 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
890 device_printf(dev, "can't create RX tag\n");
895 * Now allocate a chunk of DMA-able memory based on the tag
898 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf,
899 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap);
902 device_printf(dev, "can't allocate RX memory!\n");
907 /* Leave a few bytes before the start of the RX ring buffer. */
908 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
909 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
912 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
914 device_printf(dev, "MII without any phy!\n");
919 ifp = &sc->arpcom.ac_if;
921 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
922 ifp->if_mtu = ETHERMTU;
923 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
924 ifp->if_ioctl = rl_ioctl;
925 ifp->if_start = rl_start;
926 ifp->if_watchdog = rl_watchdog;
927 ifp->if_init = rl_init;
928 ifp->if_baudrate = 10000000;
929 ifp->if_capabilities = IFCAP_VLAN_MTU;
930 #ifdef DEVICE_POLLING
931 ifp->if_capabilities |= IFCAP_POLLING;
933 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
936 * Call MI attach routine.
938 ether_ifattach(ifp, eaddr);
940 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, rl_intr,
941 sc, &sc->rl_intrhand);
944 device_printf(dev, "couldn't set up irq\n");
957 rl_detach(device_t dev)
963 sc = device_get_softc(dev);
964 ifp = &sc->arpcom.ac_if;
968 if (device_is_attached(dev)) {
974 device_delete_child(dev, sc->rl_miibus);
975 bus_generic_detach(dev);
978 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
982 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
984 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
986 if (sc->rl_cdata.rl_rx_buf) {
987 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
988 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
989 sc->rl_cdata.rl_rx_dmamap);
992 bus_dma_tag_destroy(sc->rl_tag);
993 if (sc->rl_parent_tag)
994 bus_dma_tag_destroy(sc->rl_parent_tag);
1000 * Initialize the transmit descriptors.
1003 rl_list_tx_init(struct rl_softc *sc)
1005 struct rl_chain_data *cd;
1009 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1010 cd->rl_tx_chain[i] = NULL;
1012 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1015 sc->rl_cdata.cur_tx = 0;
1016 sc->rl_cdata.last_tx = 0;
1020 * A frame has been uploaded: pass the resulting mbuf chain up to
1021 * the higher level protocols.
1023 * You know there's something wrong with a PCI bus-master chip design
1024 * when you have to use m_devget().
1026 * The receive operation is badly documented in the datasheet, so I'll
1027 * attempt to document it here. The driver provides a buffer area and
1028 * places its base address in the RX buffer start address register.
1029 * The chip then begins copying frames into the RX buffer. Each frame
1030 * is preceded by a 32-bit RX status word which specifies the length
1031 * of the frame and certain other status bits. Each frame (starting with
1032 * the status word) is also 32-bit aligned. The frame length is in the
1033 * first 16 bits of the status word; the lower 15 bits correspond with
1034 * the 'rx status register' mentioned in the datasheet.
1036 * Note: to make the Alpha happy, the frame payload needs to be aligned
1037 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1038 * the ring buffer starting at an address two bytes before the actual
1039 * data location. We can then shave off the first two bytes using m_adj().
1040 * The reason we do this is because m_devget() doesn't let us specify an
1041 * offset into the mbuf storage space, so we have to artificially create
1042 * one. The ring is allocated in such a way that there are a few unused
1043 * bytes of space preceecing it so that it will be safe for us to do the
1044 * 2-byte backstep even if reading from the ring at offset 0.
1047 rl_rxeof(struct rl_softc *sc)
1055 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0;
1057 ifp = &sc->arpcom.ac_if;
1059 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1060 BUS_DMASYNC_POSTREAD);
1062 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1064 /* Do not try to read past this point. */
1065 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1068 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1070 max_bytes = limit - cur_rx;
1072 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1073 #ifdef DEVICE_POLLING
1074 if (ifp->if_flags & IFF_POLLING) {
1075 if (sc->rxcycles <= 0)
1079 #endif /* DEVICE_POLLING */
1080 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1081 rxstat = le32toh(*(uint32_t *)rxbufpos);
1084 * Here's a totally undocumented fact for you. When the
1085 * RealTek chip is in the process of copying a packet into
1086 * RAM for you, the length will be 0xfff0. If you spot a
1087 * packet header with this value, you need to stop. The
1088 * datasheet makes absolutely no mention of this and
1089 * RealTek should be shot for this.
1091 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1094 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
1100 /* No errors; receive the packet. */
1101 total_len = rxstat >> 16;
1102 rx_bytes += total_len + 4;
1105 * XXX The RealTek chip includes the CRC with every
1106 * received frame, and there's no way to turn this
1107 * behavior off (at least, I can't find anything in
1108 * the manual that explains how to do it) so we have
1109 * to trim off the CRC manually.
1111 total_len -= ETHER_CRC_LEN;
1114 * Avoid trying to read more bytes than we know
1115 * the chip has prepared for us.
1117 if (rx_bytes > max_bytes)
1120 rxbufpos = sc->rl_cdata.rl_rx_buf +
1121 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1123 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1124 rxbufpos = sc->rl_cdata.rl_rx_buf;
1126 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1128 if (total_len > wrap) {
1130 * Fool m_devget() into thinking we want to copy
1131 * the whole buffer so we don't end up fragmenting
1134 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1135 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1139 m_adj(m, RL_ETHER_ALIGN);
1140 m_copyback(m, wrap, total_len - wrap,
1141 sc->rl_cdata.rl_rx_buf);
1143 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1145 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1146 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1150 m_adj(m, RL_ETHER_ALIGN);
1151 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1155 * Round up to 32-bit boundary.
1157 cur_rx = (cur_rx + 3) & ~3;
1158 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1165 (*ifp->if_input)(ifp, m);
1170 * A frame was downloaded to the chip. It's safe for us to clean up
1174 rl_txeof(struct rl_softc *sc)
1179 ifp = &sc->arpcom.ac_if;
1182 * Go through our tx list and free mbufs for those
1183 * frames that have been uploaded.
1186 if (RL_LAST_TXMBUF(sc) == NULL)
1188 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1189 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1190 RL_TXSTAT_TXABRT)) == 0)
1193 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1195 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1196 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1197 m_freem(RL_LAST_TXMBUF(sc));
1198 RL_LAST_TXMBUF(sc) = NULL;
1200 if ((txstat & RL_TXSTAT_TX_OK) == 0) {
1204 if ((txstat & RL_TXSTAT_TXABRT) ||
1205 (txstat & RL_TXSTAT_OUTOFWIN))
1206 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1207 oldthresh = sc->rl_txthresh;
1208 /* error recovery */
1212 * If there was a transmit underrun,
1213 * bump the TX threshold.
1215 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1216 sc->rl_txthresh = oldthresh + 32;
1220 RL_INC(sc->rl_cdata.last_tx);
1221 ifp->if_flags &= ~IFF_OACTIVE;
1222 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1224 if (RL_LAST_TXMBUF(sc) == NULL)
1226 else if (ifp->if_timer == 0)
1233 struct rl_softc *sc = xsc;
1234 struct mii_data *mii;
1239 mii = device_get_softc(sc->rl_miibus);
1244 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1247 #ifdef DEVICE_POLLING
1248 static poll_handler_t rl_poll;
1251 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1253 struct rl_softc *sc = ifp->if_softc;
1255 if ((ifp->if_capenable & IFCAP_POLLING) == 0) {
1256 ether_poll_deregister(ifp);
1257 cmd = POLL_DEREGISTER;
1259 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1260 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1264 sc->rxcycles = count;
1267 if (ifp->if_snd.ifq_head != NULL)
1270 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1273 status = CSR_READ_2(sc, RL_ISR);
1274 if (status == 0xffff)
1277 CSR_WRITE_2(sc, RL_ISR, status);
1280 * XXX check behaviour on receiver stalls.
1283 if (status & RL_ISR_SYSTEM_ERR) {
1289 #endif /* DEVICE_POLLING */
1294 struct rl_softc *sc;
1303 ifp = &sc->arpcom.ac_if;
1304 #ifdef DEVICE_POLLING
1305 if (ifp->if_flags & IFF_POLLING)
1307 if ((ifp->if_capenable & IFCAP_POLLING) &&
1308 ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1309 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1313 #endif /* DEVICE_POLLING */
1316 status = CSR_READ_2(sc, RL_ISR);
1317 /* If the card has gone away, the read returns 0xffff. */
1318 if (status == 0xffff)
1322 CSR_WRITE_2(sc, RL_ISR, status);
1324 if ((status & RL_INTRS) == 0)
1327 if (status & RL_ISR_RX_OK)
1330 if (status & RL_ISR_RX_ERR)
1333 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1336 if (status & RL_ISR_SYSTEM_ERR) {
1343 if (ifp->if_snd.ifq_head != NULL)
1348 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1349 * pointers to the fragment pointers.
1352 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1354 struct mbuf *m_new = NULL;
1357 * The RealTek is brain damaged and wants longword-aligned
1358 * TX buffers, plus we can only have one fragment buffer
1359 * per packet. We have to copy pretty much all the time.
1361 m_new = m_defrag(m_head, MB_DONTWAIT);
1363 if (m_new == NULL) {
1369 /* Pad frames to at least 60 bytes. */
1370 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1372 * Make security concious people happy: zero out the
1373 * bytes in the pad area, since we don't know what
1374 * this mbuf cluster buffer's previous user might
1377 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1378 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1379 m_head->m_pkthdr.len +=
1380 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1381 m_head->m_len = m_head->m_pkthdr.len;
1384 RL_CUR_TXMBUF(sc) = m_head;
1390 * Main transmit routine.
1394 rl_start(struct ifnet *ifp)
1396 struct rl_softc *sc;
1397 struct mbuf *m_head = NULL;
1401 while(RL_CUR_TXMBUF(sc) == NULL) {
1402 IF_DEQUEUE(&ifp->if_snd, m_head);
1406 if (rl_encap(sc, m_head))
1410 * If there's a BPF listener, bounce a copy of this frame
1413 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1416 * Transmit the frame.
1418 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1419 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1420 mtod(RL_CUR_TXMBUF(sc), void *),
1421 RL_CUR_TXMBUF(sc)->m_pkthdr.len,
1422 rl_dma_map_txbuf, sc, 0);
1423 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1424 BUS_DMASYNC_PREREAD);
1425 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1426 RL_TXTHRESH(sc->rl_txthresh) |
1427 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1429 RL_INC(sc->rl_cdata.cur_tx);
1432 * Set a timeout in case the chip goes out to lunch.
1438 * We broke out of the loop because all our TX slots are
1439 * full. Mark the NIC as busy until it drains some of the
1440 * packets from the queue.
1442 if (RL_CUR_TXMBUF(sc) != NULL)
1443 ifp->if_flags |= IFF_OACTIVE;
1449 struct rl_softc *sc = xsc;
1450 struct ifnet *ifp = &sc->arpcom.ac_if;
1451 struct mii_data *mii;
1457 mii = device_get_softc(sc->rl_miibus);
1460 * Cancel pending I/O and free all RX/TX buffers.
1465 * Init our MAC address. Even though the chipset documentation
1466 * doesn't mention it, we need to enter "Config register write enable"
1467 * mode to modify the ID registers.
1469 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1470 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1471 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1472 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1473 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1474 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1476 /* Init the RX buffer pointer register. */
1477 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1478 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf,
1480 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1481 BUS_DMASYNC_PREWRITE);
1483 /* Init TX descriptors. */
1484 rl_list_tx_init(sc);
1487 * Enable transmit and receive.
1489 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1492 * Set the initial TX and RX configuration.
1494 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1495 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1497 /* Set the individual bit to receive frames for this host only. */
1498 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1499 rxcfg |= RL_RXCFG_RX_INDIV;
1501 /* If we want promiscuous mode, set the allframes bit. */
1502 if (ifp->if_flags & IFF_PROMISC) {
1503 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1504 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1506 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1507 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1511 * Set capture broadcast bit to capture broadcast frames.
1513 if (ifp->if_flags & IFF_BROADCAST) {
1514 rxcfg |= RL_RXCFG_RX_BROAD;
1515 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1517 rxcfg &= ~RL_RXCFG_RX_BROAD;
1518 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1522 * Program the multicast filter, if necessary.
1526 #ifdef DEVICE_POLLING
1528 * Only enable interrupts if we are polling, keep them off otherwise.
1530 if (ifp->if_flags & IFF_POLLING)
1531 CSR_WRITE_2(sc, RL_IMR, 0);
1533 #endif /* DEVICE_POLLING */
1535 * Enable interrupts.
1537 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1539 /* Set initial TX threshold */
1540 sc->rl_txthresh = RL_TX_THRESH_INIT;
1542 /* Start RX/TX process. */
1543 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1545 /* Enable receiver and transmitter. */
1546 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1550 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1552 ifp->if_flags |= IFF_RUNNING;
1553 ifp->if_flags &= ~IFF_OACTIVE;
1557 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1561 * Set media options.
1564 rl_ifmedia_upd(struct ifnet *ifp)
1566 struct rl_softc *sc;
1567 struct mii_data *mii;
1570 mii = device_get_softc(sc->rl_miibus);
1577 * Report current media status.
1580 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1582 struct rl_softc *sc = ifp->if_softc;
1583 struct mii_data *mii = device_get_softc(sc->rl_miibus);
1586 ifmr->ifm_active = mii->mii_media_active;
1587 ifmr->ifm_status = mii->mii_media_status;
1591 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1593 struct rl_softc *sc = ifp->if_softc;
1594 struct ifreq *ifr = (struct ifreq *) data;
1595 struct mii_data *mii;
1602 if (ifp->if_flags & IFF_UP) {
1605 if (ifp->if_flags & IFF_RUNNING)
1617 mii = device_get_softc(sc->rl_miibus);
1618 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1621 ifp->if_capenable &= ~IFCAP_POLLING;
1622 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
1625 error = ether_ioctl(ifp, command, data);
1635 rl_watchdog(struct ifnet *ifp)
1637 struct rl_softc *sc = ifp->if_softc;
1642 device_printf(sc->rl_dev, "watchdog timeout\n");
1653 * Stop the adapter and free any mbufs allocated to the
1657 rl_stop(struct rl_softc *sc)
1659 struct ifnet *ifp = &sc->arpcom.ac_if;
1664 callout_stop(&sc->rl_stat_timer);
1665 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1666 #ifdef DEVICE_POLLING
1667 ether_poll_deregister(ifp);
1668 #endif /* DEVICE_POLLING */
1670 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1671 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1672 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1675 * Free the TX list buffers.
1677 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1678 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1679 bus_dmamap_unload(sc->rl_tag,
1680 sc->rl_cdata.rl_tx_dmamap[i]);
1681 bus_dmamap_destroy(sc->rl_tag,
1682 sc->rl_cdata.rl_tx_dmamap[i]);
1683 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1684 sc->rl_cdata.rl_tx_chain[i] = NULL;
1685 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1692 * Stop all chip I/O so that the kernel's probe routines don't
1693 * get confused by errant DMAs when rebooting.
1696 rl_shutdown(device_t dev)
1698 struct rl_softc *sc;
1700 sc = device_get_softc(dev);
1706 * Device suspend routine. Stop the interface and save some PCI
1707 * settings in case the BIOS doesn't restore them properly on
1711 rl_suspend(device_t dev)
1713 struct rl_softc *sc = device_get_softc(dev);
1718 for (i = 0; i < 5; i++)
1719 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
1720 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1721 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1722 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1723 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1731 * Device resume routine. Restore some PCI settings in case the BIOS
1732 * doesn't, re-enable busmastering, and restart the interface if
1735 static int rl_resume(device_t dev)
1737 struct rl_softc *sc = device_get_softc(dev);
1738 struct ifnet *ifp = &sc->arpcom.ac_if;
1741 /* better way to do this? */
1742 for (i = 0; i < 5; i++)
1743 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1744 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1745 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1746 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1747 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1749 /* reenable busmastering */
1750 pci_enable_busmaster(dev);
1751 pci_enable_io(dev, RL_RES);
1753 /* reinitialize interface if necessary */
1754 if (ifp->if_flags & IFF_UP)