2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.2 2003/06/17 04:28:22 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <machine/clock.h>
47 #include <machine/md_var.h>
50 #include <pci/pcivar.h>
51 #include <pci/pcireg.h>
52 #include <dev/ata/ata-all.h>
54 /* device structures */
55 struct ata_pci_controller {
56 struct resource *bmio;
63 #define IOMASK 0xfffffffc
64 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
65 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
66 (pci_get_progif(dev) & 0x05) != 0x05)
69 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
74 if (device_get_children(device_get_parent(dev), &children, &nchildren))
77 for (i = 0; i < nchildren; i++) {
78 if (pci_get_devid(children[i]) == devid &&
79 pci_get_revid(children[i]) >= revid) {
80 free(children, M_TEMP);
84 free(children, M_TEMP);
89 ata_via_southbridge_fixup(device_t dev)
94 if (device_get_children(device_get_parent(dev), &children, &nchildren))
97 for (i = 0; i < nchildren; i++) {
98 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
99 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
100 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
101 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
102 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
104 if ((reg76 & 0xf0) != 0xd0) {
106 "Correcting VIA config for southbridge data corruption bug\n");
107 pci_write_config(children[i], 0x75, 0x80, 1);
108 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
113 free(children, M_TEMP);
117 ata_pci_match(device_t dev)
119 if (pci_get_class(dev) != PCIC_STORAGE)
122 switch (pci_get_devid(dev)) {
123 /* supported chipsets */
125 return "Intel PIIX ATA controller";
128 return "Intel PIIX3 ATA controller";
133 return "Intel PIIX4 ATA33 controller";
136 return "Intel ICH0 ATA33 controller";
140 return "Intel ICH ATA66 controller";
144 return "Intel ICH2 ATA100 controller";
148 return "Intel ICH3 ATA100 controller";
151 return "Intel ICH4 ATA100 controller";
154 return "Intel ICH5 ATA100 controller";
157 if (pci_get_revid(dev) >= 0xc4)
158 return "AcerLabs Aladdin ATA100 controller";
159 else if (pci_get_revid(dev) >= 0xc2)
160 return "AcerLabs Aladdin ATA66 controller";
161 else if (pci_get_revid(dev) >= 0x20)
162 return "AcerLabs Aladdin ATA33 controller";
164 return "AcerLabs Aladdin ATA controller";
167 if (ata_find_dev(dev, 0x05861106, 0x02))
168 return "VIA 82C586 ATA33 controller";
169 if (ata_find_dev(dev, 0x05861106, 0))
170 return "VIA 82C586 ATA controller";
171 if (ata_find_dev(dev, 0x05961106, 0x12))
172 return "VIA 82C596 ATA66 controller";
173 if (ata_find_dev(dev, 0x05961106, 0))
174 return "VIA 82C596 ATA33 controller";
175 if (ata_find_dev(dev, 0x06861106, 0x40))
176 return "VIA 82C686 ATA100 controller";
177 if (ata_find_dev(dev, 0x06861106, 0x10))
178 return "VIA 82C686 ATA66 controller";
179 if (ata_find_dev(dev, 0x06861106, 0))
180 return "VIA 82C686 ATA33 controller";
181 if (ata_find_dev(dev, 0x82311106, 0))
182 return "VIA 8231 ATA100 controller";
183 if (ata_find_dev(dev, 0x30741106, 0) ||
184 ata_find_dev(dev, 0x31091106, 0))
185 return "VIA 8233 ATA100 controller";
186 if (ata_find_dev(dev, 0x31471106, 0))
187 return "VIA 8233 ATA133 controller";
188 if (ata_find_dev(dev, 0x31771106, 0))
189 return "VIA 8235 ATA133 controller";
190 return "VIA Apollo ATA controller";
193 if (ata_find_dev(dev, 0x06301039, 0x30) ||
194 ata_find_dev(dev, 0x06331039, 0) ||
195 ata_find_dev(dev, 0x06351039, 0) ||
196 ata_find_dev(dev, 0x06401039, 0) ||
197 ata_find_dev(dev, 0x06451039, 0) ||
198 ata_find_dev(dev, 0x06501039, 0) ||
199 ata_find_dev(dev, 0x07301039, 0) ||
200 ata_find_dev(dev, 0x07331039, 0) ||
201 ata_find_dev(dev, 0x07351039, 0) ||
202 ata_find_dev(dev, 0x07401039, 0) ||
203 ata_find_dev(dev, 0x07451039, 0) ||
204 ata_find_dev(dev, 0x07501039, 0))
205 return "SiS 5591 ATA100 controller";
206 else if (ata_find_dev(dev, 0x05301039, 0) ||
207 ata_find_dev(dev, 0x05401039, 0) ||
208 ata_find_dev(dev, 0x06201039, 0) ||
209 ata_find_dev(dev, 0x06301039, 0))
210 return "SiS 5591 ATA66 controller";
212 return "SiS 5591 ATA33 controller";
215 return "SiI 0680 ATA133 controller";
218 return "CMD 649 ATA100 controller";
221 return "CMD 648 ATA66 controller";
224 return "CMD 646 ATA controller";
227 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
228 return "Cypress 82C693 ATA controller";
232 return "Cyrix 5530 ATA33 controller";
235 return "AMD 756 ATA66 controller";
238 return "AMD 766 ATA100 controller";
241 return "AMD 768 ATA100 controller";
244 return "nVIDIA nForce ATA100 controller";
247 return "ServerWorks ROSB4 ATA33 controller";
250 if (pci_get_revid(dev) >= 0x92)
251 return "ServerWorks CSB5 ATA100 controller";
253 return "ServerWorks CSB5 ATA66 controller";
256 return "Promise ATA33 controller";
260 return "Promise ATA66 controller";
264 return "Promise ATA100 controller";
268 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
269 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
270 static long start = 0, end = 0;
272 /* we belive we are on a TX4, now do our (simple) magic */
273 if (pci_get_slot(dev) == 1) {
274 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
275 return "Promise TX4 ATA100 controller (channel 0+1)";
277 else if (pci_get_slot(dev) == 2 && start && end) {
278 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
280 return "Promise TX4 ATA100 controller (channel 2+3)";
285 return "Promise TX2 ATA100 controller";
291 return "Promise TX2 ATA133 controller";
294 switch (pci_get_revid(dev)) {
297 return "HighPoint HPT366 ATA66 controller";
299 return "HighPoint HPT368 ATA66 controller";
302 return "HighPoint HPT370 ATA100 controller";
304 return "HighPoint HPT372 ATA133 controller";
309 switch (pci_get_revid(dev)) {
312 return "HighPoint HPT372 ATA133 controller";
317 switch (pci_get_revid(dev)) {
319 return "HighPoint HPT374 ATA133 controller";
324 return "Cenatek Rocket Drive controller";
326 /* unsupported but known chipsets, generic DMA only */
329 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
332 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
334 /* unknown chipsets, try generic DMA if it seems possible */
336 if (pci_get_class(dev) == PCIC_STORAGE &&
337 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
338 return "Generic PCI ATA controller";
344 ata_pci_probe(device_t dev)
346 const char *desc = ata_pci_match(dev);
349 device_set_desc(dev, desc);
357 ata_pci_add_child(device_t dev, int unit)
361 /* check if this is located at one of the std addresses */
362 if (ATA_MASTERDEV(dev)) {
363 if (!(child = device_add_child(dev, "ata", unit)))
367 if (!(child = device_add_child(dev, "ata", 2)))
374 ata_pci_attach(device_t dev)
376 struct ata_pci_controller *controller = device_get_softc(dev);
377 u_int8_t class, subclass;
381 /* set up vendor-specific stuff */
382 type = pci_get_devid(dev);
383 class = pci_get_class(dev);
384 subclass = pci_get_subclass(dev);
385 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
387 if (!(cmd & PCIM_CMD_PORTEN)) {
388 device_printf(dev, "ATA channel disabled by BIOS\n");
392 /* is busmastering supported ? */
393 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
394 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
396 /* is there a valid port range to connect to ? */
398 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
399 0, ~0, 1, RF_ACTIVE);
400 if (!controller->bmio)
401 device_printf(dev, "Busmastering DMA not configured\n");
404 device_printf(dev, "Busmastering DMA not supported\n");
406 /* do extra chipset specific setups */
408 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
409 pci_write_config(dev, 0x53,
410 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
413 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
416 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
419 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
420 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
423 case 0x00041103: /* HighPoint HPT366/368/370/372 */
424 if (pci_get_revid(dev) < 2) { /* HPT 366 */
425 /* turn off interrupt prediction */
426 pci_write_config(dev, 0x51,
427 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
430 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
431 /* turn off interrupt prediction */
432 pci_write_config(dev, 0x51,
433 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
434 pci_write_config(dev, 0x55,
435 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
437 /* turn on interrupts */
438 pci_write_config(dev, 0x5a,
439 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
442 pci_write_config(dev, 0x5b, 0x22, 1);
447 case 0x00051103: /* HighPoint HPT372 */
448 case 0x00081103: /* HighPoint HPT374 */
449 /* turn off interrupt prediction */
450 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
451 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
453 /* turn on interrupts */
454 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
457 pci_write_config(dev, 0x5b,
458 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
461 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
462 /* prepare for ATA-66 on the 82C686a and 82C596b */
463 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
464 !ata_find_dev(dev, 0x06861106, 0x40)) ||
465 ata_find_dev(dev, 0x05961106, 0x12))
466 pci_write_config(dev, 0x50, 0x030b030b, 4);
468 /* the southbridge might need the data corruption fix */
469 if (ata_find_dev(dev, 0x06861106, 0x40) ||
470 ata_find_dev(dev, 0x82311106, 0x10))
471 ata_via_southbridge_fixup(dev);
474 case 0x74091022: /* AMD 756 default setup */
475 case 0x74111022: /* AMD 766 default setup */
476 case 0x74411022: /* AMD 768 default setup */
477 case 0x01bc10de: /* nVIDIA nForce default setup */
478 /* set prefetch, postwrite */
479 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
481 /* set fifo configuration half'n'half */
482 pci_write_config(dev, 0x43,
483 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
485 /* set status register read retry */
486 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
488 /* set DMA read & end-of-sector fifo flush */
489 pci_write_config(dev, 0x46,
490 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
492 /* set sector size */
493 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
494 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
497 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
498 pci_write_config(dev, 0x64,
499 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
503 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
504 pci_write_config(dev, 0x5a,
505 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
506 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
509 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
510 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
511 pci_write_config(dev, 0x8a,
512 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
513 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
514 device_printf(dev, "SiI 0680 could not set clock\n");
519 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
520 pci_write_config(dev, 0x71, 0x01, 1);
523 case 0x10001042: /* RZ 100? known bad, no DMA */
525 case 0x06401095: /* CMD 640 known bad, no DMA */
526 controller->bmio = NULL;
527 device_printf(dev, "Busmastering DMA disabled\n");
530 if (controller->bmio) {
531 controller->bmaddr = rman_get_start(controller->bmio);
532 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
533 SYS_RES_IOPORT, rid, controller->bmio);
534 controller->bmio = NULL;
538 * the Cypress chip is a mess, it contains two ATA functions, but
539 * both channels are visible on the first one.
540 * simply ignore the second function for now, as the right
541 * solution (ignoring the second channel on the first function)
542 * doesn't work with the crappy ATA interrupt setup on the alpha.
544 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
547 ata_pci_add_child(dev, 0);
549 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
550 ata_pci_add_child(dev, 1);
552 return bus_generic_attach(dev);
556 ata_pci_intr(struct ata_channel *ch)
561 * since we might share the IRQ with another device, and in some
562 * cases with our twin channel, we only want to process interrupts
563 * that we know this channel generated.
565 switch (ch->chiptype) {
566 case 0x00041103: /* HighPoint HPT366/368/370/372 */
567 case 0x00051103: /* HighPoint HPT372 */
568 case 0x00081103: /* HighPoint HPT374 */
569 if (((dmastat = ata_dmastatus(ch)) &
570 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
572 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
576 case 0x06481095: /* CMD 648 */
577 case 0x06491095: /* CMD 649 */
578 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
579 (ch->unit ? 0x08 : 0x04)))
583 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
584 case 0x0d38105a: /* Promise Fasttrak 66 */
585 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
586 case 0x0d30105a: /* Promise OEM ATA100 */
587 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
588 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
589 (ch->unit ? 0x00004000 : 0x00000400)))
593 case 0x4d68105a: /* Promise TX2 ATA100 */
594 case 0x6268105a: /* Promise TX2 ATA100 */
595 case 0x4d69105a: /* Promise TX2 ATA133 */
596 case 0x5275105a: /* Promise TX2 ATA133 */
597 case 0x6269105a: /* Promise TX2 ATA133 */
598 case 0x7275105a: /* Promise TX2 ATA133 */
599 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
600 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
605 if (ch->flags & ATA_DMA_ACTIVE) {
606 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
608 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
615 ata_pci_print_child(device_t dev, device_t child)
617 struct ata_channel *ch = device_get_softc(child);
620 retval += bus_print_child_header(dev, child);
621 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
623 if (ATA_MASTERDEV(dev))
624 retval += printf(" irq %d", 14 + ch->unit);
626 retval += bus_print_child_footer(dev, child);
631 static struct resource *
632 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
633 u_long start, u_long end, u_long count, u_int flags)
635 struct ata_pci_controller *controller = device_get_softc(dev);
636 struct resource *res = NULL;
637 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
640 if (type == SYS_RES_IOPORT) {
643 if (ATA_MASTERDEV(dev)) {
645 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
646 end = start + ATA_IOSIZE - 1;
648 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
649 SYS_RES_IOPORT, &myrid,
650 start, end, count, flags);
653 myrid = 0x10 + 8 * unit;
654 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
655 SYS_RES_IOPORT, &myrid,
656 start, end, count, flags);
660 case ATA_ALTADDR_RID:
661 if (ATA_MASTERDEV(dev)) {
663 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
664 end = start + ATA_ALTIOSIZE - 1;
665 count = ATA_ALTIOSIZE;
666 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
667 SYS_RES_IOPORT, &myrid,
668 start, end, count, flags);
671 myrid = 0x14 + 8 * unit;
672 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
673 SYS_RES_IOPORT, &myrid,
674 start, end, count, flags);
676 start = rman_get_start(res) + 2;
677 end = rman_get_start(res) + ATA_ALTIOSIZE - 1;
678 count = ATA_ALTIOSIZE;
679 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
680 SYS_RES_IOPORT, myrid, res);
681 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
682 SYS_RES_IOPORT, &myrid,
683 start, end, count, flags);
689 if (controller->bmaddr) {
692 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
693 end = start + ATA_BMIOSIZE - 1;
694 count = ATA_BMIOSIZE;
695 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
696 SYS_RES_IOPORT, &myrid,
697 start, end, count, flags);
703 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
704 if (ATA_MASTERDEV(dev)) {
706 return alpha_platform_alloc_ide_intr(unit);
708 int irq = (unit == 0 ? 14 : 15);
710 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
711 SYS_RES_IRQ, rid, irq, irq, 1, flags);
715 /* primary and secondary channels share interrupt, keep track */
716 if (!controller->irq)
717 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
719 rid, 0, ~0, 1, flags);
720 controller->irqcnt++;
721 return controller->irq;
728 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
731 struct ata_pci_controller *controller = device_get_softc(dev);
732 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
734 if (type == SYS_RES_IOPORT) {
737 if (ATA_MASTERDEV(dev))
738 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
739 SYS_RES_IOPORT, 0x0, r);
741 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
742 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
745 case ATA_ALTADDR_RID:
746 if (ATA_MASTERDEV(dev))
747 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
748 SYS_RES_IOPORT, 0x0, r);
750 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
751 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
755 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
756 SYS_RES_IOPORT, 0x20, r);
761 if (type == SYS_RES_IRQ) {
762 if (rid != ATA_IRQ_RID)
765 if (ATA_MASTERDEV(dev)) {
767 return alpha_platform_release_ide_intr(unit, r);
769 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
770 SYS_RES_IRQ, rid, r);
774 /* primary and secondary channels share interrupt, keep track */
775 if (--controller->irqcnt)
777 controller->irq = NULL;
778 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
779 SYS_RES_IRQ, rid, r);
786 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
787 int flags, driver_intr_t *intr, void *arg,
790 if (ATA_MASTERDEV(dev)) {
792 return alpha_platform_setup_ide_intr(irq, intr, arg, cookiep);
794 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
795 flags, intr, arg, cookiep);
799 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
800 flags, intr, arg, cookiep);
804 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
807 if (ATA_MASTERDEV(dev)) {
809 return alpha_platform_teardown_ide_intr(irq, cookie);
811 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
815 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
818 static device_method_t ata_pci_methods[] = {
819 /* device interface */
820 DEVMETHOD(device_probe, ata_pci_probe),
821 DEVMETHOD(device_attach, ata_pci_attach),
822 DEVMETHOD(device_shutdown, bus_generic_shutdown),
823 DEVMETHOD(device_suspend, bus_generic_suspend),
824 DEVMETHOD(device_resume, bus_generic_resume),
827 DEVMETHOD(bus_print_child, ata_pci_print_child),
828 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
829 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
830 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
831 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
832 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
833 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
837 static driver_t ata_pci_driver = {
840 sizeof(struct ata_pci_controller),
843 static devclass_t ata_pci_devclass;
845 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
848 ata_pcisub_probe(device_t dev)
850 struct ata_channel *ch = device_get_softc(dev);
854 /* find channel number on this controller */
855 device_get_children(device_get_parent(dev), &children, &count);
856 for (i = 0; i < count; i++) {
857 if (children[i] == dev)
860 free(children, M_TEMP);
861 ch->chiptype = pci_get_devid(device_get_parent(dev));
862 ch->intr_func = ata_pci_intr;
863 return ata_probe(dev);
866 static device_method_t ata_pcisub_methods[] = {
867 /* device interface */
868 DEVMETHOD(device_probe, ata_pcisub_probe),
869 DEVMETHOD(device_attach, ata_attach),
870 DEVMETHOD(device_detach, ata_detach),
871 DEVMETHOD(device_resume, ata_resume),
875 static driver_t ata_pcisub_driver = {
878 sizeof(struct ata_channel),
881 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);