1 /* $FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.5.2.5 2003/06/04 17:56:59 sam Exp $ */
2 /* $DragonFly: src/sys/dev/crypto/hifn/hifn7751.c,v 1.5 2003/11/20 22:07:22 dillon Exp $ */
3 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */
6 * Invertex AEON / Hifn 7751 driver
7 * Copyright (c) 1999 Invertex Inc. All rights reserved.
8 * Copyright (c) 1999 Theo de Raadt
9 * Copyright (c) 2000-2001 Network Security Technologies, Inc.
10 * http://www.netsec.net
12 * This driver is based on a previous driver by Invertex, for which they
13 * requested: Please send any comments, feedback, bug-fixes, or feature
14 * requests to software@invertex.com.
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. The name of the author may not be used to endorse or promote products
26 * derived from this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * Effort sponsored in part by the Defense Advanced Research Projects
40 * Agency (DARPA) and Air Force Research Laboratory, Air Force
41 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
46 * Driver for the Hifn 7751 encryption processor.
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
57 #include <sys/sysctl.h>
62 #include <machine/clock.h>
63 #include <machine/bus.h>
64 #include <machine/resource.h>
68 #include <opencrypto/cryptodev.h>
69 #include <sys/random.h>
71 #include <bus/pci/pcivar.h>
72 #include <bus/pci/pcireg.h>
75 #include "../rndtest/rndtest.h"
77 #include "hifn7751reg.h"
78 #include "hifn7751var.h"
81 * Prototypes and count for the pci_device structure
83 static int hifn_probe(device_t);
84 static int hifn_attach(device_t);
85 static int hifn_detach(device_t);
86 static int hifn_suspend(device_t);
87 static int hifn_resume(device_t);
88 static void hifn_shutdown(device_t);
90 static device_method_t hifn_methods[] = {
91 /* Device interface */
92 DEVMETHOD(device_probe, hifn_probe),
93 DEVMETHOD(device_attach, hifn_attach),
94 DEVMETHOD(device_detach, hifn_detach),
95 DEVMETHOD(device_suspend, hifn_suspend),
96 DEVMETHOD(device_resume, hifn_resume),
97 DEVMETHOD(device_shutdown, hifn_shutdown),
100 DEVMETHOD(bus_print_child, bus_generic_print_child),
101 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
105 static driver_t hifn_driver = {
108 sizeof (struct hifn_softc)
110 static devclass_t hifn_devclass;
112 DECLARE_DUMMY_MODULE(hifn);
113 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0);
114 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
116 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
119 static void hifn_reset_board(struct hifn_softc *, int);
120 static void hifn_reset_puc(struct hifn_softc *);
121 static void hifn_puc_wait(struct hifn_softc *);
122 static int hifn_enable_crypto(struct hifn_softc *);
123 static void hifn_set_retry(struct hifn_softc *sc);
124 static void hifn_init_dma(struct hifn_softc *);
125 static void hifn_init_pci_registers(struct hifn_softc *);
126 static int hifn_sramsize(struct hifn_softc *);
127 static int hifn_dramsize(struct hifn_softc *);
128 static int hifn_ramtype(struct hifn_softc *);
129 static void hifn_sessions(struct hifn_softc *);
130 static void hifn_intr(void *);
131 static u_int hifn_write_command(struct hifn_command *, u_int8_t *);
132 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
133 static int hifn_newsession(void *, u_int32_t *, struct cryptoini *);
134 static int hifn_freesession(void *, u_int64_t);
135 static int hifn_process(void *, struct cryptop *, int);
136 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
137 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
138 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
139 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
140 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
141 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
142 static int hifn_init_pubrng(struct hifn_softc *);
144 static void hifn_rng(void *);
146 static void hifn_tick(void *);
147 static void hifn_abort(struct hifn_softc *);
148 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
150 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
151 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
153 static __inline__ u_int32_t
154 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
156 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
157 sc->sc_bar0_lastreg = (bus_size_t) -1;
160 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val)
162 static __inline__ u_int32_t
163 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
165 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
166 sc->sc_bar1_lastreg = (bus_size_t) -1;
169 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val)
171 SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters");
174 static int hifn_debug = 0;
175 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
176 0, "control debugging msgs");
179 static struct hifn_stats hifnstats;
180 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
181 hifn_stats, "driver statistics");
182 static int hifn_maxbatch = 1;
183 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
184 0, "max ops to batch w/o interrupt");
187 * Probe for a supported device. The PCI vendor and device
188 * IDs are used to detect devices we know how to handle.
191 hifn_probe(device_t dev)
193 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
194 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
196 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
197 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
198 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
199 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
201 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
202 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
208 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
210 bus_addr_t *paddr = (bus_addr_t*) arg;
211 *paddr = segs->ds_addr;
215 hifn_partname(struct hifn_softc *sc)
217 /* XXX sprintf numbers when not decoded */
218 switch (pci_get_vendor(sc->sc_dev)) {
219 case PCI_VENDOR_HIFN:
220 switch (pci_get_device(sc->sc_dev)) {
221 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500";
222 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751";
223 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811";
224 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951";
226 return "Hifn unknown-part";
227 case PCI_VENDOR_INVERTEX:
228 switch (pci_get_device(sc->sc_dev)) {
229 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
231 return "Invertex unknown-part";
232 case PCI_VENDOR_NETSEC:
233 switch (pci_get_device(sc->sc_dev)) {
234 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751";
236 return "NetSec unknown-part";
238 return "Unknown-vendor unknown-part";
242 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
244 u_int32_t *p = (u_int32_t *)buf;
245 for (count /= sizeof (u_int32_t); count; count--)
246 add_true_randomness(*p++);
250 * Attach an interface that successfully probed.
253 hifn_attach(device_t dev)
255 struct hifn_softc *sc = device_get_softc(dev);
262 KASSERT(sc != NULL, ("hifn_attach: null software carrier!"));
263 bzero(sc, sizeof (*sc));
266 /* XXX handle power management */
269 * The 7951 has a random number generator and
270 * public key support; note this.
272 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
273 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951)
274 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
276 * The 7811 has a random number generator and
277 * we also note it's identity 'cuz of some quirks.
279 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
280 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
281 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
284 * Configure support for memory-mapped access to
285 * registers and for DMA operations.
287 #define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN)
288 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
290 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
291 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
292 if ((cmd & PCIM_ENA) != PCIM_ENA) {
293 device_printf(dev, "failed to enable %s\n",
294 (cmd & PCIM_ENA) == 0 ?
295 "memory mapping & bus mastering" :
296 (cmd & PCIM_CMD_MEMEN) == 0 ?
297 "memory mapping" : "bus mastering");
303 * Setup PCI resources. Note that we record the bus
304 * tag and handle for each register mapping, this is
305 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
306 * and WRITE_REG_1 macros throughout the driver.
309 sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
310 0, ~0, 1, RF_ACTIVE);
311 if (sc->sc_bar0res == NULL) {
312 device_printf(dev, "cannot map bar%d register space\n", 0);
315 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
316 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
317 sc->sc_bar0_lastreg = (bus_size_t) -1;
320 sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
321 0, ~0, 1, RF_ACTIVE);
322 if (sc->sc_bar1res == NULL) {
323 device_printf(dev, "cannot map bar%d register space\n", 1);
326 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
327 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
328 sc->sc_bar1_lastreg = (bus_size_t) -1;
333 * Setup the area where the Hifn DMA's descriptors
334 * and associated data structures.
336 if (bus_dma_tag_create(NULL, /* parent */
337 1, 0, /* alignment,boundary */
338 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
339 BUS_SPACE_MAXADDR, /* highaddr */
340 NULL, NULL, /* filter, filterarg */
341 HIFN_MAX_DMALEN, /* maxsize */
342 MAX_SCATTER, /* nsegments */
343 HIFN_MAX_SEGLEN, /* maxsegsize */
344 BUS_DMA_ALLOCNOW, /* flags */
346 device_printf(dev, "cannot allocate DMA tag\n");
349 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
350 device_printf(dev, "cannot create dma map\n");
351 bus_dma_tag_destroy(sc->sc_dmat);
354 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
355 device_printf(dev, "cannot alloc dma buffer\n");
356 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
357 bus_dma_tag_destroy(sc->sc_dmat);
360 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
361 sizeof (*sc->sc_dma),
362 hifn_dmamap_cb, &sc->sc_dma_physaddr,
364 device_printf(dev, "cannot load dma map\n");
365 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
366 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
367 bus_dma_tag_destroy(sc->sc_dmat);
370 sc->sc_dma = (struct hifn_dma *)kva;
371 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
373 KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!"));
374 KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!"));
375 KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!"));
376 KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!"));
379 * Reset the board and do the ``secret handshake''
380 * to enable the crypto support. Then complete the
381 * initialization procedure by setting up the interrupt
382 * and hooking in to the system crypto support so we'll
383 * get used for system services like the crypto device,
384 * IPsec, RNG device, etc.
386 hifn_reset_board(sc, 0);
388 if (hifn_enable_crypto(sc) != 0) {
389 device_printf(dev, "crypto enabling failed\n");
395 hifn_init_pci_registers(sc);
397 if (hifn_ramtype(sc))
400 if (sc->sc_drammodel == 0)
406 * Workaround for NetSec 7751 rev A: half ram size because two
407 * of the address lines were left floating
409 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
410 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
411 pci_get_revid(dev) == 0x61) /*XXX???*/
412 sc->sc_ramsize >>= 1;
415 * Arrange the interrupt line.
418 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
419 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
420 if (sc->sc_irq == NULL) {
421 device_printf(dev, "could not map interrupt\n");
425 * NB: Network code assumes we are blocked with splimp()
426 * so make sure the IRQ is marked appropriately.
428 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET,
429 hifn_intr, sc, &sc->sc_intrhand)) {
430 device_printf(dev, "could not setup interrupt\n");
437 * NB: Keep only the low 16 bits; this masks the chip id
440 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
442 rseg = sc->sc_ramsize / 1024;
444 if (sc->sc_ramsize >= (1024 * 1024)) {
448 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n",
449 hifn_partname(sc), rev,
450 rseg, rbase, sc->sc_drammodel ? 'd' : 's',
453 sc->sc_cid = crypto_get_driverid(0);
454 if (sc->sc_cid < 0) {
455 device_printf(dev, "could not get crypto driver id\n");
459 WRITE_REG_0(sc, HIFN_0_PUCNFG,
460 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
461 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
464 case HIFN_PUSTAT_ENA_2:
465 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
466 hifn_newsession, hifn_freesession, hifn_process, sc);
467 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0,
468 hifn_newsession, hifn_freesession, hifn_process, sc);
470 case HIFN_PUSTAT_ENA_1:
471 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0,
472 hifn_newsession, hifn_freesession, hifn_process, sc);
473 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0,
474 hifn_newsession, hifn_freesession, hifn_process, sc);
475 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
476 hifn_newsession, hifn_freesession, hifn_process, sc);
477 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
478 hifn_newsession, hifn_freesession, hifn_process, sc);
479 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
480 hifn_newsession, hifn_freesession, hifn_process, sc);
484 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
487 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
488 hifn_init_pubrng(sc);
490 /* NB: 1 means the callout runs w/o Giant locked */
491 callout_init(&sc->sc_tickto);
492 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
497 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
499 /* XXX don't store rid */
500 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
502 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
503 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
504 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
505 bus_dma_tag_destroy(sc->sc_dmat);
507 /* Turn off DMA polling */
508 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
509 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
511 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
513 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
519 * Detach an interface that successfully probed.
522 hifn_detach(device_t dev)
524 struct hifn_softc *sc = device_get_softc(dev);
527 KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
531 /*XXX other resources */
532 callout_stop(&sc->sc_tickto);
533 callout_stop(&sc->sc_rngto);
536 rndtest_detach(sc->sc_rndtest);
539 /* Turn off DMA polling */
540 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
541 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
543 crypto_unregister_all(sc->sc_cid);
545 bus_generic_detach(dev); /*XXX should be no children, right? */
547 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
548 /* XXX don't store rid */
549 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
551 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
552 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
553 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
554 bus_dma_tag_destroy(sc->sc_dmat);
556 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
557 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
565 * Stop all chip I/O so that the kernel's probe routines don't
566 * get confused by errant DMAs when rebooting.
569 hifn_shutdown(device_t dev)
572 hifn_stop(device_get_softc(dev));
577 * Device suspend routine. Stop the interface and save some PCI
578 * settings in case the BIOS doesn't restore them properly on
582 hifn_suspend(device_t dev)
584 struct hifn_softc *sc = device_get_softc(dev);
589 for (i = 0; i < 5; i++)
590 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
591 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
592 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
593 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
594 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
596 sc->sc_suspended = 1;
602 * Device resume routine. Restore some PCI settings in case the BIOS
603 * doesn't, re-enable busmastering, and restart the interface if
607 hifn_resume(device_t dev)
609 struct hifn_softc *sc = device_get_softc(dev);
613 /* better way to do this? */
614 for (i = 0; i < 5; i++)
615 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
616 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
617 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
618 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
619 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
621 /* reenable busmastering */
622 pci_enable_busmaster(dev);
623 pci_enable_io(dev, HIFN_RES);
625 /* reinitialize interface if necessary */
626 if (ifp->if_flags & IFF_UP)
629 sc->sc_suspended = 0;
635 hifn_init_pubrng(struct hifn_softc *sc)
641 sc->sc_rndtest = rndtest_attach(sc->sc_dev);
643 sc->sc_harvest = rndtest_harvest;
645 sc->sc_harvest = default_harvest;
647 sc->sc_harvest = default_harvest;
649 if ((sc->sc_flags & HIFN_IS_7811) == 0) {
650 /* Reset 7951 public key/rng engine */
651 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
652 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
654 for (i = 0; i < 100; i++) {
656 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
657 HIFN_PUBRST_RESET) == 0)
662 device_printf(sc->sc_dev, "public key init failed\n");
668 /* Enable the rng, if available */
669 if (sc->sc_flags & HIFN_HAS_RNG) {
670 if (sc->sc_flags & HIFN_IS_7811) {
671 r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
672 if (r & HIFN_7811_RNGENA_ENA) {
673 r &= ~HIFN_7811_RNGENA_ENA;
674 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
676 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
677 HIFN_7811_RNGCFG_DEFL);
678 r |= HIFN_7811_RNGENA_ENA;
679 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
681 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
682 READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
687 sc->sc_rnghz = hz / 100;
690 /* NB: 1 means the callout runs w/o Giant locked */
691 callout_init(&sc->sc_rngto);
692 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
696 /* Enable public key engine, if available */
697 if (sc->sc_flags & HIFN_HAS_PUBLIC) {
698 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
699 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
700 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
710 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
711 struct hifn_softc *sc = vsc;
712 u_int32_t sts, num[2];
715 if (sc->sc_flags & HIFN_IS_7811) {
716 for (i = 0; i < 5; i++) {
717 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
718 if (sts & HIFN_7811_RNGSTS_UFL) {
719 device_printf(sc->sc_dev,
720 "RNG underflow: disabling\n");
723 if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
727 * There are at least two words in the RNG FIFO
730 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
731 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
732 /* NB: discard first data read */
736 (*sc->sc_harvest)(sc->sc_rndtest,
740 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
742 /* NB: discard first data read */
746 (*sc->sc_harvest)(sc->sc_rndtest,
747 num, sizeof (num[0]));
750 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
756 hifn_puc_wait(struct hifn_softc *sc)
760 for (i = 5000; i > 0; i--) {
762 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET))
766 device_printf(sc->sc_dev, "proc unit did not reset\n");
770 * Reset the processing unit.
773 hifn_reset_puc(struct hifn_softc *sc)
775 /* Reset processing unit */
776 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
781 * Set the Retry and TRDY registers; note that we set them to
782 * zero because the 7811 locks up when forced to retry (section
783 * 3.6 of "Specification Update SU-0014-04". Not clear if we
784 * should do this for all Hifn parts, but it doesn't seem to hurt.
787 hifn_set_retry(struct hifn_softc *sc)
789 /* NB: RETRY only responds to 8-bit reads/writes */
790 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
791 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4);
795 * Resets the board. Values in the regesters are left as is
796 * from the reset (i.e. initial values are assigned elsewhere).
799 hifn_reset_board(struct hifn_softc *sc, int full)
804 * Set polling in the DMA configuration register to zero. 0x7 avoids
805 * resetting the board and zeros out the other fields.
807 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
808 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
811 * Now that polling has been disabled, we have to wait 1 ms
812 * before resetting the board.
816 /* Reset the DMA unit */
818 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
821 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
822 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
826 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
827 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
829 /* Bring dma unit out of reset */
830 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
831 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
836 if (sc->sc_flags & HIFN_IS_7811) {
837 for (reg = 0; reg < 1000; reg++) {
838 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
839 HIFN_MIPSRST_CRAMINIT)
844 printf(": cram init timeout\n");
849 hifn_next_signature(u_int32_t a, u_int cnt)
854 for (i = 0; i < cnt; i++) {
864 a = (v & 1) ^ (a << 1);
875 static struct pci2id pci2id[] = {
878 PCI_PRODUCT_HIFN_7951,
879 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
880 0x00, 0x00, 0x00, 0x00, 0x00 }
883 PCI_PRODUCT_NETSEC_7751,
884 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
885 0x00, 0x00, 0x00, 0x00, 0x00 }
888 PCI_PRODUCT_INVERTEX_AEON,
889 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
890 0x00, 0x00, 0x00, 0x00, 0x00 }
893 PCI_PRODUCT_HIFN_7811,
894 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
895 0x00, 0x00, 0x00, 0x00, 0x00 }
898 * Other vendors share this PCI ID as well, such as
899 * http://www.powercrypt.com, and obviously they also
903 PCI_PRODUCT_HIFN_7751,
904 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
905 0x00, 0x00, 0x00, 0x00, 0x00 }
910 * Checks to see if crypto is already enabled. If crypto isn't enable,
911 * "hifn_enable_crypto" is called to enable it. The check is important,
912 * as enabling crypto twice will lock the board.
915 hifn_enable_crypto(struct hifn_softc *sc)
917 u_int32_t dmacfg, ramcfg, encl, addr, i;
920 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
921 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
922 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
923 offtbl = pci2id[i].card_id;
927 if (offtbl == NULL) {
928 device_printf(sc->sc_dev, "Unknown card!\n");
932 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
933 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
936 * The RAM config register's encrypt level bit needs to be set before
937 * every read performed on the encryption level register.
939 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
941 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
944 * Make sure we don't re-unlock. Two unlocks kills chip until the
947 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
950 device_printf(sc->sc_dev,
951 "Strong crypto already enabled!\n");
956 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
959 device_printf(sc->sc_dev,
960 "Unknown encryption level 0x%x\n", encl);
965 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
966 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
968 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
970 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
973 for (i = 0; i <= 12; i++) {
974 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
975 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
980 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
981 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
985 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
986 device_printf(sc->sc_dev, "Engine is permanently "
987 "locked until next system reset!\n");
989 device_printf(sc->sc_dev, "Engine enabled "
995 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
996 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
999 case HIFN_PUSTAT_ENA_1:
1000 case HIFN_PUSTAT_ENA_2:
1002 case HIFN_PUSTAT_ENA_0:
1004 device_printf(sc->sc_dev, "disabled");
1012 * Give initial values to the registers listed in the "Register Space"
1013 * section of the HIFN Software Development reference manual.
1016 hifn_init_pci_registers(struct hifn_softc *sc)
1018 /* write fixed values needed by the Initialization registers */
1019 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1020 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1021 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1023 /* write all 4 ring address registers */
1024 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1025 offsetof(struct hifn_dma, cmdr[0]));
1026 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1027 offsetof(struct hifn_dma, srcr[0]));
1028 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1029 offsetof(struct hifn_dma, dstr[0]));
1030 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1031 offsetof(struct hifn_dma, resr[0]));
1035 /* write status register */
1036 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1037 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1038 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1039 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1040 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1041 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1042 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1043 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1044 HIFN_DMACSR_S_WAIT |
1045 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1046 HIFN_DMACSR_C_WAIT |
1047 HIFN_DMACSR_ENGINE |
1048 ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1049 HIFN_DMACSR_PUBDONE : 0) |
1050 ((sc->sc_flags & HIFN_IS_7811) ?
1051 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1053 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1054 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1055 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1056 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1057 ((sc->sc_flags & HIFN_IS_7811) ?
1058 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1059 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1060 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1062 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1063 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1064 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1065 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1067 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1068 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1069 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1070 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1071 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1075 * The maximum number of sessions supported by the card
1076 * is dependent on the amount of context ram, which
1077 * encryption algorithms are enabled, and how compression
1078 * is configured. This should be configured before this
1079 * routine is called.
1082 hifn_sessions(struct hifn_softc *sc)
1087 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1089 if (pucnfg & HIFN_PUCNFG_COMPSING) {
1090 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1095 ((sc->sc_ramsize - 32768) / ctxsize);
1097 sc->sc_maxses = sc->sc_ramsize / 16384;
1099 if (sc->sc_maxses > 2048)
1100 sc->sc_maxses = 2048;
1104 * Determine ram type (sram or dram). Board should be just out of a reset
1105 * state when this is called.
1108 hifn_ramtype(struct hifn_softc *sc)
1110 u_int8_t data[8], dataexpect[8];
1113 for (i = 0; i < sizeof(data); i++)
1114 data[i] = dataexpect[i] = 0x55;
1115 if (hifn_writeramaddr(sc, 0, data))
1117 if (hifn_readramaddr(sc, 0, data))
1119 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1120 sc->sc_drammodel = 1;
1124 for (i = 0; i < sizeof(data); i++)
1125 data[i] = dataexpect[i] = 0xaa;
1126 if (hifn_writeramaddr(sc, 0, data))
1128 if (hifn_readramaddr(sc, 0, data))
1130 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1131 sc->sc_drammodel = 1;
1138 #define HIFN_SRAM_MAX (32 << 20)
1139 #define HIFN_SRAM_STEP_SIZE 16384
1140 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1143 hifn_sramsize(struct hifn_softc *sc)
1147 u_int8_t dataexpect[sizeof(data)];
1150 for (i = 0; i < sizeof(data); i++)
1151 data[i] = dataexpect[i] = i ^ 0x5a;
1153 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1154 a = i * HIFN_SRAM_STEP_SIZE;
1155 bcopy(&i, data, sizeof(i));
1156 hifn_writeramaddr(sc, a, data);
1159 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1160 a = i * HIFN_SRAM_STEP_SIZE;
1161 bcopy(&i, dataexpect, sizeof(i));
1162 if (hifn_readramaddr(sc, a, data) < 0)
1164 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1166 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1173 * XXX For dram boards, one should really try all of the
1174 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG
1175 * is already set up correctly.
1178 hifn_dramsize(struct hifn_softc *sc)
1182 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1183 HIFN_PUCNFG_DRAMMASK;
1184 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1189 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1191 struct hifn_dma *dma = sc->sc_dma;
1193 if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1195 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1196 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1197 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1198 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1200 *cmdp = dma->cmdi++;
1201 dma->cmdk = dma->cmdi;
1203 if (dma->srci == HIFN_D_SRC_RSIZE) {
1205 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1206 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1207 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1210 *srcp = dma->srci++;
1211 dma->srck = dma->srci;
1213 if (dma->dsti == HIFN_D_DST_RSIZE) {
1215 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1216 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1217 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1218 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1220 *dstp = dma->dsti++;
1221 dma->dstk = dma->dsti;
1223 if (dma->resi == HIFN_D_RES_RSIZE) {
1225 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1226 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1227 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1228 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1230 *resp = dma->resi++;
1231 dma->resk = dma->resi;
1235 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1237 struct hifn_dma *dma = sc->sc_dma;
1238 hifn_base_command_t wc;
1239 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1240 int r, cmdi, resi, srci, dsti;
1242 wc.masks = htole16(3 << 13);
1243 wc.session_num = htole16(addr >> 14);
1244 wc.total_source_count = htole16(8);
1245 wc.total_dest_count = htole16(addr & 0x3fff);
1247 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1249 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1250 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1251 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1253 /* build write command */
1254 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1255 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1256 bcopy(data, &dma->test_src, sizeof(dma->test_src));
1258 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1259 + offsetof(struct hifn_dma, test_src));
1260 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1261 + offsetof(struct hifn_dma, test_dst));
1263 dma->cmdr[cmdi].l = htole32(16 | masks);
1264 dma->srcr[srci].l = htole32(8 | masks);
1265 dma->dstr[dsti].l = htole32(4 | masks);
1266 dma->resr[resi].l = htole32(4 | masks);
1268 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1269 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1271 for (r = 10000; r >= 0; r--) {
1273 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1274 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1275 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1277 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1278 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1281 device_printf(sc->sc_dev, "writeramaddr -- "
1282 "result[%d](addr %d) still valid\n", resi, addr);
1288 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1289 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1290 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1296 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1298 struct hifn_dma *dma = sc->sc_dma;
1299 hifn_base_command_t rc;
1300 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1301 int r, cmdi, srci, dsti, resi;
1303 rc.masks = htole16(2 << 13);
1304 rc.session_num = htole16(addr >> 14);
1305 rc.total_source_count = htole16(addr & 0x3fff);
1306 rc.total_dest_count = htole16(8);
1308 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1310 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1311 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1312 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1314 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1315 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1317 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1318 offsetof(struct hifn_dma, test_src));
1320 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr +
1321 offsetof(struct hifn_dma, test_dst));
1323 dma->cmdr[cmdi].l = htole32(8 | masks);
1324 dma->srcr[srci].l = htole32(8 | masks);
1325 dma->dstr[dsti].l = htole32(8 | masks);
1326 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1328 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1331 for (r = 10000; r >= 0; r--) {
1333 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1334 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1335 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1337 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1338 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1341 device_printf(sc->sc_dev, "readramaddr -- "
1342 "result[%d](addr %d) still valid\n", resi, addr);
1346 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1349 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1350 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1351 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1357 * Initialize the descriptor rings.
1360 hifn_init_dma(struct hifn_softc *sc)
1362 struct hifn_dma *dma = sc->sc_dma;
1367 /* initialize static pointer values */
1368 for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1369 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1370 offsetof(struct hifn_dma, command_bufs[i][0]));
1371 for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1372 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1373 offsetof(struct hifn_dma, result_bufs[i][0]));
1375 dma->cmdr[HIFN_D_CMD_RSIZE].p =
1376 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1377 dma->srcr[HIFN_D_SRC_RSIZE].p =
1378 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1379 dma->dstr[HIFN_D_DST_RSIZE].p =
1380 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1381 dma->resr[HIFN_D_RES_RSIZE].p =
1382 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1384 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
1385 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
1386 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
1390 * Writes out the raw command buffer space. Returns the
1391 * command buffer size.
1394 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1397 hifn_base_command_t *base_cmd;
1398 hifn_mac_command_t *mac_cmd;
1399 hifn_crypt_command_t *cry_cmd;
1400 int using_mac, using_crypt, len;
1401 u_int32_t dlen, slen;
1404 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1405 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1407 base_cmd = (hifn_base_command_t *)buf_pos;
1408 base_cmd->masks = htole16(cmd->base_masks);
1409 slen = cmd->src_mapsize;
1411 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1413 dlen = cmd->dst_mapsize;
1414 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1415 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1418 base_cmd->session_num = htole16(cmd->session_num |
1419 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1420 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1421 buf_pos += sizeof(hifn_base_command_t);
1424 mac_cmd = (hifn_mac_command_t *)buf_pos;
1425 dlen = cmd->maccrd->crd_len;
1426 mac_cmd->source_count = htole16(dlen & 0xffff);
1428 mac_cmd->masks = htole16(cmd->mac_masks |
1429 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1430 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1431 mac_cmd->reserved = 0;
1432 buf_pos += sizeof(hifn_mac_command_t);
1436 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1437 dlen = cmd->enccrd->crd_len;
1438 cry_cmd->source_count = htole16(dlen & 0xffff);
1440 cry_cmd->masks = htole16(cmd->cry_masks |
1441 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1442 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1443 cry_cmd->reserved = 0;
1444 buf_pos += sizeof(hifn_crypt_command_t);
1447 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1448 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1449 buf_pos += HIFN_MAC_KEY_LENGTH;
1452 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1453 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1454 case HIFN_CRYPT_CMD_ALG_3DES:
1455 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1456 buf_pos += HIFN_3DES_KEY_LENGTH;
1458 case HIFN_CRYPT_CMD_ALG_DES:
1459 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1460 buf_pos += cmd->cklen;
1462 case HIFN_CRYPT_CMD_ALG_RC4:
1467 clen = MIN(cmd->cklen, len);
1468 bcopy(cmd->ck, buf_pos, clen);
1478 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1479 bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH);
1480 buf_pos += HIFN_IV_LENGTH;
1483 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1488 return (buf_pos - buf);
1493 hifn_dmamap_aligned(struct hifn_operand *op)
1497 for (i = 0; i < op->nsegs; i++) {
1498 if (op->segs[i].ds_addr & 3)
1500 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1507 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1509 struct hifn_dma *dma = sc->sc_dma;
1510 struct hifn_operand *dst = &cmd->dst;
1512 int idx, used = 0, i;
1515 for (i = 0; i < dst->nsegs - 1; i++) {
1516 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1517 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1518 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1519 HIFN_DSTR_SYNC(sc, idx,
1520 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1523 if (++idx == HIFN_D_DST_RSIZE) {
1524 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1525 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1526 HIFN_DSTR_SYNC(sc, idx,
1527 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1532 if (cmd->sloplen == 0) {
1533 p = dst->segs[i].ds_addr;
1534 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1535 dst->segs[i].ds_len;
1537 p = sc->sc_dma_physaddr +
1538 offsetof(struct hifn_dma, slop[cmd->slopidx]);
1539 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1542 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1543 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1544 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1545 HIFN_D_MASKDONEIRQ |
1546 (dst->segs[i].ds_len - cmd->sloplen));
1547 HIFN_DSTR_SYNC(sc, idx,
1548 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1551 if (++idx == HIFN_D_DST_RSIZE) {
1552 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1553 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1554 HIFN_DSTR_SYNC(sc, idx,
1555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1560 dma->dstr[idx].p = htole32(p);
1561 dma->dstr[idx].l = htole32(l);
1562 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1565 if (++idx == HIFN_D_DST_RSIZE) {
1566 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1567 HIFN_D_MASKDONEIRQ);
1568 HIFN_DSTR_SYNC(sc, idx,
1569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1579 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1581 struct hifn_dma *dma = sc->sc_dma;
1582 struct hifn_operand *src = &cmd->src;
1587 for (i = 0; i < src->nsegs; i++) {
1588 if (i == src->nsegs - 1)
1591 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1592 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1593 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1594 HIFN_SRCR_SYNC(sc, idx,
1595 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1597 if (++idx == HIFN_D_SRC_RSIZE) {
1598 dma->srcr[idx].l = htole32(HIFN_D_VALID |
1599 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1600 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1601 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1606 dma->srcu += src->nsegs;
1611 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1613 struct hifn_operand *op = arg;
1615 KASSERT(nsegs <= MAX_SCATTER,
1616 ("hifn_op_cb: too many DMA segments (%u > %u) "
1617 "returned when mapping operand", nsegs, MAX_SCATTER));
1618 op->mapsize = mapsize;
1620 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1625 struct hifn_softc *sc,
1626 struct hifn_command *cmd,
1627 struct cryptop *crp,
1630 struct hifn_dma *dma = sc->sc_dma;
1632 int cmdi, resi, err = 0;
1635 * need 1 cmd, and 1 res
1637 * NB: check this first since it's easy.
1639 if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE ||
1640 (dma->resu + 1) > HIFN_D_RES_RSIZE) {
1643 device_printf(sc->sc_dev,
1644 "cmd/result exhaustion, cmdu %u resu %u\n",
1645 dma->cmdu, dma->resu);
1648 hifnstats.hst_nomem_cr++;
1652 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1653 hifnstats.hst_nomem_map++;
1657 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1658 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map,
1659 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1660 hifnstats.hst_nomem_load++;
1664 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1665 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,
1666 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1667 hifnstats.hst_nomem_load++;
1676 if (hifn_dmamap_aligned(&cmd->src)) {
1677 cmd->sloplen = cmd->src_mapsize & 3;
1678 cmd->dst = cmd->src;
1680 if (crp->crp_flags & CRYPTO_F_IOV) {
1683 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1685 struct mbuf *m, *m0, *mlast;
1687 KASSERT(cmd->dst_m == cmd->src_m,
1688 ("hifn_crypto: dst_m initialized improperly"));
1689 hifnstats.hst_unaligned++;
1691 * Source is not aligned on a longword boundary.
1692 * Copy the data to insure alignment. If we fail
1693 * to allocate mbufs or clusters while doing this
1694 * we return ERESTART so the operation is requeued
1695 * at the crypto later, but only if there are
1696 * ops already posted to the hardware; otherwise we
1697 * have no guarantee that we'll be re-entered.
1699 totlen = cmd->src_mapsize;
1700 if (cmd->src_m->m_flags & M_PKTHDR) {
1702 MGETHDR(m0, M_DONTWAIT, MT_DATA);
1703 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) {
1709 MGET(m0, M_DONTWAIT, MT_DATA);
1712 hifnstats.hst_nomem_mbuf++;
1713 err = dma->cmdu ? ERESTART : ENOMEM;
1716 if (totlen >= MINCLSIZE) {
1717 MCLGET(m0, M_DONTWAIT);
1718 if ((m0->m_flags & M_EXT) == 0) {
1719 hifnstats.hst_nomem_mcl++;
1720 err = dma->cmdu ? ERESTART : ENOMEM;
1727 m0->m_pkthdr.len = m0->m_len = len;
1730 while (totlen > 0) {
1731 MGET(m, M_DONTWAIT, MT_DATA);
1733 hifnstats.hst_nomem_mbuf++;
1734 err = dma->cmdu ? ERESTART : ENOMEM;
1739 if (totlen >= MINCLSIZE) {
1740 MCLGET(m, M_DONTWAIT);
1741 if ((m->m_flags & M_EXT) == 0) {
1742 hifnstats.hst_nomem_mcl++;
1743 err = dma->cmdu ? ERESTART : ENOMEM;
1752 m0->m_pkthdr.len += len;
1762 if (cmd->dst_map == NULL) {
1763 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) {
1764 hifnstats.hst_nomem_map++;
1768 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1769 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map,
1770 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1771 hifnstats.hst_nomem_map++;
1775 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1776 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,
1777 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1778 hifnstats.hst_nomem_load++;
1787 device_printf(sc->sc_dev,
1788 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1789 READ_REG_1(sc, HIFN_1_DMA_CSR),
1790 READ_REG_1(sc, HIFN_1_DMA_IER),
1791 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1792 cmd->src_nsegs, cmd->dst_nsegs);
1796 if (cmd->src_map == cmd->dst_map) {
1797 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1798 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1800 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1801 BUS_DMASYNC_PREWRITE);
1802 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1803 BUS_DMASYNC_PREREAD);
1807 * need N src, and N dst
1809 if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1810 (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1813 device_printf(sc->sc_dev,
1814 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1815 dma->srcu, cmd->src_nsegs,
1816 dma->dstu, cmd->dst_nsegs);
1819 hifnstats.hst_nomem_sd++;
1824 if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1826 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1827 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1828 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1832 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
1833 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
1835 /* .p for command/result already set */
1836 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
1837 HIFN_D_MASKDONEIRQ);
1838 HIFN_CMDR_SYNC(sc, cmdi,
1839 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1841 if (sc->sc_c_busy == 0) {
1842 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1847 * We don't worry about missing an interrupt (which a "command wait"
1848 * interrupt salvages us from), unless there is more than one command
1851 if (dma->cmdu > 1) {
1852 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
1853 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1856 hifnstats.hst_ipackets++;
1857 hifnstats.hst_ibytes += cmd->src_mapsize;
1859 hifn_dmamap_load_src(sc, cmd);
1860 if (sc->sc_s_busy == 0) {
1861 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1866 * Unlike other descriptors, we don't mask done interrupt from
1867 * result descriptor.
1871 printf("load res\n");
1873 if (dma->resi == HIFN_D_RES_RSIZE) {
1875 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1876 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1877 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1881 KASSERT(dma->hifn_commands[resi] == NULL,
1882 ("hifn_crypto: command slot %u busy", resi));
1883 dma->hifn_commands[resi] = cmd;
1884 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
1885 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
1886 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
1887 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1889 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
1890 hifnstats.hst_maxbatch = sc->sc_curbatch;
1891 hifnstats.hst_totbatch++;
1893 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
1894 HIFN_D_VALID | HIFN_D_LAST);
1895 sc->sc_curbatch = 0;
1897 HIFN_RESR_SYNC(sc, resi,
1898 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1900 if (sc->sc_r_busy == 0) {
1901 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1906 cmd->slopidx = resi;
1908 hifn_dmamap_load_dst(sc, cmd);
1910 if (sc->sc_d_busy == 0) {
1911 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1917 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
1918 READ_REG_1(sc, HIFN_1_DMA_CSR),
1919 READ_REG_1(sc, HIFN_1_DMA_IER));
1924 KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
1925 return (err); /* success */
1928 if (cmd->src_map != cmd->dst_map)
1929 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
1931 if (cmd->src_map != cmd->dst_map)
1932 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
1934 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1935 if (cmd->src_m != cmd->dst_m)
1936 m_freem(cmd->dst_m);
1938 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
1940 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
1945 hifn_tick(void* vsc)
1947 struct hifn_softc *sc = vsc;
1951 if (sc->sc_active == 0) {
1952 struct hifn_dma *dma = sc->sc_dma;
1955 if (dma->cmdu == 0 && sc->sc_c_busy) {
1957 r |= HIFN_DMACSR_C_CTRL_DIS;
1959 if (dma->srcu == 0 && sc->sc_s_busy) {
1961 r |= HIFN_DMACSR_S_CTRL_DIS;
1963 if (dma->dstu == 0 && sc->sc_d_busy) {
1965 r |= HIFN_DMACSR_D_CTRL_DIS;
1967 if (dma->resu == 0 && sc->sc_r_busy) {
1969 r |= HIFN_DMACSR_R_CTRL_DIS;
1972 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
1976 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
1980 hifn_intr(void *arg)
1982 struct hifn_softc *sc = arg;
1983 struct hifn_dma *dma;
1984 u_int32_t dmacsr, restart;
1989 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
1993 device_printf(sc->sc_dev,
1994 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
1995 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
1996 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1997 dma->cmdk, dma->srck, dma->dstk, dma->resk,
1998 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2002 /* Nothing in the DMA unit interrupted */
2003 if ((dmacsr & sc->sc_dmaier) == 0) {
2004 hifnstats.hst_noirq++;
2008 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2010 if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2011 (dmacsr & HIFN_DMACSR_PUBDONE))
2012 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2013 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2015 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2017 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2019 if (sc->sc_flags & HIFN_IS_7811) {
2020 if (dmacsr & HIFN_DMACSR_ILLR)
2021 device_printf(sc->sc_dev, "illegal read\n");
2022 if (dmacsr & HIFN_DMACSR_ILLW)
2023 device_printf(sc->sc_dev, "illegal write\n");
2026 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2027 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2029 device_printf(sc->sc_dev, "abort, resetting.\n");
2030 hifnstats.hst_abort++;
2035 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
2037 * If no slots to process and we receive a "waiting on
2038 * command" interrupt, we disable the "waiting on command"
2041 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2042 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2045 /* clear the rings */
2046 i = dma->resk; u = dma->resu;
2048 HIFN_RESR_SYNC(sc, i,
2049 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2050 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2051 HIFN_RESR_SYNC(sc, i,
2052 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2056 if (i != HIFN_D_RES_RSIZE) {
2057 struct hifn_command *cmd;
2058 u_int8_t *macbuf = NULL;
2060 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2061 cmd = dma->hifn_commands[i];
2062 KASSERT(cmd != NULL,
2063 ("hifn_intr: null command slot %u", i));
2064 dma->hifn_commands[i] = NULL;
2066 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2067 macbuf = dma->result_bufs[i];
2071 hifn_callback(sc, cmd, macbuf);
2072 hifnstats.hst_opackets++;
2076 if (++i == (HIFN_D_RES_RSIZE + 1))
2079 dma->resk = i; dma->resu = u;
2081 i = dma->srck; u = dma->srcu;
2083 if (i == HIFN_D_SRC_RSIZE)
2085 HIFN_SRCR_SYNC(sc, i,
2086 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2087 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2088 HIFN_SRCR_SYNC(sc, i,
2089 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2094 dma->srck = i; dma->srcu = u;
2096 i = dma->cmdk; u = dma->cmdu;
2098 HIFN_CMDR_SYNC(sc, i,
2099 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2100 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2101 HIFN_CMDR_SYNC(sc, i,
2102 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2105 if (i != HIFN_D_CMD_RSIZE) {
2107 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2109 if (++i == (HIFN_D_CMD_RSIZE + 1))
2112 dma->cmdk = i; dma->cmdu = u;
2114 if (sc->sc_needwakeup) { /* XXX check high watermark */
2115 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
2118 device_printf(sc->sc_dev,
2119 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2121 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2123 sc->sc_needwakeup &= ~wakeup;
2124 crypto_unblock(sc->sc_cid, wakeup);
2129 * Allocate a new 'session' and return an encoded session id. 'sidp'
2130 * contains our registration id, and should contain an encoded session
2131 * id on successful allocation.
2134 hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
2136 struct cryptoini *c;
2137 struct hifn_softc *sc = arg;
2138 int i, mac = 0, cry = 0;
2140 KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2141 if (sidp == NULL || cri == NULL || sc == NULL)
2144 for (i = 0; i < sc->sc_maxses; i++)
2145 if (sc->sc_sessions[i].hs_state == HS_STATE_FREE)
2147 if (i == sc->sc_maxses)
2150 for (c = cri; c != NULL; c = c->cri_next) {
2151 switch (c->cri_alg) {
2154 case CRYPTO_MD5_HMAC:
2155 case CRYPTO_SHA1_HMAC:
2160 case CRYPTO_DES_CBC:
2161 case CRYPTO_3DES_CBC:
2162 /* XXX this may read fewer, does it matter? */
2163 read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH);
2174 if (mac == 0 && cry == 0)
2177 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i);
2178 sc->sc_sessions[i].hs_state = HS_STATE_USED;
2184 * Deallocate a session.
2185 * XXX this routine should run a zero'd mac/encrypt key into context ram.
2186 * XXX to blow away any keys already stored there.
2189 hifn_freesession(void *arg, u_int64_t tid)
2191 struct hifn_softc *sc = arg;
2193 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff;
2195 KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2199 session = HIFN_SESSION(sid);
2200 if (session >= sc->sc_maxses)
2203 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
2208 hifn_process(void *arg, struct cryptop *crp, int hint)
2210 struct hifn_softc *sc = arg;
2211 struct hifn_command *cmd = NULL;
2213 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
2215 if (crp == NULL || crp->crp_callback == NULL) {
2216 hifnstats.hst_invalid++;
2219 session = HIFN_SESSION(crp->crp_sid);
2221 if (sc == NULL || session >= sc->sc_maxses) {
2226 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO);
2228 hifnstats.hst_nomem++;
2233 if (crp->crp_flags & CRYPTO_F_IMBUF) {
2234 cmd->src_m = (struct mbuf *)crp->crp_buf;
2235 cmd->dst_m = (struct mbuf *)crp->crp_buf;
2236 } else if (crp->crp_flags & CRYPTO_F_IOV) {
2237 cmd->src_io = (struct uio *)crp->crp_buf;
2238 cmd->dst_io = (struct uio *)crp->crp_buf;
2241 goto errout; /* XXX we don't handle contiguous buffers! */
2244 crd1 = crp->crp_desc;
2249 crd2 = crd1->crd_next;
2252 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
2253 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2254 crd1->crd_alg == CRYPTO_SHA1 ||
2255 crd1->crd_alg == CRYPTO_MD5) {
2258 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
2259 crd1->crd_alg == CRYPTO_3DES_CBC ||
2260 crd1->crd_alg == CRYPTO_ARC4) {
2261 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2262 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2270 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
2271 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2272 crd1->crd_alg == CRYPTO_MD5 ||
2273 crd1->crd_alg == CRYPTO_SHA1) &&
2274 (crd2->crd_alg == CRYPTO_DES_CBC ||
2275 crd2->crd_alg == CRYPTO_3DES_CBC ||
2276 crd2->crd_alg == CRYPTO_ARC4) &&
2277 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2278 cmd->base_masks = HIFN_BASE_CMD_DECODE;
2281 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
2282 crd1->crd_alg == CRYPTO_ARC4 ||
2283 crd1->crd_alg == CRYPTO_3DES_CBC) &&
2284 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
2285 crd2->crd_alg == CRYPTO_SHA1_HMAC ||
2286 crd2->crd_alg == CRYPTO_MD5 ||
2287 crd2->crd_alg == CRYPTO_SHA1) &&
2288 (crd1->crd_flags & CRD_F_ENCRYPT)) {
2293 * We cannot order the 7751 as requested
2301 cmd->enccrd = enccrd;
2302 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2303 switch (enccrd->crd_alg) {
2305 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4;
2306 if ((enccrd->crd_flags & CRD_F_ENCRYPT)
2307 != sc->sc_sessions[session].hs_prev_op)
2308 sc->sc_sessions[session].hs_state =
2311 case CRYPTO_DES_CBC:
2312 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES |
2313 HIFN_CRYPT_CMD_MODE_CBC |
2314 HIFN_CRYPT_CMD_NEW_IV;
2316 case CRYPTO_3DES_CBC:
2317 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES |
2318 HIFN_CRYPT_CMD_MODE_CBC |
2319 HIFN_CRYPT_CMD_NEW_IV;
2325 if (enccrd->crd_alg != CRYPTO_ARC4) {
2326 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2327 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2328 bcopy(enccrd->crd_iv, cmd->iv,
2331 bcopy(sc->sc_sessions[session].hs_iv,
2332 cmd->iv, HIFN_IV_LENGTH);
2334 if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2336 if (crp->crp_flags & CRYPTO_F_IMBUF)
2337 m_copyback(cmd->src_m,
2339 HIFN_IV_LENGTH, cmd->iv);
2340 else if (crp->crp_flags & CRYPTO_F_IOV)
2341 cuio_copyback(cmd->src_io,
2343 HIFN_IV_LENGTH, cmd->iv);
2346 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2347 bcopy(enccrd->crd_iv, cmd->iv,
2349 else if (crp->crp_flags & CRYPTO_F_IMBUF)
2350 m_copydata(cmd->src_m,
2352 HIFN_IV_LENGTH, cmd->iv);
2353 else if (crp->crp_flags & CRYPTO_F_IOV)
2354 cuio_copydata(cmd->src_io,
2356 HIFN_IV_LENGTH, cmd->iv);
2360 cmd->ck = enccrd->crd_key;
2361 cmd->cklen = enccrd->crd_klen >> 3;
2363 if (sc->sc_sessions[session].hs_state == HS_STATE_USED)
2364 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2368 cmd->maccrd = maccrd;
2369 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2371 switch (maccrd->crd_alg) {
2373 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2374 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2375 HIFN_MAC_CMD_POS_IPSEC;
2377 case CRYPTO_MD5_HMAC:
2378 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2379 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2380 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2383 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2384 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2385 HIFN_MAC_CMD_POS_IPSEC;
2387 case CRYPTO_SHA1_HMAC:
2388 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2389 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2390 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2394 if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC ||
2395 maccrd->crd_alg == CRYPTO_MD5_HMAC) &&
2396 sc->sc_sessions[session].hs_state == HS_STATE_USED) {
2397 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2398 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2399 bzero(cmd->mac + (maccrd->crd_klen >> 3),
2400 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2405 cmd->session_num = session;
2408 err = hifn_crypto(sc, cmd, crp, hint);
2411 sc->sc_sessions[session].hs_prev_op =
2412 enccrd->crd_flags & CRD_F_ENCRYPT;
2413 if (sc->sc_sessions[session].hs_state == HS_STATE_USED)
2414 sc->sc_sessions[session].hs_state = HS_STATE_KEY;
2416 } else if (err == ERESTART) {
2418 * There weren't enough resources to dispatch the request
2419 * to the part. Notify the caller so they'll requeue this
2420 * request and resubmit it again soon.
2424 device_printf(sc->sc_dev, "requeue request\n");
2426 free(cmd, M_DEVBUF);
2427 sc->sc_needwakeup |= CRYPTO_SYMQ;
2433 free(cmd, M_DEVBUF);
2435 hifnstats.hst_invalid++;
2437 hifnstats.hst_nomem++;
2438 crp->crp_etype = err;
2444 hifn_abort(struct hifn_softc *sc)
2446 struct hifn_dma *dma = sc->sc_dma;
2447 struct hifn_command *cmd;
2448 struct cryptop *crp;
2451 i = dma->resk; u = dma->resu;
2453 cmd = dma->hifn_commands[i];
2454 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2455 dma->hifn_commands[i] = NULL;
2458 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2459 /* Salvage what we can. */
2462 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2463 macbuf = dma->result_bufs[i];
2467 hifnstats.hst_opackets++;
2468 hifn_callback(sc, cmd, macbuf);
2470 if (cmd->src_map == cmd->dst_map) {
2471 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2472 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2474 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2475 BUS_DMASYNC_POSTWRITE);
2476 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2477 BUS_DMASYNC_POSTREAD);
2480 if (cmd->src_m != cmd->dst_m) {
2481 m_freem(cmd->src_m);
2482 crp->crp_buf = (caddr_t)cmd->dst_m;
2485 /* non-shared buffers cannot be restarted */
2486 if (cmd->src_map != cmd->dst_map) {
2488 * XXX should be EAGAIN, delayed until
2491 crp->crp_etype = ENOMEM;
2492 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2493 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2495 crp->crp_etype = ENOMEM;
2497 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2498 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2500 free(cmd, M_DEVBUF);
2501 if (crp->crp_etype != EAGAIN)
2505 if (++i == HIFN_D_RES_RSIZE)
2509 dma->resk = i; dma->resu = u;
2511 /* Force upload of key next time */
2512 for (i = 0; i < sc->sc_maxses; i++)
2513 if (sc->sc_sessions[i].hs_state == HS_STATE_KEY)
2514 sc->sc_sessions[i].hs_state = HS_STATE_USED;
2516 hifn_reset_board(sc, 1);
2518 hifn_init_pci_registers(sc);
2522 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2524 struct hifn_dma *dma = sc->sc_dma;
2525 struct cryptop *crp = cmd->crp;
2526 struct cryptodesc *crd;
2530 if (cmd->src_map == cmd->dst_map) {
2531 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2532 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2534 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2535 BUS_DMASYNC_POSTWRITE);
2536 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2537 BUS_DMASYNC_POSTREAD);
2540 if (crp->crp_flags & CRYPTO_F_IMBUF) {
2541 if (cmd->src_m != cmd->dst_m) {
2542 crp->crp_buf = (caddr_t)cmd->dst_m;
2543 totlen = cmd->src_mapsize;
2544 for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2545 if (totlen < m->m_len) {
2551 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2552 m_freem(cmd->src_m);
2556 if (cmd->sloplen != 0) {
2557 if (crp->crp_flags & CRYPTO_F_IMBUF)
2558 m_copyback((struct mbuf *)crp->crp_buf,
2559 cmd->src_mapsize - cmd->sloplen,
2560 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]);
2561 else if (crp->crp_flags & CRYPTO_F_IOV)
2562 cuio_copyback((struct uio *)crp->crp_buf,
2563 cmd->src_mapsize - cmd->sloplen,
2564 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]);
2567 i = dma->dstk; u = dma->dstu;
2569 if (i == HIFN_D_DST_RSIZE)
2571 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2572 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2573 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2574 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2575 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2580 dma->dstk = i; dma->dstu = u;
2582 hifnstats.hst_obytes += cmd->dst_mapsize;
2584 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) ==
2585 HIFN_BASE_CMD_CRYPT) {
2586 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2587 if (crd->crd_alg != CRYPTO_DES_CBC &&
2588 crd->crd_alg != CRYPTO_3DES_CBC)
2590 if (crp->crp_flags & CRYPTO_F_IMBUF)
2591 m_copydata((struct mbuf *)crp->crp_buf,
2592 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH,
2594 cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2595 else if (crp->crp_flags & CRYPTO_F_IOV) {
2596 cuio_copydata((struct uio *)crp->crp_buf,
2597 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH,
2599 cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2605 if (macbuf != NULL) {
2606 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2609 if (crd->crd_alg == CRYPTO_MD5)
2611 else if (crd->crd_alg == CRYPTO_SHA1)
2613 else if (crd->crd_alg == CRYPTO_MD5_HMAC ||
2614 crd->crd_alg == CRYPTO_SHA1_HMAC)
2619 if (crp->crp_flags & CRYPTO_F_IMBUF)
2620 m_copyback((struct mbuf *)crp->crp_buf,
2621 crd->crd_inject, len, macbuf);
2622 else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac)
2623 bcopy((caddr_t)macbuf, crp->crp_mac, len);
2628 if (cmd->src_map != cmd->dst_map) {
2629 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2630 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2632 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2633 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2634 free(cmd, M_DEVBUF);
2639 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2640 * and Group 1 registers; avoid conditions that could create
2641 * burst writes by doing a read in between the writes.
2643 * NB: The read we interpose is always to the same register;
2644 * we do this because reading from an arbitrary (e.g. last)
2645 * register may not always work.
2648 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2650 if (sc->sc_flags & HIFN_IS_7811) {
2651 if (sc->sc_bar0_lastreg == reg - 4)
2652 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2653 sc->sc_bar0_lastreg = reg;
2655 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2659 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2661 if (sc->sc_flags & HIFN_IS_7811) {
2662 if (sc->sc_bar1_lastreg == reg - 4)
2663 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2664 sc->sc_bar1_lastreg = reg;
2666 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);