2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.12 2004/03/02 20:59:46 drhodus Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <machine/clock.h>
47 #include <machine/md_var.h>
50 #include <bus/pci/pcivar.h>
51 #include <bus/pci/pcireg.h>
54 /* device structures */
55 struct ata_pci_controller {
56 struct resource *bmio;
63 #define IOMASK 0xfffffffc
64 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
65 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
66 (pci_get_progif(dev) & 0x05) != 0x05)
69 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
74 if (device_get_children(device_get_parent(dev), &children, &nchildren))
77 for (i = 0; i < nchildren; i++) {
78 if (pci_get_devid(children[i]) == devid &&
79 pci_get_revid(children[i]) >= revid) {
80 free(children, M_TEMP);
84 free(children, M_TEMP);
89 ata_via_southbridge_fixup(device_t dev)
94 if (device_get_children(device_get_parent(dev), &children, &nchildren))
97 for (i = 0; i < nchildren; i++) {
98 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
99 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
100 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
101 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
102 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
104 if ((reg76 & 0xf0) != 0xd0) {
106 "Correcting VIA config for southbridge data corruption bug\n");
107 pci_write_config(children[i], 0x75, 0x80, 1);
108 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
113 free(children, M_TEMP);
117 ata_pci_match(device_t dev)
119 if (pci_get_class(dev) != PCIC_STORAGE)
122 switch (pci_get_devid(dev)) {
123 /* supported chipsets */
125 return "Intel PIIX ATA controller";
128 return "Intel PIIX3 ATA controller";
133 return "Intel PIIX4 ATA33 controller";
136 return "Intel ICH0 ATA33 controller";
140 return "Intel ICH ATA66 controller";
144 return "Intel ICH2 ATA100 controller";
148 return "Intel ICH3 ATA100 controller";
152 return "Intel ICH4 ATA100 controller";
155 return "Intel ICH5 SATA150 controller";
158 return "Intel ICH5 ATA100 controller";
161 if (pci_get_revid(dev) >= 0xc4)
162 return "AcerLabs Aladdin ATA100 controller";
163 else if (pci_get_revid(dev) >= 0xc2)
164 return "AcerLabs Aladdin ATA66 controller";
165 else if (pci_get_revid(dev) >= 0x20)
166 return "AcerLabs Aladdin ATA33 controller";
168 return "AcerLabs Aladdin ATA controller";
171 if (ata_find_dev(dev, 0x05861106, 0x02))
172 return "VIA 82C586 ATA33 controller";
173 if (ata_find_dev(dev, 0x05861106, 0))
174 return "VIA 82C586 ATA controller";
175 if (ata_find_dev(dev, 0x05961106, 0x12))
176 return "VIA 82C596 ATA66 controller";
177 if (ata_find_dev(dev, 0x05961106, 0))
178 return "VIA 82C596 ATA33 controller";
179 if (ata_find_dev(dev, 0x06861106, 0x40))
180 return "VIA 82C686 ATA100 controller";
181 if (ata_find_dev(dev, 0x06861106, 0x10))
182 return "VIA 82C686 ATA66 controller";
183 if (ata_find_dev(dev, 0x06861106, 0))
184 return "VIA 82C686 ATA33 controller";
185 if (ata_find_dev(dev, 0x82311106, 0))
186 return "VIA 8231 ATA100 controller";
187 if (ata_find_dev(dev, 0x30741106, 0) ||
188 ata_find_dev(dev, 0x31091106, 0))
189 return "VIA 8233 ATA100 controller";
190 if (ata_find_dev(dev, 0x31471106, 0))
191 return "VIA 8233 ATA133 controller";
192 if (ata_find_dev(dev, 0x31771106, 0))
193 return "VIA 8235 ATA133 controller";
194 if (ata_find_dev(dev, 0x31491106, 0))
195 return "VIA 8237 ATA133 controller";
196 return "VIA Apollo ATA controller";
199 return "VIA 8237 SATA 150 controller";
202 if (ata_find_dev(dev, 0x07461039, 0))
203 return "SiS 5591 ATA133 controller";
204 if (ata_find_dev(dev, 0x06301039, 0x30) ||
205 ata_find_dev(dev, 0x06331039, 0) ||
206 ata_find_dev(dev, 0x06351039, 0) ||
207 ata_find_dev(dev, 0x06401039, 0) ||
208 ata_find_dev(dev, 0x06451039, 0) ||
209 ata_find_dev(dev, 0x06461039, 0) ||
210 ata_find_dev(dev, 0x06481039, 0) ||
211 ata_find_dev(dev, 0x06501039, 0) ||
212 ata_find_dev(dev, 0x07301039, 0) ||
213 ata_find_dev(dev, 0x07331039, 0) ||
214 ata_find_dev(dev, 0x07351039, 0) ||
215 ata_find_dev(dev, 0x07401039, 0) ||
216 ata_find_dev(dev, 0x07451039, 0) ||
217 ata_find_dev(dev, 0x07501039, 0))
218 return "SiS 5591 ATA100 controller";
219 else if (ata_find_dev(dev, 0x05301039, 0) ||
220 ata_find_dev(dev, 0x05401039, 0) ||
221 ata_find_dev(dev, 0x06201039, 0) ||
222 ata_find_dev(dev, 0x06301039, 0))
223 return "SiS 5591 ATA66 controller";
225 return "SiS 5591 ATA33 controller";
228 return "SiI 3512 SATA controller";
231 return "SiI 0680 ATA133 controller";
234 return "CMD 649 ATA100 controller";
237 return "CMD 648 ATA66 controller";
240 return "CMD 646 ATA controller";
243 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
244 return "Cypress 82C693 ATA controller";
248 return "Cyrix 5530 ATA33 controller";
251 return "AMD 756 ATA66 controller";
254 return "AMD 766 ATA100 controller";
257 return "AMD 768 ATA100 controller";
260 return "AMD 8111 UltraATA/133 controller";
263 return "nVIDIA nForce ATA100 controller";
266 return "nVIDIA nForce ATA133 controller";
269 return "nVIDIA nForce2 ATA133 controller";
272 return "ServerWorks ROSB4 ATA33 controller";
275 if (pci_get_revid(dev) >= 0x92)
276 return "ServerWorks CSB5 ATA100 controller";
278 return "ServerWorks CSB5 ATA66 controller";
281 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
284 return "ServerWorks CSB6 ATA66 controller (channel 2)";
287 return "Promise ATA33 controller";
291 return "Promise ATA66 controller";
295 return "Promise ATA100 controller";
299 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
300 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
301 static long start = 0, end = 0;
303 /* we belive we are on a TX4, now do our (simple) magic */
304 if (pci_get_slot(dev) == 1) {
305 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
306 return "Promise TX4 ATA100 controller (channel 0+1)";
308 else if (pci_get_slot(dev) == 2 && start && end) {
309 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
311 return "Promise TX4 ATA100 controller (channel 2+3)";
316 return "Promise TX2 ATA100 controller";
322 return "Promise TX2 ATA133 controller";
325 switch (pci_get_revid(dev)) {
328 return "HighPoint HPT366 ATA66 controller";
330 return "HighPoint HPT368 ATA66 controller";
333 return "HighPoint HPT370 ATA100 controller";
335 return "HighPoint HPT372 ATA133 controller";
340 switch (pci_get_revid(dev)) {
343 return "HighPoint HPT372 ATA133 controller";
348 switch (pci_get_revid(dev)) {
350 return "HighPoint HPT374 ATA133 controller";
355 return "Cenatek Rocket Drive controller";
357 /* unsupported but known chipsets, generic DMA only */
360 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
363 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
365 /* unknown chipsets, try generic DMA if it seems possible */
367 if (pci_get_class(dev) == PCIC_STORAGE &&
368 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
369 return "Generic PCI ATA controller";
375 ata_pci_probe(device_t dev)
377 const char *desc = ata_pci_match(dev);
380 device_set_desc(dev, desc);
388 ata_pci_add_child(device_t dev, int unit)
392 /* check if this is located at one of the std addresses */
393 if (ATA_MASTERDEV(dev)) {
394 if (!(child = device_add_child(dev, "ata", unit)))
398 if (!(child = device_add_child(dev, "ata", 2)))
405 ata_pci_attach(device_t dev)
407 struct ata_pci_controller *controller = device_get_softc(dev);
408 u_int8_t class, subclass;
412 /* set up vendor-specific stuff */
413 type = pci_get_devid(dev);
414 class = pci_get_class(dev);
415 subclass = pci_get_subclass(dev);
416 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
418 if (!(cmd & PCIM_CMD_PORTEN)) {
419 device_printf(dev, "ATA channel disabled by BIOS\n");
423 /* is busmastering supported ? */
424 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
425 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
427 /* is there a valid port range to connect to ? */
429 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
430 0, ~0, 1, RF_ACTIVE);
431 if (!controller->bmio)
432 device_printf(dev, "Busmastering DMA not configured\n");
435 device_printf(dev, "Busmastering DMA not supported\n");
437 /* do extra chipset specific setups */
439 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
440 pci_write_config(dev, 0x53,
441 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
444 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
447 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
450 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
451 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
454 case 0x00041103: /* HighPoint HPT366/368/370/372 */
455 if (pci_get_revid(dev) < 2) { /* HPT 366 */
456 /* turn off interrupt prediction */
457 pci_write_config(dev, 0x51,
458 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
461 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
462 /* turn off interrupt prediction */
463 pci_write_config(dev, 0x51,
464 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
465 pci_write_config(dev, 0x55,
466 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
468 /* turn on interrupts */
469 pci_write_config(dev, 0x5a,
470 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
473 pci_write_config(dev, 0x5b, 0x22, 1);
478 case 0x00051103: /* HighPoint HPT372 */
479 case 0x00081103: /* HighPoint HPT374 */
480 /* turn off interrupt prediction */
481 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
482 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
484 /* turn on interrupts */
485 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
488 pci_write_config(dev, 0x5b,
489 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
492 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
493 /* prepare for ATA-66 on the 82C686a and 82C596b */
494 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
495 !ata_find_dev(dev, 0x06861106, 0x40)) ||
496 ata_find_dev(dev, 0x05961106, 0x12))
497 pci_write_config(dev, 0x50, 0x030b030b, 4);
499 /* the southbridge might need the data corruption fix */
500 if (ata_find_dev(dev, 0x06861106, 0x40) ||
501 ata_find_dev(dev, 0x82311106, 0x10))
502 ata_via_southbridge_fixup(dev);
505 case 0x74091022: /* AMD 756 default setup */
506 case 0x74111022: /* AMD 766 default setup */
507 case 0x74411022: /* AMD 768 default setup */
508 case 0x746d1022: /* AMD 8111 default setup */
509 case 0x01bc10de: /* NVIDIA nForce default setup */
510 case 0x006510de: /* NVIDIA nForce2 default setup */
511 /* set prefetch, postwrite */
512 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
514 /* set fifo configuration half'n'half */
515 pci_write_config(dev, 0x43,
516 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
518 /* set status register read retry */
519 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
521 /* set DMA read & end-of-sector fifo flush */
522 pci_write_config(dev, 0x46,
523 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
525 /* set sector size */
526 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
527 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
530 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
531 pci_write_config(dev, 0x64,
532 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
536 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
537 pci_write_config(dev, 0x5a,
538 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
539 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
542 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
543 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
544 pci_write_config(dev, 0x8a,
545 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
546 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
547 device_printf(dev, "SiI 0680 could not set clock\n");
552 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
553 pci_write_config(dev, 0x71, 0x01, 1);
556 case 0x10001042: /* RZ 100? known bad, no DMA */
558 case 0x06401095: /* CMD 640 known bad, no DMA */
559 controller->bmio = NULL;
560 device_printf(dev, "Busmastering DMA disabled\n");
563 if (controller->bmio) {
564 controller->bmaddr = rman_get_start(controller->bmio);
565 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
566 SYS_RES_IOPORT, rid, controller->bmio);
567 controller->bmio = NULL;
571 * the Cypress chip is a mess, it contains two ATA functions, but
572 * both channels are visible on the first one.
573 * simply ignore the second function for now, as the right
574 * solution (ignoring the second channel on the first function)
575 * doesn't work with the crappy ATA interrupt setup on the alpha.
577 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
580 ata_pci_add_child(dev, 0);
582 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
583 ata_pci_add_child(dev, 1);
585 return bus_generic_attach(dev);
589 ata_pci_intr(struct ata_channel *ch)
594 * since we might share the IRQ with another device, and in some
595 * cases with our twin channel, we only want to process interrupts
596 * that we know this channel generated.
598 switch (ch->chiptype) {
599 case 0x00041103: /* HighPoint HPT366/368/370/372 */
600 case 0x00051103: /* HighPoint HPT372 */
601 case 0x00081103: /* HighPoint HPT374 */
602 if (((dmastat = ata_dmastatus(ch)) &
603 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
605 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
609 case 0x06481095: /* CMD 648 */
610 case 0x06491095: /* CMD 649 */
611 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
612 (ch->unit ? 0x08 : 0x04)))
614 #if !defined(NO_ATANG)
615 pci_write_config(device_get_parent(ch->dev), 0x71,
616 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
617 ~(ch->unit ? 0x04 : 0x08), 1);
621 case 0x06801095: /* SiI 680 */
622 if (!(pci_read_config(device_get_parent(ch->dev),
623 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
627 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
628 case 0x0d38105a: /* Promise Fasttrak 66 */
629 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
630 case 0x0d30105a: /* Promise OEM ATA100 */
631 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
632 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
633 (ch->unit ? 0x00004000 : 0x00000400)))
637 case 0x4d68105a: /* Promise TX2 ATA100 */
638 case 0x6268105a: /* Promise TX2 ATA100 */
639 case 0x4d69105a: /* Promise TX2 ATA133 */
640 case 0x5275105a: /* Promise TX2 ATA133 */
641 case 0x6269105a: /* Promise TX2 ATA133 */
642 case 0x7275105a: /* Promise TX2 ATA133 */
643 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
644 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
648 case 0x24d18086: /* Intel ICH5 SATA150 */
649 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
650 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
651 ATA_BMSTAT_INTERRUPT)
653 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
654 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
660 if (ch->flags & ATA_DMA_ACTIVE) {
661 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
663 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
670 ata_pci_print_child(device_t dev, device_t child)
672 struct ata_channel *ch = device_get_softc(child);
675 retval += bus_print_child_header(dev, child);
676 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
678 if (ATA_MASTERDEV(dev))
679 retval += printf(" irq %d", 14 + ch->unit);
681 retval += bus_print_child_footer(dev, child);
686 static struct resource *
687 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
688 u_long start, u_long end, u_long count, u_int flags)
690 struct ata_pci_controller *controller = device_get_softc(dev);
691 struct resource *res = NULL;
692 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
695 if (type == SYS_RES_IOPORT) {
698 if (ATA_MASTERDEV(dev)) {
700 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
701 end = start + ATA_IOSIZE - 1;
703 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
704 SYS_RES_IOPORT, &myrid,
705 start, end, count, flags);
708 myrid = 0x10 + 8 * unit;
709 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
710 SYS_RES_IOPORT, &myrid,
711 start, end, count, flags);
715 case ATA_ALTADDR_RID:
716 if (ATA_MASTERDEV(dev)) {
718 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
719 end = start + ATA_ALTIOSIZE - 1;
720 count = ATA_ALTIOSIZE;
721 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
722 SYS_RES_IOPORT, &myrid,
723 start, end, count, flags);
726 myrid = 0x14 + 8 * unit;
727 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
728 SYS_RES_IOPORT, &myrid,
729 start, end, count, flags);
731 start = rman_get_start(res) + 2;
732 end = start + ATA_ALTIOSIZE - 1;
733 count = ATA_ALTIOSIZE;
734 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
735 SYS_RES_IOPORT, myrid, res);
736 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
737 SYS_RES_IOPORT, &myrid,
738 start, end, count, flags);
744 if (controller->bmaddr) {
747 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
748 end = start + ATA_BMIOSIZE - 1;
749 count = ATA_BMIOSIZE;
750 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
751 SYS_RES_IOPORT, &myrid,
752 start, end, count, flags);
758 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
759 if (ATA_MASTERDEV(dev)) {
761 return alpha_platform_alloc_ide_intr(unit);
763 int irq = (unit == 0 ? 14 : 15);
765 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
766 SYS_RES_IRQ, rid, irq, irq, 1, flags);
770 /* primary and secondary channels share interrupt, keep track */
771 if (!controller->irq)
772 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
774 rid, 0, ~0, 1, flags);
775 controller->irqcnt++;
776 return controller->irq;
783 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
786 struct ata_pci_controller *controller = device_get_softc(dev);
787 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
789 if (type == SYS_RES_IOPORT) {
792 if (ATA_MASTERDEV(dev))
793 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
794 SYS_RES_IOPORT, 0x0, r);
796 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
797 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
800 case ATA_ALTADDR_RID:
801 if (ATA_MASTERDEV(dev))
802 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
803 SYS_RES_IOPORT, 0x0, r);
805 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
806 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
810 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
811 SYS_RES_IOPORT, 0x20, r);
816 if (type == SYS_RES_IRQ) {
817 if (rid != ATA_IRQ_RID)
820 if (ATA_MASTERDEV(dev)) {
822 return alpha_platform_release_ide_intr(unit, r);
824 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
825 SYS_RES_IRQ, rid, r);
829 /* primary and secondary channels share interrupt, keep track */
830 if (--controller->irqcnt)
832 controller->irq = NULL;
833 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
834 SYS_RES_IRQ, rid, r);
841 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
842 int flags, driver_intr_t *intr, void *arg,
845 if (ATA_MASTERDEV(dev)) {
847 return alpha_platform_setup_ide_intr(irq, intr, arg, cookiep);
849 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
850 flags, intr, arg, cookiep);
854 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
855 flags, intr, arg, cookiep);
859 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
862 if (ATA_MASTERDEV(dev)) {
864 return alpha_platform_teardown_ide_intr(irq, cookie);
866 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
870 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
873 static device_method_t ata_pci_methods[] = {
874 /* device interface */
875 DEVMETHOD(device_probe, ata_pci_probe),
876 DEVMETHOD(device_attach, ata_pci_attach),
877 DEVMETHOD(device_shutdown, bus_generic_shutdown),
878 DEVMETHOD(device_suspend, bus_generic_suspend),
879 DEVMETHOD(device_resume, bus_generic_resume),
882 DEVMETHOD(bus_print_child, ata_pci_print_child),
883 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
884 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
885 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
886 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
887 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
888 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
892 static driver_t ata_pci_driver = {
895 sizeof(struct ata_pci_controller),
898 static devclass_t ata_pci_devclass;
900 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
903 ata_pcisub_probe(device_t dev)
905 struct ata_channel *ch = device_get_softc(dev);
909 /* find channel number on this controller */
910 device_get_children(device_get_parent(dev), &children, &count);
911 for (i = 0; i < count; i++) {
912 if (children[i] == dev)
915 free(children, M_TEMP);
916 ch->chiptype = pci_get_devid(device_get_parent(dev));
917 ch->intr_func = ata_pci_intr;
918 return ata_probe(dev);
921 static device_method_t ata_pcisub_methods[] = {
922 /* device interface */
923 DEVMETHOD(device_probe, ata_pcisub_probe),
924 DEVMETHOD(device_attach, ata_attach),
925 DEVMETHOD(device_detach, ata_detach),
926 DEVMETHOD(device_resume, ata_resume),
930 static driver_t ata_pcisub_driver = {
933 sizeof(struct ata_channel),
936 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);