2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.18 2005/02/21 18:40:37 joerg Exp $
37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
38 * Manuals, sample driver and firmware source kits are available
39 * from http://www.alteon.com/support/openkits.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Electrical Engineering Department
43 * Columbia University, New York City
47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
51 * filtering and jumbo (9014 byte) frames. The hardware is largely
52 * controlled by firmware, which must be loaded into the NIC during
55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
56 * revision, which supports new features such as extended commands,
57 * extended jumbo receive ring desciptors and a mini receive ring.
59 * Alteon Networks is to be commended for releasing such a vast amount
60 * of development material for the Tigon NIC without requiring an NDA
61 * (although they really should have done it a long time ago). With
62 * any luck, the other vendors will finally wise up and follow Alteon's
65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
66 * this driver by #including it as a C header file. This bloats the
67 * driver somewhat, but it's the easiest method considering that the
68 * driver code and firmware code need to be kept in sync. The source
69 * for the firmware is not provided with the FreeBSD distribution since
70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
72 * The following people deserve special thanks:
73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
75 * - Raymond Lee of Netgear, for providing a pair of Netgear
76 * GA620 Tigon 2 boards for testing
77 * - Ulf Zimmermann, for bringing the GA260 to my attention and
78 * convincing me to write this driver.
79 * - Andrew Gallatin for providing FreeBSD/Alpha support.
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/sockio.h>
86 #include <sys/malloc.h>
87 #include <sys/kernel.h>
88 #include <sys/socket.h>
89 #include <sys/queue.h>
92 #include <net/ifq_var.h>
93 #include <net/if_arp.h>
94 #include <net/ethernet.h>
95 #include <net/if_dl.h>
96 #include <net/if_media.h>
97 #include <net/if_types.h>
98 #include <net/vlan/if_vlan_var.h>
102 #include <netinet/in_systm.h>
103 #include <netinet/in.h>
104 #include <netinet/ip.h>
106 #include <vm/vm.h> /* for vtophys */
107 #include <vm/pmap.h> /* for vtophys */
108 #include <machine/clock.h> /* for DELAY */
109 #include <machine/bus_memio.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 #include <bus/pci/pcireg.h>
116 #include <bus/pci/pcivar.h>
118 #include "if_tireg.h"
123 * Temporarily disable the checksum offload support for now.
124 * Tests with ftp.freesoftware.com show that after about 12 hours,
125 * the firmware will begin calculating completely bogus TX checksums
126 * and refuse to stop until the interface is reset. Unfortunately,
127 * there isn't enough time to fully debug this before the 4.1
128 * release, so this will need to stay off for now.
131 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
133 #define TI_CSUM_FEATURES 0
137 * Various supported device vendors/types and their names.
140 static struct ti_type ti_devs[] = {
141 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
142 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
143 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
144 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
145 { TC_VENDORID, TC_DEVICEID_3C985,
146 "3Com 3c985-SX Gigabit Ethernet" },
147 { NG_VENDORID, NG_DEVICEID_GA620,
148 "Netgear GA620 1000baseSX Gigabit Ethernet" },
149 { NG_VENDORID, NG_DEVICEID_GA620T,
150 "Netgear GA620 1000baseT Gigabit Ethernet" },
151 { SGI_VENDORID, SGI_DEVICEID_TIGON,
152 "Silicon Graphics Gigabit Ethernet" },
153 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
154 "Farallon PN9000SX Gigabit Ethernet" },
158 static int ti_probe (device_t);
159 static int ti_attach (device_t);
160 static int ti_detach (device_t);
161 static void ti_txeof (struct ti_softc *);
162 static void ti_rxeof (struct ti_softc *);
164 static void ti_stats_update (struct ti_softc *);
165 static int ti_encap (struct ti_softc *, struct mbuf *,
168 static void ti_intr (void *);
169 static void ti_start (struct ifnet *);
170 static int ti_ioctl (struct ifnet *, u_long, caddr_t,
172 static void ti_init (void *);
173 static void ti_init2 (struct ti_softc *);
174 static void ti_stop (struct ti_softc *);
175 static void ti_watchdog (struct ifnet *);
176 static void ti_shutdown (device_t);
177 static int ti_ifmedia_upd (struct ifnet *);
178 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *);
180 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int);
181 static u_int8_t ti_eeprom_getbyte (struct ti_softc *,
183 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int);
185 static void ti_add_mcast (struct ti_softc *, struct ether_addr *);
186 static void ti_del_mcast (struct ti_softc *, struct ether_addr *);
187 static void ti_setmulti (struct ti_softc *);
189 static void ti_mem (struct ti_softc *, u_int32_t,
191 static void ti_loadfw (struct ti_softc *);
192 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *);
193 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *,
195 static void ti_handle_events (struct ti_softc *);
196 static int ti_alloc_jumbo_mem (struct ti_softc *);
197 static void *ti_jalloc (struct ti_softc *);
198 static void ti_jfree (caddr_t, u_int);
199 static void ti_jref (caddr_t, u_int);
200 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *);
201 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *);
202 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *);
203 static int ti_init_rx_ring_std (struct ti_softc *);
204 static void ti_free_rx_ring_std (struct ti_softc *);
205 static int ti_init_rx_ring_jumbo (struct ti_softc *);
206 static void ti_free_rx_ring_jumbo (struct ti_softc *);
207 static int ti_init_rx_ring_mini (struct ti_softc *);
208 static void ti_free_rx_ring_mini (struct ti_softc *);
209 static void ti_free_tx_ring (struct ti_softc *);
210 static int ti_init_tx_ring (struct ti_softc *);
212 static int ti_64bitslot_war (struct ti_softc *);
213 static int ti_chipinit (struct ti_softc *);
214 static int ti_gibinit (struct ti_softc *);
216 static device_method_t ti_methods[] = {
217 /* Device interface */
218 DEVMETHOD(device_probe, ti_probe),
219 DEVMETHOD(device_attach, ti_attach),
220 DEVMETHOD(device_detach, ti_detach),
221 DEVMETHOD(device_shutdown, ti_shutdown),
225 static driver_t ti_driver = {
228 sizeof(struct ti_softc)
231 static devclass_t ti_devclass;
233 DECLARE_DUMMY_MODULE(if_ti);
234 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
237 * Send an instruction or address to the EEPROM, check for ACK.
239 static u_int32_t ti_eeprom_putbyte(sc, byte)
246 * Make sure we're in TX mode.
248 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
251 * Feed in each bit and stobe the clock.
253 for (i = 0x80; i; i >>= 1) {
255 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
257 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
260 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
262 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
268 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
273 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
274 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
275 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
281 * Read a byte of data stored in the EEPROM at address 'addr.'
282 * We have to send two address bytes since the EEPROM can hold
283 * more than 256 bytes of data.
285 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
296 * Send write control code to EEPROM.
298 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
299 printf("ti%d: failed to send write command, status: %x\n",
300 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
305 * Send first byte of address of byte we want to read.
307 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
308 printf("ti%d: failed to send address, status: %x\n",
309 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
313 * Send second byte address of byte we want to read.
315 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
316 printf("ti%d: failed to send address, status: %x\n",
317 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
324 * Send read control code to EEPROM.
326 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
327 printf("ti%d: failed to send read command, status: %x\n",
328 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
333 * Start reading bits from EEPROM.
335 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
336 for (i = 0x80; i; i >>= 1) {
337 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
339 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
341 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
348 * No ACK generated for read, so just return byte.
357 * Read a sequence of bytes from the EEPROM.
359 static int ti_read_eeprom(sc, dest, off, cnt)
368 for (i = 0; i < cnt; i++) {
369 err = ti_eeprom_getbyte(sc, off + i, &byte);
379 * NIC memory access function. Can be used to either clear a section
380 * of NIC local memory or (if buf is non-NULL) copy data into it.
382 static void ti_mem(sc, addr, len, buf)
387 int segptr, segsize, cnt;
388 caddr_t ti_winbase, ptr;
392 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
399 segsize = TI_WINLEN - (segptr % TI_WINLEN);
400 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
402 bzero((char *)ti_winbase + (segptr &
403 (TI_WINLEN - 1)), segsize);
405 bcopy((char *)ptr, (char *)ti_winbase +
406 (segptr & (TI_WINLEN - 1)), segsize);
417 * Load firmware image into the NIC. Check that the firmware revision
418 * is acceptable and see if we want the firmware for the Tigon 1 or
421 static void ti_loadfw(sc)
424 switch(sc->ti_hwrev) {
426 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
427 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
428 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
429 printf("ti%d: firmware revision mismatch; want "
430 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
431 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
432 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
433 tigonFwReleaseMinor, tigonFwReleaseFix);
436 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
437 (caddr_t)tigonFwText);
438 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
439 (caddr_t)tigonFwData);
440 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
441 (caddr_t)tigonFwRodata);
442 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
443 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
444 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
446 case TI_HWREV_TIGON_II:
447 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
448 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
449 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
450 printf("ti%d: firmware revision mismatch; want "
451 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
452 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
453 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
454 tigon2FwReleaseMinor, tigon2FwReleaseFix);
457 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
458 (caddr_t)tigon2FwText);
459 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
460 (caddr_t)tigon2FwData);
461 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
462 (caddr_t)tigon2FwRodata);
463 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
464 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
465 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
468 printf("ti%d: can't load firmware: unknown hardware rev\n",
477 * Send the NIC a command via the command ring.
479 static void ti_cmd(sc, cmd)
481 struct ti_cmd_desc *cmd;
485 if (sc->ti_rdata->ti_cmd_ring == NULL)
488 index = sc->ti_cmd_saved_prodidx;
489 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
490 TI_INC(index, TI_CMD_RING_CNT);
491 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
492 sc->ti_cmd_saved_prodidx = index;
498 * Send the NIC an extended command. The 'len' parameter specifies the
499 * number of command slots to include after the initial command.
501 static void ti_cmd_ext(sc, cmd, arg, len)
503 struct ti_cmd_desc *cmd;
510 if (sc->ti_rdata->ti_cmd_ring == NULL)
513 index = sc->ti_cmd_saved_prodidx;
514 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
515 TI_INC(index, TI_CMD_RING_CNT);
516 for (i = 0; i < len; i++) {
517 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
518 *(u_int32_t *)(&arg[i * 4]));
519 TI_INC(index, TI_CMD_RING_CNT);
521 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
522 sc->ti_cmd_saved_prodidx = index;
528 * Handle events that have triggered interrupts.
530 static void ti_handle_events(sc)
533 struct ti_event_desc *e;
535 if (sc->ti_rdata->ti_event_ring == NULL)
538 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
539 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
540 switch(e->ti_event) {
541 case TI_EV_LINKSTAT_CHANGED:
542 sc->ti_linkstat = e->ti_code;
543 if (e->ti_code == TI_EV_CODE_LINK_UP)
544 printf("ti%d: 10/100 link up\n", sc->ti_unit);
545 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
546 printf("ti%d: gigabit link up\n", sc->ti_unit);
547 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
548 printf("ti%d: link down\n", sc->ti_unit);
551 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
552 printf("ti%d: invalid command\n", sc->ti_unit);
553 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
554 printf("ti%d: unknown command\n", sc->ti_unit);
555 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
556 printf("ti%d: bad config data\n", sc->ti_unit);
558 case TI_EV_FIRMWARE_UP:
561 case TI_EV_STATS_UPDATED:
564 case TI_EV_RESET_JUMBO_RING:
565 case TI_EV_MCAST_UPDATED:
569 printf("ti%d: unknown event: %d\n",
570 sc->ti_unit, e->ti_event);
573 /* Advance the consumer index. */
574 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
575 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
582 * Memory management for the jumbo receive ring is a pain in the
583 * butt. We need to allocate at least 9018 bytes of space per frame,
584 * _and_ it has to be contiguous (unless you use the extended
585 * jumbo descriptor format). Using malloc() all the time won't
586 * work: malloc() allocates memory in powers of two, which means we
587 * would end up wasting a considerable amount of space by allocating
588 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
589 * to do our own memory management.
591 * The driver needs to allocate a contiguous chunk of memory at boot
592 * time. We then chop this up ourselves into 9K pieces and use them
593 * as external mbuf storage.
595 * One issue here is how much memory to allocate. The jumbo ring has
596 * 256 slots in it, but at 9K per slot than can consume over 2MB of
597 * RAM. This is a bit much, especially considering we also need
598 * RAM for the standard ring and mini ring (on the Tigon 2). To
599 * save space, we only actually allocate enough memory for 64 slots
600 * by default, which works out to between 500 and 600K. This can
601 * be tuned by changing a #define in if_tireg.h.
604 static int ti_alloc_jumbo_mem(sc)
609 struct ti_jpool_entry *entry;
611 /* Grab a big chunk o' storage. */
612 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
613 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
615 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
616 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
620 SLIST_INIT(&sc->ti_jfree_listhead);
621 SLIST_INIT(&sc->ti_jinuse_listhead);
624 * Now divide it up into 9K pieces and save the addresses
625 * in an array. Note that we play an evil trick here by using
626 * the first few bytes in the buffer to hold the the address
627 * of the softc structure for this interface. This is because
628 * ti_jfree() needs it, but it is called by the mbuf management
629 * code which will not pass it to us explicitly.
631 ptr = sc->ti_cdata.ti_jumbo_buf;
632 for (i = 0; i < TI_JSLOTS; i++) {
634 aptr = (u_int64_t **)ptr;
635 aptr[0] = (u_int64_t *)sc;
636 ptr += sizeof(u_int64_t);
637 sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
638 sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
639 ptr += (TI_JLEN - sizeof(u_int64_t));
640 entry = malloc(sizeof(struct ti_jpool_entry),
643 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
645 sc->ti_cdata.ti_jumbo_buf = NULL;
646 printf("ti%d: no memory for jumbo "
647 "buffer queue!\n", sc->ti_unit);
651 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
658 * Allocate a jumbo buffer.
660 static void *ti_jalloc(sc)
663 struct ti_jpool_entry *entry;
665 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
668 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
672 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
673 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
674 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
675 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
679 * Adjust usage count on a jumbo buffer. In general this doesn't
680 * get used much because our jumbo buffers don't get passed around
681 * too much, but it's implemented for correctness.
683 static void ti_jref(buf, size)
691 /* Extract the softc struct pointer. */
692 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
693 sc = (struct ti_softc *)(aptr[0]);
696 panic("ti_jref: can't find softc pointer!");
698 if (size != TI_JUMBO_FRAMELEN)
699 panic("ti_jref: adjusting refcount of buf of wrong size!");
701 /* calculate the slot this buffer belongs to */
703 i = ((vm_offset_t)aptr
704 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
706 if ((i < 0) || (i >= TI_JSLOTS))
707 panic("ti_jref: asked to reference buffer "
708 "that we don't manage!");
709 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
710 panic("ti_jref: buffer already free!");
712 sc->ti_cdata.ti_jslots[i].ti_inuse++;
718 * Release a jumbo buffer.
720 static void ti_jfree(buf, size)
727 struct ti_jpool_entry *entry;
729 /* Extract the softc struct pointer. */
730 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
731 sc = (struct ti_softc *)(aptr[0]);
734 panic("ti_jfree: can't find softc pointer!");
736 if (size != TI_JUMBO_FRAMELEN)
737 panic("ti_jfree: freeing buffer of wrong size!");
739 /* calculate the slot this buffer belongs to */
741 i = ((vm_offset_t)aptr
742 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
744 if ((i < 0) || (i >= TI_JSLOTS))
745 panic("ti_jfree: asked to free buffer that we don't manage!");
746 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
747 panic("ti_jfree: buffer already free!");
749 sc->ti_cdata.ti_jslots[i].ti_inuse--;
750 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
751 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
753 panic("ti_jfree: buffer not in use!");
755 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead,
757 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
758 entry, jpool_entries);
767 * Intialize a standard receive ring descriptor.
769 static int ti_newbuf_std(sc, i, m)
774 struct mbuf *m_new = NULL;
775 struct ti_rx_desc *r;
778 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
782 MCLGET(m_new, MB_DONTWAIT);
783 if (!(m_new->m_flags & M_EXT)) {
787 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
790 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
791 m_new->m_data = m_new->m_ext.ext_buf;
794 m_adj(m_new, ETHER_ALIGN);
795 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
796 r = &sc->ti_rdata->ti_rx_std_ring[i];
797 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
798 r->ti_type = TI_BDTYPE_RECV_BD;
800 if (sc->arpcom.ac_if.if_hwassist)
801 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
802 r->ti_len = m_new->m_len;
809 * Intialize a mini receive ring descriptor. This only applies to
812 static int ti_newbuf_mini(sc, i, m)
817 struct mbuf *m_new = NULL;
818 struct ti_rx_desc *r;
821 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
825 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
828 m_new->m_data = m_new->m_pktdat;
829 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
832 m_adj(m_new, ETHER_ALIGN);
833 r = &sc->ti_rdata->ti_rx_mini_ring[i];
834 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
835 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
836 r->ti_type = TI_BDTYPE_RECV_BD;
837 r->ti_flags = TI_BDFLAG_MINI_RING;
838 if (sc->arpcom.ac_if.if_hwassist)
839 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
840 r->ti_len = m_new->m_len;
847 * Initialize a jumbo receive ring descriptor. This allocates
848 * a jumbo buffer from the pool managed internally by the driver.
850 static int ti_newbuf_jumbo(sc, i, m)
855 struct mbuf *m_new = NULL;
856 struct ti_rx_desc *r;
861 /* Allocate the mbuf. */
862 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
867 /* Allocate the jumbo buffer */
871 printf("ti%d: jumbo allocation failed "
872 "-- packet dropped!\n", sc->ti_unit);
876 /* Attach the buffer to the mbuf. */
877 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
878 m_new->m_flags |= M_EXT | M_EXT_OLD;
879 m_new->m_len = m_new->m_pkthdr.len =
880 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
881 m_new->m_ext.ext_nfree.old = ti_jfree;
882 m_new->m_ext.ext_nref.old = ti_jref;
885 m_new->m_data = m_new->m_ext.ext_buf;
886 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
889 m_adj(m_new, ETHER_ALIGN);
890 /* Set up the descriptor. */
891 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
892 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
893 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
894 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
895 r->ti_flags = TI_BDFLAG_JUMBO_RING;
896 if (sc->arpcom.ac_if.if_hwassist)
897 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
898 r->ti_len = m_new->m_len;
905 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
906 * that's 1MB or memory, which is a lot. For now, we fill only the first
907 * 256 ring entries and hope that our CPU is fast enough to keep up with
910 static int ti_init_rx_ring_std(sc)
914 struct ti_cmd_desc cmd;
916 for (i = 0; i < TI_SSLOTS; i++) {
917 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
921 TI_UPDATE_STDPROD(sc, i - 1);
927 static void ti_free_rx_ring_std(sc)
932 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
933 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
934 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
935 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
937 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
938 sizeof(struct ti_rx_desc));
944 static int ti_init_rx_ring_jumbo(sc)
948 struct ti_cmd_desc cmd;
950 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
951 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
955 TI_UPDATE_JUMBOPROD(sc, i - 1);
956 sc->ti_jumbo = i - 1;
961 static void ti_free_rx_ring_jumbo(sc)
966 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
967 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
968 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
969 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
971 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
972 sizeof(struct ti_rx_desc));
978 static int ti_init_rx_ring_mini(sc)
983 for (i = 0; i < TI_MSLOTS; i++) {
984 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
988 TI_UPDATE_MINIPROD(sc, i - 1);
994 static void ti_free_rx_ring_mini(sc)
999 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1000 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1001 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1002 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1004 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1005 sizeof(struct ti_rx_desc));
1011 static void ti_free_tx_ring(sc)
1012 struct ti_softc *sc;
1016 if (sc->ti_rdata->ti_tx_ring == NULL)
1019 for (i = 0; i < TI_TX_RING_CNT; i++) {
1020 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1021 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1022 sc->ti_cdata.ti_tx_chain[i] = NULL;
1024 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1025 sizeof(struct ti_tx_desc));
1031 static int ti_init_tx_ring(sc)
1032 struct ti_softc *sc;
1035 sc->ti_tx_saved_considx = 0;
1036 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1041 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1042 * but we have to support the old way too so that Tigon 1 cards will
1045 void ti_add_mcast(sc, addr)
1046 struct ti_softc *sc;
1047 struct ether_addr *addr;
1049 struct ti_cmd_desc cmd;
1051 u_int32_t ext[2] = {0, 0};
1053 m = (u_int16_t *)&addr->octet[0];
1055 switch(sc->ti_hwrev) {
1056 case TI_HWREV_TIGON:
1057 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1058 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1059 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1061 case TI_HWREV_TIGON_II:
1062 ext[0] = htons(m[0]);
1063 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1064 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1067 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1074 void ti_del_mcast(sc, addr)
1075 struct ti_softc *sc;
1076 struct ether_addr *addr;
1078 struct ti_cmd_desc cmd;
1080 u_int32_t ext[2] = {0, 0};
1082 m = (u_int16_t *)&addr->octet[0];
1084 switch(sc->ti_hwrev) {
1085 case TI_HWREV_TIGON:
1086 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1087 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1088 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1090 case TI_HWREV_TIGON_II:
1091 ext[0] = htons(m[0]);
1092 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1093 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1096 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1104 * Configure the Tigon's multicast address filter.
1106 * The actual multicast table management is a bit of a pain, thanks to
1107 * slight brain damage on the part of both Alteon and us. With our
1108 * multicast code, we are only alerted when the multicast address table
1109 * changes and at that point we only have the current list of addresses:
1110 * we only know the current state, not the previous state, so we don't
1111 * actually know what addresses were removed or added. The firmware has
1112 * state, but we can't get our grubby mits on it, and there is no 'delete
1113 * all multicast addresses' command. Hence, we have to maintain our own
1114 * state so we know what addresses have been programmed into the NIC at
1117 static void ti_setmulti(sc)
1118 struct ti_softc *sc;
1121 struct ifmultiaddr *ifma;
1122 struct ti_cmd_desc cmd;
1123 struct ti_mc_entry *mc;
1126 ifp = &sc->arpcom.ac_if;
1128 if (ifp->if_flags & IFF_ALLMULTI) {
1129 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1132 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1135 /* Disable interrupts. */
1136 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1137 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1139 /* First, zot all the existing filters. */
1140 while (sc->ti_mc_listhead.slh_first != NULL) {
1141 mc = sc->ti_mc_listhead.slh_first;
1142 ti_del_mcast(sc, &mc->mc_addr);
1143 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1147 /* Now program new ones. */
1148 for (ifma = ifp->if_multiaddrs.lh_first;
1149 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1150 if (ifma->ifma_addr->sa_family != AF_LINK)
1152 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT);
1153 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1154 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1155 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1156 ti_add_mcast(sc, &mc->mc_addr);
1159 /* Re-enable interrupts. */
1160 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1166 * Check to see if the BIOS has configured us for a 64 bit slot when
1167 * we aren't actually in one. If we detect this condition, we can work
1168 * around it on the Tigon 2 by setting a bit in the PCI state register,
1169 * but for the Tigon 1 we must give up and abort the interface attach.
1171 static int ti_64bitslot_war(sc)
1172 struct ti_softc *sc;
1174 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1175 CSR_WRITE_4(sc, 0x600, 0);
1176 CSR_WRITE_4(sc, 0x604, 0);
1177 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1178 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1179 if (sc->ti_hwrev == TI_HWREV_TIGON)
1182 TI_SETBIT(sc, TI_PCI_STATE,
1183 TI_PCISTATE_32BIT_BUS);
1193 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1194 * self-test results.
1196 static int ti_chipinit(sc)
1197 struct ti_softc *sc;
1199 u_int32_t cacheline;
1200 u_int32_t pci_writemax = 0;
1202 /* Initialize link to down state. */
1203 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1205 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1206 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1208 sc->arpcom.ac_if.if_hwassist = 0;
1210 /* Set endianness before we access any non-PCI registers. */
1211 #if BYTE_ORDER == BIG_ENDIAN
1212 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1213 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1215 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1216 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1219 /* Check the ROM failed bit to see if self-tests passed. */
1220 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1221 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1226 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1228 /* Figure out the hardware revision. */
1229 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1230 case TI_REV_TIGON_I:
1231 sc->ti_hwrev = TI_HWREV_TIGON;
1233 case TI_REV_TIGON_II:
1234 sc->ti_hwrev = TI_HWREV_TIGON_II;
1237 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1241 /* Do special setup for Tigon 2. */
1242 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1243 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1245 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1248 /* Set up the PCI state register. */
1249 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1250 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1251 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1254 /* Clear the read/write max DMA parameters. */
1255 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1256 TI_PCISTATE_READ_MAXDMA));
1258 /* Get cache line size. */
1259 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1262 * If the system has set enabled the PCI memory write
1263 * and invalidate command in the command register, set
1264 * the write max parameter accordingly. This is necessary
1265 * to use MWI with the Tigon 2.
1267 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1277 /* Disable PCI memory write and invalidate. */
1279 printf("ti%d: cache line size %d not "
1280 "supported; disabling PCI MWI\n",
1281 sc->ti_unit, cacheline);
1282 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1283 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1288 #ifdef __brokenalpha__
1290 * From the Alteon sample driver:
1291 * Must insure that we do not cross an 8K (bytes) boundary
1292 * for DMA reads. Our highest limit is 1K bytes. This is a
1293 * restriction on some ALPHA platforms with early revision
1294 * 21174 PCI chipsets, such as the AlphaPC 164lx
1296 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1298 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1301 /* This sets the min dma param all the way up (0xff). */
1302 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1304 /* Configure DMA variables. */
1305 #if BYTE_ORDER == BIG_ENDIAN
1306 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1307 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1308 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1309 TI_OPMODE_DONT_FRAG_JUMBO);
1311 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1312 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1313 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1317 * Only allow 1 DMA channel to be active at a time.
1318 * I don't think this is a good idea, but without it
1319 * the firmware racks up lots of nicDmaReadRingFull
1320 * errors. This is not compatible with hardware checksums.
1322 if (sc->arpcom.ac_if.if_hwassist == 0)
1323 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1325 /* Recommended settings from Tigon manual. */
1326 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1327 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1329 if (ti_64bitslot_war(sc)) {
1330 printf("ti%d: bios thinks we're in a 64 bit slot, "
1331 "but we aren't", sc->ti_unit);
1339 * Initialize the general information block and firmware, and
1340 * start the CPU(s) running.
1342 static int ti_gibinit(sc)
1343 struct ti_softc *sc;
1349 ifp = &sc->arpcom.ac_if;
1351 /* Disable interrupts for now. */
1352 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1354 /* Tell the chip where to find the general information block. */
1355 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1358 /* Load the firmware into SRAM. */
1361 /* Set up the contents of the general info and ring control blocks. */
1363 /* Set up the event ring and producer pointer. */
1364 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1366 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1368 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1369 vtophys(&sc->ti_ev_prodidx);
1370 sc->ti_ev_prodidx.ti_idx = 0;
1371 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1372 sc->ti_ev_saved_considx = 0;
1374 /* Set up the command ring and producer mailbox. */
1375 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1377 sc->ti_rdata->ti_cmd_ring =
1378 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1379 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1381 rcb->ti_max_len = 0;
1382 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1383 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1385 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1386 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1387 sc->ti_cmd_saved_prodidx = 0;
1390 * Assign the address of the stats refresh buffer.
1391 * We re-use the current stats buffer for this to
1394 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1395 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1397 /* Set up the standard receive ring. */
1398 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1399 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1400 rcb->ti_max_len = TI_FRAMELEN;
1402 if (sc->arpcom.ac_if.if_hwassist)
1403 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1404 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1405 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1407 /* Set up the jumbo receive ring. */
1408 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1409 TI_HOSTADDR(rcb->ti_hostaddr) =
1410 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1411 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1413 if (sc->arpcom.ac_if.if_hwassist)
1414 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1415 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1416 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1419 * Set up the mini ring. Only activated on the
1420 * Tigon 2 but the slot in the config block is
1421 * still there on the Tigon 1.
1423 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1424 TI_HOSTADDR(rcb->ti_hostaddr) =
1425 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1426 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1427 if (sc->ti_hwrev == TI_HWREV_TIGON)
1428 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1431 if (sc->arpcom.ac_if.if_hwassist)
1432 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1433 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1434 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1437 * Set up the receive return ring.
1439 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1440 TI_HOSTADDR(rcb->ti_hostaddr) =
1441 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1443 rcb->ti_max_len = TI_RETURN_RING_CNT;
1444 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1445 vtophys(&sc->ti_return_prodidx);
1448 * Set up the tx ring. Note: for the Tigon 2, we have the option
1449 * of putting the transmit ring in the host's address space and
1450 * letting the chip DMA it instead of leaving the ring in the NIC's
1451 * memory and accessing it through the shared memory region. We
1452 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1453 * so we have to revert to the shared memory scheme if we detect
1456 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1457 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1458 sc->ti_rdata->ti_tx_ring_nic =
1459 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1461 bzero((char *)sc->ti_rdata->ti_tx_ring,
1462 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1463 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1464 if (sc->ti_hwrev == TI_HWREV_TIGON)
1467 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1468 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1469 if (sc->arpcom.ac_if.if_hwassist)
1470 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1471 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1472 rcb->ti_max_len = TI_TX_RING_CNT;
1473 if (sc->ti_hwrev == TI_HWREV_TIGON)
1474 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1476 TI_HOSTADDR(rcb->ti_hostaddr) =
1477 vtophys(&sc->ti_rdata->ti_tx_ring);
1478 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1479 vtophys(&sc->ti_tx_considx);
1481 /* Set up tuneables */
1482 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1483 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1484 (sc->ti_rx_coal_ticks / 10));
1486 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1487 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1488 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1489 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1490 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1491 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1493 /* Turn interrupts on. */
1494 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1495 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1498 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1504 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1505 * against our list and return its name if we find a match.
1507 static int ti_probe(dev)
1514 while(t->ti_name != NULL) {
1515 if ((pci_get_vendor(dev) == t->ti_vid) &&
1516 (pci_get_device(dev) == t->ti_did)) {
1517 device_set_desc(dev, t->ti_name);
1526 static int ti_attach(dev)
1532 struct ti_softc *sc;
1533 int unit, error = 0, rid;
1537 sc = device_get_softc(dev);
1538 unit = device_get_unit(dev);
1539 bzero(sc, sizeof(struct ti_softc));
1540 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM;
1541 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
1544 * Map control/status registers.
1546 command = pci_read_config(dev, PCIR_COMMAND, 4);
1547 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1548 pci_write_config(dev, PCIR_COMMAND, command, 4);
1549 command = pci_read_config(dev, PCIR_COMMAND, 4);
1551 if (!(command & PCIM_CMD_MEMEN)) {
1552 printf("ti%d: failed to enable memory mapping!\n", unit);
1558 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1559 0, ~0, 1, RF_ACTIVE);
1561 if (sc->ti_res == NULL) {
1562 printf ("ti%d: couldn't map memory\n", unit);
1567 sc->ti_btag = rman_get_bustag(sc->ti_res);
1568 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1569 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1572 * XXX FIXME: rman_get_virtual() on the alpha is currently
1573 * broken and returns a physical address instead of a kernel
1574 * virtual address. Consequently, we need to do a little
1575 * extra mangling of the vhandle on the alpha. This should
1576 * eventually be fixed! The whole idea here is to get rid
1577 * of platform dependencies.
1580 if (pci_cvt_to_bwx(sc->ti_vhandle))
1581 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle);
1583 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle);
1584 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle);
1587 /* Allocate interrupt */
1590 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1591 RF_SHAREABLE | RF_ACTIVE);
1593 if (sc->ti_irq == NULL) {
1594 printf("ti%d: couldn't map interrupt\n", unit);
1599 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1600 ti_intr, sc, &sc->ti_intrhand);
1603 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1604 bus_release_resource(dev, SYS_RES_MEMORY,
1605 TI_PCI_LOMEM, sc->ti_res);
1606 printf("ti%d: couldn't set up irq\n", unit);
1612 if (ti_chipinit(sc)) {
1613 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1614 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1615 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1616 bus_release_resource(dev, SYS_RES_MEMORY,
1617 TI_PCI_LOMEM, sc->ti_res);
1622 /* Zero out the NIC's on-board SRAM. */
1623 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1625 /* Init again -- zeroing memory may have clobbered some registers. */
1626 if (ti_chipinit(sc)) {
1627 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1628 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1629 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1630 bus_release_resource(dev, SYS_RES_MEMORY,
1631 TI_PCI_LOMEM, sc->ti_res);
1637 * Get station address from the EEPROM. Note: the manual states
1638 * that the MAC address is at offset 0x8c, however the data is
1639 * stored as two longwords (since that's how it's loaded into
1640 * the NIC). This means the MAC address is actually preceeded
1641 * by two zero bytes. We need to skip over those.
1643 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1644 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1645 printf("ti%d: failed to read station address\n", unit);
1646 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1647 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1648 bus_release_resource(dev, SYS_RES_MEMORY,
1649 TI_PCI_LOMEM, sc->ti_res);
1654 /* Allocate the general information block and ring buffers. */
1655 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1656 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1658 if (sc->ti_rdata == NULL) {
1659 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1660 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1661 bus_release_resource(dev, SYS_RES_MEMORY,
1662 TI_PCI_LOMEM, sc->ti_res);
1664 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1668 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1670 /* Try to allocate memory for jumbo buffers. */
1671 if (ti_alloc_jumbo_mem(sc)) {
1672 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1673 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1674 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1675 bus_release_resource(dev, SYS_RES_MEMORY,
1676 TI_PCI_LOMEM, sc->ti_res);
1677 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1684 * We really need a better way to tell a 1000baseTX card
1685 * from a 1000baseSX one, since in theory there could be
1686 * OEMed 1000baseTX cards from lame vendors who aren't
1687 * clever enough to change the PCI ID. For the moment
1688 * though, the AceNIC is the only copper card available.
1690 if (pci_get_vendor(dev) == ALT_VENDORID &&
1691 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1693 /* Ok, it's not the only copper card available. */
1694 if (pci_get_vendor(dev) == NG_VENDORID &&
1695 pci_get_device(dev) == NG_DEVICEID_GA620T)
1698 /* Set default tuneable values. */
1699 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1700 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1701 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1702 sc->ti_rx_max_coal_bds = 64;
1703 sc->ti_tx_max_coal_bds = 128;
1704 sc->ti_tx_buf_ratio = 21;
1706 /* Set up ifnet structure */
1707 ifp = &sc->arpcom.ac_if;
1709 if_initname(ifp, "ti", sc->ti_unit);
1710 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1711 ifp->if_ioctl = ti_ioctl;
1712 ifp->if_start = ti_start;
1713 ifp->if_watchdog = ti_watchdog;
1714 ifp->if_init = ti_init;
1715 ifp->if_mtu = ETHERMTU;
1716 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1);
1717 ifq_set_ready(&ifp->if_snd);
1719 /* Set up ifmedia support. */
1720 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1721 if (sc->ti_copper) {
1723 * Copper cards allow manual 10/100 mode selection,
1724 * but not manual 1000baseTX mode selection. Why?
1725 * Becuase currently there's no way to specify the
1726 * master/slave setting through the firmware interface,
1727 * so Alteon decided to just bag it and handle it
1728 * via autonegotiation.
1730 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1731 ifmedia_add(&sc->ifmedia,
1732 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1733 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1734 ifmedia_add(&sc->ifmedia,
1735 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1736 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
1737 ifmedia_add(&sc->ifmedia,
1738 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL);
1740 /* Fiber cards don't support 10/100 modes. */
1741 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1742 ifmedia_add(&sc->ifmedia,
1743 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1745 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1746 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1749 * Call MI attach routine.
1751 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1759 static int ti_detach(dev)
1762 struct ti_softc *sc;
1768 sc = device_get_softc(dev);
1769 ifp = &sc->arpcom.ac_if;
1771 ether_ifdetach(ifp);
1774 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1775 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1776 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1778 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1779 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1780 ifmedia_removeall(&sc->ifmedia);
1788 * Frame reception handling. This is called if there's a frame
1789 * on the receive return list.
1791 * Note: we have to be able to handle three possibilities here:
1792 * 1) the frame is from the mini receive ring (can only happen)
1793 * on Tigon 2 boards)
1794 * 2) the frame is from the jumbo recieve ring
1795 * 3) the frame is from the standard receive ring
1798 static void ti_rxeof(sc)
1799 struct ti_softc *sc;
1802 struct ti_cmd_desc cmd;
1804 ifp = &sc->arpcom.ac_if;
1806 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1807 struct ti_rx_desc *cur_rx;
1809 struct mbuf *m = NULL;
1810 u_int16_t vlan_tag = 0;
1814 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1815 rxidx = cur_rx->ti_idx;
1816 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1818 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1820 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1823 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1824 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1825 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1826 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1827 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1829 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1832 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1834 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1837 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1838 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1839 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1840 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1841 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1843 ti_newbuf_mini(sc, sc->ti_mini, m);
1846 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1848 ti_newbuf_mini(sc, sc->ti_mini, m);
1852 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1853 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1854 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1855 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1857 ti_newbuf_std(sc, sc->ti_std, m);
1860 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1862 ti_newbuf_std(sc, sc->ti_std, m);
1867 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1869 m->m_pkthdr.rcvif = ifp;
1871 if (ifp->if_hwassist) {
1872 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1874 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1875 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1876 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1880 * If we received a packet with a vlan tag, pass it
1881 * to vlan_input() instead of ether_input().
1884 VLAN_INPUT_TAG(m, vlan_tag);
1885 have_tag = vlan_tag = 0;
1887 (*ifp->if_input)(ifp, m);
1891 /* Only necessary on the Tigon 1. */
1892 if (sc->ti_hwrev == TI_HWREV_TIGON)
1893 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1894 sc->ti_rx_saved_considx);
1896 TI_UPDATE_STDPROD(sc, sc->ti_std);
1897 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1898 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1903 static void ti_txeof(sc)
1904 struct ti_softc *sc;
1906 struct ti_tx_desc *cur_tx = NULL;
1909 ifp = &sc->arpcom.ac_if;
1912 * Go through our tx ring and free mbufs for those
1913 * frames that have been sent.
1915 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1918 idx = sc->ti_tx_saved_considx;
1919 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1921 CSR_WRITE_4(sc, TI_WINBASE,
1922 TI_TX_RING_BASE + 6144);
1924 CSR_WRITE_4(sc, TI_WINBASE,
1925 TI_TX_RING_BASE + 4096);
1927 CSR_WRITE_4(sc, TI_WINBASE,
1928 TI_TX_RING_BASE + 2048);
1930 CSR_WRITE_4(sc, TI_WINBASE,
1932 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1934 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1935 if (cur_tx->ti_flags & TI_BDFLAG_END)
1937 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1938 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1939 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1942 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1947 ifp->if_flags &= ~IFF_OACTIVE;
1952 static void ti_intr(xsc)
1955 struct ti_softc *sc;
1959 ifp = &sc->arpcom.ac_if;
1962 /* Avoid this for now -- checking this register is expensive. */
1963 /* Make sure this is really our interrupt. */
1964 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1968 /* Ack interrupt and stop others from occuring. */
1969 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1971 if (ifp->if_flags & IFF_RUNNING) {
1972 /* Check RX return ring producer/consumer */
1975 /* Check TX ring producer/consumer */
1979 ti_handle_events(sc);
1981 /* Re-enable interrupts. */
1982 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1984 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1990 static void ti_stats_update(sc)
1991 struct ti_softc *sc;
1995 ifp = &sc->arpcom.ac_if;
1997 ifp->if_collisions +=
1998 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
1999 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2000 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2001 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2008 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2009 * pointers to descriptors.
2011 static int ti_encap(sc, m_head, txidx)
2012 struct ti_softc *sc;
2013 struct mbuf *m_head;
2016 struct ti_tx_desc *f = NULL;
2018 u_int32_t frag, cur, cnt = 0;
2019 u_int16_t csum_flags = 0;
2020 struct ifvlan *ifv = NULL;
2022 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2023 m_head->m_pkthdr.rcvif != NULL &&
2024 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2025 ifv = m_head->m_pkthdr.rcvif->if_softc;
2028 cur = frag = *txidx;
2030 if (m_head->m_pkthdr.csum_flags) {
2031 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2032 csum_flags |= TI_BDFLAG_IP_CKSUM;
2033 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2034 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2035 if (m_head->m_flags & M_LASTFRAG)
2036 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2037 else if (m_head->m_flags & M_FRAG)
2038 csum_flags |= TI_BDFLAG_IP_FRAG;
2041 * Start packing the mbufs in this chain into
2042 * the fragment pointers. Stop when we run out
2043 * of fragments or hit the end of the mbuf chain.
2045 for (m = m_head; m != NULL; m = m->m_next) {
2046 if (m->m_len != 0) {
2047 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2049 CSR_WRITE_4(sc, TI_WINBASE,
2050 TI_TX_RING_BASE + 6144);
2051 else if (frag > 255)
2052 CSR_WRITE_4(sc, TI_WINBASE,
2053 TI_TX_RING_BASE + 4096);
2054 else if (frag > 127)
2055 CSR_WRITE_4(sc, TI_WINBASE,
2056 TI_TX_RING_BASE + 2048);
2058 CSR_WRITE_4(sc, TI_WINBASE,
2060 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2062 f = &sc->ti_rdata->ti_tx_ring[frag];
2063 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2065 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2066 f->ti_len = m->m_len;
2067 f->ti_flags = csum_flags;
2070 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2071 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
2077 * Sanity check: avoid coming within 16 descriptors
2078 * of the end of the ring.
2080 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2083 TI_INC(frag, TI_TX_RING_CNT);
2091 if (frag == sc->ti_tx_saved_considx)
2094 if (sc->ti_hwrev == TI_HWREV_TIGON)
2095 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2098 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2099 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2100 sc->ti_txcnt += cnt;
2108 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2109 * to the mbuf data regions directly in the transmit descriptors.
2111 static void ti_start(ifp)
2114 struct ti_softc *sc;
2115 struct mbuf *m_head = NULL;
2116 u_int32_t prodidx = 0;
2120 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2122 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2123 m_head = ifq_poll(&ifp->if_snd);
2129 * safety overkill. If this is a fragmented packet chain
2130 * with delayed TCP/UDP checksums, then only encapsulate
2131 * it if we have enough descriptors to handle the entire
2133 * (paranoia -- may not actually be needed)
2135 if (m_head->m_flags & M_FIRSTFRAG &&
2136 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2137 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2138 m_head->m_pkthdr.csum_data + 16) {
2139 ifp->if_flags |= IFF_OACTIVE;
2145 * Pack the data into the transmit ring. If we
2146 * don't have room, set the OACTIVE flag and wait
2147 * for the NIC to drain the ring.
2149 if (ti_encap(sc, m_head, &prodidx)) {
2150 ifp->if_flags |= IFF_OACTIVE;
2154 m_head = ifq_dequeue(&ifp->if_snd);
2155 BPF_MTAP(ifp, m_head);
2159 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2162 * Set a timeout in case the chip goes out to lunch.
2169 static void ti_init(xsc)
2172 struct ti_softc *sc = xsc;
2177 /* Cancel pending I/O and flush buffers. */
2180 /* Init the gen info block, ring control blocks and firmware. */
2181 if (ti_gibinit(sc)) {
2182 printf("ti%d: initialization failure\n", sc->ti_unit);
2192 static void ti_init2(sc)
2193 struct ti_softc *sc;
2195 struct ti_cmd_desc cmd;
2198 struct ifmedia *ifm;
2201 ifp = &sc->arpcom.ac_if;
2203 /* Specify MTU and interface index. */
2204 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit);
2205 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2206 ETHER_HDR_LEN + ETHER_CRC_LEN);
2207 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2209 /* Load our MAC address. */
2210 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2211 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2212 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2213 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2215 /* Enable or disable promiscuous mode as needed. */
2216 if (ifp->if_flags & IFF_PROMISC) {
2217 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2219 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2222 /* Program multicast filter. */
2226 * If this is a Tigon 1, we should tell the
2227 * firmware to use software packet filtering.
2229 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2230 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2234 ti_init_rx_ring_std(sc);
2236 /* Init jumbo RX ring. */
2237 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2238 ti_init_rx_ring_jumbo(sc);
2241 * If this is a Tigon 2, we can also configure the
2244 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2245 ti_init_rx_ring_mini(sc);
2247 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2248 sc->ti_rx_saved_considx = 0;
2251 ti_init_tx_ring(sc);
2253 /* Tell firmware we're alive. */
2254 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2256 /* Enable host interrupts. */
2257 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2259 ifp->if_flags |= IFF_RUNNING;
2260 ifp->if_flags &= ~IFF_OACTIVE;
2263 * Make sure to set media properly. We have to do this
2264 * here since we have to issue commands in order to set
2265 * the link negotiation and we can't issue commands until
2266 * the firmware is running.
2269 tmp = ifm->ifm_media;
2270 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2271 ti_ifmedia_upd(ifp);
2272 ifm->ifm_media = tmp;
2278 * Set media options.
2280 static int ti_ifmedia_upd(ifp)
2283 struct ti_softc *sc;
2284 struct ifmedia *ifm;
2285 struct ti_cmd_desc cmd;
2290 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2293 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2295 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2296 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2297 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2298 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2299 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2300 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2301 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2302 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2306 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2307 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2308 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2309 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2310 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2312 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2313 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2319 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2320 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2321 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2322 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2323 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2325 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2327 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2328 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2330 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2332 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2333 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2341 * Report current media status.
2343 static void ti_ifmedia_sts(ifp, ifmr)
2345 struct ifmediareq *ifmr;
2347 struct ti_softc *sc;
2348 u_int32_t media = 0;
2352 ifmr->ifm_status = IFM_AVALID;
2353 ifmr->ifm_active = IFM_ETHER;
2355 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2358 ifmr->ifm_status |= IFM_ACTIVE;
2360 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2361 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2363 ifmr->ifm_active |= IFM_1000_T;
2365 ifmr->ifm_active |= IFM_1000_SX;
2366 if (media & TI_GLNK_FULL_DUPLEX)
2367 ifmr->ifm_active |= IFM_FDX;
2369 ifmr->ifm_active |= IFM_HDX;
2370 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2371 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2372 if (sc->ti_copper) {
2373 if (media & TI_LNK_100MB)
2374 ifmr->ifm_active |= IFM_100_TX;
2375 if (media & TI_LNK_10MB)
2376 ifmr->ifm_active |= IFM_10_T;
2378 if (media & TI_LNK_100MB)
2379 ifmr->ifm_active |= IFM_100_FX;
2380 if (media & TI_LNK_10MB)
2381 ifmr->ifm_active |= IFM_10_FL;
2383 if (media & TI_LNK_FULL_DUPLEX)
2384 ifmr->ifm_active |= IFM_FDX;
2385 if (media & TI_LNK_HALF_DUPLEX)
2386 ifmr->ifm_active |= IFM_HDX;
2392 static int ti_ioctl(ifp, command, data, cr)
2398 struct ti_softc *sc = ifp->if_softc;
2399 struct ifreq *ifr = (struct ifreq *) data;
2400 int s, mask, error = 0;
2401 struct ti_cmd_desc cmd;
2408 error = ether_ioctl(ifp, command, data);
2411 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2414 ifp->if_mtu = ifr->ifr_mtu;
2419 if (ifp->if_flags & IFF_UP) {
2421 * If only the state of the PROMISC flag changed,
2422 * then just use the 'set promisc mode' command
2423 * instead of reinitializing the entire NIC. Doing
2424 * a full re-init means reloading the firmware and
2425 * waiting for it to start up, which may take a
2428 if (ifp->if_flags & IFF_RUNNING &&
2429 ifp->if_flags & IFF_PROMISC &&
2430 !(sc->ti_if_flags & IFF_PROMISC)) {
2431 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2432 TI_CMD_CODE_PROMISC_ENB, 0);
2433 } else if (ifp->if_flags & IFF_RUNNING &&
2434 !(ifp->if_flags & IFF_PROMISC) &&
2435 sc->ti_if_flags & IFF_PROMISC) {
2436 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2437 TI_CMD_CODE_PROMISC_DIS, 0);
2441 if (ifp->if_flags & IFF_RUNNING) {
2445 sc->ti_if_flags = ifp->if_flags;
2450 if (ifp->if_flags & IFF_RUNNING) {
2457 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2460 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2461 if (mask & IFCAP_HWCSUM) {
2462 if (IFCAP_HWCSUM & ifp->if_capenable)
2463 ifp->if_capenable &= ~IFCAP_HWCSUM;
2465 ifp->if_capenable |= IFCAP_HWCSUM;
2466 if (ifp->if_flags & IFF_RUNNING)
2481 static void ti_watchdog(ifp)
2484 struct ti_softc *sc;
2488 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2498 * Stop the adapter and free any mbufs allocated to the
2501 static void ti_stop(sc)
2502 struct ti_softc *sc;
2505 struct ti_cmd_desc cmd;
2507 ifp = &sc->arpcom.ac_if;
2509 /* Disable host interrupts. */
2510 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2512 * Tell firmware we're shutting down.
2514 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2516 /* Halt and reinitialize. */
2518 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2521 /* Free the RX lists. */
2522 ti_free_rx_ring_std(sc);
2524 /* Free jumbo RX list. */
2525 ti_free_rx_ring_jumbo(sc);
2527 /* Free mini RX list. */
2528 ti_free_rx_ring_mini(sc);
2530 /* Free TX buffers. */
2531 ti_free_tx_ring(sc);
2533 sc->ti_ev_prodidx.ti_idx = 0;
2534 sc->ti_return_prodidx.ti_idx = 0;
2535 sc->ti_tx_considx.ti_idx = 0;
2536 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2538 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2544 * Stop all chip I/O so that the kernel's probe routines don't
2545 * get confused by errant DMAs when rebooting.
2547 static void ti_shutdown(dev)
2550 struct ti_softc *sc;
2552 sc = device_get_softc(dev);